A MEMS micromirror and a method for preparing the same

Abstract

The present application relates to the field of semiconductor technology, and in particular to a method for preparing a MEMS micromirror, the method comprising: providing a wafer substrate, the wafer substrate having a relative front and back, the front being a functional surface for forming a MEMS micromirror; forming a conductive column and a first mark on the wafer substrate, the conductive column passing through the wafer substrate, and the first mark being located on the back of the wafer substrate; forming a second mark and a first functional structure on the front of the wafer substrate; forming a bonding layer on the front side of the wafer substrate, the bonding layer being located above the conductive column, the second mark and the first functional structure; using the first mark as an overlay alignment point, forming a mark window exposing the second mark on the bonding layer; using the second mark as an overlay alignment point, forming a second functional structure on the bonding layer, and the second functional structure is overlaid and aligned with the first functional structure. Based on the above technical solution, the alignment accuracy in the preparation process of the MEMS micromirror can be effectively improved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a MEMS micromirror and a method for preparing the same. Background Art

[0002] In the structural design and manufacturing process of some semiconductor devices, such as MEMS (Micro ElectroMechanical System) micromirrors, wire bonding is usually used for electrical connection. The front wire bonding process increases the length of wiring and the possibility of cross interference, which affects the efficiency and quality of signal transmission, and makes array packaging extremely complicated. The introduction of through silicon via (TSV) process can reduce the power consumption and parasitic capacitance of the chip and reduce signal delay. However, the manufacturing process of TSV process is very complicated. It not only needs to consider the X and Y axis insulation design brought by the introduction of TSV process, but also involves the integration of multiple materials, such as silicon, copper, gold and insulation layer materials. Due to the different thermal expansion coefficients of these materials, the original alignment marks will be misaligned during the bonding process of overlay and multi-functional layer, and the overlay alignment accuracy will be reduced, resulting in low device yield and affecting device function. Summary of the invention

[0003] In view of the above problems in the prior art, the present application provides a MEMS micromirror and a method for manufacturing the same. The specific technical solution is as follows:

[0004] In one aspect, the present application provides a method for preparing a MEMS micromirror, the method comprising:

[0005] Providing a wafer substrate, wherein the wafer substrate has a front side and a back side opposite to each other, wherein the front side is a functional side for forming the MEMS micromirror;

[0006] forming a conductive column and a first mark on the wafer substrate, wherein the conductive column penetrates the wafer substrate, and the first mark is located on the back side of the wafer substrate;

[0007] forming a second mark and a first functional structure on the front side of the wafer substrate;

[0008] forming a bonding layer on the front side of the wafer substrate, wherein the bonding layer is located above the conductive pillar, the second mark and the first functional structure;

[0009] Taking the first mark as an overlay alignment point, forming a mark window exposing the second mark on the bonding layer;

[0010] A second functional structure is formed on the bonding layer using the second mark as an overlay alignment point, and the second functional structure is overlaid and aligned with the first functional structure.

[0011] In a possible implementation manner, the first functional structure is fixed comb teeth, and the second functional structure is movable comb teeth.

[0012] In a possible implementation, the wafer substrate includes a first substrate layer, an insulating layer and a second substrate layer, the insulating layer is arranged between the first substrate layer and the substrate layer, the front side is located on the side of the first substrate layer away from the insulating layer, and the back side is located on the side of the substrate layer away from the insulating layer.

[0013] In a possible implementation manner, before forming the conductive pillar and the first mark on the wafer substrate, the method further includes: forming a third mark on the front surface of the wafer substrate;

[0014] The process of forming the conductive pillar includes:

[0015] Using the third mark as an overlay alignment point, forming a through hole penetrating the wafer substrate;

[0016] A conductive material is filled in the through hole to form the conductive pillar.

[0017] In a possible implementation manner, the process of forming the first mark includes:

[0018] The first mark is formed on the back side of the wafer substrate using the third mark as an overlay alignment point.

[0019] In a possible implementation manner, before forming the second mark on the front side of the wafer substrate, the method further includes: forming a fourth mark on the front side of the wafer substrate;

[0020] The process of forming the second mark includes: using the fourth mark as an overlay alignment point to form the second mark on the front side of the wafer substrate.

[0021] In a possible implementation manner, the process of forming the first functional structure includes:

[0022] The first functional structure is formed on the front surface of the wafer substrate using the fourth mark as an overlay alignment point, wherein the first functional structure is formed in an area outside the second mark.

[0023] In a possible implementation manner, the third mark and the fourth mark are formed by etching based on the same mask.

[0024] In a possible implementation manner, the preparation method further comprises:

[0025] The third mark is used as an overlay alignment point to form a conductive bump on the back side of the wafer substrate, wherein the conductive bump is connected to one end of the conductive column.

[0026] In a possible implementation manner, the process of forming the bonding layer includes:

[0027] Taking the fourth mark as an overlay alignment point, forming a transition layer on the front side of the wafer substrate, wherein the transition layer covers the front side of the wafer substrate and exposes the conductive pillar, the second mark, the third mark, the fourth mark and the first functional structure;

[0028] The bonding layer is bonded to the front side of the wafer substrate, and the bonding layer is bonded to the front side of the wafer substrate through the transition layer.

[0029] In a possible implementation manner, after forming a bonding layer on the front side of the wafer substrate, the preparation method further includes:

[0030] The bonding layer is thinned, and the thickness of the prepared MEMS micromirror is 30-50 μm.

[0031] On the other hand, a MEMS micromirror is provided, which is prepared by the above-mentioned preparation method.

[0032] Based on the above technical solution, this application has the following beneficial effects:

[0033] The technical solution of the present application converts the back side overlay alignment of the second functional structure into the front side overlay alignment by forming a first mark and a second mark relatively arranged on the wafer substrate and providing a mark window capable of exposing the second mark, so that the functional structures arranged on different layers can be directly overlaid and aligned, thereby avoiding the problem of large back side overlay error caused by misalignment of the original marks due to the bonding of the overlay and the multifunctional layer, which is beneficial to improving the overlay alignment accuracy in the MEMS micromirror preparation process, thereby improving the manufacturing yield of the MEMS micromirror. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] In order to more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0035] Figure 1 : A flow chart of the preparation of a MEMS micromirror provided in an embodiment of the present application;

[0036] Figure 2 : A cross-sectional view of a MEMS micromirror during a formation process provided in an embodiment of the present application;

[0037] Figure 3: A cross-sectional view of a MEMS micromirror during another formation process provided in an embodiment of the present application;

[0038] Figure 4 : A cross-sectional view of a MEMS micromirror during another formation process provided in an embodiment of the present application;

[0039] Figure 5 : A cross-sectional view of a MEMS micromirror during another formation process provided in an embodiment of the present application;

[0040] Figure 6 : A cross-sectional view of a MEMS micromirror during another formation process provided in an embodiment of the present application;

[0041] Figure 7 : A cross-sectional view of a MEMS micromirror during another formation process provided in an embodiment of the present application;

[0042] Figure markings: 1-wafer substrate, 101-first substrate layer, 102-insulating layer, 103-second substrate layer, 2-third mark, 3-fourth mark, 4-conductive column, 5-conductive bump, 6-first mark, 7-second mark, 8-first functional structure, 9-transition layer, 10-bonding layer, 11-marking window, 12-second functional structure. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application.

[0044] It should be noted that in the description of the present application, for the following defined terms, unless a different definition is given in the claims or elsewhere in this specification, these definitions should be applied. All numerical values, whether or not explicitly indicated, are defined herein as being modified by the term "about". The term "about" generally refers to a numerical range that a person of ordinary skill in the art would consider to be equivalent to the stated value to produce substantially the same properties, functions, results, etc. A numerical range indicated by a low value and a high value is defined to include all numerical values ​​included in the numerical range and all subranges included in the numerical range.

[0045] It should be noted that, in the description of the present application, the terms "first", "second", etc. are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0046] It should be noted that, in the description of the present application, the meaning of the terms "on", "above", "above", and "above" should be interpreted in the broadest sense, meaning that the description containing these terms is interpreted as "the component can be set on another component in direct contact, or there can be an intermediate component or layer between the components". In addition, for the convenience of description, the present application may also use spatial relative terms such as "under", "below", "under", "on", "above", "above", "lower", "upper", etc. to describe the relationship between an element or component and another element or component shown in the drawings. In addition to the orientations described in the figures, the spatially relative terms are also intended to cover different orientations of the device in use or operation. The device can be oriented in other ways (rotated 90° or in other orientations), and the spatially relative descriptors used in the present application can be interpreted accordingly.

[0047] The term "layer" as used in this application refers to a portion of a material including an area with a certain thickness. A layer may extend over the entire underlying or superstructure, or may extend over a local range of the underlying or superstructure. In addition, a layer may be an area of ​​a homogeneous or inhomogeneous continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure or between any pair of horizontal planes therebetween. A layer may extend horizontally, vertically and / or along a tapered surface. A layer may include multiple layers. For example, bonding layer 10 may include one or more doped or undoped semiconductor layers, and may have the same or different materials.

[0048] It should be understood that the “surface” used in this application, such as the “first surface”, the “second surface”, etc., refers to the XY plane of the wafer substrate 1, the bonding layer 10, etc., corresponding to the XY plane of the MEMS micromirror, and the “thickness direction” refers to the Z direction perpendicular to the XY plane. The “thickness” or “height” mentioned in this application refers to the Z-direction thickness or Z-direction height.

[0049] The following combination Figure 1-7 A method for preparing a MEMS micromirror provided in an embodiment of the present application is introduced. Figure 1It is a flow chart of a method for forming a MEMS micromirror provided in an embodiment of the present application. This specification provides method operation steps such as the embodiment or flow chart, but more or fewer operation steps may be included based on conventional or non-creative labor. The order of steps listed in the embodiment is only one way of executing the order of many steps and does not represent the only execution order. When the preparation method is actually executed, it can be executed in the order of the method shown in the embodiment or the accompanying drawings or in parallel. The preparation method of a MEMS micromirror includes:

[0050] S1: providing a wafer substrate 1, wherein the wafer substrate 1 has a front side and a back side opposite to each other, and the front side is a functional surface for forming a MEMS micromirror;

[0051] Specifically, the constituent material of the wafer substrate 1 may include, but is not limited to, at least one of the following materials: silicon, germanium, gallium arsenide, gallium nitride, silicon carbide, or other semiconductor materials that can be device substrates.

[0052] In some embodiments, the preparation method further includes forming a multilayer structure on the wafer substrate 1, and the multilayer structure may include a first substrate layer 101, an insulating layer 102, and a second substrate layer 103, etc. The insulating layer 102 is disposed between the first substrate layer 101 and the second substrate layer 103, and the front side of the wafer substrate 1 is located on the side of the surface layer away from the insulating layer, and the back side of the wafer substrate 1 is located on the side of the substrate layer away from the insulating layer. Specifically, the constituent material of the first substrate layer 101 may include, but is not limited to, at least one of the following materials: silicon, germanium, gallium arsenide, gallium nitride, silicon carbide, or other suitable semiconductor materials; the constituent material of the insulating layer 102 may include, but is not limited to, at least one of the following materials: silicon dioxide, silicon nitride, aluminum oxide, or other suitable insulating materials; the constituent material of the second substrate layer 103 may include, but is not limited to, at least one of the following materials: silicon, germanium, gallium arsenide, gallium nitride, silicon carbide, or other suitable semiconductor materials. Preferably, the material of the first substrate layer 101 is silicon, the material of the insulating layer 102 is silicon dioxide, and the material of the second substrate layer 103 is silicon. The insulating layer 102 can effectively isolate the first substrate layer 101 and the second substrate layer 103, reduce the undesired current between the layers, and thus significantly improve the reliability of the MEMS micromirror.

[0053] S2: forming a conductive column 4 and a first mark 6 on the wafer substrate 1, wherein the conductive column 4 penetrates the wafer substrate 1, and the first mark 6 is located on the back side of the wafer substrate 1;

[0054] In some embodiments, reference Figure 2-3 , S2 may include the following steps S21-S23:

[0055] S21: forming a third mark 2 on the front surface of the wafer substrate 1;

[0056] S22: using the third mark 2 as an overlay alignment point to form a through hole penetrating the wafer substrate 1;

[0057] S23 : Filling the through hole with a conductive material to form a conductive column 4 .

[0058] Specifically, the third mark 2 can be formed on the front side of the wafer substrate 1 at least by a patterning process, and the patterning process may include but is not limited to the steps of photoresist coating, baking, exposure, development, etching, rinsing and drying, and can form the third mark 2 for aligning the mask with the wafer substrate 1. Among them, the etching process includes but is not limited to wet etching, plasma etching, reactive ion etching, etc. Preferably, the etching process is deep reactive ion etching, which can bombard the silicon material with a high-energy ion beam to remove unnecessary parts, and form the third mark 2 with a high aspect ratio structure on the surface of the wafer substrate 1.

[0059] Specifically, the method of forming a through hole includes laser drilling, dry etching, wet etching, etc., to form a through hole that can penetrate the wafer substrate 1, and then fill the through hole with conductive material to form a conductive column 4, one end of the conductive column 4 is located on the front side of the wafer substrate 1, and the other end of the conductive column 4 is located on the back side of the wafer substrate 1.

[0060] Optionally, before filling the conductive material, the method for forming the conductive column 4 also includes depositing a barrier layer in the through hole. The deposition process may include but is not limited to chemical vapor deposition, physical vapor deposition, atomic layer deposition and other methods. The barrier layer can block the electrical conduction between the conductive material and the wafer substrate 1; the barrier layer can be formed of materials such as silicon oxide, silicon nitride and polymer.

[0061] Specifically, the conductive material can be filled in the through hole by at least electroplating, magnetron sputtering, chemical vapor deposition, atomic layer deposition and other methods to form the conductive column 4. The conductive material filled in the through hole includes a combination of one or more of copper, titanium, tungsten, aluminum, gold, nickel and tantalum, or other conductive materials. Preferably, copper is filled in the through hole to form a conductive copper column. Copper has excellent electrical and thermal properties and can effectively realize electrical interconnection in the vertical direction inside the MEMS micromirror.

[0062] In some embodiments, one or more conductive pillars 4 may be formed on the wafer substrate 1 to enhance the electrical connection between the MEMS micromirror multilayer structures.

[0063] In some embodiments, the process of forming the first mark 6 includes: using the third mark 2 as an overlay alignment point to form the first mark 6 on the back side of the wafer substrate 1 .

[0064] Specifically, after forming the conductive column 4, the third mark 2 is used as the overlay alignment point for mark etching to form the first mark 6 on the back of the wafer substrate. The process of forming the conductive column 4 involves the integration of multiple materials. Due to the different thermal expansion coefficients of different materials, the original mark may be misaligned. In this way, the first mark 6 is formed after the conductive column 4 is formed, which can effectively avoid the misalignment of the first mark 6, and further avoid the misalignment of the mark window 11 and the second mark 7.

[0065] Specifically, the first mark 6 is formed in a region outside the conductive pillar 4 to avoid affecting the electrical connection between the conductive pillar 4 and other devices.

[0066] Specifically, the first mark 6 may be formed by at least photolithography, development, etching, ion implantation and other processes.

[0067] In some embodiments, the first mark 6 may include one or more protrusions protruding from the back side of the wafer substrate 1; preferably, the first mark 6 includes at least 2 protrusions. It can be understood that the number of protrusions in the first mark 6 can be 2, 3, 4, etc., which is conducive to improving the accuracy of back side alignment.

[0068] Specifically, the shape of the protrusion may include but is not limited to a circle, a triangle, an elongated shape, or other shapes suitable for the protrusion. The first mark 6 may be a figure composed of protrusions, and the first mark 6 may be a figure including but not limited to a square, a circle, a triangle, or other figures suitable for the alignment mark. Preferably, the first mark 6 is a square mark composed of a plurality of elongated protrusions.

[0069] In some embodiments, the first mark 6 may include one or more grooves. Preferably, the first mark 6 includes at least two grooves. It is understandable that the number of grooves in the first mark 6 may be 2, 3, 4, etc., which is conducive to improving the alignment accuracy between the mask and the wafer substrate. Specifically, the shape of the groove may include but is not limited to a circle, a triangle, an elongated shape, etc., or other shapes suitable for the groove; the first mark 6 may be a figure composed of grooves, and the first mark 6 may be but is not limited to a square, a circle, a triangle, or other figures suitable for the alignment mark.

[0070] In some embodiments, reference Figure 3 After forming the conductive pillar 4, the preparation method further includes: using the third mark 2 as an overlay alignment point, forming a conductive bump 5 on the back side of the wafer substrate 1, and connecting the conductive bump 5 to one end of the conductive pillar 4 for electrical interconnection between the MEMS micromirror and other devices.

[0071] Specifically, the method of forming the conductive bump 5 may include but is not limited to at least one of the following methods: photolithography, vacuum sputtering, electroplating and etching, etc. The material of the conductive bump 5 may include but is not limited to copper, nickel, aluminum, palladium, gold, silver, tin, etc. or a combination of multiple thereof, or other alternative conductive materials. Preferably, the material of the conductive bump 5 is a composite metal material.

[0072] In some embodiments, the MEMS micromirror may include a plurality of conductive bumps 5 , which are spaced apart and distributed on the back side of the wafer substrate 1 , and can provide the MEMS micromirror with more connection points to external devices, thereby improving the connection density.

[0073] S3: forming a second mark 7 and a first functional structure 8 on the front side of the wafer substrate 1;

[0074] In some embodiments, reference Figure 4 , S3 may include the following steps S31-S33:

[0075] S31: forming a fourth mark 3 on the front surface of the wafer substrate 1;

[0076] S32: using the fourth mark 3 as an overlay alignment point, forming a second mark 7 on the front surface of the wafer substrate 1;

[0077] S33 : using the fourth mark 3 as an overlay alignment point, forming a first functional structure 8 on the front surface of the wafer substrate 1 , wherein the first functional structure 8 is formed in an area outside the second mark 7 .

[0078] Specifically, the fourth mark 3 can be formed on the front side of the wafer substrate 1 at least by a patterning process, and the patterning process can include but is not limited to photoresist coating, baking, exposure, development, etching, rinsing and drying methods, which can form the fourth mark 3 for aligning the mask with the wafer substrate 1. Among them, the etching process includes but is not limited to wet etching, plasma etching, reactive ion etching, etc. Preferably, the etching process is deep reactive ion etching, which can bombard the silicon material with a high-energy ion beam to remove unnecessary parts, and form the fourth mark 3 with a high aspect ratio structure on the surface of the wafer substrate 1.

[0079] In some embodiments, the third mark 2 and the fourth mark 3 may be formed by the same patterning process, that is, after the photoresist is coated and developed, the third mark 2 and the fourth mark 3 are formed on the front side of the wafer substrate 1 by etching through the same mask. Specifically, the fourth mark 3 is a pattern different from the third mark 2 to prevent the mask alignment from being misaligned and affecting the alignment accuracy.

[0080] In some embodiments, the second mark 7 is formed at a position close to the third mark 2 and / or the fourth mark 3, wherein there is a gap between the second mark 7 and the third mark 2, and there is a gap between the second mark 7 and the fourth mark 3. This is conducive to optimizing the design layout of the MEMS micromirror, so that more functional areas can be formed within a unit area, and misalignment of the marks can be avoided.

[0081] Specifically, the second mark 7 can be formed by at least photolithography, development, etching, ion implantation and other processes; the second mark 7 can include one or more grooves, preferably, the second mark 7 includes at least 2 grooves; it can be understood that the number of grooves in the second mark 7 can be 2, 3, 4, etc., which is beneficial to improve the alignment accuracy of the mask and the wafer substrate.

[0082] Specifically, the shape of the groove may include but is not limited to a circle, a triangle, an elongated shape, or other shapes suitable for a groove; the second mark 7 may be a pattern composed of grooves, and the second mark 7 may be a pattern including but not limited to a square, a circle, a triangle, or other shapes suitable for an alignment mark. Preferably, the second mark 7 is a square mark composed of a plurality of elongated grooves.

[0083] In some embodiments, the position of the second mark 7 on the front side of the wafer substrate 1 is arranged relative to the position of the first mark 6 on the back side of the wafer substrate 1, which is conducive to the subsequent formation of a mark window 11 above the second mark 7 with the first mark 6 as the overlay alignment point, thereby improving the alignment accuracy of the mark window 11 and the second mark 7.

[0084] In some embodiments, the first mark, the second mark, the third mark and the fourth mark are distinguished from each other, that is, each mark can have a different shape and depth, each mark can include a different number of grooves, and the shape of the grooves in each mark can be different, so that the mask corresponding to each mark can be quickly and accurately positioned, which is beneficial to improve the alignment accuracy.

[0085] In some embodiments, after forming the second mark 7, the first functional structure 8 is formed with the fourth mark 3 as the overlay alignment point, and the first functional structure 8 is formed in the area outside the second mark 7, the third mark 2 and the fourth mark 3. In this way, the first functional structure 8 is prevented from overlapping with the alignment mark, thereby avoiding affecting the performance of the first functional structure and the alignment accuracy of the second mark 7.

[0086] Specifically, the first functional structure 8 can be formed by at least photolithography, development, etching, ion implantation and other processes, and the first functional structure 8 is formed in the area outside the second mark 7 to avoid the second functional structure 12 being unable to be overlaid and aligned due to the overlap of the second mark 7 and the first functional structure 8. Preferably, the first functional structure 8 can be a fixed comb tooth structure, which can match the upper and lower positions of the movable parts in the MEMS micromirror to realize the function of the MEMS micromirror.

[0087] S4: forming a bonding layer 10 on the front side of the wafer substrate 1, wherein the bonding layer 10 is located above the conductive pillar 4, the second mark 7 and the first functional structure 8;

[0088] Specifically, the bonding layer 10 can be formed by methods such as melt bonding, anodic bonding, eutectic bonding and thermocompression bonding, which can realize the integration of the wafer substrate 1 and the functional layer, thereby improving the performance and reliability of the MEMS micromirror.

[0089] In some embodiments, reference Figure 5 , the formation process of the bonding layer 10 may include S41-S42:

[0090] S41: taking the fourth mark 3 as an overlay alignment point, forming a transition layer 9 on the front side of the wafer substrate 1, the transition layer 9 covers the front side of the wafer substrate 1 and exposes the conductive pillar 4, the second mark 7, the third mark 2, the fourth mark 3 and the first functional structure 8;

[0091] S41: The bonding layer 10 is bonded to the front side of the wafer substrate 1 , and the bonding layer 10 is bonded to the front side of the wafer substrate 1 via the transition layer 9 .

[0092] Specifically, the transition layer 9 can be formed by at least patterning, etching, material deposition and other techniques, and the material of the transition layer 9 can include a combination of one or more of gold, aluminum, titanium, titanium silicide and platinum silicide. Preferably, the material of the transition layer 9 is gold, which can effectively connect the wafer substrate 1 and the bonding layer 10.

[0093] Specifically, the transition layer 9 covers the front side of the wafer substrate 1 and exposes the conductive pillar 4, the second mark 7, the third mark 2, the fourth mark 3 and the first functional structure 8. It can be understood that the transition layer 9 covers the area of ​​the surface of the wafer substrate 1 except the mark pattern and the functional area, and avoids damaging the functional structure of the front side of the wafer substrate 1 while achieving the connection between the wafer substrate 1 and the bonding layer 10.

[0094] In some embodiments, at least one bonding layer 10 may be formed on the front side of the wafer substrate 1 to integrate the functional structure on the wafer substrate 1. Specifically, the material constituting the bonding layer 10 may include but is not limited to at least one of the following materials: silicon, germanium, gallium arsenide, gallium nitride, silicon carbide, or other suitable semiconductor materials.

[0095] In some embodiments, after forming the bonding layer 10 on the front side of the wafer substrate 1, the preparation method further includes thinning the bonding layer 10. The thinning method may include but is not limited to processes such as mechanical grinding and chemical mechanical polishing.

[0096] Specifically, the thickness of the prepared MEMS micromirror after thinning is 30-50 μm, preferably 40 μm; it is understandable that the thickness of the MEMS micromirror can be any point value within the above range; illustratively, the thickness of the MEMS micromirror can be 30 μm, 35 μm, 40 μm, 45 μm, 50 μm, etc. The lateral size of the MEMS micromirror can be selected based on the application size requirements and is not limited here. By forming a MEMS micromirror of the above thickness, it is possible to meet the mechanical strength requirements of the device while reducing the electrical transmission distance in the thickness direction.

[0097] S5: using the first mark 6 as an overlay alignment point, forming a mark window 11 exposing the second mark 7 on the bonding layer 10;

[0098] Specifically, the mark window 11 may be formed at least by etching, and the etching method here may adopt a process such as dry etching or wet etching. Preferably, the mark window 11 is formed by a reactive ion etching process.

[0099] refer to Figure 6 The mark window 11 can penetrate the bonding layer 10 and completely expose the second mark 7. The size of the mark window 11 is greater than or equal to the size of the second mark 7, so that the second mark 7 can be aligned with the mask mark, thereby converting the back-side overlay alignment into the front-side overlay alignment in the subsequent process of forming the functional structure on the bonding layer 10, avoiding the error accumulation caused by the back-side overlay process, and effectively improving the overlay alignment accuracy.

[0100] Preferably, the marking window 11 is formed in the projection area of ​​the second mark 7 on the bonding layer 10, so that the marking window 11 can completely expose the second mark 7 without exposing the transition layer, which is beneficial to improving the overlay alignment accuracy, and further improving the alignment accuracy between the first functional structure 8 and the second functional structure 12.

[0101] S6 : using the second mark 7 as an overlay alignment point, forming a second functional structure 12 on the bonding layer 10 , and the second functional structure 12 is overlaid and aligned with the first functional structure 8 .

[0102] Specifically, by using the second mark 7 as the overlay alignment point of the second functional structure 12 and performing front overlay alignment, the overlay error caused by wafer deformation can be effectively avoided, which is beneficial to improving the overlay alignment accuracy, and further improving the alignment accuracy between the second functional structure 12 and the first functional structure 8 .

[0103] Specifically, the second functional structure 12 can be formed at least by photolithography, development, etching and other processes, and the second functional structure 12 is formed on the bonding layer 10 and arranged opposite to the first functional structure 8. By using the second mark 7 as the overlay alignment point, the alignment accuracy of the first functional structure 8 and the second functional structure 12 can be effectively improved.

[0104] In some embodiments, the second functional structure 12 is a movable comb tooth, Figure 7 , the first functional structure 8 and the second functional structure 12 form a comb tooth structure that cooperates with each other, and the movable comb teeth can move in the gaps between the fixed comb teeth; the comb tooth structure is applied to semiconductor devices to improve device performance and enhance the mechanical strength of the device, so that it can still maintain good performance under multiple bending or vibration conditions. For example, when the semiconductor device is a MEMS micromirror, through the electrostatic interaction between the comb tooth structures, a larger torsion angle or movement amount can be obtained under a smaller driving voltage, thereby improving the control accuracy and movement range of the micromirror surface.

[0105] Based on some or all of the above embodiments, in some embodiments, the overlay alignment accuracy of the second functional structure 12 is ±0.5μm; and the error of the back overlay alignment is ±3μm. Compared with the back overlay alignment of the second functional structure 12, the front overlay alignment by setting the mark window 11 can effectively improve the alignment accuracy.

[0106] If only back-side mark alignment is used in the overlay alignment process, the precision error of back-side overlay is often large, and the high-temperature stress generated in the bonding process will cause the wafer to deform, which will deteriorate the alignment accuracy of the pattern, further leading to the accumulation of back-side overlay process errors, and resulting in poor alignment accuracy between the first functional structure and the second functional structure, causing the comb teeth to be unable to move. Compared with only back-side mark alignment in the overlay alignment process, the technical solution provided in the embodiment of the present application can convert back-side overlay alignment into front-side overlay alignment, so that the second functional structure can be directly overlaid and aligned with the first functional structure, which is beneficial to improving the alignment accuracy of the second functional structure, thereby improving the manufacturing yield of semiconductor devices.

[0107] On the other hand, an embodiment of the present application provides a MEMS micromirror, which is prepared by the preparation method as described above. The MEMS micromirror of the embodiment of the present application includes a wafer substrate 1, a transition layer 9 and a bonding layer 10. The wafer substrate 1 has a front side and a back side arranged opposite to each other, the transition layer 9 is formed on the front side of the wafer substrate 1, and the bonding layer 10 is connected to the wafer substrate 1 through the transition layer 9.

[0108] The MEMS micromirror further includes a first functional structure 8 and a second functional structure 12 . The first functional structure 8 is formed on the front side of the wafer substrate 1 , and the second functional structure 12 is formed on a region of the bonding layer 10 corresponding to the first functional structure 8 .

[0109] Specifically, a mark window 11 is provided on the bonding layer 10 , which can expose an alignment mark provided on the front side of the wafer substrate 1 , and the alignment mark is used for overlay alignment of the second functional structure 12 .

[0110] Specifically, the MEMS micromirror also includes a conductive column 4 and a conductive bump 5. The conductive column 4 penetrates the wafer substrate 1 in the thickness direction. The conductive bump 5 is formed on the back side of the wafer substrate 1 and connected to one end of the conductive column 4 for electrically connecting the MEMS micromirror with other devices.

[0111] Specifically, the wafer substrate 1 includes a first substrate layer 101, an insulating layer 102 and a second substrate layer 103. The front side of the wafer substrate 1 is arranged on the first substrate layer 101. The insulating layer 102 is formed between the first substrate layer 101 and the second substrate layer 103. The insulating layer 102 can effectively isolate the first substrate layer 101 and the second substrate layer 103, improve the clock frequency, and reduce current leakage.

[0112] In some embodiments, the first functional structure 8 is a fixed comb tooth, and the second functional structure 12 is a movable comb tooth. The fixed comb teeth and the movable comb teeth can match each other in structure, and electrostatic force can be used to drive the movable comb teeth to move relative to the fixed comb teeth, thereby controlling the deflection of the micromirror, and obtaining a larger torsion angle or movement amount under a smaller driving voltage, thereby improving the control accuracy and movement range of the micromirror.

[0113] It can be understood that the above-mentioned MEMS micromirror is only a technical solution of an exemplary embodiment of the present application. The MEMS micromirror of the present application may include fewer or more structural features and is not limited to the device structure described in the embodiment.

[0114] It should be noted that the various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0115] The above description has fully disclosed the specific implementation methods of the present application. It should be pointed out that any changes made by technicians familiar with the field to the specific implementation methods of the present application do not deviate from the scope of the claims of the present application. Accordingly, the scope of the claims of the present application is not limited to the above specific implementation methods.

Claims

1. A method for preparing a MEMS micromirror, characterized in that: The preparation method comprises: Providing a wafer substrate, wherein the wafer substrate has a front side and a back side opposite to each other, wherein the front side is a functional side for forming a MEMS micromirror; forming a conductive column on the wafer substrate, wherein the conductive column penetrates the wafer substrate; forming a first mark on the back side of the wafer substrate; forming a fourth mark on the front surface of the wafer substrate; Using the fourth mark as an overlay alignment point, forming a second mark and a first functional structure on the front side of the wafer substrate; forming a bonding layer on the front side of the wafer substrate, wherein the bonding layer is located above the conductive pillar, the second mark and the first functional structure; Taking the first mark as an overlay alignment point, forming a mark window exposing the second mark on the bonding layer; A second functional structure is formed on the bonding layer using the second mark as an overlay alignment point, and the second functional structure is overlaid and aligned with the first functional structure.

2. The preparation method according to claim 1, characterized in that: The first functional structure is fixed comb teeth, and the second functional structure is movable comb teeth.

3. The preparation method according to claim 1, characterized in that: The wafer substrate includes a first substrate layer, an insulating layer and a second substrate layer, the insulating layer is arranged between the first substrate layer and the substrate layer, the front side is located on the side of the first substrate layer away from the insulating layer, and the back side is located on the side of the substrate layer away from the insulating layer.

4. The preparation method according to claim 1, characterized in that: Before forming the conductive pillar and the first mark on the wafer substrate, the method further includes: forming a third mark on the front surface of the wafer substrate; The process of forming the conductive pillar includes: Using the third mark as an overlay alignment point, forming a through hole penetrating the wafer substrate; A conductive material is filled in the through hole to form the conductive pillar.

5. The preparation method according to claim 4, characterized in that: The forming process of the first mark includes: The first mark is formed on the back side of the wafer substrate using the third mark as an overlay alignment point.

6. The preparation method according to claim 4, characterized in that: The process of forming the first functional structure includes: The first functional structure is formed on the front surface of the wafer substrate using the fourth mark as an overlay alignment point, wherein the first functional structure is formed in an area outside the second mark.

7. The preparation method according to claim 4, characterized in that: The third mark and the fourth mark are formed by etching based on the same mask.

8. The preparation method according to any one of claims 4 to 7, characterized in that: The preparation method further comprises: The third mark is used as an overlay alignment point to form a conductive bump on the back side of the wafer substrate, wherein the conductive bump is connected to one end of the conductive column.

9. The preparation method according to claim 4, characterized in that: The process of forming the bonding layer includes: Taking the fourth mark as an overlay alignment point, forming a transition layer on the front side of the wafer substrate, wherein the transition layer covers the front side of the wafer substrate and exposes the conductive pillar, the second mark, the third mark, the fourth mark and the first functional structure; The bonding layer is bonded to the front side of the wafer substrate, and the bonding layer is bonded to the front side of the wafer substrate through the transition layer.

10. The preparation method according to claim 4, characterized in that: The first mark, the second mark, the third mark and the fourth mark are distinguishable from each other.

11. The preparation method according to claim 1, characterized in that: The mark window is located in a projection area of ​​the second mark on the bonding layer.

12. The preparation method according to any one of claims 1 to 5, characterized in that: After forming a bonding layer on the front side of the wafer substrate, the preparation method further includes: The bonding layer is thinned, and the thickness of the prepared MEMS micromirror is 30-50 μm.

13. A MEMS micromirror, characterized in that: The method is prepared according to any one of claims 1 to 12.

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