Reset control method and electronic equipment

Abstract

The invention discloses a reset control method and electronic equipment, and the method comprises the steps: monitoring whether second equipment executes a reset process or not on a field programmable gate array in first equipment through a connection bus between the first equipment and the second equipment; and in response to the reset process executed by the second device, sending an interrupt signal to a processor in the first device, the interrupt signal being used for indicating the processor to execute the reset process.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a reset control method and an electronic device. Background Art

[0002] On 5G devices, high-speed serial computer expansion bus PCIe (peripheral component interconnect express) acceleration cards are usually used to implement baseband data transmission. For example, a PCIe-based board is connected to the server, and the board is implemented using a system-on-chip (SOC) chip.

[0003] At present, a hardware reset circuit is usually required to be provided on the board, and the SOC on the board is reset by the hardware reset circuit when the server is reset.

[0004] However, this reset method will cause high hardware complexity on the board. Summary of the invention

[0005] In view of this, the present application provides a reset control method and an electronic device, as follows:

[0006] A reset control method, comprising:

[0007] On a field programmable gate array in a first device, using a connection bus between the first device and a second device, monitoring whether the second device performs a reset process;

[0008] In response to the second device executing the reset process, an interrupt signal is sent to the processor in the first device, where the interrupt signal is used to instruct the processor to execute the reset process.

[0009] The above method preferably monitors whether the second device executes the reset process, including:

[0010] monitoring a target pin in the connection bus;

[0011] If the pin level of the target pin meets the reset condition, it is determined that the second device executes a reset process.

[0012] In the above method, preferably, the reset condition includes: the duration of time during which the pin level of the target pin is pulled down to the target level value reaches the target duration.

[0013] In the above method, preferably, the processor is provided with an interrupt handling program and a reset triggering program; the interrupt handling program runs in the kernel state of the processor, and the reset triggering program runs in the user state of the processor;

[0014] The interrupt handling program is used to detect whether the processor receives the interrupt signal sent by the field programmable gate array, and, in the case of detecting that the processor receives the interrupt signal sent by the field programmable gate array, send a target signal to the reset trigger program;

[0015] The reset trigger program is used to call a reset instruction in response to the target signal, and the reset instruction is used to instruct the processor to execute a reset process.

[0016] In the above method, preferably, after the reset trigger program starts running, the program identifier corresponding to the reset trigger program is sent to the character device node, so that the interrupt handler sends the target signal to the reset trigger program according to the program identifier in the character device node.

[0017] In the above method, preferably, the character device node is created by the interrupt handler, and the character device node runs in the user state of the processor.

[0018] In the above method, preferably, if the character device node does not have a program identifier corresponding to the reset trigger program, the method further includes:

[0019] A hardware restart signal is sent to the processor, so that the processor executes a hardware restart process.

[0020] The above method, preferably, after the reset trigger program calls the reset instruction, the method further includes:

[0021] Monitoring whether the target sub-process in the reset process is executed and completed within the first time period;

[0022] If the target sub-process is not executed to completion within the first time period, a hardware restart signal is sent to the processor, so that the processor executes a hardware restart process.

[0023] In the above method, preferably, the reset process includes:

[0024] Sending a warning message to an operating system corresponding to the processor, wherein the warning message is at least used to prompt data saving;

[0025] Sending a stop signal to a process in a running state through the operating system, wherein the stop signal is used to instruct the process to exit;

[0026] Unmounting the file system corresponding to the operating system;

[0027] A hardware restart signal is sent to the processor, so that the processor executes a hardware restart process.

[0028] An electronic device, as a first device, comprises: a processor and a field programmable gate array;

[0029] Among them, the field programmable gate array is used to: utilize the connection bus between the first device and the second device to monitor whether the second device executes the reset process; in response to the second device executing the reset process, send an interrupt signal to the processor, and the interrupt signal is used to instruct the processor to execute the reset process.

[0030] It can be seen from the above technical scheme that in a reset control method and electronic device disclosed in the present application, by using the field programmable gate array in the first device and the connection bus between the first device and the second device, it is monitored whether the second device executes the reset process. If the second device executes the reset process, the field programmable gate array sends an interrupt signal to the processor in the first device, and the interrupt signal is used to instruct the processor to execute the reset process. It can be seen that in this embodiment, after the second device executes the reset process, the field programmable gate array on the first device can be used to control the processor to execute the reset process, without deploying a hardware reset circuit on the first device. In this way, the reset control of the first device can be realized based on the existing field programmable gate array, so that while ensuring the realization of reset control, the hardware complexity on the first device will not be increased. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0032] Figure 1 A flowchart of a reset control method provided in an embodiment of the present application;

[0033] Figure 2 This is a system architecture diagram of the server and board in the embodiment of the present application;

[0034] Figure 3 This is an example diagram of deploying programs in CPU user mode and kernel mode in an embodiment of the present application;

[0035] Figure 4 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0036] Figure 5 An overall flow chart showing the addition of a reset interrupt trigger in the embodiment of the present application;

[0037] Figure 6This is a flow chart of the FPGA implementing reset detection through the processing module in the embodiment of the present application;

[0038] Figure 7 is a processing flow chart of the interrupt processing program in the embodiment of the present application;

[0039] Figure 8 This is a processing flow chart of the user-mode APP in an embodiment of the present application. DETAILED DESCRIPTION

[0040] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0041] refer to Figure 1 As shown, it is a flow chart for implementing a reset control method provided in an embodiment of the present application. The method can be applied to an electronic device having a field programmable gate array FPGA (Field Programmable Gate Array) and a processor CPU (Central Processing Unit), and the electronic device is interconnected with the second device as a first device through a connection bus. The first device provides baseband data transmission services for the second device. For example, the second device may be an electronic device that implements the fifth generation mobile communication technology 5G (5th Generation Mobile Communication Technology) communication, and the first device implements baseband data transmission as a PCIe acceleration card of the second device, and the first device is connected to the second device through the PCIe gold finger. The operating system on the first device is independent of the operating system on the second device. The FPGA in the first device is mainly responsible for business data transmission, and the CPU in the first device is mainly responsible for board management. As Figure 2 As shown in , the second device can be a server, in which CPU1 is deployed, the second device is a board, in which FPGA and CPU2 are arranged, the server and the board are physically connected through PCIe gold finger, the PCIe root point in the server communicates with the PCIe end point on the FPGA in the board through the PCIe bus, and the FPGA and CPU2 in the board communicate through the AXI (Advanced Xtensible Interface) bus and other buses. The server and the board belong to two independent operating systems. The technical solution in this embodiment is mainly used to realize the reset control of the electronic device to reduce the hardware complexity of the electronic device.

[0042] Specifically, the method in this embodiment may include the following steps:

[0043] Step 101: On a field programmable gate array in a first device, using a connection bus between the first device and a second device, monitor whether the second device executes a reset process, and execute step 102 in response to the second device executing the reset process.

[0044] Whether the second device executes the reset process can be understood as: whether the second device has started to execute the reset process.

[0045] In one implementation, monitoring whether the second device executes the reset process on the field programmable gate array can be implemented in the following manner:

[0046] The field programmable gate array monitors the target pin in the connection bus, and if the pin level of the target pin meets the reset condition, it can be determined that the second device executes the reset process.

[0047] The target pin may be a specific pin connected to a bus, such as a PERST pin in a PCIe bus. When the second device executes the reset process, the target pin will be pulled low. Based on this, in this embodiment, whether the second device executes the reset process can be determined on the field programmable gate array by monitoring whether the target pin meets the reset condition.

[0048] Based on the above implementation, in one implementation, the reset condition may be: the pin level of the target pin is pulled down to the target level value. Based on this, in this embodiment, as long as the field programmable gate array detects that the target pin is pulled down to the target level value, it can be determined that the second device has started to execute the reset process.

[0049] The target level value may be 0. For example, as long as the FPGA detects that the PERST pin in the PCIe bus is pulled down to 0, it can be determined that the second device has started to execute the reset process.

[0050] In another implementation, the reset condition may be: the duration of the pin level of the target pin being pulled down to the target level value reaches the target duration. Based on this, in this embodiment, after monitoring that the target pin is pulled down to the target level value, the field programmable gate array records the duration of the target pin being pulled down to the target level value. If the duration of the target pin being pulled down to the target level value reaches the target duration, it can be determined that the second device has started to execute the reset process.

[0051] The target duration can be set according to business requirements, such as 1 second. For example, after the FPGA detects that the PERST pin in the PCIe bus is pulled down to 0, it records the duration of the PERST pin being pulled down to 0. If the duration of the PERST pin being pulled down to 0 reaches 1 second, it can be determined that the second device has started to execute the reset process.

[0052] Step 102: The field programmable gate array sends an interrupt signal to a processor in the first device.

[0053] The interrupt signal is used to instruct the processor to execute a reset process.

[0054] Specifically, the field programmable gate array can send an interrupt signal to the processor via a bus such as an AXI bus between the field programmable gate array and the processor in the first device. After the processor receives the interrupt signal, it starts to execute the reset process in response to the interrupt signal.

[0055] In one implementation, the reset process may include the following sub-processes:

[0056] First, a warning message is sent to the operating system corresponding to the processor, where the warning message is at least used to prompt data saving; for example, a warning message "about to be reset, please save data" is output on the display interface corresponding to the operating system.

[0057] Then, a stop signal is sent to the running process through the operating system, and the stop signal is used to instruct the process to exit. Thus, the process can exit normally in response to the stop signal, avoiding the situation of data loss caused by abnormal exit.

[0058] Afterwards, the file system corresponding to the operating system is unmounted. Specifically, the file system is uninstalled from the operating system to ensure the consistency and data integrity of the file system.

[0059] Finally, the operating system sends a hardware restart signal to the processor, so that the processor executes the hardware restart process, that is, the processor responds to the hardware restart signal and triggers a hardware-level restart, that is, a kernel reset of the processor.

[0060] It can be seen from the above technical solution that in a reset control method provided in an embodiment of the present application, by using the field programmable gate array in the first device and the connection bus between the first device and the second device, it is monitored whether the second device has executed the reset process. If the second device has executed the reset process, the field programmable gate array sends an interrupt signal to the processor in the first device, and the interrupt signal is used to instruct the processor to execute the reset process. It can be seen that in this embodiment, after the second device executes the reset process, the field programmable gate array on the first device can be used to control the processor to execute the reset process, without deploying a hardware reset circuit on the first device. In this way, the reset control of the first device can be realized based on the existing field programmable gate array, thereby ensuring the realization of reset control while not causing an increase in the hardware complexity of the first device.

[0061] In one implementation, an interrupt processing program and a reset trigger program are set in the processor of the first device.

[0062] The interrupt processing program runs in the kernel state of the processor, so that the interrupt processing program can detect whether the processor receives an interrupt signal sent by the field programmable gate array.

[0063] The reset trigger program runs in the user state of the processor. Based on this, when the interrupt handler detects that the processor receives an interrupt signal sent by the field programmable gate array, it sends a target signal to the reset trigger program. As a result, the reset trigger program can respond to the target signal and call the reset instruction, which is used to instruct the processor to execute the reset process.

[0064] The target signal may be a custom signal set according to business requirements.

[0065] For example, Figure 3 As shown in , an interrupt handler is deployed in the kernel state of the CPU of the first device, and a reset trigger program is deployed in the user state of the CPU. Therefore, when the interrupt handler in the kernel state detects that the CPU receives an interrupt signal sent by the FPGA, the target signal is sent to the reset trigger program in the user state through the interaction channel between the kernel state and the user state. Since the reset trigger program is a user state program, the reset trigger program can call the reset instruction in the operating system in response to the target signal. Therefore, the CPU responds to the called reset instruction and executes the reset process, which specifically includes: first prompting the user to save data, then controlling the normal exit of each process running in the operating system, then unmounting the file system, and finally the CPU triggers a hardware-level restart.

[0066] Based on the above implementation, the reset trigger program can be started when the first device is turned on, or started in response to a trigger instruction. The trigger instruction can be based on a user's trigger operation, or the trigger instruction can be received from other programs, or the trigger instruction can be generated in response to a trigger condition. After the reset trigger program starts running, the program identifier corresponding to the reset trigger program is sent to the character device node, so that the interrupt handler sends a target signal to the reset trigger program according to the program identifier in the character device node.

[0067] That is to say, in this embodiment, the program identifier corresponding to the reset trigger program, the process number corresponding to the reset trigger program after the reset trigger program is started, etc. are recorded through the character device node. Therefore, the interrupt handler can locate the reset trigger program according to the program identifier recorded in the character device node, and then the interrupt handler can send the target signal to the reset trigger program according to the program identifier.

[0068] Among them, the character device node is created by the interrupt handler. For example, the character device node is a device node constructed by a function in the character device driver, and the character device node runs in the user state of the device. Therefore, the character device node in the user state can receive the program identifier sent by the reset trigger program in the user state.

[0069] Based on the above implementation, if there is no program identifier corresponding to the reset trigger program in the character device node, the reset trigger program may not be able to receive the target signal sent by the interrupt handler, and the reset instruction cannot be called, and the processor will not execute the reset process. At this time, the interrupt handler can send a hardware restart signal to the processor through the operating system to enable the processor to execute the hardware restart process, thereby avoiding the situation where the reset process cannot be executed due to the lack of a program identifier corresponding to the reset trigger program in the character device node, thereby improving the reliability of reset control.

[0070] In one implementation, in this embodiment, after the reset trigger program calls the reset instruction, it is also possible to monitor whether the target sub-process in the reset process is executed within the first time period to determine whether the processor executes the reset process.

[0071] For example, the target sub-process may be: sending a stop signal to a running process through the operating system, the stop signal is used to instruct the running process to exit. The target sub-process is executed and completed, specifically: the running process exits.

[0072] Based on this, in this embodiment, it is monitored whether the process that is in a running state within the first time period has exited. If so, it indicates that the target sub-process has been executed, indicating that the processor has executed the reset process; if not, that is, there is a process that is in a running state within the first time period and has not exited and is still running. At this time, the reset trigger program can send a hardware restart signal to the processor through the operating system, so that the processor executes the hardware restart process.

[0073] refer to Figure 4 , is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application, and the electronic device as a first device may include: a processor 401 and a field programmable gate array 402;

[0074] Among them, the field programmable gate array 402 is used to: utilize the connection bus 403 between the first device and the second device to monitor whether the second device executes the reset process; in response to the second device executing the reset process, send an interrupt signal to the processor 401, and the interrupt signal is used to instruct the processor 401 to execute the reset process.

[0075] It can be seen from the above technical solution that in an electronic device provided by an embodiment of the present application, by using the field programmable gate array in the first device and the connection bus between the first device and the second device, it is monitored whether the second device has executed the reset process. If the second device has executed the reset process, the field programmable gate array sends an interrupt signal to the processor in the first device, and the interrupt signal is used to instruct the processor to execute the reset process. It can be seen that in this embodiment, after the second device executes the reset process, the field programmable gate array on the first device can be used to control the processor to execute the reset process, without deploying a hardware reset circuit on the first device. In this way, the reset control of the first device can be realized based on the existing field programmable gate array, so that while ensuring the reset control, the hardware complexity on the first device will not be increased.

[0076] In one implementation, when the field programmable gate array 402 monitors whether the second device executes the reset process, it is specifically used to: monitor the target pin in the connection bus 403; if the pin level of the target pin meets the reset condition, determine that the second device executes the reset process. The reset condition includes: the pin level of the target pin is pulled down to the target level value for a duration that reaches the target duration.

[0077] In one implementation, the processor 401 is provided with an interrupt handler and a reset trigger program; the interrupt handler runs in the kernel state of the processor, and the reset trigger program runs in the user state of the processor 401; the interrupt handler is used to detect whether the processor 401 receives the interrupt signal sent by the field programmable gate array 402, and, when it is detected that the processor 401 receives the interrupt signal sent by the field programmable gate array 402, sends a target signal to the reset trigger program; the reset trigger program is used to call a reset instruction in response to the target signal, and the reset instruction is used to instruct the processor 401 to execute a reset process.

[0078] After the reset trigger program starts running, the program identifier corresponding to the reset trigger program is sent to the character device node, so that the interrupt handler sends the target signal to the reset trigger program according to the program identifier in the character device node. The character device node is created by the interrupt handler, and the character device node runs in the user state of the processor.

[0079] In one implementation, if the character device node does not have a program identifier corresponding to the reset trigger program, the interrupt processing program also sends a hardware restart signal to the processor, so that the processor executes a hardware restart process.

[0080] Among them, after the reset trigger program calls the reset instruction, the reset trigger program monitors whether the target sub-process in the reset process is executed within a first time period; if the target sub-process is not executed within the first time period, a hardware restart signal is sent to the processor to enable the processor to execute the hardware restart process.

[0081] In one implementation, the reset process includes:

[0082] Sending a warning message to an operating system corresponding to the processor, wherein the warning message is at least used to prompt data saving;

[0083] Sending a stop signal to a process in a running state through the operating system, wherein the stop signal is used to instruct the process to exit;

[0084] Unmounting the file system corresponding to the operating system;

[0085] A hardware restart signal is sent to the processor, so that the processor executes a hardware restart process.

[0086] It should be noted that the specific implementation of the processor and the field programmable gate array in this embodiment can refer to the corresponding content in the previous text and will not be described in detail here.

[0087] based on Figure 2 The system architecture of the server and the board shown in the figure, the technical solution of this embodiment is described in detail below:

[0088] First, the technical solution of this application aims at the problem of high hardware complexity in implementing reset control in the previous text, and proposes the following solution:

[0089] (1) A processing module is added inside the FPGA of the board. When it detects that the PERST pin of the server is pulled low for a specified time (such as the target duration mentioned above), an interrupt signal is triggered to CPU2, thereby associating the server reset with CPU2 of the board.

[0090] (2) Add an interrupt processing module (i.e., the interrupt handling program and reset trigger program mentioned above) on the CPU2 side. When receiving the interrupt signal sent by the FPGA, the interrupt processing module can call the reboot command (i.e., the reset instruction mentioned above) to exit and reset the entire subsystem of CPU2 normally.

[0091] It can be seen that the technical solution of this application has the following advantages:

[0092] 1) The subsystem of the board can be associated with the reset of the server without the help of a hardware reset circuit, thereby achieving the purpose of resetting the board while resetting the server, reducing the complexity and cost of hardware design.

[0093] 2) The server reset can notify the running process on the board to exit normally, and then reset the board after the process exits normally to avoid damage to the board data.

[0094] like Figure 5 As shown in FIG. 1 , it is an overall flow chart of adding a reset interrupt trigger in this embodiment, and the specific implementation is divided into the following three parts:

[0095] 1. In the FPGA of the board, add a module to continuously detect and process the PERST pin. After CPU1 executes the reboot instruction, it pulls down the PERST pin in the PCIe end point through the PCIe root point. Once the PERST pin is pulled down for 1 second, the FPGA triggers an interrupt signal to CPU2. Figure 6 As shown in , it is a flow chart of implementing reset detection through a processing module in FPGA.

[0096] 2. Add an interrupt monitoring module (i.e. the interrupt handler mentioned above) in the kernel state of CPU2 to monitor the interrupt signal triggered by FPGA after detecting that PERST is pulled low for 1s.

[0097] First, the interrupt handler creates a user-mode character device node in the driver to obtain the process number of the user-mode APP (i.e., the reset trigger program mentioned above), that is, to bind the file operation structure. Then, the interrupt handler sends a custom signal (i.e., the target signal mentioned above) to the user-mode APP based on the process number of the user-mode APP obtained from the character device node. If, after sending the custom signal to the user-mode APP, the user-mode APP program fails to exit and reset the program on CPU2 for more than 10s (application reset timeout period), or the interrupt handler does not obtain the process number of the user-mode APP from the character device node, it directly triggers a kernel reset (it will not notify the program on CPU2 to exit). Specifically, the interrupt handler sends a hardware restart signal to CPU2, so that CPU2 executes the hardware restart process. Processing flow of the interrupt handler Figure 7 as shown in .

[0098] 3. Add a user-mode APP on CPU2. The user-mode APP passes the user-mode APP process number to the kernel interrupt handler through the character device node (created by the kernel interrupt handler), and then registers a signal processing function for the custom signal (i.e. the target signal in the previous article) (i.e. the signal processing function in the reset trigger program in the previous article). The function content continuously monitors whether the custom signal is received. Once the custom signal is received, the reboot command (i.e. the reset instruction in the previous article) is called through the operating system to trigger the CPU2 subsystem program to exit and reset normally. The reboot command will perform the following 4 steps:

[0099] ① Send a warning message to inform that the operating system is about to restart and ask all users to save their work and log out;

[0100] ②The operating system sends a signal to all running processes to notify them that the system is about to restart;

[0101] ③ The file system is unmounted and unmounted to ensure the consistency and data integrity of the file system;

[0102] ④The operating system sends a signal to the CPU, triggering a hardware-level restart, namely a kernel reset.

[0103] Among them, the processing flow of user-mode APP is as follows Figure 8 As shown,

[0104] In summary, the technical solution of this application has the following key technologies:

[0105] 1. Add a mechanism in the FPGA on the board side to convert the PERST pin low signal sent by the server into an interrupt to CPU2, associate the server reset with the board CPU2, and replace the hardware reset circuit, which helps to reduce the complexity of hardware design and hardware cost.

[0106] 2. Add an interrupt monitoring kernel driver (i.e. the interrupt handler mentioned above) and a user-mode APP program (i.e. the reset trigger program mentioned above) in the CPU2 on the board side to notify the CPU2 subsystem to exit and reset normally, which helps to improve the system robustness and make the data on CPU2 more secure.

[0107] In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

[0108] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described in the above description according to function. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0109] The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

[0110] The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A reset control method, comprising: On a field programmable gate array in a first device, using a connection bus between the first device and a second device, monitoring whether the second device performs a reset process; In response to the second device executing the reset process, an interrupt signal is sent to the processor in the first device, where the interrupt signal is used to instruct the processor to execute the reset process.

2. The method according to claim 1, monitoring whether the second device performs a reset process, comprises: monitoring a target pin in the connection bus; If the pin level of the target pin meets the reset condition, it is determined that the second device executes a reset process.

3. The method according to claim 2, wherein the reset condition comprises: The duration for which the pin level of the target pin is pulled down to the target level value reaches the target duration.

4. According to the method of claim 1 or 2, the processor is provided with an interrupt handling program and a reset triggering program; the interrupt handling program runs in the kernel state of the processor, and the reset triggering program runs in the user state of the processor; in, The interrupt handling program is used to detect whether the processor receives the interrupt signal sent by the field programmable gate array, and, in the case of detecting that the processor receives the interrupt signal sent by the field programmable gate array, send a target signal to the reset trigger program; The reset trigger program is used to call a reset instruction in response to the target signal, and the reset instruction is used to instruct the processor to execute a reset process.

5. According to the method described in claim 4, after the reset trigger program starts running, the program identifier corresponding to the reset trigger program is sent to the character device node, so that the interrupt handler sends the target signal to the reset trigger program according to the program identifier in the character device node. 6 . The method according to claim 5 , wherein the character device node is created by the interrupt handler, and the character device node runs in the user mode of the processor.

7. The method according to claim 5, if the character device node does not have a program identifier corresponding to the reset trigger program, the method further comprises: A hardware restart signal is sent to the processor, so that the processor executes a hardware restart process.

8. The method according to claim 4, after the reset trigger program calls the reset instruction, the method further comprises: Monitoring whether the target sub-process in the reset process is executed and completed within the first time period; If the target sub-process is not executed to completion within the first time period, a hardware restart signal is sent to the processor, so that the processor executes a hardware restart process.

9. The method according to claim 1, wherein the reset process comprises: Sending a warning message to an operating system corresponding to the processor, wherein the warning message is at least used to prompt data saving; Sending a stop signal to a process in a running state through the operating system, wherein the stop signal is used to instruct the process to exit; Unmounting the file system corresponding to the operating system; A hardware restart signal is sent to the processor, so that the processor executes a hardware restart process.

10. An electronic device, as a first device, comprising: processors and field programmable gate arrays; Among them, the field programmable gate array is used to: utilize the connection bus between the first device and the second device to monitor whether the second device executes the reset process; in response to the second device executing the reset process, send an interrupt signal to the processor, and the interrupt signal is used to instruct the processor to execute the reset process.

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