A fault injection method, system, device and medium of an FPGA chip

Abstract

The application relates to the technical field of fault attack, and discloses a fault injection method, system, device and medium for an FPGA chip. The method comprises the following steps: acquiring actual power consumption data of the FPGA chip at a time sequence in a process in which the FPGA chip runs a preset encryption algorithm; simulating the process in which the FPGA chip runs the preset encryption algorithm to obtain simulation power consumption data of the FPGA chip at the time sequence; respectively performing multiplication operation and accumulation operation on data at corresponding moments in the actual power consumption data and the simulation power consumption data, and acquiring a moment corresponding to actual power consumption data and simulation power consumption data when values obtained through the multiplication operation and the accumulation operation exceed a preset threshold value as a fault injection moment of the FPGA chip; and generating a voltage drop in the FPGA chip at the fault injection moment to complete fault injection of the FPGA chip, so that the fault injection can be realized without changing an original circuit of the FPGA or triggering a signal.

Description

Technical Field

[0001] The present invention relates to the field of fault attack technology, and in particular to a fault injection method, system, device and medium for an FPGA chip. Background Art

[0002] Currently, cryptographic algorithms are widely used, playing a vital role in ensuring network communication security, protecting the integrity of data storage, supporting the development of blockchain technology, and ensuring the security of electronic payments. Due to the reconfigurability and parallel computing capabilities of field-programmable gate arrays (FPGAs), FPGAs are often used in embedded systems to implement hardware acceleration and custom logic for various algorithms, including cryptographic algorithms. However, cryptographic algorithms implemented in FPGAs are vulnerable to malicious attacks. Fault injection attacks (FIAs) are an attack method that can assess the security of cryptographic algorithms implemented in FPGAs by injecting faults into FPGA chips. Traditional fault injection methods include voltage or clock glitch attacks, electromagnetic or laser attacks, and temperature attacks.

[0003] Among them, voltage glitches and clock glitches require changes to the original circuitry of the device (i.e., the FPGA chip), and other attack methods also require a certain degree of physical access to the device. For example, during the fault injection process, in order to locate the fault injection interval, the target device must first provide a signal as a trigger. After capturing this signal, it is synchronized with the power consumption / electromagnetic trajectory to accurately locate the encryption and decryption interval and achieve fault injection. However, only the devices used in experiments have dedicated trigger pins reserved. In actual devices, attackers need to search for available trigger signals. If the attacker does not have physical access to the target device, the available trigger signal may not exist, resulting in the failure of fault injection. Summary of the Invention

[0004] The purpose of the present invention is to provide a fault injection method, system, device and medium for an FPGA chip, which can achieve fault injection without changing the original circuit of the FPGA and without requiring a trigger signal.

[0005] To solve the above technical problems, an embodiment of the present invention provides a fault injection method for an FPGA chip, comprising the following steps:

[0006] Obtain the actual power consumption data of the FPGA chip in the timing process when the FPGA chip runs the preset encryption algorithm;

[0007] Simulate the process of running a preset encryption algorithm on the FPGA chip to obtain the simulated power consumption data of the FPGA chip in timing;

[0008] Perform multiplication and accumulation operations on the data at corresponding moments in the actual power consumption data and the simulated power consumption data, respectively, and obtain the time corresponding to the actual power consumption data and the simulated power consumption data when the value obtained by the multiplication and accumulation operations exceeds a preset threshold value as the fault injection time of the FPGA chip;

[0009] At the moment of fault injection, a voltage drop is generated in the FPGA chip to complete the fault injection of the FPGA chip.

[0010] In some optional embodiments, simulating a process of running a preset encryption algorithm on an FPGA chip to obtain simulated power consumption data of the FPGA chip in timing includes:

[0011] Get the total clock consumed by the FPGA chip to run the preset encryption algorithm;

[0012] According to the preset ideal clock for injecting faults into the FPGA chip, all clocks before the ideal clock in the total clock are obtained as the target clock;

[0013] The process of running a preset encryption algorithm on the FPGA chip is simulated to obtain the simulated power consumption data of the FPGA chip within the target clock.

[0014] In some optional embodiments, before performing multiplication and accumulation operations on the actual power consumption data and the data at corresponding moments in the simulated power consumption data, the method further includes:

[0015] The simulated power consumption data is downsampled to the same sampling frequency as the actual power consumption data.

[0016] In some optional embodiments, obtaining actual power consumption data in a timing manner during the process of the FPGA chip running a preset encryption algorithm includes:

[0017] While the FPGA chip is running a preset encryption algorithm, changes in the combinational logic delay within the FPGA chip are obtained;

[0018] The change in the voltage drop of the FPGA chip is determined by the change in the combinational logic delay in the FPGA chip, and the actual power consumption data of the FPGA chip is determined by the change in the voltage drop.

[0019] In some optional embodiments, generating a voltage drop within the FPGA chip to complete fault injection into the FPGA chip includes:

[0020] At the moment of fault injection, the operating voltage of each working circuit of the FPGA chip is reduced to below the preset operating voltage, and the delay of each working circuit is increased, so that each working circuit of the FPGA chip does not meet the preset timing, thereby completing the fault injection of the FPGA chip.

[0021] In some optional embodiments, reducing the operating voltage of each working circuit of the FPGA chip to below a preset operating voltage includes:

[0022] The ring oscillator is used to reduce the operating voltage of each working circuit of the FPGA chip to below the preset operating voltage.

[0023] In some optional embodiments, there are multiple ring oscillators, and generating a voltage drop within the FPGA chip includes:

[0024] By adjusting the number of ring oscillators enabled simultaneously, the speed, holding time, and range of the voltage drop can be adjusted.

[0025] An embodiment of the present invention further provides a fault injection system for an FPGA chip, comprising:

[0026] The first data acquisition module is used to obtain the actual power consumption data of the FPGA chip in a timing manner during the process of the FPGA chip running a preset encryption algorithm;

[0027] The second data acquisition module is used to simulate the process of running a preset encryption algorithm on the FPGA chip to obtain the simulated power consumption data of the FPGA chip in time sequence;

[0028] A data processing module is used to perform multiplication and accumulation operations on the data at corresponding moments in the actual power consumption data and the simulated power consumption data, and obtain the time corresponding to the actual power consumption data and the simulated power consumption data when the value obtained by the multiplication and accumulation operations exceeds a preset threshold value as the fault injection time of the FPGA chip;

[0029] The fault injection module is used to generate a voltage drop in the FPGA chip at the time of fault injection to complete the fault injection of the FPGA chip.

[0030] An embodiment of the present invention also provides a computer device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the above-mentioned FPGA chip fault injection method.

[0031] An embodiment of the present invention further provides a computer-readable storage medium storing a computer program, wherein the computer program implements the above-mentioned fault injection method for the FPGA chip when executed by a processor.

[0032] The fault injection method for FPGA chips provided by the present invention has at least the following beneficial effects:

[0033] By obtaining the actual power consumption data of the FPGA chip in the process of running the preset encryption algorithm, and simulating the process of the FPGA chip running the preset encryption algorithm, the simulated power consumption data of the FPGA chip in the time sequence is obtained, and the fault injection time of the FPGA chip is determined by combining the actual power consumption data and the simulated power consumption data, that is, multiplication and accumulation operations are performed on the data at the corresponding time in the actual power consumption data and the simulated power consumption data respectively. If the value obtained by the multiplication and accumulation operations exceeds the preset threshold, it means that the correlation between the actual power consumption data and the simulated power consumption data at that moment is the highest, and the success rate of injecting the fault at this time is the highest. Therefore, the present invention does not need to obtain any physical permissions of the FPGA chip (that is, it does not need to obtain the FPGA chip to give a trigger signal), but instead indirectly obtains the trigger signal by processing the power consumption information, so as to determine the fault injection time of the FPGA chip, which has stronger concealment.

[0034] Furthermore, since all working circuits in the FPGA chip need to meet the setup time in terms of timing, the present invention generates a voltage drop in the FPGA chip at the time of fault injection, causing the operating voltage of the circuit of the FPGA chip to drop, so that the circuit no longer meets the timing requirements for its normal operation, thereby completing the fault injection into the circuit (i.e., the FPGA chip).

[0035] Furthermore, this solution does not change the original circuit structure of the FPGA chip and is not easy to detect. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] One or more embodiments are exemplarily described by the figures in the corresponding drawings, and these exemplified descriptions do not constitute limitations on the embodiments.

[0037] Figure 1 This is a process of a fault injection method for an FPGA chip provided according to an embodiment of the present invention. Figure 1 ;

[0038] Figure 2 is a schematic diagram of a side information collection module provided according to an embodiment of the present invention;

[0039] Figure 3 is a waveform diagram of actual power consumption data provided according to an embodiment of the present invention;

[0040] Figure 4 is a schematic diagram of power consumption data processing provided according to an embodiment of the present invention;

[0041] Figure 5 is a schematic diagram of a voltage drop provided according to an embodiment of the present invention;

[0042] Figure 6 This is a process of a fault injection method for an FPGA chip provided according to an embodiment of the present invention. Figure 2 . DETAILED DESCRIPTION

[0043] To make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be understood by those skilled in the art that in the embodiments of the present invention, many technical details are provided to enable the reader to better understand the present invention. However, even without these technical details and the various changes and modifications based on the following embodiments, the technical solutions claimed in the present invention can be implemented. The division of the following embodiments is for convenience of description and should not constitute any limitation on the specific implementation of the present invention. The various embodiments can be combined with each other and referenced to each other under the premise that there is no contradiction.

[0044] One embodiment of the present invention relates to a fault injection method for an FPGA chip. The implementation details of the fault injection method for the FPGA chip of this embodiment are specifically described below. The following content is only the implementation details provided for ease of understanding and is not necessary for implementing this solution.

[0045] The specific process of the fault injection method for the FPGA chip of this embodiment can be as follows: Figure 1 Shown, including:

[0046] Step 101: Acquire actual power consumption data of the FPGA chip in timing when the FPGA chip runs a preset encryption algorithm.

[0047] Specifically, when the FPGA chip runs the preset encryption algorithm, the actual power consumption data in the timing can reveal the running status and operation mode of the FPGA chip. In a fault injection attack, the attacker may use the actual power consumption data in the timing to locate the attack time.

[0048] In the specific implementation, a side information collection module is deployed to collect the actual power consumption data inside the FPGA chip in real time. The side information collection module is composed of a hardware Trojan that can reflect power consumption leakage. The hardware Trojan can be used to obtain changes in the combinational logic delay in the FPGA chip. Through the changes in the combinational logic delay, the actual power consumption data of the FPGA chip can be obtained.

[0049] The working principle of the hardware Trojan is as follows: In a hardware circuit, a power distribution network converts and distributes power from a power source to various circuit components. High switching activity often causes transient voltage drops in the FPGA chip's power distribution network, and this voltage drop reflects power consumption. This voltage drop depends on the steady-state current consumption and the short transients caused by the switching logic on the FPGA chip. In a typical complementary metal-oxide-semiconductor (CMOS) circuit, the combinational logic delay can be modeled as inversely proportional to the voltage supplied to each gate. Therefore, changes in the combinational logic delay reflect the voltage drop, which in turn reflects the circuit's power consumption and switching activity. This correlation between combinational logic delay and power consumption can be used to build an on-chip power monitor on the FPGA chip. A circuit is constructed to measure the combinational path delay and use this delay to estimate the power consumption of other modules on the FPGA chip. For example, a ring oscillator and a time-to-digital converter can be used to build a voltage meter on the FPGA chip. The ring oscillator-based design is easier to implement and more versatile, while the time-to-digital converter has a higher sampling resolution.

[0050] In one example, the design of the above-mentioned side information collection module is as follows: Figure 2 As shown in the figure, the entire system is divided into four parts: a delay chain, a latch, a counter, and a register. In the delay chain, the clock signal propagates through a series of buffers. Since the delay of these buffers depends on the supply voltage, the buffers can be monitored as a surrogate for the supply voltage. The delay line is tapped by adding latches between these buffers. The latches are enabled with the same clock signal connected to the start of the delay line, thus showing how far the clock can propagate through the buffers during the latch's enable time, which is half a clock cycle. The tapped data, after passing through a counter composed of combinational logic, outputs the number of 1s in the data chain and is stored in a register. When any other circuit on the same PDN becomes active, power is consumed, causing a voltage drop, slowing down the delay line's buffers and reducing the value in the TDC output register. To save some sensor area, typically only the last bit of the buffer chain is tapped, as the buffer's delay does not change enough to affect the entire delay line. Therefore, only a portion of the delay chain is observable; the other portion is the initial delay. In FPGA, the observable part is usually implemented using carry chain primitives, which provides the best resolution, while the initial delay is based on lookup tables (LUTs) and flip-flops with smaller area overhead but higher latency. Finally, the power consumption waveform collected by the module can be as follows Figure 3 shown.

[0051] Step 102 , simulating the process of running a preset encryption algorithm on the FPGA chip to obtain simulated power consumption data of the FPGA chip in timing.

[0052] In a specific implementation, the total clock consumed by the FPGA chip running the preset encryption algorithm is obtained. Based on a preset ideal clock for injecting a fault into the FPGA chip, all clocks in the total clock that precede the ideal clock are obtained as the target clock. The process of the FPGA chip running the preset encryption algorithm is simulated to obtain the simulated power consumption data of the FPGA chip within the target clock. For example, if the total clock consumed by the FPGA chip running the preset encryption algorithm is four, and the preset ideal clock for injecting a fault into the FPGA chip is the third clock, in actual operation, since it is unknown when the preset encryption algorithm begins running, it is naturally unknown when the third clock of the preset encryption algorithm occurs. Therefore, all waveforms before the third clock are obtained through simulation in advance, namely the simulated power consumption data of the FPGA chip within the target clock.

[0053] In one example, the simulated power consumption data of the FPGA chip within the target clock is obtained in the following manner: first, the simulation waveform of the FPGA chip running the preset encryption algorithm is obtained, and the (NM, N) time period is intercepted in the simulation waveform as the target time window, where N is the preset ideal time to inject a fault into the FPGA chip, and M is the length of the target time window. The larger M is, the more resources are consumed in the subsequent correlation coefficient calculation, and the accuracy of the subsequent Pearson correlation coefficient calculation is also higher, making it easier to obtain the correct fault injection moment of the FPGA chip. Figure 4 As shown in the figure, (a) represents the waveform of the simulated power consumption data, (b) represents the waveform of the actual power consumption data, the dotted box part is the waveform corresponding to the target time window, and (c) represents the waveform used to reflect the degree of correlation between the actual power consumption data and the simulated power consumption data at the corresponding moment when calculating the Pearson correlation coefficient between the simulated power consumption data corresponding to the target time window and the actual power consumption data at each moment.

[0054] In step 103, multiplication and accumulation operations are performed on the data at corresponding moments in the actual power consumption data and the simulated power consumption data, and the moments corresponding to the actual power consumption data and the simulated power consumption data used when the values ​​obtained by the multiplication and accumulation operations exceed the preset threshold are obtained as the fault injection moment of the FPGA chip.

[0055] Specifically, the time corresponding to the data whose correlation degree exceeds the preset threshold between the actual power consumption data and the above-mentioned simulated power consumption data is obtained, and multiplication and accumulation operations are performed on the actual power consumption data and the data at the corresponding time in the simulated power consumption data, respectively. This is equivalent to calculating the Pearson correlation coefficient between the simulated power consumption data corresponding to the target time window and the actual power consumption data at each moment. When the Pearson correlation coefficient exceeds the preset threshold, the moment corresponding to the simulated power consumption data and the actual power consumption data is the fault injection moment of the FPGA chip.

[0056] It is understandable that the level of simulation accuracy in the simulation software used to simulate the FPGA chip running the preset encryption algorithm process can be determined according to the attacker's understanding of the FPGA chip. If the attacker knows the process of the FPGA chip in advance, he can select the corresponding process library file to simulate it.

[0057] In one example, when simulating the process of running a preset encryption algorithm on an FPGA chip, the process of running the preset encryption algorithm on the FPGA chip within a target time window formed by all moments before an ideal moment can be simulated to directly obtain the simulated power consumption data corresponding to the above target time window.

[0058] In one example, before obtaining the moment corresponding to the data in the actual power consumption data and the simulated power consumption data whose correlation degree exceeds a preset threshold, it is first necessary to downsample the obtained simulated power consumption data of the FPGA chip in timing to a sampling frequency consistent with the actual power consumption data, and then store it in the on-chip register for subsequent calculations to ensure its accuracy.

[0059] In the specific implementation, a shift register is used to store the actual power consumption data in the most recent period. The depth of the shift register is equal to the length of the simulated power consumption data. At each new sampling moment, the actual power consumption data of the current moment is stored in the lowest bit of the shift register. At each moment, the Pearson correlation coefficient between the actual power consumption data and the simulated power consumption data is recalculated, and a reasonable threshold is set to determine whether the correlation value at that moment exceeds the threshold. If it exceeds the threshold, it means that the moment is the fault injection moment of the FPGA chip, and the fault injection trigger signal of one clock cycle is raised. If it does not exceed the threshold, wait for the next moment to update the actual power consumption data in the shift register.

[0060] Step 104 : At the time of fault injection, a voltage drop is generated in the FPGA chip to complete the fault injection of the FPGA chip.

[0061] Specifically, the aforementioned hardware Trojan consists of multiple ring oscillators, allowing it to generate a voltage drop within the FPGA chip during fault injection. The speed, duration, and range of the voltage drop are determined by the ring oscillator's oscillation parameters, which can be adjusted by changing the ring oscillator's oscillation parameters. Reducing the enable signal's fanout value can speed up the voltage drop, while increasing the number of ring oscillators can increase the voltage drop amplitude, but this also increases resource consumption. The voltage drop duration is controlled by the enable signal's pull-up time.

[0062] In the specific implementation, when the trigger signal is pulled high, a single or multiple clock enable signal is generated according to the preset parameters. The enable signal drives the ring oscillator to perform 0-1-0 conversion. If the voltage drop speed is accelerated, the enable signal is stored in N registers once. In the next clock, each register drives M / N ROs, where M is the number of ring counters. The actual voltage drop is Figure 5 As shown, the voltage signal passes through a 30dB amplifier, the number of ring counters is 10,000, there is no fan-out reduction process, and the enable clock maintains one clock.

[0063] In one example, after completing the fault injection of the FPGA chip, the following method can be used to verify whether the fault injection of the FPGA chip is successful: assuming that the preset encryption algorithm is a digital signature verification algorithm, the digital signature verification algorithm is run in the FPGA chip, and the first hash value obtained by decrypting the digital signature of the digital signature verification algorithm and the original data of the digital signature verification algorithm, and the second hash value obtained by encrypting the original data of the digital signature verification algorithm through the hash algorithm are verified to be the same. If the first hash value is different from the second hash value, it is confirmed that the fault injection of the FPGA chip is successful. Otherwise, the fault injection of the FPGA chip fails. At this time, the process of fault injection of the FPGA chip of this embodiment can be as follows: Figure 6 shown.

[0064] In this embodiment, actual power consumption data of the FPGA chip during execution of a preset encryption algorithm is obtained, and the FPGA chip's execution of the preset encryption algorithm is simulated to obtain the simulated power consumption data of the FPGA chip during execution. This data is then combined with the actual power consumption data to determine the timing of fault injection into the FPGA chip. This method does not require any physical access to the FPGA chip to determine the timing of fault injection into the FPGA chip. However, when the operating voltage drops, circuit delays increase, potentially causing the circuit to no longer meet timing requirements. Therefore, a fault injection attack can be performed on the FPGA chip by generating a voltage drop within the FPGA chip at the time of fault injection. Furthermore, this solution does not alter the original circuit structure of the FPGA chip, making it difficult to detect.

[0065] The steps of the various methods above are divided only for the purpose of clear description. When implemented, they can be combined into one step or some steps can be split and decomposed into multiple steps. As long as they include the same logical relationship, they are within the scope of protection of the present invention. Adding insignificant modifications or introducing insignificant designs to the algorithm or process without changing the core design of the algorithm and process are all within the scope of protection of the invention.

[0066] Another embodiment of the present invention relates to a fault injection system for an FPGA chip. The implementation details of the FPGA chip fault injection system of this embodiment are described in detail below. The following content is only provided for ease of understanding and is not required for implementing this solution. The FPGA chip fault injection system of this embodiment includes:

[0067] The first data acquisition module is used to obtain the actual power consumption data of the FPGA chip in a timing manner during the process of the FPGA chip running a preset encryption algorithm;

[0068] The second data acquisition module is used to simulate the process of running a preset encryption algorithm on the FPGA chip to obtain the simulated power consumption data of the FPGA chip in time sequence;

[0069] A data processing module is used to perform multiplication and accumulation operations on the data at corresponding moments in the actual power consumption data and the simulated power consumption data, and obtain the time corresponding to the actual power consumption data and the simulated power consumption data when the value obtained by the multiplication and accumulation operations exceeds a preset threshold value as the fault injection time of the FPGA chip;

[0070] The fault injection module is used to generate a voltage drop in the FPGA chip at the time of fault injection to complete the fault injection of the FPGA chip.

[0071] It is not difficult to find that this embodiment is a system embodiment corresponding to the above-mentioned method embodiment, and this embodiment can be implemented in conjunction with the above-mentioned method embodiment. The relevant technical details and technical effects mentioned in the above-mentioned embodiment are still valid in this embodiment, and to reduce repetition, they are not repeated here. Accordingly, the relevant technical details mentioned in this embodiment can also be applied to the above-mentioned embodiment.

[0072] It is worth noting that all modules involved in this embodiment are logical modules. In actual applications, a logical unit can be a physical unit, a part of a physical unit, or a combination of multiple physical units. In addition, to highlight the innovations of the present invention, this embodiment does not include units that are not closely related to solving the technical problems proposed by the present invention. However, this does not mean that other units do not exist in this embodiment.

[0073] Another embodiment of the present invention relates to a computer device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the fault injection method for the FPGA chip in the above-mentioned embodiments.

[0074] The memory and processor are connected using a bus, which can include any number of interconnected buses and bridges. The bus connects various circuits of one or more processors and memories. The bus can also connect various other circuits such as peripheral devices, voltage regulators, and power management circuits. These are all well known in the art and are therefore not described further herein. The bus interface provides an interface between the bus and the transceiver. The transceiver can be a single component or multiple components, such as multiple receivers and transmitters, providing a unit for communicating with various other devices over a transmission medium. Data processed by the processor is transmitted over a wireless medium via an antenna. Furthermore, the antenna receives data and transmits it to the processor.

[0075] The processor is responsible for managing the bus and general processing, and can also provide various functions, including timing, peripheral interfaces, voltage regulation, power management, and other control functions. Memory can be used to store data used by the processor when performing operations.

[0076] Another embodiment of the present invention relates to a computer-readable storage medium storing a computer program, which implements the above method embodiment when executed by a processor.

[0077] That is, those skilled in the art will understand that all or part of the steps in the above-described method embodiments can be implemented by instructing related hardware through a program, which is stored in a storage medium and includes a number of instructions for causing a device (such as a microcontroller or chip) or a processor to execute all or part of the steps in the method embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as a USB flash drive, a mobile hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk.

[0078] Those skilled in the art will appreciate that the above embodiments are specific embodiments for implementing the present invention, and that in actual applications, various changes may be made thereto in form and detail without departing from the spirit and scope of the present invention.

Claims

1. A fault injection method for an FPGA chip, characterized in that: The method comprises: Obtain the actual power consumption data of the FPGA chip in the timing process when the FPGA chip runs the preset encryption algorithm; Simulate the process of running a preset encryption algorithm on the FPGA chip to obtain the simulated power consumption data of the FPGA chip in timing; Perform multiplication and accumulation operations on the data at corresponding moments in the actual power consumption data and the simulated power consumption data, respectively, and obtain the time corresponding to the actual power consumption data and the simulated power consumption data when the value obtained by the multiplication and accumulation operations exceeds a preset threshold value as the fault injection time of the FPGA chip; At the moment of fault injection, a voltage drop is generated in the FPGA chip to complete the fault injection of the FPGA chip; The step of generating a voltage drop within the FPGA chip to inject faults into the FPGA chip includes: At the moment of fault injection, the operating voltage of each working circuit of the FPGA chip is reduced to below the preset operating voltage, and the delay of each working circuit is increased, so that each working circuit of the FPGA chip does not meet the preset timing, thereby completing the fault injection of the FPGA chip.

2. The fault injection method for an FPGA chip according to claim 1, wherein: The process of simulating the FPGA chip running the preset encryption algorithm to obtain the simulated power consumption data of the FPGA chip in timing includes: Get the total clock consumed by the FPGA chip to run the preset encryption algorithm; According to the preset ideal clock for injecting faults into the FPGA chip, all clocks before the ideal clock in the total clock are obtained as the target clock; The process of running a preset encryption algorithm on the FPGA chip is simulated to obtain the simulated power consumption data of the FPGA chip within the target clock.

3. The fault injection method for an FPGA chip according to claim 2, wherein: Before performing multiplication and accumulation operations on the actual power consumption data and the data at corresponding moments in the simulated power consumption data, the method further includes: The simulated power consumption data is downsampled to the same sampling frequency as the actual power consumption data.

4. The fault injection method for an FPGA chip according to claim 1, wherein: The acquisition of actual power consumption data in a timing manner during the process of the FPGA chip running a preset encryption algorithm includes: While the FPGA chip is running a preset encryption algorithm, changes in the combinational logic delay within the FPGA chip are obtained; The change in the voltage drop of the FPGA chip is determined by the change in the combinational logic delay in the FPGA chip, and the actual power consumption data of the FPGA chip is determined by the change in the voltage drop.

5. The fault injection method for FPGA chip according to claim 1, characterized in that: The step of reducing the operating voltage of each working circuit of the FPGA chip to below a preset operating voltage includes: The ring oscillator is used to reduce the operating voltage of each working circuit of the FPGA chip to below the preset operating voltage.

6. The fault injection method for an FPGA chip according to claim 5, wherein: There are multiple ring oscillators, and the voltage drop generated in the FPGA chip includes: By adjusting the number of ring oscillators enabled simultaneously, the speed, holding time, and range of the voltage drop can be adjusted.

7. A fault injection system for an FPGA chip, characterized in that: The system comprises: The first data acquisition module is used to obtain the actual power consumption data of the FPGA chip in a timing manner during the process of the FPGA chip running a preset encryption algorithm; The second data acquisition module is used to simulate the process of running a preset encryption algorithm on the FPGA chip to obtain the simulated power consumption data of the FPGA chip in time sequence; A data processing module is used to perform multiplication and accumulation operations on the data at corresponding moments in the actual power consumption data and the simulated power consumption data, and obtain the time corresponding to the actual power consumption data and the simulated power consumption data when the value obtained by the multiplication and accumulation operations exceeds a preset threshold value as the fault injection time of the FPGA chip; A fault injection module is used to generate a voltage drop in the FPGA chip at the time of fault injection to complete the fault injection of the FPGA chip; Among them, the fault injection module is also used to reduce the operating voltage of each working circuit of the FPGA chip to below the preset operating voltage at the time of fault injection, increase the delay of each working circuit, and make each working circuit of the FPGA chip fail to meet the preset timing, so as to complete the fault injection of the FPGA chip.

8. A computer device, characterized in that: include: at least one processor; And, a memory communicatively connected to the at least one processor; wherein the memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the fault injection method for the FPGA chip as described in any one of claims 1 to 6.

9. A computer-readable storage medium storing a computer program, characterized in that: When the computer program is executed by a processor, the fault injection method for an FPGA chip according to any one of claims 1 to 6 is implemented.

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