FPGA prototype verification architecture and method of storage and calculation integrated intelligent calculation architecture

Abstract

The invention discloses an FPGA prototype verification architecture and method for a storage and calculation integrated intelligent calculation architecture, storage resources in an FPGA are used for simulating a storage function, a multiplier and an adder are used for simulating a calculation function, so that functionally equivalent in-storage calculation is realized, weight data stored in a calculation macro are stored in a memory of the FPGA, and the weight data are stored in a memory of the FPGA. Reading is carried out when data is needed, and calculation is divided into two schemes including a bit-by-bit calculation mode and a pure simulation calculation mode; the calculation delay of the analog calculation macro is determined, and correct coupling of the calculation speed of the analog calculation macro and the memory bandwidth is realized by adopting an equal-proportion frequency reduction method, so that the cache unit before the calculation macro completes one-time complete data caching within the time of single calculation of the calculation macro. According to the invention, the correctness of the chip function can be verified with low cost at the initial stage of design.

Description

Technical Field

[0001] The present invention relates to a storage-computing integrated system, and in particular to an FPGA prototype verification architecture and method for a storage-computing integrated intelligent computing architecture. Background Art

[0002] In recent years, artificial intelligence has developed rapidly. Artificial intelligence algorithms represented by neural networks are computationally and memory-intensive tasks. Most of the hardware resources in traditional CPUs (processors) are used for general control rather than computing, so they cannot provide sufficient computing power for the deployment of artificial intelligence algorithms. GPGPUs (general-purpose graphics processors) provide more computing resources at the expense of general control performance, providing an ideal deployment platform for artificial intelligence algorithms. However, GPGPUs still belong to the von Neumann architecture, and their computing and storage are separated. Therefore, in GPGPUs, data transfer between neural network layers must pass through memory. As the computing speed of GPGPUs increases, the time it takes to perform a calculation is getting smaller and smaller, which makes the proportion of the time spent on data exchange between computing units and memory continue to increase, even exceeding the computing time, forming a memory constraint. Memory constraints mean that memory access has become a bottleneck for computing. At this time, it is difficult to expand computing power simply by expanding the scale of computing units.

[0003] In order to eliminate memory constraints, it is necessary to reduce or avoid data movement between computing units and memory. However, in the von Neumann architecture where computing and storage are separated, memory cannot be bypassed by data. Therefore, it is necessary to go beyond the scope of the von Neumann architecture and explore a computing architecture that integrates storage and computing, that is, a storage-computing integrated architecture. In the storage-computing integrated architecture, the memory is given the function of computing, so the data generated by the memory can be calculated on the spot, thereby greatly reducing or even avoiding data movement during computing and eliminating memory constraints.

[0004] The current storage-computing integrated systems are mainly divided into three categories according to the type of in-memory computing devices they are based on: SRAM (static random access memory) storage-computing integrated, DRAM (dynamic random access memory) storage-computing integrated, and NVM (Non-Volatile Memory) storage-computing integrated. Due to the low storage density of SRAM, SRAM storage-computing integrated is difficult to achieve large capacity and is insufficient to support the deployment of large-scale artificial intelligence algorithms. DRAM has an extremely complex and closed hardware model and protocol stack, so only memory manufacturers have the conditions to conduct DRAM storage-computing integrated research. NVM, such as ReRAM, MRAM, PCM, and NOR-FLASH, not only has high storage density, but also has a simple and unified hardware model and strong universality. In addition, NVM also has the advantage of low power consumption. Therefore, how to design an NVM storage-computing integrated intelligent computing architecture to achieve an energy-efficient artificial intelligence algorithm deployment platform has become an open and valuable research topic. Summary of the invention

[0005] The purpose of the present invention is to propose an FPGA prototype verification architecture and method for a storage-computing integrated intelligent computing architecture.

[0006] The technical solution to achieve the purpose of the present invention is: an FPGA prototype verification architecture of a storage-computing integrated intelligent computing architecture, characterized in that it includes the following two parts:

[0007] (1) Use FPGA internal resources to simulate calculation macros:

[0008] Use the storage resources in the FPGA to simulate the "storage" function, and use multipliers and adders to simulate the "calculation" function, so as to achieve functionally equivalent "in-memory calculation". Store the weight data stored in the calculation macro in the memory of the FPGA and read it when the data is needed. There are two schemes for "calculation", namely bit-by-bit calculation mode and pure simulation calculation mode.

[0009] (2) Achieve the correct coupling between the computation speed of the analog computing macro and the memory bandwidth;

[0010] The calculation delay of the simulation calculation macro is determined, and the proportional frequency reduction method is used to achieve the correct coupling of the calculation speed of the simulation calculation macro and the memory bandwidth, so that the cache unit before the calculation macro can complete a complete data cache within the time of a single calculation of the calculation macro.

[0011] Furthermore, (1) using FPGA internal resources to simulate computational macros: using the storage resources in the FPGA to simulate the "storage" function, and using multipliers and adders to simulate the "calculation" function, thereby achieving functionally equivalent "in-memory computation", where:

[0012] If the calculation macro adopts the bit-by-bit calculation mode, logic gates are used to implement single-bit multiplication, adders are used to complete bit-by-bit accumulation, and finally shift adders are used to fuse the bit-by-bit accumulation results; if the calculation macro adopts the pure analog calculation mode, floating-point multipliers are used to simulate the multiplication function, and adder trees are used to simulate the accumulation function.

[0013] Furthermore, (2) the correct coupling between the computation speed of the analog computing macro and the memory bandwidth: the proportional frequency reduction method is adopted to achieve the correct coupling between the computation speed of the analog computing macro and the memory bandwidth, so that the cache unit before the computing macro completes a complete data cache within the time of a single computation of the computing macro. The specific method is as follows:

[0014] If the calculation macro adopts the bit-by-bit calculation mode, the minimum calculation speed is the bandwidth of the memory. The delay of the simulation calculation macro is greater than the delay of the calculation macro. The other modules except the calculation macro are proportionally reduced in frequency, so that the calculation of the simulation calculation macro is completed with the same number of cycles of other modules.

[0015] If the calculation macro adopts a purely analog calculation mode, the minimum calculation speed is determined by the maximum number of floating-point multipliers and memory bandwidth that the FPGA can bear. The memory bandwidth and the number of multipliers are compared, and the minimum value of the two is taken. The other modules except the calculation macro are proportionally reduced in frequency to adapt to the calculation cycle of the analog calculation macro.

[0016] Furthermore, the other modules except the calculation macro are proportionally down-clocked. The specific method is as follows:

[0017] Assume the original in-memory computing architecture chip main frequency f, the original computing macro computing cycle T, the computing macro bit line number L B , calculate the number of word lines of the macro L W , operation data width W data , the maximum data bit width of the FPGA internal RAM storage unit is W ram , the maximum number of multipliers that can be placed inside the FPGA is N mul , the bottleneck cycle number T of the virtual computing macro caused by the memory width limitation ram , the bottleneck cycle number T of the virtual computing macro caused by the limitation of the number of multipliers mul , the ratio of proportional frequency reduction is α, and the frequency of other modules except the calculation macro is reduced to f′ in the FPGA. Then the bottleneck cycle number of the virtual calculation macro caused by the memory bit width limitation is T ram The calculation formula is as follows:

[0018]

[0019] The bottleneck cycle number T of the virtual computing macro caused by the limitation of the number of multipliers mul The calculation formula is as follows:

[0020]

[0021] The calculation formula of the ratio α of equal-proportional frequency reduction is as follows:

[0022]

[0023] Then the frequency of other modules except the calculation macro is reduced to f′ in FPGA:

[0024] f′=αf.

[0025] A FPGA prototype verification method for a storage-computing integrated intelligent computing architecture is provided to realize FPGA prototype verification of the storage-computing integrated intelligent computing architecture based on an FPGA prototype verification architecture of the storage-computing integrated intelligent computing architecture.

[0026] Compared with the prior art, the present invention has the following significant advantages: it takes into account the simulation method of the storage-computing integrated computing unit on the FPGA, provides a complete FPGA simulation solution for the storage-computing integrated intelligent architecture, analyzes the computing bottleneck, and uses the proportional frequency reduction method to fully simulate the computing form of the real storage-computing integrated intelligent computing architecture, providing a high-quality and low-cost simulation verification method. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 It is a schematic diagram of the computing form of the in-memory computing unit.

[0028] Figure 2 It is a schematic diagram of the structure of the virtual computing macro inside the FPGA. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0030] In the NVM storage-computing integrated intelligent computing architecture (hereinafter referred to as the storage-computing integrated intelligent computing architecture), multiple computing units (Tiles) are usually combined into a computing array, and a special interconnection structure is provided in the computing array for communication between multiple computing units. When executing algorithm tasks, each Tile is responsible for performing a part of the matrix multiplication operation. Multiple Tiles can perform calculations in parallel and rely on the interconnection network to send input data and transmit calculation results, ultimately realizing the forward reasoning process of the neural network.

[0031] In the storage-computing integrated intelligent computing architecture of the present invention, the in-memory computing unit that performs key computing tasks is deployed inside the tile to perform multiplication and accumulation operations. The computing form is as follows: Figure 1As shown in the figure (the calculation form of the calculation macro determines all subsequent processing methods, so it is described clearly), the horizontal wire is called wordline, and the vertical wire is called bitline. Each wordline is connected to each bitline through a resistive memory cell. Assume that the resistance values ​​of the resistive memory cells in the first bitline are R1, R2, ..., R n , as the derivative of resistance, their conductances are G1, G2, ..., G n If the voltages V1, V2, ..., V n are applied to the word lines corresponding to these memory cells, then according to Kirchhoff's law, the i-th memory cell will transfer the current V i / R i or V i G i is transferred to the current bit line. Figure 1 As shown, the total current generated from the current bit line is equal to the sum of the currents stimulated by all memory cells in the current column, as shown in formula (1).

[0032]

[0033] Where V=[V1 V2 ... V n ] T , G=[G1 G2 ... G n ] T This shows that the computation mode of a single bit line in RRAM is a multiplication-accumulation or vector inner product operation. The computation macro combines multiple bit lines by its two-dimensional cross structure to implement matrix-vector multiplication, as shown in Equation (2), where G ij represents the conductance value of the memory cell at the intersection of the i-th bit line and the j-th word line in Xbar.

[0034]

[0035] If each vector in the matrix data is converted into voltage and input into Xbar in sequence, the matrix multiplication operation can be realized. Such a matrix multiplication accumulation calculation array cannot be integrated by FPGA. How to realize this in-memory calculation form using the internal digital circuit resources of FPGA while considering the correct coupling with peripheral modules is the key technical problem to be solved by the present invention.

[0036] The present invention aims to use FPGA to simulate the computing function of the in-memory computing array, perform functional simulation of the in-memory computing unit through the internal multiplier, adder, and memory of the FPGA, and discuss the coupling situation inside the entire computing tile, and propose a complete FPGA verification solution for the integrated storage and computing intelligent computing architecture.

[0037] The in-memory computing array (hereinafter referred to as computing macro) exhibits analog computing characteristics. The input data of all word lines must be ready before a calculation can be performed. In the early stage of the deployment of the storage-computing integrated intelligent computing architecture, it is necessary to first clarify the calculation delay of the computing macro, that is, when the input data of the word line of the in-memory computing array is all ready, the time required for the correct result to be output to the bit line. Therefore, the cache unit before the computing macro is designed to complete a complete data cache in the same time, realizing a matching pipeline design. How to simulate the function of the computing macro and how to correctly couple it with the cache unit are two core issues.

[0038] 1. First, determine the computing form of the in-memory computing unit, and complete the hardware pure digital circuit design of the analog computing macro and the design of the RAM memory based on the computing form.

[0039] In order to simulate the function of the calculation macro, the storage resources in the FPGA are used to simulate the "storage" function, and the multipliers and adders are used to simulate the "calculation" function, so as to achieve functionally equivalent "in-memory calculation". The weight data stored in the calculation macro is stored in the memory of the FPGA, and the data is read from it each time it is needed. There are two schemes for "calculation". If the in-memory calculation array uses the bit-by-bit calculation mode, that is, a single calculation only receives a single-bit digital signal from the word line, then it only needs to use a simple logic gate to implement single-bit multiplication, use an adder to complete the bit-by-bit accumulation, and finally use a shift adder to fuse the bit-by-bit accumulation results; if a pure analog calculation mode is used, the multi-bit digital signal at the input end needs to be converted into an analog signal after passing through the DAC before entering the calculation macro, then a floating-point multiplier is needed to simulate the multiplication function, and an addition tree is needed to simulate the accumulation function.

[0040] 2. Analyze the calculation bottleneck of the number of multipliers and the memory bandwidth bottleneck in the design, and reduce the frequency of the peripheral circuits proportionally to simulate the actual situation of the actual storage and computing integrated intelligent computing architecture.

[0041] In order to correctly couple with the cache unit, it is necessary to consider the calculation delay of the simulated calculation macro. The two schemes are still considered. If the bit-by-bit calculation mode is adopted, the calculation bottleneck lies in the bandwidth of the memory. In order to store large-scale weight data, the IP core of the RAM needs to be called, which brings bandwidth limitation. Because all weight data in the calculation macro are calculated on the spot, there is no data transfer. It may take many cycles to get the data required for a single operation of the calculation macro. This makes the delay of the virtual calculation macro in the FPGA greater than the delay of the actual calculation macro. In order to simulate the real situation, the other modules except the calculation macro are proportionally reduced in frequency. For example, the time taken by the virtual calculation macro in the FPGA to complete a multiplication and accumulation operation is twice that of the actual calculation macro. Then the clock frequency of other modules in the FPGA needs to be reduced to 1 / 2, so that the operation of the virtual calculation macro in the FPGA can be completed with the same number of cycles of other modules.

[0042] If a pure simulation computing mode is used, since the FPGA internal hardware resource area occupied by the floating-point multiplier is much larger than the single-bit multiplication logic gate, the resource limitation of the floating-point multiplier needs to be considered. The maximum number of floating-point multipliers that the FPGA can bear may result in a new computing bottleneck. During the FPGA simulation process, it is necessary to compare the FPGA internal memory bandwidth bottleneck and the multiplier number bottleneck in advance, take the smaller computing bottleneck as the new computing bottleneck, and further calculate the fastest computing time that the FPGA virtual computing macro can achieve. Similarly, the peripheral modules are proportionally reduced in frequency to adapt to the computing cycle of the simulation computing macro.

[0043] 3. The specific calculation steps are as follows:

[0044] First, input the following parameters: the original in-memory computing architecture chip frequency f, the original computing macro computing cycle T, the number of bit lines of the computing macro L B , calculate the number of word lines of the macro L W , operation data width W data , the maximum data bit width of the FPGA internal RAM storage unit is W ram , the maximum number of multipliers that can be placed inside the FPGA is N mul .

[0045] The following parameters are defined at the same time: The bottleneck cycle number T of the virtual computing macro caused by the memory width limitation ram , the bottleneck cycle number T of the virtual computing macro caused by the limitation of the number of multipliers mul , the ratio of proportional frequency reduction is α, and the frequency of other modules except the calculation macro is reduced to f′ in FPGA.

[0046] The bottleneck cycle number T of the virtual computing macro caused by the memory width limitation ram The calculation formula is as follows:

[0047]

[0048] The bottleneck cycle number T of the virtual computing macro caused by the limitation of the number of multipliers mul The calculation formula is as follows:

[0049]

[0050] The calculation formula of the ratio α of equal-proportional frequency reduction is as follows:

[0051]

[0052] Then the frequency of other modules except the calculation macro is reduced to f′ in FPGA:

[0053] f′=αf.

[0054] The present invention also proposes an FPGA prototype verification method for a storage-computing integrated intelligent computing architecture, and implements FPGA prototype verification of the storage-computing integrated intelligent computing architecture based on an FPGA prototype verification architecture of the storage-computing integrated intelligent computing architecture.

[0055] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0056] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. An FPGA prototype verification architecture of a storage-computing integrated intelligent computing architecture, characterized in that: It consists of the following two parts: (1) Use FPGA internal resources to simulate calculation macros: Use the storage resources in the FPGA to simulate the "storage" function, and use multipliers and adders to simulate the "calculation" function, so as to achieve functionally equivalent "in-memory calculation". The weight data stored in the calculation macro is stored in the memory of the FPGA, and read when the data is needed. There are two schemes for "calculation", namely bit-by-bit calculation mode and pure simulation calculation mode. (2) Achieve the correct coupling between the computation speed of the analog computing macro and the memory bandwidth; The calculation delay of the simulation calculation macro is determined, and the proportional frequency reduction method is used to achieve the correct coupling of the calculation speed of the simulation calculation macro and the memory bandwidth, so that the cache unit before the calculation macro can complete a complete data cache within the time of a single calculation of the calculation macro.

2. The FPGA prototype verification architecture of the storage-computing integrated intelligent computing architecture according to claim 1 is characterized in that: (1) Use FPGA internal resources to simulate calculation macros: Use the storage resources in the FPGA to simulate the "storage" function, and use multipliers and adders to simulate the "calculation" function, thereby achieving functionally equivalent "in-memory calculation", where: If the calculation macro adopts the bit-by-bit calculation mode, logic gates are used to implement single-bit multiplication, adders are used to complete bit-by-bit accumulation, and finally shift adders are used to fuse the bit-by-bit accumulation results; if the calculation macro adopts the pure analog calculation mode, floating-point multipliers are used to simulate the multiplication function, and adder trees are used to simulate the accumulation function.

3. The FPGA prototype verification architecture of the storage-computing-in-one intelligent computing architecture according to claim 1 is characterized in that: (2) Correct coupling between the computation speed of the analog computing macro and the memory bandwidth: The proportional frequency reduction method is used to achieve the correct coupling between the computation speed of the analog computing macro and the memory bandwidth, so that the cache unit before the computing macro completes a complete data cache within the time of a single computation of the computing macro. The specific method is as follows: If the calculation macro adopts the bit-by-bit calculation mode, the minimum calculation speed is the bandwidth of the memory. The delay of the simulation calculation macro is greater than the delay of the calculation macro. The other modules except the calculation macro are proportionally reduced in frequency, so that the calculation of the simulation calculation macro is completed with the same number of cycles of other modules. If the calculation macro adopts a purely analog calculation mode, the minimum calculation speed is determined by the maximum number of floating-point multipliers and memory bandwidth that the FPGA can bear. The memory bandwidth and the number of multipliers are compared, and the minimum value of the two is taken. The other modules except the calculation macro are proportionally reduced in frequency to adapt to the calculation cycle of the analog calculation macro.

4. The FPGA prototype verification architecture of the storage-computing-in-one intelligent computing architecture according to claim 3 is characterized in that: Reduce the frequency of other modules except the calculation macro in equal proportion. The specific method is as follows: Assume the original in-memory computing architecture chip main frequency f, the original computing macro computing cycle T, the computing macro bit line number L B , calculate the number of word lines of the macro L W , operation data width W data , the maximum data bit width of the FPGA internal RAM storage unit is W ram , the maximum number of multipliers that can be placed inside the FPGA is N mul , the bottleneck cycle number T of the virtual computing macro caused by the memory width limitation ram , the bottleneck cycle number T of the virtual computing macro caused by the limitation of the number of multipliers mul , the ratio of proportional frequency reduction is α, and the frequency of other modules except the calculation macro is reduced to f' in the FPGA. Then the bottleneck cycle number of the virtual calculation macro caused by the memory bit width limitation is T ram The calculation formula is as follows: The bottleneck cycle number T of the virtual computing macro caused by the limitation of the number of multipliers mul The calculation formula is as follows: The calculation formula of the ratio α of equal-proportional frequency reduction is as follows: Then the other modules except the calculation macro are down-converted to f' in the FPGA: f′=αf.

5. A FPGA prototype verification method for a storage-computing integrated intelligent computing architecture, characterized in that: Based on the FPGA prototype verification architecture of the storage-computing integrated intelligent computing architecture described in any one of claims 1-4, FPGA prototype verification of the storage-computing integrated intelligent computing architecture is implemented.

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