Integrated multi-beam feed network chip

Abstract

The invention relates to an integrated multi-beam feed network chip in the technical field of satellite communication, and aims to solve the problems that a traditional multi-beam feed network is high in cost and low in integration level. The integrated multi-beam feed network chip comprises a chip body, an input port, an output port and a signal layer. Based on the integrated multi-beam feed network chip provided by the invention, a novel feed network routing method is constructed by properly designing the routing of different beam signals, the number of signal layers is reduced to the greatest extent, and the design cost of the feed network is reduced. According to the invention, the problems of large scale, high cost and the like caused by the fact that a traditional multi-beam feed network spans a plurality of signal layers can be effectively solved, a complete technical solution is provided for chip-level design of the multi-beam feed network, and the requirements of low cost and miniaturization of a multi-beam phased array system can be met.

Description

Technical Field

[0001] The invention relates to the technical field of satellite communication technology, and in particular to an integrated multi-beam feeding network chip. Background Art

[0002] With the rapid development of phased array systems, the demand for low cost and miniaturization is increasing. On the one hand, since most of the feeding networks in phased array systems are directly connected in the PCB circuit board using multiple signal layers, in order to further meet the needs of large-scale phased arrays, the required feeding network is more complex. However, these complex feeding networks will increase the PCB area. Traditional multi-layer PCBs cannot meet the needs of low-cost design of phased arrays.

[0003] On the other hand, the traditional feed network occupies many layers when routing in multiple layers. For the requirements of miniaturization and integration, it is necessary to reduce the number of PCB routing layers. Reducing the PCB routing layers will lead to signal crossing in different signal layers. Therefore, the loss of the feed network crossing the alternate routing is the bottleneck restricting the performance of the feed network. In current phased array systems, it is widely required that the feed network loss be as small as possible to reduce the system design cost.

[0004] In summary, how to use large-scale multi-beam phased arrays to realize integrated multi-beam feeding network design with new architecture and new methods has become an important solution to the bottleneck problem of traditional multi-beam feeding networks. Summary of the invention

[0005] In order to solve the technical problems existing in the above-mentioned prior art, the purpose of the present invention is to provide an integrated multi-beam feed network chip, which has a highly integrated, low-cost multi-beam feed network architecture, and is connected to the chip to reduce the number of routing layers in the feed network, thereby realizing a low-cost, highly integrated design of the feed network.

[0006] To achieve the above-mentioned object of the invention, the present invention provides an integrated multi-beam feed network chip, including a chip body, and further comprising:

[0007] A plurality of input port groups, for receiving multi-beam input signals; each of the input port groups comprises a plurality of beam input ports;

[0008] A plurality of output ports for outputting multi-beam output signals; the number of the beam input ports and the number of the output ports in each of the input port groups is the same as the number of beams;

[0009] A plurality of sequentially connected signal layers, each of which is provided with a plurality of groups of beam synthesis circuits, the number of groups of the beam synthesis circuits being the same as the number of the beams; the beam synthesis circuits are used to perform beam synthesis between two of the same beam signals between the plurality of input port groups; the beam synthesis circuits of the first layer of the signal layers are respectively connected to the beam input ports, and the beam synthesis circuits of the last layer of the signal layers are respectively connected to the output ports;

[0010] The input port and the output port are arranged along the outer edge of the chip body.

[0011] According to a technical solution of the present invention, the chip body is rectangular, the output ports are distributed on the wide sides of the chip body, and the input ports are distributed on the long sides of the chip body.

[0012] According to a technical solution of the present invention, the plurality of input port groups and the plurality of output ports are evenly distributed along the outer edge of the chip body, and the beam input ports in two adjacent input port groups are symmetrically arranged according to their beam numbers.

[0013] According to a technical solution of the present invention, the beam numbering rule of the beam input port is as follows:

[0014] For the plurality of input port groups, group numbers are sequentially assigned in alphabetical order along the long side of the chip body, and the total number of group numbers is M;

[0015] The N beam input ports in each input port group are evenly distributed on two long sides of the chip body, and beam numbers are sequentially assigned to the N beam input ports in numerical order;

[0016] For any of the beam input ports, its beam number includes a group number and a beam number;

[0017] The total number of the beam input ports is N*M, and the values ​​of M and N are both greater than or equal to 1.

[0018] According to a technical solution of the present invention, the interior of the chip is a passive architecture.

[0019] According to a technical solution of the present invention, the number of the input port groups and the number of the signal layers satisfy:

[0020] log2(M)=γ

[0021] Wherein, M represents the number of the input port groups, M≥1, and M is an even number; γ represents the number of the signal layers, and γ is an integer.

[0022] According to a technical solution of the present invention, a plurality of the signal layers are stacked and arranged, and adjacent signal layers are connected via through holes and vertical connection structures.

[0023] Compared with the prior art, the present invention has the following beneficial effects:

[0024] The present invention proposes an integrated multi-beam feed network chip, which has a smaller size and significantly reduces the loss between layers. The integrated multi-beam feed network chip proposed by the present invention breaks through the technical bottleneck of large-scale and high-cost multi-layer routing of traditional multi-beam feed networks on PCBs, and thus provides a solution for realizing low-cost, high-performance integrated design. The chip can not only reduce the number of signal routing layers, but also significantly reduce the loss of the feed network, solving the problem of large routing area and high loss of traditional multi-beam feed networks on PCBs. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A schematic diagram schematically shows the structure of an integrated multi-beam feed network chip provided in one embodiment of the present invention;

[0027] Figure 2 A schematic diagram showing a wiring principle diagram of an integrated multi-beam feed network chip provided in one embodiment of the present invention;

[0028] Figure 3 A schematic cross-sectional view schematically showing an integrated multi-beam feed network chip provided in one embodiment of the present invention;

[0029] Figure 4 A schematic diagram schematically illustrates a micro-assembly of an integrated multi-beam feed network chip provided in another embodiment of the present invention;

[0030] Figure 5 A schematic diagram of a phased array sub-array of an integrated multi-beam feed network chip provided in another embodiment of the present invention is schematically shown.

[0031] Integrated multi-beam feed network chip 1, transceiver / receiver chip 2, phased array sub-array 3,

[0032] Chip body 11, first signal layer 12, second signal layer 13, first beam synthesis circuit 14, second beam synthesis circuit 15,

[0033] Antenna unit 31. DETAILED DESCRIPTION

[0034] The description of the embodiments of this specification should be combined with the corresponding drawings, which should be considered as part of the complete specification. In the drawings, the shape or thickness of the embodiments may be enlarged and indicated for simplification or convenience. Furthermore, the parts of each structure in the drawings will be described separately. It is worth noting that the elements not shown in the drawings or not described in words are in a form known to ordinary technicians in the relevant technical field.

[0035] The description of the embodiments herein and any reference to directions and orientations are only for the convenience of description and are not to be construed as any limitation on the scope of protection of the present invention. The following description of the preferred embodiments may involve combinations of features, which may exist independently or in combination, and the present invention is not particularly limited to the preferred embodiments. The scope of the present invention is defined by the claims.

[0036] like Figure 1 As shown, the present invention provides an integrated multi-beam feed network chip 1, which realizes a low-loss, low-cost miniaturized integrated design through a novel internal signal routing method. Figure 1-5 As shown, the integrated multi-beam feeding network chip 1 includes a chip body 11, and also includes a plurality of input port groups, a plurality of output ports and a plurality of signal layers.

[0037] Several input port groups are used to access multi-beam input signals; each input port group includes several beam input ports. Several output ports are used to output multi-beam output signals, and the number of beam input ports and the number of output ports in each input port group are the same as the number of beams. Several signal layers are connected in sequence, and each signal layer is provided with several groups of beam synthesis circuits, and the number of groups of beam synthesis circuits is the same as the number of beams; the beam synthesis circuits are used to perform beam synthesis between the same beam signals between several input port groups; the beam synthesis circuits of the first layer of signal layers are respectively connected to the beam input ports, and the beam synthesis circuits of the last layer of signal layers are respectively connected to the output ports; the input port groups and the output ports are arranged along the outer edge of the chip body 11.

[0038] The chip body 11 is rectangular, the output ports are distributed on the wide side of the chip body 11, and the beam input ports are distributed on the long side of the chip body 11. Several input port groups and several output ports are evenly distributed along the outer edge of the chip body 11, and the beam input ports in two adjacent input port groups are symmetrically arranged according to their beam numbers.

[0039] The beam numbering rules for the beam input port are as follows:

[0040] For a plurality of input port groups, group numbers are sequentially assigned in alphabetical order along the long side of the chip body 11, and the total number of group numbers is M;

[0041] The N beam input ports in each input port group are evenly distributed on the two long sides of the chip body 11, and beam numbers are sequentially assigned to the N beam input ports in numerical order;

[0042] For any beam input port, its beam number includes the group number and the beam number;

[0043] The total number of beam input ports is N*M, and the values ​​of M and N are both greater than or equal to 1.

[0044] like Figure 1 As shown, the group numbers of the input port groups are A, B, C, ..., X, and the beam numbers are 1, 2, 3, ..., N. The beam numbers of the beam input ports in the input port groups of the first group are A1, A2, A3, ..., AN, and the beam numbers of the beam input ports in the input port groups of the second group are B1, B2, B3, ..., BN. And so on, until all the group numbers of the X group of input port groups are completed. When N is equal to 8, in the input port groups of the first group, the beam input ports with beam numbers A1-A4 are arranged along one long side of the chip body 11, and the beam input ports with beam numbers A5-AN are arranged along the other long side of the chip body 11. In the input port groups of the second group, the beam input ports with beam numbers B1-B4 are arranged along one long side of the chip body 11, and the beam input ports with beam numbers A1 and B1 are symmetrically arranged along the dividing line between the input port groups of the first group and the second group.

[0045] Figure 2 This is a basic working principle diagram of chip multi-layer routing. In the figure, a first beam synthesis circuit 14 is set on the first signal layer 121, and a second beam synthesis circuit 15 is set on the second signal layer 13. The principle of chip multi-layer routing is as follows: First, according to the value of M, the number of signal layers is determined. If the value of M is greater than 2, the required number of signal layers can be obtained according to the formula log2(M)=γ. When the signal layer is greater than 1, the multiple signal layers are connected through through holes and vertical connection structures. For example, when M=4, 2 signal layers are required; when M=8, 3 signal layers are required. This routing method can be applied to different chip process designs, including but not limited to CMOS, GaAs, GaN, InP, etc.

[0046] Figure 3It is a cross-sectional diagram of the signal routing. After different beam signals are loaded into the beam input port, the same beam is synthesized, such as A1 and B1, C1 and D1 are beam synthesized in the first signal layer 12, and the synthesized signal of A1 and B1 passes through the through hole, and the synthesized signal is transmitted to the second signal layer 2. In the second signal layer 13, the synthesized beam of A1 and B1 and the synthesized beam of C1 and D1 are synthesized again, and the synthesized beam is BM1. Similarly, the numbered decibels of the output port are beams BM1, BM2,..., BMN, and these signals are output from the second signal layer 13.

[0047] Figure 4 This is a schematic diagram of chip micro-assembly in another embodiment of the present invention. In this embodiment, the integrated multi-beam feeding network chip 1 can be micro-assembled with the transceiver / transmitter chip 2 to realize the feeding of the transceiver / transmitter chip. The number of input ports of the multi-beam feeding network chip 1 is 64, and the beam input ports of the multi-beam feeding network chip 1 are numbered from A1-A8, B1-B8 to H1-H8; the number of output ports of the multi-beam feeding network chip 1 is 8, and the output ports are numbered from BM1 to BM8. The micro-assembly of the chip is achieved by: reasonably laying out 8 transceiver / transmitter chips 2 (M=8), and then connecting the input end of the transceiver / transmitter chip 2 to the beam input port of the entire integrated multi-beam feeding network chip 1 through bonding wires, and the output end of the transceiver / transmitter chip 2 is connected through bonding wires. Figure 1 The routing method shown is designed, and then the synthesized signal is output through ports BM1-BM8. According to the formula log2(M)=γ, substituting M=8 into the above formula, it can be obtained that the number of signal layers γ is 3. Therefore, when 8 transceiver / transmitter chips 2 are micro-assembled, the entire chip only needs 3 layers to realize the multi-beam feeding network. Similarly, if there are 16 transceiver / transmitter chips 2 inside the chip, 4 layers of signal lines are required.

[0048] Figure 5 It is a schematic diagram of a phased array according to another embodiment of the present invention. The integrated multi-beam feeding network chip 1 can be applied to the phased array sub-array to realize the feeding of the phased array antenna unit. In the phased array, there are two phased array sub-arrays 3, each phased array sub-array 3 has 8 antenna units 31, and the 8 antenna units 31 are respectively connected to the integrated multi-beam feeding network chip 1. The 8 antenna units 31 can be expanded to 256, 512, 1020 and 2048 array elements, so the number of antenna units 31 of the phased array phased array sub-array 3 includes but is not limited to 8. The number of phased array sub-arrays 3 includes but is not limited to 2, and the increase in the scale of the phased array sub-array 3 requires correspondingly more multi-beam feeding network chips.

[0049] By adopting the proposed signal layer routing rules and utilizing the integrated multi-beam feeding network chip proposed in the present invention, the chip has a smaller size and the loss between layers can be significantly reduced.

[0050] It should be noted that the above is a preferred embodiment of the present invention. It should be pointed out that although the preferred embodiment of the present invention has been described, once the basic creative concept of the present invention is known, a number of improvements and modifications can be made by a person skilled in the art without departing from the principles of the present invention, and these improvements and modifications should also be regarded as the protection scope of the present invention. Therefore, the attached claims are intended to be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the embodiments of the present invention.

Claims

1. An integrated multi-beam feed network chip, characterized in that: Including the chip body, also includes: A plurality of input port groups, for receiving multi-beam input signals; each of the input port groups comprises a plurality of beam input ports; A plurality of output ports for outputting multi-beam output signals; the number of the beam input ports and the number of the output ports in each of the input port groups is the same as the number of beams; A plurality of sequentially connected signal layers, each of which is provided with a plurality of groups of beam synthesis circuits, the number of groups of the beam synthesis circuits being the same as the number of the beams; the beam synthesis circuits are used to perform beam synthesis between two of the same beam signals between the plurality of input port groups; the beam synthesis circuits of the first layer of the signal layers are respectively connected to the beam input ports, and the beam synthesis circuits of the last layer of the signal layers are respectively connected to the output ports; The input port and the output port are arranged along the outer edge of the chip body.

2. The integrated multi-beam feed network chip according to claim 1, characterized in that: The chip body is rectangular, the output ports are distributed on the wide sides of the chip body, and the input ports are distributed on the long sides of the chip body.

3. The integrated multi-beam feed network chip according to claim 1, characterized in that: The plurality of input port groups and the plurality of output ports are evenly distributed along the outer edge of the chip body, and the beam input ports in two adjacent input port groups are symmetrically arranged according to their beam numbers.

4. The integrated multi-beam feed network chip according to claim 3, characterized in that: The beam numbering rules of the beam input port are as follows: For the plurality of input port groups, group numbers are sequentially assigned in alphabetical order along the long side of the chip body, and the total number of group numbers is M; The N beam input ports in each input port group are evenly distributed on two long sides of the chip body, and beam numbers are sequentially assigned to the N beam input ports in numerical order; For any of the beam input ports, its beam number includes a group number and a beam number; The total number of the beam input ports is N*M, and the values ​​of M and N are both greater than or equal to 1.

5. The integrated multi-beam feed network chip according to claim 3, characterized in that: The interior of the chip is a passive structure.

6. The integrated multi-beam feed network chip according to claim 1, characterized in that: The number of the input port groups and the number of the signal layers satisfy: log2(M)=γ Wherein, M represents the number of the input port groups, M≥1, and M is an even number; γ represents the number of the signal layers, γ is an integer, γ≥1.

7. The integrated multi-beam feed network chip according to claim 1, characterized in that: A plurality of the signal layers are stacked and arranged, and adjacent signal layers are connected via through holes and vertical connection structures.

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