Radio frequency energy collection management device, method, equipment and medium

Abstract

The invention relates to a radio frequency energy collection management device, method and equipment and a medium. The management device receives radio frequency electromagnetic waves through a plurality of antennas of the antenna module and converts the radio frequency electromagnetic waves into high-frequency current signals; synthesizing the high-frequency current signal by using a power synthesizer to obtain a synthesized current signal; circuit components of the matching circuit are adjusted with the purpose of minimizing reflection and loss in signal transmission, and the matching circuit with the adjusted circuit components is used for transmitting a synthesized current signal to the rectification voltage doubling circuit; the rectification voltage doubling circuit is used for carrying out boosting and alternating current-direct current conversion on the synthesized current signal to obtain a direct current signal; the high-efficiency LDO chip is used for carrying out voltage stabilization on the direct-current signal, the direct-current signal after voltage stabilization is transmitted to the working circuit driving circuit for working, and through the circuit design, high-efficiency radio frequency energy collection, conversion and management can be carried out under the conditions of low noise, low power consumption and low cost.

Description

Technical Field

[0001] The present invention relates to the technical field of radio frequency integrated circuits, and primarily to a radio frequency energy acquisition and management device, method, equipment, and medium. Background Art

[0002] In the era of the Internet of Things, many electrical devices are buried deep underground or in locations where battery replacement is difficult. Replacing batteries requires significant manpower and resources. Radio frequency energy is ubiquitous in the surrounding environment, such as broadcast signals, television signals, and wireless LAN signals, which are radiated continuously from base stations 24 hours a day. With technological advancements, an increasing number of electromagnetic wave signals are present in free space. Electromagnetic wave energy harvesting devices can collect electromagnetic wave energy in free space for wireless charging. To improve wireless charging efficiency, reduce reliance on traditional batteries, and optimize energy utilization, research on efficient radio frequency energy harvesting, conversion, and management devices has become crucial.

[0003] For example, CN110676951B "Self-powered system based on environmental radio frequency energy collection" discloses "a self-powered system based on environmental radio frequency energy collection, including a receiving antenna, a matching circuit, a rectifier circuit, a boost energy storage circuit and a voltage stabilizing circuit. The receiving antenna is used to obtain radio frequency energy in the environment and convert the obtained radio frequency energy into AC output. The matching circuit is used to transmit the AC output of the receiving antenna to the rectifier circuit and at the same time to match the input impedance of the rectifier circuit to 50Ω. The rectifier circuit is connected to the AC output of the matching circuit and converts the AC input thereinto into a DC voltage output. The boost energy storage circuit is used to connect to the DC voltage output of the rectifier circuit and boost the DC voltage. After processing, the electrical energy is stored, and the voltage stabilizing circuit obtains electrical energy from the boost energy storage circuit to power an external low-power IoT node; the advantage is high power supply stability and reliability. However, the RF energy source in the actual environment is very weak, which makes energy collection very difficult. The above invention relies on the RF energy in the environment. The strength of the ambient signal may be very low, especially in some places far away from the signal source. The system may require a strong input power to work properly, which may limit its application scenarios. If the energy of the ambient signal is insufficient, the system will not work effectively. In addition, the above invention is complex in design, and the components used, such as high-frequency oscillators, boost converters, and voltage stabilizing chips, will increase the overall cost of the system. Summary of the Invention

[0004] In order to solve the above-mentioned problems existing in the prior art, the present application provides a radio frequency energy collection and management device, method, equipment and medium.

[0005] The technical solution of this application is as follows: A radio frequency energy collection and management device, comprising an antenna module, a power combiner, a matching circuit, a rectifier and voltage multiplier circuit, a high-efficiency LDO chip, and a working circuit, wherein: The antenna module includes a plurality of antennas, which receive radio frequency electromagnetic waves and convert the radio frequency electromagnetic waves into high frequency current signals; The power synthesizer is used to synthesize the high-frequency current signal to obtain a synthesized current signal; The matching circuit is designed to minimize reflection and loss in signal transmission, achieves impedance matching by adjusting circuit component parameters, and transmits the synthesized current signal to the rectifier and voltage doubler circuit; The rectifier and voltage multiplier circuit is used to perform voltage boosting and AC-DC current conversion on the synthesized current signal to obtain a DC signal; The high-efficiency LDO chip is used to stabilize the DC signal and transmit the stabilized DC signal to the working circuit drive circuit for operation.

[0006] As a preferred embodiment of the present invention, the power combiner is a one-to-four power combiner, which is composed of three one-to-two power combiners.

[0007] As a preferred embodiment of the present invention, the matching circuit adopts discrete component matching, including a parallel capacitor C2 and a series inductor L1, wherein one end of the parallel capacitor C2 is connected to the output end of the power combiner, and the other end is respectively connected to the input end of the rectifier and voltage doubler circuit and one end of the series inductor L1, and the other end of the series inductor L1 is grounded. The center frequency of the matching circuit is 2.4 GHz, and the input impedance and the output impedance constitute a conjugate impedance.

[0008] As a preferred embodiment of the present invention, the rectifier and voltage doubler circuit includes a capacitor C3, a capacitor C4, a diode D1 and a diode D2, one end of the capacitor C3 is connected to the output end of the matching circuit, and the other end is connected to the negative end of the diode D1 and the positive end of the diode D2, the positive end of the diode D1 is grounded, and the negative end of the diode D2 is respectively connected to the capacitor C4 and the load resistor RL.

[0009] As a preferred embodiment of the present invention, a high-efficiency LDO chip includes a Vref generation circuit, an error feedback amplifier, a power MOS transistor M1, a voltage divider, and a storage capacitor CL, wherein: The input end of the Vref generating circuit is connected to the output end of the rectifier voltage multiplier circuit, and is used to generate a reference voltage Vref according to the DC signal. The output end of the Vref generating circuit is connected to the negative input end of the error feedback amplifier, and is used to use the reference voltage Vref as an input signal of the error feedback amplifier; The voltage divider includes a low-threshold voltage MOS transistor M2 and a low-threshold voltage MOS transistor M3, which are connected in series. The gate of the low-threshold voltage MOS transistor M2 is connected to the drain of the low-threshold voltage MOS transistor M2 and the drain of the power MOS transistor M1, respectively. The gate of the low-threshold voltage MOS transistor M3 is connected to the drain of the low-threshold voltage MOS transistor M3 and the source of the low-threshold voltage MOS transistor M2, respectively. The voltage divider is used to sample the output voltage Vo of the error feedback amplifier and generate a feedback voltage Vp. The series node of the low-threshold voltage MOS transistor M2 and the low-threshold voltage MOS transistor M3 is connected to the positive input terminal of the error feedback amplifier, so as to use the feedback voltage Vp as another input signal of the error feedback amplifier. The error feedback amplifier is used to compare the reference voltage Vref and the feedback voltage Vp to obtain a comparison result. The signal input terminal of the error feedback amplifier and the drain of the power MOS transistor M1 are both connected to the output terminal of the rectifier and voltage doubler circuit. The output terminal of the error feedback amplifier is connected to the gate of the power MOS transistor M1. The error feedback amplifier is used to adjust the conduction state of the power MOS transistor M1 according to the comparison result and adjust the output voltage Vo; The storage capacitor CL is connected in parallel with the voltage divider and is used to store charge to provide energy for the working circuit.

[0010] As a preferred embodiment of the present invention, the Vref generating circuit includes depletion-type N-type MOS transistors M4 and M5, enhancement-type N-type MOS transistors M6 and M7, a resistor R3, and a capacitor C1, wherein: The drain of the depletion-type N-type MOS transistor M4 is connected to the output of the rectifier and voltage multiplier circuit as the input of the Vref generating circuit, and the source is connected to the drain of the depletion-type N-type MOS transistor M5. The source of the depletion-type N-type MOS transistor M5 is connected to the drain of the enhancement-type N-type MOS transistor M6. The source of the enhancement-type N-type MOS transistor M6 is connected to one end of the resistor R3. The other end of the resistor R3 is respectively connected to the drain of the enhancement-type N-type MOS transistor M7 and the gate of the depletion-type N-type MOS transistor M4. The source of the enhancement-type N-type MOS transistor M7 is grounded. The source and gate of the depletion-type N-type MOS transistor M5, the drain and gate of the depletion-type N-type MOS transistor M6, and the gate of the depletion-type N-type MOS transistor M7 form a common node. The common node is connected to one end of the capacitor C1. The other end of the capacitor C1 is grounded.

[0011] As a preferred embodiment of the present invention, the error feedback amplifier includes a PMOS transistor M8, a PMOS transistor M9, a PMOS transistor M10, an NMOS transistor M11, and an NMOS transistor M12, wherein: The gate of the PMOS transistor M8 is connected to the bias voltage Vb, the source of the PMOS transistor M8 is connected to the input voltage Vin, and the drain of the PMOS transistor M8 is connected to the source of the PMOS transistor M9 and the source of the PMOS transistor M10 respectively; the gate of the PMOS transistor M9 is connected to the feedback voltage Vp, and the drain of the PMOS transistor M9 is connected to the drain of the NMOS transistor M11 and the gate of the NMOS transistor M11 respectively; the gate of the PMOS transistor M10 is connected to the reference voltage Vn, and the drain of the PMOS transistor M10 is connected to the drain of the NMOS transistor M12; the gate of the NMOS transistor M11 is connected to the gate of the NMOS transistor M12, and the source of the NMOS transistor M11 is connected to the source of the NMOS transistor M12 and is connected to the ground potential.

[0012] The present invention further provides a radio frequency energy acquisition management method. According to the radio frequency energy acquisition management device of the present invention, energy acquisition management is performed. The method includes: Multiple antennas are used to receive external radio frequency electromagnetic waves and convert them into high-frequency current signals. A power synthesizer is used to synthesize the high-frequency current signals to obtain a synthesized current signal. The synthesized current signal is transmitted to a rectifier and voltage multiplier circuit through a matching circuit for rectification and boosting, and converted into a DC signal. The DC signal is stabilized by a high-efficiency LDO chip, and the stabilized DC signal is used to drive the working circuit to operate.

[0013] The present invention also provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, a radio frequency energy collection and management method as described in any embodiment of the present invention is implemented.

[0014] The present invention further provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements a radio frequency energy collection and management method as described in any embodiment of the present invention.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1) The present invention provides a radio frequency energy collection and management device, method, equipment, and medium. The device receives radio frequency electromagnetic waves through multiple antenna modules and uses a power combiner to combine multiple high-frequency current signals. The power combiner uses a one-to-four power combiner composed of three one-to-two power combiners, which improves the efficiency of energy combination and increases the flexibility and scalability of the device. 2) The present invention provides a radio frequency energy harvesting and management device, method, equipment, and medium. The matching circuit uses discrete components for matching, which can accurately adjust circuit components so that the input impedance and output impedance form a conjugate impedance, further optimizing signal transmission. The matching circuit design minimizes reflections and losses in signal transmission, ensuring efficient and stable signal transmission. 3) The present invention provides a radio frequency energy harvesting and management device, method, apparatus, and medium. Through the coordinated operation of the Vref generation circuit, error feedback amplifier, and power MOS transistor in a high-efficiency LDO chip, the output voltage is precisely adjusted to ensure voltage stability and reliability. Furthermore, the high-efficiency LDO chip of the present invention is relatively simple in design. While ensuring a very clean, low-noise output voltage, it does not require an external inductor or complex control circuit. The small number of peripheral components simplifies circuit design and debugging. Furthermore, because the high-efficiency LDO chip of the present invention is simple in design and does not require an inductor, the component cost and overall cost are low, making it suitable for cost-sensitive applications. 4) The present invention provides a radio frequency energy harvesting and management device, method, equipment, and medium. By using storage capacitors in high-efficiency LDO chips, energy regulation is performed between energy harvesting and use, further optimizing the system's energy management. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 is a block diagram of the device structure of an embodiment of the present invention; Figure 2 This is a schematic diagram of a high-efficiency LDO chip circuit according to an embodiment of the present invention; Figure 3 is a schematic diagram of a power combiner according to an embodiment of the present invention; Figure 4 is a schematic diagram of a matching circuit according to an embodiment of the present invention; Figure 5 is a schematic diagram of a rectifier and voltage doubling circuit according to an embodiment of the present invention; Figure 6 4 is a schematic diagram of a Vref generating circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The specific embodiments of the present invention are described below to facilitate understanding of the present invention by those skilled in the art. However, it should be clear that the present invention is not limited to the scope of the specific embodiments. For those skilled in the art, as long as various changes are within the spirit and scope of the present invention as defined and determined by the appended claims, these changes are obvious, and all inventions and creations utilizing the concepts of the present invention are protected.

[0018] The present invention provides the following technical solutions: a radio frequency energy collection and management device, method, equipment and medium.

[0019] Example 1: like Figure 1 As shown, this embodiment provides a radio frequency energy collection and management device, which includes an antenna module, a power combiner, a matching circuit, a rectifier and voltage multiplier circuit, a high-efficiency LDO chip, and a working circuit, wherein: S1, antenna module; The antenna module includes multiple antennas, which receive radio frequency electromagnetic waves and convert them into high-frequency current signals to improve signal capture capabilities and overall system efficiency; Preferably, the antenna module includes different types of antennas, such as monopole antennas, patch antennas, or array antennas, depending on different frequency ranges and signal characteristics. By selecting antennas suitable for specific operating frequency bands and reception conditions, the signal reception strength and quality are maximized. The antennas are rationally arranged taking into account space limitations and signal interference, and are arranged at appropriate spacing and angles to obtain optimal directivity and gain characteristics. Taking the antenna module in the RF energy harvesting and management device operating in a smart traffic light as an example, the antenna module uses a combination of a patch antenna and a monopole antenna, with a frequency range designed to cover 2.4 GHz (Wi-Fi band) and 900 MHz (GSM band). It is used to capture RF energy from wireless communication devices. Multiple antennas are arranged on the top and sides of the smart traffic light to maximize the signal reception area and reduce interference with other metal structures. By optimizing the antenna's directivity and gain, the strength of the received RF signal is enhanced, thereby improving energy collection efficiency; S2, power combiner; The power synthesizer is used to synthesize the high-frequency current signal to obtain a synthesized current signal; like Figure 3 As shown, the power combiner is a one-to-four power combiner, which is composed of three one-to-two power combiners, including a quarter-wavelength impedance converter, a 50-ohm characteristic impedance, and three isolation resistors. The three one-to-two power combiners are integrated on the same substrate, which facilitates high-density integration and miniaturization. Furthermore, to effectively reduce mutual interference, the distance between the four output ports of the one-to-four power combiner is designed to be 80 mm. To achieve impedance matching at a specific frequency and thus optimize power transmission efficiency, the length of the quarter-wavelength impedance converter is designed to be 27 mm and the width is designed to be 1.6 mm. Considering the impedance matching of signal transmission, the 50-ohm characteristic impedance line width is designed to be 3 mm. In order to provide sufficient signal isolation, thereby reducing interference between various signal paths and improving the performance of the overall system, the three isolation resistors are designed to have a value of 100 Ω. The design of dividing the power combiner into multiple one-to-two modules is more flexible and easier to test and maintain. Each module can work independently, making it easy to troubleshoot and replace faults. The one-to-two power combiner effectively distributes power evenly, ensuring a more uniform power output signal and reducing imbalances in the system. It is worth noting that this embodiment does not limit the number of one-to-two power combiners to three. Technicians can adjust the final output quantity by adding or reducing one-to-two modules as needed, conveniently expanding the system to meet higher output requirements. S3, matching circuit; The matching circuit is designed to minimize reflection and loss in signal transmission, achieves impedance matching by adjusting circuit component parameters, and transmits the synthesized current signal to the rectifier and voltage doubler circuit; like Figure 4 As shown, the matching circuit uses discrete components for matching, including a parallel capacitor C2 and a series inductor L1, wherein one end of the parallel capacitor C2 is connected to the output of the power combiner, and the other end is respectively connected to the input of the rectifier and voltage doubler circuit and one end of the series inductor L1. The other end of the series inductor L1 is grounded. The center frequency of the matching circuit is 2.4 GHz, and the input impedance and the output impedance form a conjugate impedance. By setting a suitable center frequency and conjugate impedance configuration, the stability of the circuit at the operating frequency is improved, and performance changes caused by frequency drift or other external factors are reduced. S4, rectifier and voltage doubler circuit; The rectifier and voltage doubler circuit is used to boost the voltage of the synthesized current signal and perform AC-DC current conversion. The rectifier and voltage doubler circuit converts the AC power output by the matching circuit into DC power by voltage doubling to obtain a DC signal. like Figure 5 As shown, the rectifier and voltage doubler circuit includes a capacitor C3, a capacitor C4, a diode D1, and a diode D2. One end of the capacitor C3 is connected to the output end of the matching circuit, and the other end is connected to the negative end of the diode D1 and the positive end of the diode D2. The positive end of the diode D1 is grounded, and the negative end of the diode D2 is connected to the capacitor C4 and the load resistor RL respectively. Furthermore, in this embodiment, the diode D1 and the diode D2 are Schottky diodes HSMS-2852, the load resistance is 5kΩ, and the two capacitors are both 100pF; S5, high-efficiency LDO chip; The high-efficiency LDO chip is used to stabilize the DC signal and transmit the stabilized DC signal to the working circuit drive circuit for operation.

[0020] like Figure 2 As shown, the high-efficiency LDO chip includes a Vref generation circuit, an error feedback amplifier, a power MOS transistor M1, a voltage divider, and a storage capacitor CL, where: S51, Vref generating circuit; The input end of the Vref generating circuit is connected to the output end of the rectifier voltage multiplier circuit, and is used to generate a reference voltage Vref according to the DC signal. The output end of the Vref generating circuit is connected to the negative input end of the error feedback amplifier, and is used to use the reference voltage Vref as an input signal of the error feedback amplifier; like Figure 6 As shown, the Vref generating circuit includes depletion-type N-type MOS transistors M4 and M5, enhancement-type N-type MOS transistors M6 and M7, a resistor R3, and a capacitor C1, wherein: The depletion-type MOS transistor is turned on when no voltage is applied to the gate. The drain of the depletion-type N-type MOS transistor M4 is connected to the output of the rectifier and voltage multiplier circuit as the input of the Vref generating circuit, and the input signal is introduced into the Vref generating circuit through M4; the source is connected to the drain of the depletion-type N-type MOS transistor M5, and the source of the depletion-type N-type MOS transistor M5 is connected to the drain of the enhancement-type N-type MOS transistor M6. M5 and M4 are connected in series, and its source is also connected to the drain of M6, forming a current source; the enhancement-type MOS transistor can only be turned on when there is sufficient voltage on the gate. The source of the enhancement-type N-type MOS transistor M6 is connected to one end of the resistor R3, forming a negative feedback mechanism to help stabilize the output voltage of Vref and ensure that Vref does not increase too much due to changes in the input signal. The other end of the resistor R3 is connected to the drain of the enhancement-type N-type MOS transistor M7 and the gate of the depletion-type N-type MOS transistor M4, respectively, and the source of the enhancement-type N-type MOS transistor M7 is grounded; the source and gate of the depletion-type N-type MOS transistor M5, the drain and gate of the depletion-type N-type MOS transistor M6, and the gate of the depletion-type N-type MOS transistor M7 form a common node, which can be regarded as a control voltage point. When the voltage of this node changes, it will affect the conduction state of M6 and M7, thereby adjusting the output voltage of Vref; the common node is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded. The capacitor C1 is responsible for filtering, suppressing the output high-frequency noise, and improving the stability of Vref. The grounding also provides a stable reference level for the rectifier circuit; The input voltage introduced by the entire circuit through M4 forms a current source at M5. M6 and M7 use negative feedback to adjust their conduction level to ensure that the output reference voltage Vref remains stable and at a preset value. When the input voltage changes, the feedback mechanism will quickly respond by adjusting the conduction state of M6 and M7 to maintain the stability of Vref. C1 ensures that the output voltage is not affected by rapid changes, thereby smoothing the output reference voltage. Furthermore, in the depletion-mode N-type MOS transistor M5, when the gate-source voltage (Vgs) is 0, due to its characteristics, a conductive channel is still formed even without an external voltage. Therefore, M5 can still conduct under certain conditions; M7M7's gate and drain are not directly connected to a voltage source, that is, the gate-drain is disconnected, and the conduction state of M7 is mainly determined by the voltage on its gate. The currents of M5 and M7 are: ; ; in is the product of the corresponding carrier mobility and the gate oxide capacitance per unit area, is the threshold voltage of the depletion-type MOS tube, is the threshold voltage of the enhancement mode MOS tube; If M4 and M5 are connected in series, the currents are equal. The gate-source voltage of M5 can be substituted into the above current expression to solve it. Substituting it into the formula yields: ; The negative threshold voltage |VTD| of a depletion-mode MOS transistor has a positive temperature coefficient, meaning that as the temperature rises, the absolute value of its threshold voltage increases, causing the circuit to conduct more easily at high temperatures under certain conditions. In contrast, the threshold voltage (VTE) of an enhancement-mode MOS transistor has a negative temperature coefficient, decreasing as the temperature rises, making it easier for the enhancement-mode MOS transistor to conduct at high temperatures. Therefore, by comprehensively considering the temperature characteristics of both depletion-mode and enhancement-mode MOS transistors and adjusting the current characteristics through a reasonable width-to-length ratio (W / L), the Vref generation circuit described in this embodiment can function properly under different temperature conditions. S52, voltage divider; The voltage divider includes a low-threshold voltage MOS transistor M2 and a low-threshold voltage MOS transistor M3, which are connected in series. The gate of the low-threshold voltage MOS transistor M2 is connected to the drain of the low-threshold voltage MOS transistor M2 and the drain of the power MOS transistor M1, respectively. The gate of the low-threshold voltage MOS transistor M3 is connected to the drain of the low-threshold voltage MOS transistor M3 and the source of the low-threshold voltage MOS transistor M2, respectively. The voltage divider is used to sample the output voltage Vo of the error feedback amplifier and generate a feedback voltage Vp. The series node of the low-threshold voltage MOS transistor M2 and the low-threshold voltage MOS transistor M3 is connected to the positive input terminal of the error feedback amplifier, so as to use the feedback voltage Vp as another input signal of the error feedback amplifier. S53, error feedback amplifier; The error feedback amplifier is used to compare the reference voltage Vref and the feedback voltage Vp to obtain a comparison result. The signal input terminal of the error feedback amplifier and the drain of the power MOS transistor M1 are both connected to the output terminal of the rectifier and voltage doubler circuit. The output terminal of the error feedback amplifier is connected to the gate of the power MOS transistor M1. The error feedback amplifier is used to adjust the conduction state of the power MOS transistor M1 according to the comparison result and adjust the output voltage Vo; The error feedback amplifier includes a PMOS transistor M8, a PMOS transistor M9, a PMOS transistor M10, an NMOS transistor M11, and an NMOS transistor M12, wherein: The gate of the PMOS transistor M8 is connected to the bias voltage Vb, the source of the PMOS transistor M8 is connected to the input voltage Vin, and the drain of the PMOS transistor M8 is connected to the source of the PMOS transistor M9 and the source of the PMOS transistor M10 respectively; the gate of the PMOS transistor M9 is connected to the feedback voltage Vp, and the drain of the PMOS transistor M9 is connected to the drain of the NMOS transistor M11 and the gate of the NMOS transistor M11 respectively; the gate of the PMOS transistor M10 is connected to the reference voltage Vn, and the drain of the PMOS transistor M10 is connected to the drain of the NMOS transistor M12; the gate of the NMOS transistor M11 is connected to the gate of the NMOS transistor M12, and the source of the NMOS transistor M11 is connected to the source of the NMOS transistor M12 and is connected to the ground potential; The designed error feedback amplifier realizes the conversion from differential input to single-ended output. It uses low threshold voltage MOS and works in the sub-threshold region, and has the advantages of low voltage and low power consumption, further improving the utilization rate of electromagnetic wave energy. S54, storage capacitor CL; The storage capacitor CL is connected in parallel with the voltage divider to store charge and provide energy for the working circuit. When there is a transient load change or input voltage fluctuation, the storage capacitor CL can quickly release energy to maintain a stable output voltage. This feature is particularly important for many applications that are sensitive to power supply noise (such as analog circuits and radio frequency circuits). In order for the storage capacitor to be effective, it is crucial to select the appropriate capacitance value. A capacitance value that is too small may not effectively smooth the output voltage, while a capacitance value that is too large will increase the size and cost of the circuit and may also cause the startup time to increase. Therefore, when designing, technicians need to comprehensively consider performance requirements, cost, and physical size. As a preferred embodiment of the present invention, Furthermore, this embodiment takes the operation of the radio frequency energy collection and management device in an intelligent traffic light as an example to illustrate the specific application method: Example 2: This embodiment provides a radio frequency energy collection and management method, the method comprising: Multiple antennas are used to receive external radio frequency electromagnetic waves and convert them into high-frequency current signals. A power synthesizer is used to synthesize the high-frequency current signals to obtain a synthesized current signal. The synthesized current signal is transmitted to a rectifier and voltage multiplier circuit through a matching circuit for rectification and boosting, and converted into a DC signal. The DC signal is stabilized by a high-efficiency LDO chip, and the stabilized DC signal is used to drive the working circuit to operate.

[0021] Example 3: An electronic device includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the program, a radio frequency energy collection and management method as described in Example 2 is implemented.

[0022] Example 4: A computer-readable storage medium stores a computer program, which, when executed by a processor, implements a radio frequency energy collection and management method as described in Example 2.

[0023] It is worth noting that the device, method, electronic device, and computer-readable storage medium described in the present invention are all based on the same inventive concept, namely, using a radio frequency energy collection and management device to run the corresponding method, which will not be described in detail here.

[0024] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent structures or equivalent process changes made using the contents of the present invention's description and drawings, or directly or indirectly applied to other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A radio frequency energy collection and management device, characterized in that: The device includes an antenna module, a power synthesizer, a matching circuit, a rectifier and voltage doubler circuit, a high-efficiency LDO chip and a working circuit, wherein: The antenna module includes a plurality of antennas, through which radio frequency electromagnetic waves are received and converted into high frequency current signals; The power synthesizer is used to synthesize the high-frequency current signal to obtain a synthesized current signal; The matching circuit aims to minimize reflection and loss in signal transmission, achieves impedance matching by adjusting circuit component parameters, and transmits the synthesized current signal to the rectifier and voltage doubler circuit; The rectifier and voltage doubler circuit is used to perform voltage boosting and AC-DC current conversion on the synthesized current signal to obtain a DC signal; The high-efficiency LDO chip is used to stabilize the DC signal and transmit the stabilized DC signal to the working circuit drive circuit for operation.

2. A radio frequency energy collection and management device according to claim 1, characterized in that: The power combiner is a one-to-four power combiner, which is composed of three one-to-two power combiners.

3. A radio frequency energy collection and management device according to claim 2, characterized in that: The matching circuit adopts discrete component matching, including a parallel capacitor C2 and a series inductor L1, wherein one end of the parallel capacitor C2 is connected to the output end of the power synthesizer, and the other end is respectively connected to the input end of the rectifier voltage doubler circuit and one end of the series inductor L1, and the other end of the series inductor L1 is grounded. The center frequency of the matching circuit is 2.4GHz, and the input impedance and the output impedance constitute a conjugate impedance.

4. The radio frequency energy collection and management device according to claim 3, characterized in that: The rectifier voltage doubler circuit includes a capacitor C3, a capacitor C4, a diode D1 and a diode D2. One end of the capacitor C3 is connected to the output end of the matching circuit, and the other end is connected to the negative end of the diode D1 and the positive end of the diode D2. The positive end of the diode D1 is grounded, and the negative end of the diode D2 is connected to the capacitor C4 and the load resistor RL respectively.

5. The radio frequency energy collection and management device according to claim 4, characterized in that: The high-efficiency LDO chip includes a Vref generation circuit, an error feedback amplifier, a power MOS transistor M1, a voltage divider, and a storage capacitor CL, wherein: The input end of the Vref generating circuit is connected to the output end of the rectifier voltage doubler circuit, and is used to generate a reference voltage Vref according to the DC signal. The output end of the Vref generating circuit is connected to the negative input end of the error feedback amplifier, and is used to use the reference voltage Vref as an input signal of the error feedback amplifier. The voltage divider comprises a low threshold voltage MOS transistor M2 and a low threshold voltage MOS transistor M3, the low threshold voltage MOS transistor M2 and the low threshold voltage MOS transistor M3 are connected in series, the gate of the low threshold voltage MOS transistor M2 is respectively connected to the drain of the low threshold voltage MOS transistor M2 and the drain of the power MOS transistor M1, the gate of the low threshold voltage MOS transistor M3 is respectively connected to the drain of the low threshold voltage MOS transistor M3 and the source of the low threshold voltage MOS transistor M2, and is used to sample from the output voltage Vo of the error feedback amplifier and generate a feedback voltage Vp; the series node of the low threshold voltage MOS transistor M2 and the low threshold voltage MOS transistor M3 is connected to the positive input terminal of the error feedback amplifier, and is used to use the feedback voltage Vp as another input signal of the error feedback amplifier; The error feedback amplifier is used to compare the reference voltage Vref and the feedback voltage Vp to obtain a comparison result. The signal input terminal of the error feedback amplifier and the drain of the power MOS transistor M1 are both connected to the output terminal of the rectifier voltage doubler circuit. The output terminal of the error feedback amplifier is connected to the gate of the power MOS transistor M1, and is used to adjust the conduction state of the power MOS transistor M1 according to the comparison result and adjust the output voltage Vo; The storage capacitor CL is connected in parallel with the voltage divider and is used to store charges to provide energy for the working circuit.

6. The radio frequency energy collection and management device according to claim 5, characterized in that: The Vref generating circuit includes depletion-type N-type MOS transistors M4 and M5, enhancement-type N-type MOS transistors M6 and M7, a resistor R3 and a capacitor C1, wherein: The drain of the depletion N-type MOS transistor M4 is connected to the output end of the rectifier voltage doubler circuit as the input end of the Vref generating circuit, the source is connected to the drain of the depletion N-type MOS transistor M5, the source of the depletion N-type MOS transistor M5 is connected to the drain of the enhancement N-type MOS transistor M6, the source of the enhancement N-type MOS transistor M6 is connected to one end of the resistor R3, the other end of the resistor R3 is respectively connected to the drain of the enhancement N-type MOS transistor M7 and the gate of the depletion N-type MOS transistor M4, and the source of the enhancement N-type MOS transistor M7 is grounded; the source and gate of the depletion N-type MOS transistor M5, the drain and gate of the depletion N-type MOS transistor M6, and the gate of the depletion N-type MOS transistor M7 form a common node, the common node is connected to one end of the capacitor C1, and the other end of the capacitor C1 is grounded.

7. The radio frequency energy collection and management device according to claim 6, characterized in that: The error feedback amplifier includes a PMOS tube M8, a PMOS tube M9, a PMOS tube M10, an NMOS tube M11 and an NMOS tube M12, wherein: The gate of the PMOS tube M8 is connected to the bias voltage Vb, the source of the PMOS tube M8 is connected to the input voltage Vin, and the drain of the PMOS tube M8 is respectively connected to the source of the PMOS tube M9 and the source of the PMOS tube M10; the gate of the PMOS tube M9 is connected to the feedback voltage Vp, and the drain of the PMOS tube M9 is respectively connected to the drain of the NMOS tube M11 and the gate of the NMOS tube M11; the gate of the PMOS tube M10 is connected to the reference voltage Vn, and the drain of the PMOS tube M10 is connected to the drain of the NMOS tube M12; the gate of the NMOS tube M11 is connected to the gate of the NMOS tube M12, and the source of the NMOS tube M11 is connected to the source of the NMOS tube M12 and is connected to the ground potential.

8. A radio frequency energy collection management method, performing energy collection management according to the radio frequency energy collection management device according to any one of claims 1 to 7, characterized in that: The method comprises: Multiple antennas are used to receive external radio frequency electromagnetic waves, and the radio frequency electromagnetic waves are converted into high-frequency current signals; the high-frequency current signals are synthesized by a power synthesizer to obtain a synthesized current signal; the synthesized current signal is transmitted to a rectifier and voltage doubler circuit through a matching circuit for rectification and boosting, and converted into a DC signal; the DC signal is stabilized by a high-efficiency LDO chip, and the stabilized DC signal is used to drive the working circuit to work.

9. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the program, the radio frequency energy collection and management method as claimed in claim 8 is implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the program is executed by a processor, a radio frequency energy collection and management method as claimed in claim 8 is implemented.

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