Driving circuit, chip and switching power supply using same

Abstract

In the driving circuit disclosed by the invention, the negative voltage circuit generates negative voltage through the charge pump circuit, most components of the negative voltage circuit are integrated in the chip, and peripheral devices of the chip are fewer, so that the application is more convenient. Moreover, the negative voltage begins to be established at the initial stage of the establishment of the power supply voltage, and the negative voltage can be established to a set voltage value before the PWM signal is output, thereby being capable of effectively preventing the power switch from being turned on by mistake. On the basis, the negative voltage amplitude is adjustable in multiple gears, and the requirements of different power switches are met.

Description

Technical Field

[0001] The present invention relates to the field of power electronics technology, and more specifically, to a drive circuit, a chip and a switching power supply using the same. Background Art

[0002] SiC transistors are increasingly used in high-voltage applications due to their high withstand voltage and low switching losses. Due to the small parasitic capacitance and fast switching speed of SiC transistors, a large voltage change rate dv / dt is easily coupled to the control end of the transistor, resulting in the phenomenon of transistor false opening. Therefore, in order to enhance reliability, negative voltage drive is generally required so that when the transistor is turned off, the control end is pulled to a lower value to prevent crosstalk from causing the control end to be instantly raised above the transistor's opening threshold and false opening.

[0003] like Figure 1 As shown in FIG. 1 , a switching power supply circuit of the prior art is used, and the peripheral circuits for driving SiC transistors are level conversion circuits, drive amplifier circuits, and control circuits of negative voltage power supply circuits. Among them, the level conversion circuit mainly converts the driving voltage of the control terminal outputted by the controller to the ground terminal GND into the driving voltage of the control terminal to the negative voltage V EE The negative voltage power supply circuit includes an auxiliary winding Na2, a diode D1 and a capacitor C VEE The negative voltage power supply circuit generates a negative voltage V through the auxiliary winding Na2. EE (V EE =-V O *Na2 / Ns), where V O is the output voltage of the switching power supply, Na2 and Ns are the turns of the auxiliary winding and the secondary winding respectively. It can be seen from this that this scheme can only control the switching power supply to work normally and generate the output voltage V after the controller generates the PWM signal. O After that, the negative voltage supply circuit starts to follow the output voltage V O change.

[0004] like Figure 2 As shown in the figure, it is a working waveform diagram of the switching power supply circuit of the prior art. When the supply voltage VCC reaches the starting threshold V UVLO_ON After starting to work, the negative voltage V EE After the controller works, that is, after the driving voltage DRV is generated, it will slowly build up through the auxiliary winding Na2. In the initial stage of the controller just generating the wave, due to the output voltage V O Lower, negative voltage V EEThe voltage is also low, so the risk of mis-turning on due to crosstalk when driving the turn-off transistor S1 is also high. This solution has many peripheral devices, complex structure and low reliability. In the prior art, some manufacturers do not even design negative voltage drive to save costs, resulting in worse reliability. Summary of the invention

[0005] In view of this, the present invention provides a driving circuit to solve the problem of numerous peripheral devices when realizing negative pressure in the prior art.

[0006] In a first aspect, the present invention provides a driving circuit, comprising:

[0007] A driving voltage generating circuit, wherein the positive terminal is coupled to the first driving voltage, the negative terminal is coupled to the second driving voltage, and the output terminal is coupled to the control terminal of the power switch;

[0008] A negative voltage circuit, used for generating the second driving voltage for driving the power switch, wherein the second driving voltage is a negative voltage;

[0009] The second driving voltage is established earlier than the time when the power switch starts to work normally.

[0010] Preferably, the driving circuit also includes a PWM logic circuit for generating a PWM signal indicating the working state of the power switch according to at least one sampling signal; the driving voltage generating circuit generates a driving signal for the power switch based on the PWM signal, and the voltage of the driving signal is clamped at the first driving voltage or the second driving voltage based on the level state of the PWM signal.

[0011] Preferably, at least some components of the negative voltage circuit, the PWM logic circuit and the driving voltage generating circuit are configured to be packaged in the same chip.

[0012] Preferably, the second driving voltage is used to ensure that the power switch can be reliably turned on or off.

[0013] Preferably, the negative voltage circuit receives a power supply voltage, converts the power supply voltage into an operating voltage, and converts the operating voltage into the second driving voltage, wherein the amplitude of the second driving voltage is consistent with the operating voltage, and the operating voltage is a positive voltage.

[0014] Preferably, the negative voltage circuit includes a first half-bridge circuit, a second half-bridge circuit, a first capacitor and a second capacitor, the first half-bridge circuit is coupled between the output end of the working voltage and the ground potential, the second half-bridge circuit is coupled between the output end of the second driving voltage and the ground potential, the first capacitor is connected across the middle node of the first half-bridge circuit and the middle node of the second half-bridge circuit, and the second capacitor is connected in parallel with the second half-bridge circuit.

[0015] Preferably, the negative voltage circuit also includes a first resistor and a first current source, the current of the first current source generates a first voltage on the first resistor, and a voltage indication signal is generated by determining the voltage range in which the first voltage is located, and the voltage indication signal is at least used to indicate the value of the operating voltage.

[0016] Preferably, the resistance of the first resistor is adjustable and corresponds to the rated driving voltage of the power switch.

[0017] Preferably, the negative voltage circuit further comprises a first linear regulator for converting the supply voltage into the operating voltage of corresponding amplitude according to the indication signal.

[0018] Preferably, the first resistor, the first capacitor and the second capacitor in the negative voltage circuit are arranged at the periphery of the chip, and the remaining components in the negative voltage circuit are arranged inside the chip.

[0019] Preferably, the negative voltage circuit further comprises a level conversion circuit, which receives a control signal of the second half-bridge circuit and converts the control signal from an amplitude relative to the ground potential to an amplitude relative to the second driving voltage.

[0020] Preferably, when the supply voltage reaches a first threshold, the negative voltage circuit is enabled to convert the operating voltage into the second driving voltage, and when the supply voltage reaches a second threshold, the PWM logic circuit is enabled to output the PWM signal, wherein the first threshold is less than the second threshold.

[0021] Preferably, the PWM logic circuit is also powered by the supply voltage.

[0022] Preferably, the supply voltage is provided by a high-voltage start-up circuit coupled to an input voltage of the switching power supply during a start-up phase, and is provided by an auxiliary winding after normal operation.

[0023] Preferably, a second linear regulator is further included to convert the supply voltage into the first driving voltage, and the first driving voltage is a positive voltage.

[0024] In a second aspect, a switching power supply is provided, comprising:

[0025] The driving circuit described above, and

[0026] The power stage circuit is used to convert the input voltage to generate the output voltage.

[0027] In a third aspect, a driver chip is provided for driving a power switch in a switching power supply, comprising:

[0028] A power supply pin coupled to an auxiliary winding to receive a power supply voltage, wherein the auxiliary winding is coupled to an inductive device in a switching power supply;

[0029] A pair of external capacitor pins, which are respectively coupled to two ends of a first capacitor, wherein the first capacitor and two half-bridge circuits inside the driving chip form a charge pump circuit to generate a second driving voltage which is a negative voltage;

[0030] A negative voltage pin coupled to a second capacitor to generate the second driving voltage on the second capacitor;

[0031] The driving pin is coupled to the control end of the power switch and is used to output the first driving voltage or the second driving voltage based on a PWM signal indicating the working state of the power switch.

[0032] Preferably, it further comprises a negative voltage regulating pin, which is coupled to a first resistor, wherein the resistance of the first resistor is adjustable and corresponds to the rated driving voltage of the power switch.

[0033] Preferably, the charge pump circuit converts the supply voltage into an operating voltage, and converts the operating voltage into the second driving voltage, wherein the amplitude of the second driving voltage is consistent with the operating voltage, and the operating voltage is a positive voltage.

[0034] Preferably, the second driving voltage is established earlier than the time when the power switch starts to work normally.

[0035] The present invention aims to provide a driving circuit in which a negative voltage circuit generates a negative voltage through a charge pump circuit, and most of the components of the negative voltage circuit are integrated inside a chip, and the chip has fewer peripheral devices, making it more convenient to use. In addition, at the initial stage of establishing the power supply voltage VCC, the negative voltage VEE begins to be established, and before the PWM signal is output, the negative voltage VEE can be established to a set voltage value, thereby effectively preventing the transistor from being turned on by mistake. On this basis, the negative voltage amplitude of the present invention is adjustable in multiple gears, which is suitable for the needs of different transistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0037] Figure 1 A schematic diagram of a switching power supply in the prior art;

[0038] Figure 2 It is a working waveform diagram of the switching power supply in the prior art;

[0039] Figure 3 A schematic diagram of a driving circuit and a switching power supply using the same according to an embodiment of the present invention;

[0040] Figure 4 is a schematic structural diagram of a driving circuit according to an embodiment of the present invention;

[0041] Figure 5 It is a partial structural schematic diagram of a negative voltage circuit according to an embodiment of the present invention;

[0042] Figure 6 is a working waveform diagram of a driving circuit according to an embodiment of the present invention;

[0043] Figure 7 It is a schematic diagram of the structure of the state selection circuit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The present invention is described below based on embodiments, but the present invention is not limited to these embodiments. In the detailed description of the present invention below, some specific details are described in detail. It is possible for a person skilled in the art to fully understand the present invention without the description of these details. In order to avoid confusing the essence of the present invention, known methods, processes, flows, components and circuits are not described in detail.

[0045] In addition, persons of ordinary skill in the art will appreciate that the drawings provided herein are for illustration purposes and are not necessarily drawn to scale.

[0046] At the same time, it should be understood that in the following description, "circuit" refers to a conductive loop composed of at least one element or subcircuit through electrical connection or electromagnetic connection. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected between" two nodes, it can be directly coupled or connected to another element or there can be an intermediate element, and the connection between the elements can be physical, logical, or a combination thereof. On the contrary, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there is no intermediate element between the two.

[0047] Unless the context clearly requires otherwise, throughout the specification and claims, the words "include", "comprising" and similar words should be interpreted in an inclusive sense rather than an exclusive or exhaustive sense; that is, in the sense of "including but not limited to".

[0048] In the description of the present invention, it should be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of the present invention, unless otherwise specified, "plurality" means two or more.

[0049] Figure 3 FIG. 1 is a schematic diagram of a driving circuit and a switching power supply using the same according to a first embodiment of the present invention. Figure 3 As shown, the switching power supply of this embodiment takes a flyback topology as an example. The flyback converter includes a power stage circuit 31 and a drive circuit 32. The power stage circuit 31 includes a power supply 31 connected in series to a voltage input terminal V IN The primary winding N between the ground potential P and the power switch Q1. In this embodiment, a current sampling resistor R is further provided between the power switch Q1 and the ground potential. CS . Input capacitor C IN Connected between the input terminal and ground potential. S With the primary winding N P Coupling, secondary side rectifier circuit (here is diode D S ) and the secondary winding N S Connect the output capacitor C O The power stage circuit 31 also includes an auxiliary winding N A and the auxiliary winding N A The voltage divider resistors R2 and R3 are used to divide the voltage at both ends. A With the primary winding N P And the secondary winding N S coupling, through the auxiliary winding N A The voltage across the two ends can obtain the output voltage V of the power stage circuit 31 O Information, secondary winding N S The current zero crossing time and current valley bottom time information are obtained. Therefore, by dividing the auxiliary winding N A The voltages at both ends are sampled to obtain the above information and control the power switch Q1 based on the above information. A It can also be connected through the diode D VCC The driving circuit 32 is provided with a supply voltage VCC.

[0050] When the power switch Q1 is a silicon carbide (SiC) transistor or other types of transistors with small parasitic capacitance and fast switching speed, in order to prevent the power switch Q1 from being mistakenly turned on, the drive circuit 32 is provided with a negative voltage drive, so that when the power switch Q1 is turned off, the control terminal is pulled down to a negative voltage to prevent the control terminal of the power switch Q1 from being mistakenly turned on due to crosstalk, which causes the control terminal to be instantaneously raised to above its turn-on threshold.

[0051] Continue to refer Figure 3 In order to optimize the existing technology and reduce the peripheral components of the chip, the driving circuit 32 of this embodiment integrates most of the components of the negative voltage circuit that provides the negative voltage driving power supply function inside the chip, and only a small number of components outside the chip need to be connected externally. Specifically, in this embodiment, the driving circuit 32 only integrates the first resistor R1 and the first capacitor C fly With the second capacitor C VEE It is arranged on the periphery of the chip, and the other components in the negative voltage circuit are arranged inside the chip.

[0052] Figure 4 FIG. 4 is a schematic diagram of the structure of the driving circuit 40 according to an embodiment of the present invention. Figure 4 As shown, the driving circuit 40 includes a negative voltage circuit 41, a PWM logic circuit 42 and a driving voltage generating circuit 43. At least some components of the negative voltage circuit 41, the PWM logic circuit 42 and the driving voltage generating circuit 43 are configured to be packaged in the same driving chip 45.

[0053] In the embodiment of the present invention, the negative voltage circuit 41 includes a first resistor R1 disposed on the periphery of the chip 45, a first capacitor C fly With the second capacitor C VEE , a linear voltage regulator circuit 412 for converting the power supply voltage VCC into an operating voltage VDD of corresponding amplitude, and a collection module 411 of other modules in the negative voltage circuit 41, wherein the linear voltage regulator circuit 412 and the collection module 411 are both packaged inside the chip 45.

[0054] Specifically, the negative voltage circuit 41 receives the power supply voltage VCC, converts the power supply voltage VCC into the working voltage VDD, and converts the working voltage VDD into the second driving voltage VEE for driving the power switch Q1, and the second driving voltage VEE is a negative voltage. Further, the amplitude of the second driving voltage VEE is consistent with the working voltage VDD, and the working voltage VDD is a positive voltage.

[0055] The resistance of the first resistor R1 in the negative voltage circuit 41 is adjustable, and the resistance value corresponds to the rated driving voltage of the power switch Q1, so that an operating voltage VDD of an amplitude suitable for the power switch Q1 to be driven in the current usage scenario can be selectively generated inside the negative voltage circuit 41, thereby making the driving circuit of the present invention compatible with different transistors.

[0056] In a preferred embodiment, the first resistor R1 can be connected to the first current source, and the current of the first current source generates a first voltage on the first resistor R1. A voltage indication signal is generated by determining the voltage range in which the first voltage is located. The voltage indication signal is at least used to indicate the value of the working voltage VDD. In the embodiment of the present invention, the linear voltage stabilizing circuit 412 receives the voltage indication signal to convert the power supply voltage VCC into the working voltage VDD corresponding to the voltage indication signal. Since the amplitude of the second driving voltage VEE is consistent with the working voltage VDD, the negative voltage circuit 41 can generate a second driving voltage VEE of the power switch Q1 adapted to the current application so that the power switch Q1 can be reliably turned off. Furthermore, the voltage indication signal can also be used to indicate the first driving voltage V clamp , so that the power switch Q1 is reliably turned on; or, the negative second drive voltage VEE makes the power switch Q1 reliably turned on, and the first drive voltage V clamp The value of makes the power switch Q1 turn off reliably.

[0057] The PWM logic circuit 42 is used to generate a PWM signal indicating the working state of the power switch Q1 according to at least one sampling signal. In the embodiment of the present invention, the PWM logic circuit 42 receives a current sampling resistor R CS The current sampling signal on the auxiliary winding N A The voltage sampling signal on the PWM signal is generated.

[0058] The driving voltage generating circuit 43 is coupled to the PWM logic circuit 42 and is used to generate a driving signal DRV of the power switch Q1 according to the PWM signal. The voltage of the driving signal DRV is clamped at a first driving voltage V based on the level state of the PWM signal. clamp Or the second driving voltage VEE.

[0059] Taking the power switch Q1 as a first type of transistor that is turned on at a high level and turned off at a low level as an example, when the PWM signal indicates that the power switch Q1 needs to be turned on, the embodiment of the present invention clamps the control terminal of the power switch Q1 at the first driving voltage V clamp , the first driving voltage V clampIt is a positive voltage and can ensure that the power switch Q1 is reliably turned on; when the PWM signal indicates that the power switch Q1 needs to be turned off, the embodiment of the present invention clamps the control end of the power switch Q1 to a second drive voltage VEE, and the second drive voltage VEE is a negative voltage and can ensure that the power switch Q1 is reliably turned off.

[0060] It should be noted that the present invention does not limit the type of the power switch Q1. The power switch Q1 may also be a second type of transistor that is turned on at a low level and turned off at a high level. In this case, when the PWM signal indicates that the power switch Q1 needs to be turned on, the embodiment of the present invention clamps the control terminal of the power switch Q1 to the second drive voltage VEE, which is a negative voltage and can ensure that the power switch Q1 is reliably turned on; when the PWM signal indicates that the power switch Q1 needs to be turned off, the embodiment of the present invention clamps the control terminal of the power switch Q1 to the first drive voltage V clamp , the first driving voltage V clamp It is a positive voltage and can ensure that the power switch Q1 is reliably turned off.

[0061] Preferably, the driving voltage generating circuit 43 is composed of a transistor M1 and a transistor M2 connected in series, wherein one end of the transistor M1 receives the first driving voltage V clamp The second end is connected to the transistor M2, the other end of the transistor M2 receives the second driving voltage VEE, and outputs the driving signal DRV at the common node of the transistor M1 and the transistor M2. The driving signal DRV is clamped to the first driving voltage V when the transistor M1 is turned on. clamp , is clamped at the second driving voltage VEE when the transistor M2 is turned on.

[0062] Taking the power switch Q1 as the first type transistor as an example, when the level state of the PWM signal indicates that the power switch Q1 is turned on, the transistor M1 is turned on, and the drive signal DRV is clamped at the first drive voltage V clamp , the control end of the power switch Q1 is pulled high to be turned on; when the level state of the PWM signal indicates that the power switch Q1 is turned off, the transistor M2 is turned on, the drive signal DRV is clamped to the second drive voltage VEE, and the control end of the power switch Q1 is pulled low to be turned off. Since the second drive voltage VEE is a negative voltage, when a large voltage change rate dv / dt caused by the rapid switching of the transistor is coupled to the control end of the power switch Q1, it is not easy for the voltage at the control end of the power switch Q1 to rise above its conduction threshold, thereby causing the power switch Q1 to be turned on by mistake. Therefore, the embodiment of the present invention enhances the reliability of the system.

[0063] The driving circuit 40 also includes a high voltage startup circuit 44, combined with Figure 3 and Figure 4It can be seen that the high voltage startup circuit 44 is coupled to the input terminal of the switching power supply to receive the input voltage V IN , and then generate a power supply voltage VCC to start the chip. Optionally, the power supply voltage VCC is provided by the high-voltage startup circuit 44 during the startup phase, and is supplied by the auxiliary winding N after normal operation. A Provided that, in an embodiment of the present invention, the auxiliary winding N A Through the diode D VCC The capacitor C VCC The power supply voltage VCC is generated and supplied to the chip 45 through the VCC pin. Meanwhile, the output end of the high voltage startup circuit 44 is also coupled to the VCC pin. The PWM logic circuit 42 is also powered by the power supply voltage VCC.

[0064] The driving chip 45 includes a power supply pin VCC coupled to an auxiliary winding N A To receive the supply voltage VCC, the auxiliary winding N A A pair of external capacitor pins CVP and CVN are coupled to the first capacitor C fly The first capacitor C fly The two half-bridge circuits in the driving chip 45 form a charge pump circuit to generate a second driving voltage VEE which is a negative voltage; the negative voltage pin VEE is connected to the second capacitor C VEE coupled to the second capacitor C VEE The driving pin DRV is coupled to the control terminal of the power switch Q1 and is used to output the first driving voltage V based on the PWM signal indicating the working state of the power switch Q1. clamp or the second driving voltage VEE; a negative voltage adjustment pin VEESET, which is coupled to the first resistor R1, the resistance of the first resistor R1 is adjustable and corresponds to the rated driving voltage of the power switch Q1. In addition, the driving chip 45 also includes a voltage detection pin VSEN and a current detection pin ISEN.

[0065] like Figure 5 FIG. 4 is a partial structural diagram of a negative voltage circuit 41 according to a preferred embodiment of the present invention. Figure 5 The circuit structure diagram mainly shows that the negative voltage circuit 41 converts the working voltage VDD into the second driving voltage VEE for driving the power switch Q1. In the embodiment of the present invention, the negative voltage circuit 41 converts the working voltage VDD into a negative voltage, namely the second driving voltage VEE, through a charge pump circuit.

[0066] The charge pump circuit 50 includes a first half-bridge circuit 51, a second half-bridge circuit 52, a first capacitor C fly And the second capacitor C VEEThe first half-bridge circuit 51 is coupled between the output terminal of the working voltage VDD and the ground potential, the second half-bridge circuit 52 is coupled between the output terminal of the second driving voltage VEE and the ground potential, and the first capacitor C fly The second capacitor C is connected between the middle node of the first half-bridge circuit 51 and the middle node of the second half-bridge circuit 52. VEE Connected in parallel with the second half-bridge circuit 52 .

[0067] The working process of the charge pump circuit 50 is as follows: when the transistors M3 and M6 are turned on so that the path 1 is turned on, there is a voltage relationship V CVP -V CVN = VDD; then path 1 is turned off, transistors M4 and M5 are turned on so that path 2 is turned on, due to the first capacitor C fly The capacitor voltage cannot change suddenly, and V CVP =0, then there is a voltage relationship VEE = V CVN -V CVP =-VDD, so that the positive voltage working voltage VDD can be converted into the negative voltage second driving voltage VEE, and the two have equal amplitudes. Therefore, the amplitude of the second driving voltage VEE can also be adjusted by adjusting the amplitude of the working voltage VDD so that it meets the driving requirements of the power switch Q1.

[0068] Preferably, the transistors M3 and M6 are turned on and off based on the same control signal Pg, and the transistors M4 and M5 are turned on and off based on the same control signal Ng. Further, since the second half-bridge circuit 52 is coupled between the node of the second driving voltage VEE and the ground potential, a level conversion circuit 53 is also provided in the charge pump circuit 50, which is used to receive the control signal of the second half-bridge circuit 52 and convert the control signal from an amplitude relative to the ground potential to an amplitude relative to the second driving voltage VEE to adapt to the driving conditions of the transistors in the second half-bridge circuit 52.

[0069] Figure 6 1 is a working waveform diagram of the driving circuit of the embodiment of the present invention. As shown in the figure, when the power supply voltage VCC reaches the first threshold VEE_EN, that is, at time t1 in the figure, the negative voltage circuit 41 is enabled to start working and directly converts the working voltage VCC into the second driving voltage VEE; when the power supply voltage VCC reaches the second threshold V UVLO_ON (That is, the chip startup threshold V UVLO_ON ), the chip 45 starts to work, and the PWM logic circuit 42 outputs a PWM signal, wherein the first threshold VEE_EN is less than the second threshold V UVLO_ON .

[0070] Combination Figure 4 and Figure 6 It can be seen that when the driving circuit 40 of the embodiment of the present invention starts to start, the input voltage VIN Through the high voltage HV foot and the internal high voltage startup circuit 44 to the capacitor C VCC The negative voltage circuit 41 is enabled, and the supply voltage VCC is converted into the working voltage VDD through the linear voltage regulator circuit 412 inside the internal negative voltage circuit 41. The working voltage VDD is then converted into the second driving voltage VEE through the charge pump circuit 50. The second driving voltage VEE begins to build up. By setting appropriate peripheral circuits and internal thresholds, the second driving voltage VEE can be set to the starting threshold V UVLO_ON Before the establishment is completed, the PWM signal is when the supply voltage VCC reaches the start threshold V UVLO_ON It starts to be generated after that, thereby avoiding the problem in the aforementioned prior art solution that the second driving voltage VEE starts to be established only after the PWM signal is generated, resulting in the inability to effectively prevent false switching in the initial stage of establishing the second driving voltage VEE due to the low voltage.

[0071] Furthermore, the negative voltage circuit 41 of the embodiment of the present invention further includes a state selection circuit 70, referring to Figure 7 In the embodiment of the present invention, the state selection circuit 70 includes a first resistor R1 , a switch K1 , a first current source I1 , a one-shot circuit 71 , a comparison circuit 72 , and a logic and state latch circuit 73 .

[0072] Specifically, the first resistor R1 is connected to the first current source I1. When the power supply voltage VCC reaches the first threshold VEE_EN, the enable signal V EN When valid, the first switch K1 is controlled by the enable signal V EN The first resistor R1 is turned on, and the current of the first current source I1 generates a first voltage V1 on the first resistor R1. The voltage indication signal VSi is generated by judging the voltage range of the first voltage V1. The voltage indication signal VSi is at least used to indicate the value of the working voltage VDD, 1≤i≤n, and n is a natural number not less than 2. It should be noted that the present invention does not limit the specific structure of the state selection circuit 70, as long as the voltage range recognition can be realized.

[0073] More specifically, the comparison circuit 72 has a plurality of comparators, which correspond to a plurality of reference voltages ref1 to fefn, respectively, and compare the first voltage V1 with the plurality of reference voltages ref1 to fefn to generate a plurality of comparison signals. The logic and state latch circuit 73 generates voltage indication signals VS1 to VSn by performing logic operations on the level states of the plurality of comparison signals and latching them. The voltage indication signal VSi can characterize the voltage range in which the first voltage V1 is located. Since the resistance value of the first resistor R1 is adjustable, and the resistance value corresponds to the rated driving voltage of the power switch Q1, the chip obtains the driving voltage requirement corresponding to the current application scenario through the first resistor R1, and can selectively generate the working voltage VDD and the first driving voltage V of the amplitude suitable for the power switch Q1 to be driven in the current application scenario in the negative voltage circuit 41. clamp , achieving multi-level adjustable driving voltage, and ultimately making the driving circuit of the present invention compatible with different transistors.

[0074] It can be seen that in the driving circuit of the present invention, the negative voltage circuit generates negative voltage through the charge pump circuit, and most of the components of the negative voltage circuit are integrated inside the chip. The chip has fewer peripheral devices, making it more convenient to use. In addition, in the early stage of the establishment of the power supply voltage VCC, the negative voltage VEE begins to be established. Before the PWM signal is output, the negative voltage VEE can be established to the set voltage value, thereby effectively preventing the transistor from being turned on by mistake. On this basis, the negative voltage amplitude of the present invention is adjustable in multiple gears, which is suitable for the needs of different transistors.

[0075] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A driving circuit, comprising: A driving voltage generating circuit, wherein the positive terminal is coupled to the first driving voltage, the negative terminal is coupled to the second driving voltage, and the output terminal is coupled to the control terminal of the power switch; A negative voltage circuit, used for generating the second driving voltage for driving the power switch, wherein the second driving voltage is a negative voltage; The second driving voltage is established earlier than the time when the power switch starts to work normally.

2. The driving circuit according to claim 1, characterized in that: The driving circuit also includes a PWM logic circuit for generating a PWM signal indicating the working state of the power switch according to at least one sampling signal; the driving voltage generating circuit generates a driving signal for the power switch based on the PWM signal, and the voltage of the driving signal is clamped at the first driving voltage or the second driving voltage based on the level state of the PWM signal.

3. The driving circuit according to claim 1, characterized in that: At least some components of the negative voltage circuit, the PWM logic circuit, and the driving voltage generating circuit are configured to be packaged in the same chip.

4. The driving circuit according to claim 1, characterized in that: The second driving voltage is used to ensure that the power switch can be turned on or off reliably.

5. The driving circuit according to claim 1, characterized in that: The negative voltage circuit receives a power supply voltage, converts the power supply voltage into an operating voltage, and converts the operating voltage into the second driving voltage, wherein the amplitude of the second driving voltage is consistent with the operating voltage, and the operating voltage is a positive voltage.

6. The driving circuit according to claim 5, characterized in that: The negative voltage circuit includes a first half-bridge circuit, a second half-bridge circuit, a first capacitor and a second capacitor. The first half-bridge circuit is coupled between the output end of the working voltage and the ground potential, the second half-bridge circuit is coupled between the output end of the second driving voltage and the ground potential, the first capacitor is connected across the middle node of the first half-bridge circuit and the middle node of the second half-bridge circuit, and the second capacitor is connected in parallel with the second half-bridge circuit.

7. The driving circuit according to claim 6, characterized in that: The negative voltage circuit also includes a first resistor and a first current source. The current of the first current source generates a first voltage on the first resistor. A voltage indication signal is generated by determining the voltage range in which the first voltage is located. The voltage indication signal is at least used to indicate the value of the operating voltage.

8. The driving circuit according to claim 7, characterized in that: The resistance value of the first resistor is adjustable and corresponds to the rated driving voltage of the power switch.

9. The driving circuit according to claim 7, characterized in that: The negative voltage circuit also includes a first linear regulator, which is used to convert the supply voltage into the working voltage of corresponding amplitude according to the indication signal.

10. The driving circuit according to claim 7, characterized in that: The first resistor, the first capacitor and the second capacitor in the negative voltage circuit are arranged on the periphery of the chip, and the remaining components in the negative voltage circuit are arranged inside the chip.

11. The driving circuit according to claim 6, characterized in that: The negative voltage circuit further includes a level conversion circuit, which receives a control signal of the second half-bridge circuit and converts the control signal from an amplitude relative to the ground potential to an amplitude relative to the second driving voltage.

12. The driving circuit according to claim 2, characterized in that: When the supply voltage reaches a first threshold, the negative voltage circuit is enabled to convert the operating voltage into the second driving voltage, and when the supply voltage reaches a second threshold, the PWM logic circuit is enabled to output the PWM signal, wherein the first threshold is less than the second threshold.

13. The driving circuit according to claim 2, characterized in that: The PWM logic circuit is also powered by the supply voltage.

14. The driving circuit according to claim 5, characterized in that: The supply voltage is provided by a high-voltage start-up circuit coupled to an input voltage of the switching power supply during a start-up phase, and is provided by an auxiliary winding after normal operation.

15. The driving circuit according to claim 5, characterized in that: A second linear regulator is also included, which is used to convert the supply voltage into the first driving voltage, and the first driving voltage is a positive voltage.

16. A switching power supply comprising: The drive circuit and the power stage circuit as described in any one of claims 1 to 15 are used to convert the input voltage to generate the output voltage.

17. A driver chip for driving a power switch in a switching power supply, comprising: A power supply pin coupled to an auxiliary winding to receive a power supply voltage, wherein the auxiliary winding is coupled to an inductive device in a switching power supply; A pair of external capacitor pins, which are respectively coupled to two ends of a first capacitor, wherein the first capacitor and two half-bridge circuits inside the driving chip form a charge pump circuit to generate a second driving voltage which is a negative voltage; A negative voltage pin coupled to a second capacitor to generate the second driving voltage on the second capacitor; The driving pin is coupled to the control end of the power switch and is used to output the first driving voltage or the second driving voltage based on a PWM signal indicating the working state of the power switch.

18. The driver chip according to claim 17, characterized in that: It also includes a negative voltage adjustment pin, which is coupled to a first resistor. The resistance of the first resistor is adjustable and corresponds to the rated driving voltage of the power switch.

19. The driver chip according to claim 17, characterized in that: The charge pump circuit converts the supply voltage into an operating voltage, and converts the operating voltage into the second driving voltage, wherein the amplitude of the second driving voltage is consistent with the operating voltage, and the operating voltage is a positive voltage.

20. The driver chip according to claim 17, characterized in that: The second driving voltage is established earlier than the time when the power switch starts to work normally.

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