Leakage-based start-up circuit

Abstract

The invention relates to a leakage-based start-up circuit. A start-up circuit includes a first circuit branch coupled between an input node and an output node and a second circuit branch coupled between the input node and the output node. The first circuit generates a first current, and the second circuit branch absorbs current from the first node based on the first current. The third circuit branch is coupled between the input node and the output node and supplies current to the second node based on the voltage at the first node, thereby generating a feedback voltage at the second node. The first circuit branch increases the first current based on the feedback voltage, thereby increasing the current drawn from the first node by the second circuit branch, and increases the current supplied to the second node by the third circuit branch, thereby generating a start-up current at the output node.

Description

Technical Field

[0001] The present disclosure relates to startup of an integrated circuit, and more particularly to a circuit for performing startup of an integrated circuit in a manner that is not affected by temperature, supply voltage, or device-to-device variations. Background Art

[0002] When an integrated circuit (IC) device is powered by a battery, it enters the startup phase. This period is characterized by providing the required bias points, voltages, and currents to various internal nodes. The goal of this startup phase is to prevent potential problems that may occur during the rise of the power supply voltage, which may put the circuit into an undesirable operating state.

[0003] During the startup phase, leakage currents play an important role in charging the internal nodes of the IC. However, these currents may vary depending on process parameters, corner cases, and operating temperature. This variability may interfere with consistent and accurate bias establishment, leading to potential device reliability issues during the startup phase. In addition, leakage current models used in existing simulations may be inaccurate. Measurement noise during device characterization may distort the model and thus affect the simulation results, leading to incorrect estimates of leakage current. Therefore, startup circuit topologies that are not only leakage-dependent but also robust to these variations are necessary.

[0004] like Figure 1 As shown, the first known startup circuit includes a resistor connected between an input voltage VIN (e.g., a battery voltage) and a node Ng. The startup circuit also includes a Zener diode Dz, whose cathode is connected to the node Ng and whose anode is connected to the ground. The power transistor T supplies power to the load circuit within the IC from the input voltage, and its gate is controlled by the voltage VZ at the node Ng. During startup, the startup current I_startup flows through the resistor R to form a voltage VZ at the node Ng.

[0005] The problem with this first known startup circuit is that it provides correct startup over the entire possible range of supply voltages VIN. For some high voltage applications this range can be quite wide. Therefore, the resistor R needs to be small enough to provide enough startup current I_startup to establish the correct voltage VZ with an appropriate slope. At the same time, it should be large enough to limit the power dissipation when the supply voltage VIN is high. If the supply voltage VIN is large, the resistor R is physically large, consuming an undesirably large area.

[0006] like Figure 2As shown, the second known startup circuit includes a diode, whose cathode is connected to the input voltage VIN and whose anode is connected to the node Ng. The cathode of the Zener diode Dz is connected to the node Ng and its anode is connected to the ground. The gate of the power transistor T is controlled by the voltage VZ present at the node Ng. During startup, the startup current I_startup flows through the diode D to form the voltage VZ at the node Ng.

[0007] A second problem with known startup circuits is that the leakage current through diode D is highly sensitive to process, voltage and temperature variations. Therefore, determining the proper size of diode D to allow sufficient startup current I_startup at process corners is challenging, especially considering the limitations of existing MOS diode models.

[0008] Therefore, further development is needed to provide reliable startup functionality across process variations, regardless of the magnitude of the startup current. Therefore, the goal of such development is to overcome the limitations imposed by process, corner and temperature dependencies and inaccuracies in leakage current simulation without consuming too much device area. Summary of the invention

[0009] A startup circuit is disclosed herein, including a startup current circuit. The startup current circuit includes a first circuit branch coupled between an input node and an output node, the first circuit branch being configured to generate a first current, a second circuit branch coupled between the input node and the output node, the second circuit branch being configured to sink current from the first node based on the first current, and a third circuit branch coupled between the input node and the output node, the third circuit branch being configured to supply current to the second node based on a voltage at the first node, thereby generating a feedback voltage at the second node. The first circuit branch is configured to increase the first current based on the feedback voltage, thereby increasing the current sunk by the second circuit branch from the first node, and increasing the current supplied to the second node by the third circuit branch, thereby generating a startup current at the output node.

[0010] The first circuit branch may include a diode-coupled transistor connected between the input node and the third node, a first mirror transistor connected between the third node and the output node and having a control terminal connected to the third node, and a feedback transistor connected between the input node and the third node and having a control terminal coupled to receive a feedback voltage.

[0011] The diode-coupled transistor and the first mirror transistor may be n-channel transistors, wherein the drain of the diode-coupled transistor is connected to the input node, the source thereof is connected to the third node, and the gate thereof is connected to the third node, and the drain of the first mirror transistor is connected to the third node, the source thereof is connected to ground, and the gate thereof is connected to the third node. The feedback transistor may be an n-channel transistor, wherein the drain thereof is connected to the input node, the source thereof is connected to the third node, and the gate thereof is connected to the second node.

[0012] The diode-coupled transistor and the first mirror transistor may be n-channel transistors, wherein the drain of the diode-coupled transistor is connected to the input node, the source thereof is connected to the third node, and the gate thereof is connected to the third node, and the drain of the first mirror transistor is connected to the third node, the source thereof is connected to ground, and the gate thereof is connected to the third node. The feedback transistor may be a p-channel transistor, wherein the source thereof is connected to the input node, the drain thereof is connected to the third node, and the gate thereof is connected to the second node.

[0013] The second circuit branch may include a second mirror transistor connected between the input node and the first node and having a control terminal connected to the first node, a sink transistor connected between the first node and the output node and having a control terminal connected to the first node, and a third mirror transistor connected between the first node and the output node through a resistor and having a control terminal connected to a third node. The second mirror transistor and the sink transistor may be p-channel transistors, wherein the source of the second mirror transistor is connected to the input node, its drain is connected to the first node, and its gate is connected to the first node, and the sink transistor has a source connected to the first node, its drain is connected to ground, and its gate is connected to the first node. The third mirror transistor may be an n-channel transistor, whose drain is connected to the first node, whose source is coupled to ground through a resistor, and whose gate is connected to the third node.

[0014] The third circuit branch may include a fourth mirror transistor connected between the input node and the second node and having a control terminal connected to the first node, the fourth mirror transistor being in a current mirroring relationship with the second mirror transistor, and a fifth mirror transistor connected between the second node and ground and having a control terminal connected to the third node, the fifth mirror transistor being in a current mirroring relationship with the first mirror transistor.

[0015] The fourth mirror transistor may be a p-channel transistor having its source connected to the input node, its drain connected to the second node, and its gate connected to the first node, and the fifth mirror transistor may be an n-channel transistor having its drain connected to the second node, its source connected to ground, and its gate connected to the first node.

[0016] A power transistor may be connected between the input node and ground via a load, the power transistor having a control terminal connected to the output node. The Zener diode may have a cathode connected to the output node and an anode connected to ground.

[0017] A mirror transistor may be connected between the input node and the control node, the mirror transistor having a control terminal connected to the first node. The Zener diode may have a cathode connected to the control node and an anode connected to an output node, the output node being connected to ground. A power transistor may be connected between the input node and ground through a load, the power transistor having a control terminal connected to the control node.

[0018] The present invention also discloses a startup circuit including a startup current circuit. The startup current circuit includes: a diode-coupled transistor connected between an input node and a third node, a feedback transistor connected between the input node and the first node and having a control terminal coupled to receive a feedback voltage at the second node, a first current mirror having an input connected to the third node and an output connected to the second node, a second current mirror having an input connected to the first node and an output connected to the second node, a first absorption transistor connected between the first node and the output node through a resistor and having a control terminal connected to the control node of the first current mirror, and a second absorption transistor connected between the first node and the output node and having a control terminal connected to the first node.

[0019] The first current mirror may include a first n-channel transistor having a drain connected to the third node, a source connected to the output node, and a gate connected to the third node; and a second n-channel transistor having a drain connected to the second node, a source connected to the output node, and a gate connected to the third node.

[0020] The feedback transistor may be an n-channel transistor having its drain connected to the input node, its source connected to the third node, and its gate connected to the second node.

[0021] The feedback transistor may be a p-channel transistor having its source connected to the input node, its drain connected to the third node, and its gate connected to the second node.

[0022] The second current mirror may include a first p-channel transistor having a source connected to the input node, a drain connected to the first node, and a gate connected to the first node; and a second p-channel transistor having a source connected to the input node, a drain connected to the second node, and a gate connected to the first node.

[0023] The first sink transistor may be an n-channel transistor having its drain connected to the first node, its source connected to the output node through a resistor, and its gate connected to the control node of the first current mirror.

[0024] The second absorption transistor may be a p-channel transistor having its source and gate connected to the first node and its drain connected to the output node. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 Schematic diagram of a first prior art starting circuit.

[0026] Figure 2 Schematic diagram of a first prior art starting circuit.

[0027] Figure 3 is a schematic diagram of the starting current circuit disclosed in this article.

[0028] Figure 3A It is shown Figure 3 A graph of the starting current circuit voltage during operation.

[0029] Figure 4 is disclosed herein and is incorporated herein by reference Figure 3 Schematic diagram of the first starting circuit of the starting current circuit.

[0030] Figure 5 is disclosed herein and is incorporated herein by reference Figure 3 Schematic diagram of the second starting circuit of the starting current circuit.

[0031] Figure 6 is a schematic diagram of an alternative starting current circuit. DETAILED DESCRIPTION

[0032] The following disclosure enables those skilled in the art to make and use the subject matter described herein. The general principles outlined in this disclosure may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of the disclosure. It is not intended to limit the disclosure to the illustrated embodiments, but rather to give it the widest scope consistent with the principles and features disclosed or suggested herein.

[0033] Note that in the following description, unless otherwise specified, any resistor or resistance mentioned is a discrete device and not a simple electrical wire between two points. Therefore, any resistor or resistance connected between two points has a higher resistance than a wire between the two points, and such a resistor or resistance cannot be interpreted as a wire. Similarly, unless otherwise specified, any capacitor or capacitance mentioned is a discrete device and is not a parasitic element unless otherwise specified. Furthermore, unless otherwise specified, any inductor or inductance mentioned is a discrete device and is not a parasitic element unless otherwise specified.

[0034] Reference now Figure 3 and 3AThe startup current circuit 10 is described. The startup current circuit 10 includes a high-voltage n-channel transistor M0 (e.g., a transistor capable of maintaining a power supply voltage VIN as its drain-to-source voltage, VIN being on the order of tens to hundreds of volts) and a high-voltage n-channel transistor M1, the drain of the high-voltage n-channel transistor M0 being connected to the input voltage node Nin and its source and gate being connected to the node N0 (e.g., the transistor M0 is diode-coupled), the drain and gate of the high-voltage n-channel transistor M1 being connected to the node N0 and its source being connected to the node Nn (e.g., the transistor M1 is diode-coupled). The drain of the high-voltage n-channel transistor M2 being connected to the node Nin, its source being connected to the node N0, and its gate being connected to the node N2 to receive the feedback voltage VFBK therefrom. The N-channel transistors M0, M1, and M2 are matched (e.g., same MOS type, same size).

[0035] In addition, the source and gate of the high-voltage p-channel transistor M7 are connected to the node N1, and the drain thereof is connected to the node Nn. The source of the high-voltage p-channel transistor M5 is connected to the node Nin, and the drain and gate thereof are connected to the node N1, and the source of the high-voltage p-channel transistor M6 is connected to the node Nin, and the drain and gate thereof are connected to the node N2. The p-channel transistors M5, M6, and M7 are matched (e.g., same MOS type, same size).

[0036] The drain of high-voltage n-channel transistor M3 is connected to node N1, its source is coupled to node Nn through resistor Rr, and its gate is connected to node N0. The drain of high-voltage n-channel transistor M4 is connected to node N2, its source is connected to node Nn, and its gate is connected to node N0.

[0037] When the power supply voltage VIN rises, Figure 3A As shown in FIG. 1 , before time T2, the drain-to-source voltage VDS across n-channel transistors M0 and M2 (which are connected in parallel) begins to increase. In contrast, at startup, the VDS across n-channel transistor M1 is zero. Since n-channel transistors M0, M1, and M2 are matched (meaning that for the same given VDS, their leakage currents are the same), the leakage current flowing from the power supply node Nin through the parallel n-channel transistors M0 and M2 is greater than the leakage current flowing through the n-channel transistor M1, which can be mathematically expressed as:

[0038]

[0039] As a result of this inequality, the voltage at node N0 rises, beginning to compensate for the leakage current due to the matching of n-channel transistors M0, M1, and M2. and The gate-to-source VGS voltage of n-channel transistor M1 is increased by process or temperature variations in the embodiment of the present invention.

[0040] When the VGS voltage of the n-channel transistor M1 increases, the leakage current begins to flow therethrough, and this current is replicated by n-channel transistors M3 and M4 because they are in a current mirror arrangement with n-channel transistor M1. Since transistor M7 is p-channel, the leakage current drawn by n-channel transistor M3 from node N1 is This is used to start turning on transistor M7. Since the p-channel transistors M7 and M5 are matched, this means that the leakage current flowing from the power supply Nin through the p-channel transistor M5 is is less than the leakage current flowing through the parallel combination of p-channel transistor M7 and n-channel transistor M3, which can be mathematically expressed as:

[0041]

[0042] As a result of this inequality, the voltage at node N1 continues to drop, beginning to increase the gate-to-source voltage of p-channel transistor M5 and, therefore, increasing the leakage current flowing through M5. Since p-channel transistors M5 and M6 are in a current mirror relationship, this leakage current is then replicated in transistor M6. Note that the gate voltage of p-channel transistor M6 (and therefore its gate-to-source voltage VGS) is defined by the voltage at node N1, which in turn is affected by the leakage current flowing through p-channel transistor M7 and n-channel transistor M3.

[0043] Therefore, if Figure 3A As shown, before time t1, the voltage VFBK at node N2 begins to rise, closing the feedback loop with n-channel transistor N2, setting the gate-to-source voltage VGS across n-channel transistor M2. This increase in current flowing through n-channel transistor M2 increases the voltage at node N0, and thus increases the gate-to-source voltage VGS of n-channel transistor M1. Increasing the VGS of n-channel transistor M1 in turn increases the VGS of n-channel transistors M3 and M4. At this point, the startup current circuit 10 thus enters a no-leakage region, where the current I flowing through n-channel transistor M3 will be controlled by the following relationship:

[0044]

[0045] Here, α=0.5 is the mirror ratio between n-channel transistors M3 and M4, ΔV gsM3 / M4 is the difference between the gate-to-source voltages VGS of transistors M3 and M4. Therefore, the current I flowing through n-channel transistor M3 does not depend on the input voltage VIN, but depends on the resistance of resistor Rr and the size of n-channel transistors M3 and M4, as Figure 3A As shown after time T2.

[0046] The starting current circuit 10 may be modified, for example, as Figure 6 As shown, transistor M2 is a p-channel transistor, allowing efficient start-up performance even at lower supply voltages.

[0047] The design of the startup current circuit 10 helps to ensure that the startup current remains substantially unaffected by the power supply voltage VIN, the manufacturing process, and the temperature. This reduces power consumption and area occupancy, thereby providing a consistent startup function under various conditions. In addition, the design of the startup current circuit 10 maximizes the efficiency of component use because it uses high-voltage (HV) transistors M0-M6 but uses low-voltage resistors Rr (e.g., resistors with a safe operating voltage range lower than VIN, such as 1.9V, 3.3V, or 5V). Considering that HV transistors generally take up less space than HV resistors, this leads to a reduction in area occupancy at the same power consumption. This reduces area consumption while maintaining power efficiency. Finally, another advantage in the design of the startup current circuit 10 is that it is independent of the absolute value of the leakage current, because the startup function depends on the matching of the transistors, making it unaffected by changes in device modeling or substantial process changes. By focusing on transistor matching rather than leakage current values, the startup current circuit 10 exhibits a level of operating stability and consistency that exceeds prior art methods. Therefore, in summary, the design of the startup current circuit 10 provides benefits in terms of energy efficiency, space efficiency, and operating stability.

[0048] Figure 4 and Figure 5 An example startup circuit using the startup current circuit 10 is shown. Figure 4 The startup circuit 20 corresponds to Figure 1 , but the resistor R is replaced by the startup current circuit 10. Therefore, here, the node Nn of the startup current circuit 10 is connected to the node Ng of the startup circuit 20, and the drain of the power transistor T is connected to the node Nin. The source of the power transistor T is coupled to the ground through the load (e.g., the internal circuit), and the gate of the power transistor T is coupled to the node Ng. The cathode of the Zener diode Dz is connected to the node Ng, and the anode is connected to the ground. This startup circuit 20 is suitable for applications with a relatively high input voltage VIN.

[0049] Figure 5 The startup circuit 30 includes a p-channel transistor M8, which is arranged in a mirror image with the p-channel transistors M5 and M6 and replaces Figure 2The diode D has its source connected to the input node Nin, its drain connected to the node Ng, and its gate connected to the node N1 of the startup current circuit 10. The cathode of the Zener diode Dz is connected to the node Ng, and its anode is connected to the ground. The drain of the power transistor T is connected to the input node Nin, its source is coupled to the ground through the load, and its gate is connected to the node Ng. The node Nn is connected to the ground. The startup circuit 30 is suitable for applications with relatively low input voltage VIN.

[0050] Thus, note that the startup current circuit 10 can be used with startup circuits over a wide input voltage range because it is very versatile and can be integrated into any high voltage design that requires low power and compact startup current generation. This applicability extends to bandgap and linear voltage regulators, whether they are directly connected to the supply voltage or not. These components typically require a startup current to properly establish the operating point, thus preventing them from stabilizing at any undesirable stable point. Depending on the application details, such as power consumption and area occupied, the startup current can be adjusted by simply changing the resistor value.

[0051] In addition, the starting current generated by the starting current circuit 10 can be directly used or mirrored multiple times with different factors according to specific design requirements, providing a wide range of current values ​​for different applications.

[0052] Finally, it is obvious that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the present disclosure.

[0053] Although the present disclosure has been described with a limited number of embodiments, those skilled in the art having benefit of this disclosure may conceive of other embodiments that do not depart from the scope of the disclosure. In addition, those skilled in the art may conceive of embodiments that represent various combinations of the embodiments disclosed herein manufactured in various ways.

Claims

1. A starting circuit, comprising: Starting current circuit, comprising: a first circuit branch coupled between the input node and the output node, the first circuit branch configured to generate a first current; a second circuit branch coupled between the input node and the output node, the second circuit branch configured to sink current from the first node based on the first current; and a third circuit branch coupled between the input node and the output node, the third circuit branch configured to supply current to a second node based on a voltage at the first node to generate a feedback voltage at the second node; The first circuit branch is configured to increase the first current based on the feedback voltage, thereby increasing the current absorbed by the second circuit branch from the first node and increasing the current supplied by the third circuit branch to the second node, thereby generating a startup current at the output node.

2. The startup circuit according to claim 1, wherein the first circuit branch comprises: a diode-coupled transistor connected between the input node and a third node; a first mirror transistor connected between the third node and the output node and having a control terminal connected to the third node; as well as A feedback transistor is connected between the input node and the third node and has a control terminal coupled to receive the feedback voltage.

3. The starting circuit according to claim 2, wherein the diode-coupled transistor and the first mirror transistor are n-channel transistors, the diode-coupled transistor having a drain connected to the input node, a source connected to the third node, and a gate connected to the third node, and the first mirror transistor having a drain connected to the third node, a source connected to ground, and a gate connected to the third node; and The feedback transistor is an n-channel transistor having a drain connected to the input node, a source connected to the third node, and a gate connected to the second node.

4. The starting circuit according to claim 2, wherein the diode-coupled transistor and the first mirror transistor are n-channel transistors, the diode-coupled transistor having a drain connected to the input node, a source connected to the third node, and a gate connected to the third node, and the first mirror transistor having a drain connected to the third node, a source connected to ground, and a gate connected to the third node; and The feedback transistor is a p-channel transistor having a source connected to the input node, a drain connected to the third node, and a gate connected to the second node.

5. The startup circuit according to claim 2, wherein the second circuit branch comprises: a second mirror transistor connected between the input node and the first node and having a control terminal connected to the first node; an absorption transistor connected between the first node and the output node and having a control terminal connected to the first node; as well as A third mirror transistor is connected between the first node and the output node through a resistor and has a control terminal connected to the third node.

6. The starting circuit according to claim 5, wherein the second mirror transistor and the sink transistor are p-channel transistors, the second mirror transistor having a source connected to the input node, a drain connected to the first node, and a gate connected to the first node, and the sink transistor having a source connected to the first node, a drain connected to ground, and a gate connected to the first node; and The third mirror transistor is an n-channel transistor, a drain of which is connected to the first node, a source of which is coupled to the ground through the resistor, and a gate of which is connected to the third node.

7. The startup circuit according to claim 5, wherein the third circuit branch comprises: a fourth mirror transistor connected between the input node and the second node and having a control terminal connected to the first node, the fourth mirror transistor being in a current mirroring relationship with the second mirror transistor; as well as A fifth mirror transistor is connected between the second node and ground and has a control terminal connected to the third node, the fifth mirror transistor being in a current mirroring relationship with the first mirror transistor.

8. The starting circuit according to claim 7, wherein the fourth mirror transistor is a p-channel transistor having its source connected to the input node, its drain connected to the second node, and its gate connected to the first node; and The fifth mirror transistor is an n-channel transistor having a drain connected to the second node, a source connected to the ground, and a gate connected to the first node.

9. The startup circuit according to claim 1, further comprising: a power transistor connected between the input node and ground via a load, the power transistor having a control terminal connected to the output node; as well as A Zener diode has its cathode connected to the output node and its anode connected to ground.

10. The startup circuit according to claim 1, further comprising: a mirror transistor connected between the input node and a control node, the mirror transistor having a control terminal connected to the first node; a Zener diode having a cathode connected to the control node and an anode connected to the output node, the output node being connected to ground; as well as A power transistor is connected between the input node and ground via a load, the power transistor having a control terminal connected to the control node.

11. A starting circuit, comprising: Starting current circuit, comprising: a diode-coupled transistor connected between the input node and a third node; a feedback transistor connected between the input node and the first node and having a control terminal coupled to receive a feedback voltage at a second node; a first current mirror having an input connected to the third node and an output connected to the second node; a second current mirror having an input connected to the first node and an output connected to the second node; a first sink transistor connected between the first node and an output node through a resistor and having a control terminal connected to a control node of the first current mirror; and A second absorption transistor is connected between the first node and the output node and has a control terminal connected to the first node.

12. The startup circuit according to claim 11, wherein the first current mirror comprises: a first n-channel transistor having a drain connected to the third node, a source connected to the output node, and a gate connected to the third node; and a second n-channel transistor having a drain connected to the second node, a source connected to the output node, and a gate connected to the third node.

13. The startup circuit of claim 11, wherein the feedback transistor is an n-channel transistor having a drain connected to the input node, a source connected to the third node, and a gate connected to the second node.

14. The startup circuit of claim 11, wherein the feedback transistor is a p-channel transistor having a source connected to the input node, a drain connected to the third node, and a gate connected to the second node.

15. The startup circuit according to claim 11, wherein the second current mirror comprises: a first p-channel transistor having a source connected to the input node, a drain connected to the first node, and a gate connected to the first node; and a second p-channel transistor having a source connected to the input node, a drain connected to the second node, and a gate connected to the first node.

16. The startup circuit of claim 11, wherein the first sink transistor is an n-channel transistor having a drain connected to the first node, a source connected to the output node through the resistor, and a gate connected to the control node of the first current mirror.

17. The startup circuit of claim 11, wherein the second sink transistor is a p-channel transistor having a source and a gate connected to the first node and a drain connected to the output node.

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