Low noise amplifier and radio frequency front-end circuit

Abstract

The invention relates to the technical field of wireless receivers, and discloses a low-noise amplifier and a radio frequency front-end circuit, the low-noise amplifier comprises a biasing circuit and an amplifying circuit, the low-noise amplifier converts an input single-ended radio frequency signal into differential output through an MOS tube NM2 and an MOS tube NM3, and large gain is provided; secondly, external impedance matching can be better realized through single-end input, and the anti-interference capability can be enhanced through differential output; the MOS tube NM0 and the MOS tube NM1 of the low-noise amplifier are connected in a cross coupling mode, differential current imbalance can be calibrated, and noise performance is improved. Finally, the structure of the low-noise amplifier enables the noise introduced by the MOS tube NM2 to become a common-mode signal, and the introduced noise is eliminated; the mixer circuit adopts a double-balanced active mixer, common-mode signals can be well suppressed by adopting differential pair input, a local oscillator input end and a radio frequency input end are well isolated, external interference is small, and the mixer adopts a folding structure, can work under low power supply voltage and effectively reduces power consumption.

Description

Technical Field

[0001] The present invention relates to the technical field of wireless receivers, and in particular to a low noise amplifier and a radio frequency front-end circuit. Background Art

[0002] The RF front-end circuit is a key component of the wireless communication system, which is mainly used to receive and send RF signals. In the RF front-end circuit, the low-noise amplifier and mixer are its core module circuits.

[0003] For a low-noise amplifier, its main function is to amplify the input signal while minimizing the interference of noise introduced during the amplification process on the system. Therefore, gain and noise factor are the core technical indicators of a low-noise amplifier.

[0004] In order to optimize the gain and noise of the low noise amplifier, different forms of low noise amplifiers have been proposed, such as the source degenerate inductor cascode common source amplifier, etc. However, the performance of the single-ended low noise amplifier is very sensitive to the change of the inductance of the source degenerate inductor L, and the single-ended circuit has no ability to suppress substrate coupled noise and has poor anti-interference ability. In addition, the traditional single-ended to differential low noise amplifier has a complex structure, requires a balun, introduces greater power consumption, and has an area twice that of a single-ended amplifier.

[0005] In addition, the function of the mixer is to convert signals of different frequencies to each other. The two most important performance parameters are conversion gain and noise figure. According to whether gain can be provided, it is divided into active mixer and passive mixer. In order to suppress external interference signals and local oscillator signal leakage and increase isolation, double-balanced mixers are often used in RF front-end circuits. However, the traditional sleeve structure mixer limits the output voltage margin, requires a higher power supply voltage, resulting in higher power consumption, and the gain is limited by the number of sleeve layers. Summary of the invention

[0006] In view of the shortcomings of the background technology, the present invention provides a low noise amplifier and a radio frequency front-end circuit. The technical problem to be solved is that the existing low noise amplifier has the problems of high noise and poor anti-interference ability, and the mixer has the problems of high power consumption, insufficient gain and poor anti-interference ability.

[0007] In order to solve the above technical problems, the present invention provides the following technical solutions: a low noise amplifier, comprising a bias circuit and an amplification circuit;

[0008] The bias circuit includes a MOS transistor NM4, a MOS transistor NM5, a capacitor C5, a capacitor C6, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6;

[0009] The drain of the MOS tube NM4 is electrically connected to the gate of the MOS tube NM4 and one end of the resistor R1 respectively, the other end of the resistor R1 is electrically connected to one end of the resistor R2 and one end of the capacitor C5 respectively, the other end of the resistor R2 is electrically connected to one end of the resistor R3 and one end of the resistor R4 respectively, the other end of the resistor R3 is used to output the reference voltage VB_REF1, and the other end of the resistor R4 is used to output the reference voltage VB_REF2;

[0010] The source of the MOS transistor NM4 is electrically connected to the drain of the MOS transistor NM5, the gate of the MOS transistor NM5, one end of the capacitor C6, one end of the resistor R5 and one end of the resistor R6 respectively; the other end of the resistor R5 is used to output the reference voltage VREF1, and the other end of the resistor R5 is used to output the reference voltage VREF2; the other end of the capacitor C5 and the other end of the capacitor C6 are both electrically connected to the ground line GS;

[0011] The amplifying circuit includes a MOS tube NM0, a MOS tube NM1, a MOS tube NM2, a MOS tube NM3, a capacitor C1 and a capacitor C2;

[0012] The drain of the MOS tube NM0 and the drain of the MOS tube NM1 are electrically connected to the power supply VS through the adjustable resistor RL_ADJ, and are two output terminals of the amplifier circuit; the gate of the MOS tube NM0 is electrically connected to the source of the MOS tube NM1, one end of the capacitor C4 and the drain of the MOS tube NM3 through the capacitor C2, and is used to input the reference voltage VB_REF2; the gate of the MOS tube NM1 is electrically connected to the source of the MOS tube NM0 and the drain of the MOS tube NM2 through the capacitor C1, and the gate of the MOS tube NM2 is electrically connected to the other end of the capacitor C3, and is used to input the reference voltage VREF2; the source of the MOS tube NM2 is electrically connected to one end of the capacitor C4, and is the input terminal of the amplifier circuit; the other end of the capacitor C4 is electrically connected to the input terminal of the MOS tube NM3, and is used to input the reference voltage VREF1; the source of the MOS tube NM3 is grounded.

[0013] In a certain implementation manner of the first aspect, the MOS transistors NM0 to NM5 are all NMOS transistors.

[0014] In a second aspect, the present invention provides a radio frequency front-end circuit, comprising the above-mentioned low-noise amplifier, and also comprising a mixer circuit, wherein the mixer circuit comprises a voltage-to-current unit and two mixer units, wherein the voltage-to-current unit is electrically connected to the drain of the MOS tube NM0 and the drain of the MOS tube NM1, and is used to convert the voltage of the two output ends of the low-noise amplifier into current, and the two mixer units are electrically connected to the two current output interfaces of the voltage-to-current unit.

[0015] In a certain implementation manner of the second aspect, the voltage-to-current unit includes a first current mirror circuit, a second current mirror circuit, MOS transistors PM5-PM8, MOS transistors NM11-NM14, capacitors C10 to C13, and a resistor R10;

[0016] The first current mirror circuit inputs current to the source of the MOS transistor PM5, the source of the MOS transistor PM6, the source of the MOS transistor PM7, and the source of the MOS transistor PM8 based on the input current I2; one end of the capacitor C10 is electrically connected to the gate of the MOS transistor PM5 and the gate of the MOS transistor PM7, respectively, and one end of the capacitor C11 is electrically connected to the gate of the MOS transistor PM6 and the gate of the MOS transistor PM8, respectively; the other end of the capacitor C10 is electrically connected to one end of the capacitor C12 and to the drain of the MOS transistor NM1, the other end of the capacitor C11 is electrically connected to one end of the capacitor C13 and to the drain of the MOS transistor NM0; the other end of the capacitor C12 is electrically connected to the gate of the MOS transistor NM11 and the gate of the MOS transistor NM13, respectively, and the other end of the capacitor C13 is electrically connected to the gate of the MOS transistor NM12 and the gate of the MOS transistor NM14, respectively;

[0017] The drain of the MOS transistor PM5 is electrically connected to the drain of the MOS transistor NM11, the drain of the MOS transistor PM6 is electrically connected to the drain of the MOS transistor NM12, and the drain of the MOS transistor PM5 and the drain of the MOS transistor PM6 are the first current output interface of the voltage-to-current unit;

[0018] The drain of the MOS transistor PM7 is electrically connected to the drain of the MOS transistor NM13, the drain of the MOS transistor PM8 is electrically connected to the drain of the MOS transistor NM14, and the drain of the MOS transistor PM7 and the drain of the MOS transistor PM8 are the second current output interface of the voltage-to-current unit;

[0019] The current I1 is electrically connected to the second current mirror circuit through the resistor R10. The second current mirror circuit provides current to the source of the MOS transistors NM11, NM12, NM13 and NM14 based on the current I1.

[0020] In a certain implementation manner of the second aspect, the first current mirror circuit includes a MOS transistor PM9, a MOS transistor PM1, a MOS transistor PM2, a MOS transistor PM3, and a MOS transistor PM4;

[0021] The source of the MOS transistor PM9, the source of the MOS transistor PM1, the source of the MOS transistor PM2, the source of the MOS transistor PM3 and the source of the MOS transistor PM4 are all electrically connected to the power supply VS, and the gate of the MOS transistor PM9 is electrically connected to the gate of the MOS transistor PM1, the gate of the MOS transistor PM2, the gate of the MOS transistor PM3 and the gate of the MOS transistor PM4 respectively; the drain of the MOS transistor PM9 inputs the current I2, the drain of the MOS transistor PM1 and the drain of the MOS transistor PM2 are electrically connected to the source of the MOS transistor PM5 and the source of the MOS transistor PM6 respectively, and the drain of the MOS transistor PM3 and the drain of the MOS transistor PM4 are electrically connected to the source of the MOS transistor PM7 and the source of the MOS transistor PM8 respectively.

[0022] In a certain implementation manner of the second aspect, the second current mirror circuit includes a MOS transistor NM15, a MOS transistor NM16, a MOS transistor NM17, a MOS transistor NM18, and a MOS transistor NM19;

[0023] The current I1 is electrically connected to the drain of the MOS tube NM19 through the resistor R10, the drain of the MOS tube NM15 and the drain of the MOS tube NM16 are electrically connected to the source of the MOS tube NM11 and the source of the MOS tube NM12 respectively, the drain of the MOS tube NM17 and the drain of the MOS tube NM18 are electrically connected to the source of the MOS tube NM13 and the source of the MOS tube NM14 respectively; the gate of the MOS tube NM19 is electrically connected to the gate of the MOS tube NM15, the gate of the MOS tube NM16, the gate of the MOS tube NM17 and the gate of the MOS tube NM18 respectively; the source of the MOS tube NM19, the source of the MOS tube NM15, the source of the MOS tube NM16, the source of the MOS tube NM17 and the source of the MOS tube NM18 are all electrically connected to the ground line CS.

[0024] In a certain implementation manner of the second aspect, the MOS tubes NM11 to NM19 are all NMOS tubes.

[0025] In a certain implementation manner of the second aspect, the MOS transistors PM1 to PM9 are all PMOS transistors.

[0026] In a certain implementation manner of the second aspect, the mixer unit includes a MOS transistor PM10, a MOS transistor PM11, a MOS transistor PM12, and a MOS transistor PM13;

[0027] The source of the MOS transistor PM10 is electrically connected to the source of the MOS transistor PM12, the source of the MOS transistor PM11 is electrically connected to the source of the MOS transistor PM13, and the source of the MOS transistor PM10 and the source of the MOS transistor PM12 are electrically connected to a current output interface of the voltage-to-current unit;

[0028] The gate of the MOS transistor PM10 is electrically connected to the gate of the MOS transistor PM13, one end of the capacitor C11 and one end of the resistor R21 respectively, the other end of the capacitor C11 is used to input the clock signal CLK_IN, the other end of the resistor R21 is electrically connected to one end of the resistor R22 and one end of the resistor R10 electrically connected to the current source I1 respectively; the other end of the resistor R22 is electrically connected to the gate of the MOS transistor PM11, the gate of the MOS transistor PM12 and one end of the capacitor C12 respectively, the other end of the capacitor C12 is used to input the clock signal CLK_IP;

[0029] The drain of the MOS transistor PM10 is electrically connected to the drain of the MOS transistor PM11, one end of the capacitor C13, the drain of the MOS transistor NM20 and one end of the adjustable resistor respectively; the drain of the MOS transistor PM12 is electrically connected to the drain of the MOS transistor PM13, one end of the capacitor C14, one end of the adjustable resistor R24 ​​and one end of the capacitor C14 respectively; the other end of the capacitor C13 and the other end of the capacitor C14 are both electrically connected to the ground line CS; the other end of the adjustable resistor R23 is electrically connected to the gate of the MOS transistor NM20, the gate of the MOS transistor NM21, the gate of the MOS transistor NM22 and the other end of the adjustable resistor R24 ​​respectively; the source of the MOS transistor NM20, the source of the MOS transistor NM21, the source of the MOS transistor NM22 and the drain of the MOS transistor NM22 are all grounded.

[0030] In a certain implementation manner of the second aspect, the MOS tubes PM10 to PM13 are all PMOS tubes, and the MOS tubes NM20 to NM22 are all NMOS tubes.

[0031] Compared with the prior art, the present invention has the following beneficial effects: firstly, the low noise amplifier of the present invention converts the input radio frequency signal from single-ended input to differential output through the MOS tube NM2 and the MOS tube NM3, and provides a large gain; secondly, the single-ended input mode can better achieve external impedance matching, and the differential output mode can enhance the anti-interference ability; in addition, the MOS tube NM0 and the MOS tube NM1 are connected in a cross-coupling mode, which can calibrate the differential current imbalance and improve the noise performance; finally, the structure of the low noise amplifier makes the noise introduced by the MOS tube NM2 become a common mode signal, thereby eliminating the noise introduced by it.

[0032] In addition, the mixer circuit of the present invention adopts a double-balanced active mixer, and the differential pair input can effectively suppress the common mode signal, and the local oscillator input end and the radio frequency input end are also well isolated, and are less affected by external interference. The mixer adopts a folded structure and can work under low power supply voltage, effectively reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] Figure 1 is a circuit diagram of the low noise amplifier in the first embodiment;

[0034] Figure 2 Schematic diagram of the structure of the radio frequency front-end circuit in the second embodiment;

[0035] Figure 3 is a circuit diagram of a voltage-to-current unit in Embodiment 2;

[0036] Figure 4 is a circuit diagram of the mixer unit in the second embodiment. DETAILED DESCRIPTION

[0037] The present invention will now be described in further detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the present invention in a schematic manner, and therefore only show the components related to the present invention.

[0038] Embodiment 1

[0039] like Figure 1 As shown, a low noise amplifier comprises a bias circuit 10 and an amplifying circuit 11;

[0040] The bias circuit 10 includes a MOS transistor NM4, a MOS transistor NM5, a capacitor C5, a capacitor C6, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6;

[0041] The drain of the MOS tube NM4 is electrically connected to the gate of the MOS tube NM4 and one end of the resistor R1, respectively, for inputting the bias current IB20U_LNA, the other end of the resistor R1 is electrically connected to one end of the resistor R2 and one end of the capacitor C5, the other end of the resistor R2 is electrically connected to one end of the resistor R3 and one end of the resistor R4, the other end of the resistor R3 is used to output the reference voltage VB_REF1, and the other end of the resistor R4 is used to output the reference voltage VB_REF2;

[0042] The source of the MOS transistor NM4 is electrically connected to the drain of the MOS transistor NM5, the gate of the MOS transistor NM5, one end of the capacitor C6, one end of the resistor R5 and one end of the resistor R6 respectively; the other end of the resistor R5 is used to output the reference voltage VREF1, and the other end of the resistor R5 is used to output the reference voltage VREF2; the other end of the capacitor C5 and the other end of the capacitor C6 are both electrically connected to the ground line GS;

[0043] The amplifier circuit 2 includes a MOS tube NM0, a MOS tube NM1, a MOS tube NM2, a MOS tube NM3, a capacitor C1 and a capacitor C2;

[0044] The drain of the MOS tube NM0 and the drain of the MOS tube NM1 are electrically connected to the power supply VS through the adjustable resistor RL_ADJ respectively, and are two output terminals of the amplifier circuit; the gate of the MOS tube NM0 is electrically connected to the source of the MOS tube NM1, one end of the capacitor C4 and the drain of the MOS tube NM3 through the capacitor C2, respectively, for inputting the reference voltage VB_REF2; the gate of the MOS tube NM1 is electrically connected to the source of the MOS tube NM0 and the drain of the MOS tube NM2 through the capacitor C1 respectively, and the gate of the MOS tube NM2 is electrically connected to the other end of the capacitor C3, for inputting the reference voltage VREF2; the source of the MOS tube NM2 is electrically connected to one end of the capacitor C4, which is the input terminal of the amplifier circuit; the other end of the capacitor C4 is electrically connected to the input terminal of the MOS tube NM3, for inputting the reference voltage VREF1; the source of the MOS tube NM3 is grounded.

[0045] Specifically, in this embodiment, the MOS transistors NM0 to NM5 are all NMOS transistors.

[0046] In this embodiment, the bias current IB20U_LNA may be 10uuA, and the MOS transistor NM4 and the MOS transistor NM5 are connected to form a diode structure.

[0047] In this embodiment, the transconductance of the MOS transistor NM2 is the same as the transconductance of the MOS transistor NM3, and the sizes of the MOS transistor NM2 and the MOS transistor NM3 are the same. The MOS transistor NM0, the MOS transistor NM1 and the two adjustable resistors RL_ADJ are symmetrical structures, that is, the sizes of the MOS transistor NM0 and the MOS transistor NM1 are the same, and the resistance values ​​of the two adjustable resistors RL_ADJ are the same. In actual use, the same sizes of the MOS transistor NM0 and the MOS transistor NM1 form a symmetrical structure of differential output, suppress common mode signals, and enhance anti-interference capability.

[0048] for Figure 1 The low noise amplifier shown in the figure converts the input RF signal from single-ended input to differential output through MOS tubes NM2 and NM3, and provides a large gain; the gain enhancement is 2gmR L , the input impedance is

[0049] The single-ended input method can better achieve external impedance matching, while the differential output method can enhance anti-interference ability;

[0050] In addition, MOS tube NM0 and MOS tube NM1 are connected in a cross-coupling manner, which can calibrate the differential current imbalance and improve the noise performance;

[0051] Finally, the structure of the low noise amplifier makes the noise introduced by the MOS tube NM2 become a common mode signal, thereby eliminating the noise introduced by it.

[0052] Embodiment 2

[0053] like Figure 2 As shown, this embodiment provides a radio frequency front-end circuit, including a low noise amplifier 1 in Embodiment 1, and also including a voltage-to-current unit 2 and two mixer circuits 3. The voltage-to-current unit 2 is electrically connected to the drain of the MOS tube NM0 and the drain of the MOS tube NM1, and is used to convert the voltage of the two output ends of the low noise amplifier 1 into current. The two mixer circuits 3 are electrically connected to the two current output interfaces of the voltage-to-current unit 2.

[0054] like Figure 3 As shown, in this embodiment, the voltage-to-current unit 2 includes a first current mirror circuit 20, a second current mirror circuit 21, MOS transistors PM5-MOS transistor PM8, MOS transistors NM11-MOS transistor NM14, capacitors C10 to C13 and a resistor R10;

[0055] The first current mirror circuit 20 inputs current to the source of the MOS transistor PM5, the source of the MOS transistor PM6, the source of the MOS transistor PM7, and the source of the MOS transistor PM8 respectively based on the external input current I2; one end of the capacitor C10 is electrically connected to the gate of the MOS transistor PM5 and the gate of the MOS transistor PM7 respectively, and one end of the capacitor C11 is electrically connected to the gate of the MOS transistor PM6 and the gate of the MOS transistor PM8 respectively; the other end of the capacitor C10 is electrically connected to one end of the capacitor C12 and to the drain of the MOS transistor NM1, and the other end of the capacitor C11 is electrically connected to one end of the capacitor C13 and to the drain of the MOS transistor NM0; the other end of the capacitor C12 is electrically connected to the gate of the MOS transistor NM11 and the gate of the MOS transistor NM13 respectively, and the other end of the capacitor C13 is electrically connected to the gate of the MOS transistor NM12 and the gate of the MOS transistor NM14 respectively;

[0056] The drain of the MOS transistor PM5 is electrically connected to the drain of the MOS transistor NM11, the drain of the MOS transistor PM6 is electrically connected to the drain of the MOS transistor NM12, and the drain of the MOS transistor PM5 and the drain of the MOS transistor PM6 are the first current output interface of the voltage-to-current unit;

[0057] The drain of the MOS transistor PM7 is electrically connected to the drain of the MOS transistor NM13, the drain of the MOS transistor PM8 is electrically connected to the drain of the MOS transistor NM14, and the drain of the MOS transistor PM7 and the drain of the MOS transistor PM8 are the second current output interface of the voltage-to-current unit;

[0058] The current I1 is electrically connected to the second current mirror circuit 21 through the resistor R10. The second current mirror circuit provides current to the source of the MOS transistors NM11, NM12, NM13 and NM14 based on the current I1.

[0059] Specifically, in this embodiment, the first current mirror circuit 20 includes a MOS transistor PM9, a MOS transistor PM1, a MOS transistor PM2, a MOS transistor PM3 and a MOS transistor PM4;

[0060] The source of the MOS transistor PM9, the source of the MOS transistor PM1, the source of the MOS transistor PM2, the source of the MOS transistor PM3 and the source of the MOS transistor PM4 are all electrically connected to the power supply VS, and the gate of the MOS transistor PM9 is electrically connected to the gate of the MOS transistor PM1, the gate of the MOS transistor PM2, the gate of the MOS transistor PM3 and the gate of the MOS transistor PM4 respectively; the drain of the MOS transistor PM9 inputs the current I2, the drain of the MOS transistor PM1 and the drain of the MOS transistor PM2 are electrically connected to the source of the MOS transistor PM5 and the source of the MOS transistor PM6 respectively, and the drain of the MOS transistor PM3 and the drain of the MOS transistor PM4 are electrically connected to the source of the MOS transistor PM7 and the source of the MOS transistor PM8 respectively.

[0061] Specifically, in this embodiment, the second current mirror circuit 21 includes a MOS transistor NM15, a MOS transistor NM16, a MOS transistor NM17, a MOS transistor NM18, and a MOS transistor NM19;

[0062] The current I1 is electrically connected to the drain of the MOS tube NM19 through the resistor R10, the drain of the MOS tube NM15 and the drain of the MOS tube NM16 are electrically connected to the source of the MOS tube NM11 and the source of the MOS tube NM12 respectively, the drain of the MOS tube NM17 and the drain of the MOS tube NM18 are electrically connected to the source of the MOS tube NM13 and the source of the MOS tube NM14 respectively; the gate of the MOS tube NM19 is electrically connected to the gate of the MOS tube NM15, the gate of the MOS tube NM16, the gate of the MOS tube NM17 and the gate of the MOS tube NM18 respectively; the source of the MOS tube NM19, the source of the MOS tube NM15, the source of the MOS tube NM16, the source of the MOS tube NM17 and the source of the MOS tube NM18 are all electrically connected to the ground line CS.

[0063] In addition, MOS tubes NM11 to NM19 are all NMOS tubes.

[0064] In addition, the MOS tubes PM1 to PM9 are all PMOS tubes.

[0065] In this embodiment, the sizes of MOS transistor PM1 and MOS transistor PM3 are the same, the sizes of MOS transistor PM2 and MOS transistor PM4 are the same, the sizes of MOS transistor PM5, MOS transistor PM6, MOS transistor PM7 and MOS transistor PM8 are the same, the sizes of MOS transistor NM11, MOS transistor NM12, MOS transistor NM13 and MOS transistor NM14 are the same, the sizes of MOS transistor NM5 and MOS transistor NM7 are the same, and the sizes of MOS transistor NM6 and MOS transistor NM8 are the same. Moreover, gmNM11=gmNM12=gmNM13=gmNM14=gm2, gmPM5=gmPM6=gmPM7=gmPM8=gm2.

[0066] for Figure 3 The circuit shown in the figure mirrors the input 10uA bias current, i.e., current I1 and current I2, to the subsequent stage, providing bias current to the input MOS tube of the subsequent stage. The current multiplexing technology is used to maximize the use of the input transconductor gm, so that the output current transconductance is increased to gm1+gm2. gm1 and gm2 are the transconductances of the input transconductors PM7 and NM13 respectively. The conversion voltage gain of the mixer RL is the load resistance of the mixer. Adding capacitors C10 to C13 for DC isolation at the input end can isolate the DC component from the previous low-noise amplifier, and adopting differential input and differential output structures can effectively suppress common-mode signals.

[0067] Specifically, in this implementation, Figure 4 As shown, the mixer unit 3 includes a MOS transistor PM10, a MOS transistor PM11, a MOS transistor PM12 and a MOS transistor PM13;

[0068] The source of the MOS transistor PM10 is electrically connected to the source of the MOS transistor PM12, the source of the MOS transistor PM11 is electrically connected to the source of the MOS transistor PM13, and the source of the MOS transistor PM10 and the source of the MOS transistor PM12 are electrically connected to a current output interface of the voltage-to-current unit;

[0069] The gate of the MOS transistor PM10 is electrically connected to the gate of the MOS transistor PM13, one end of the capacitor C11 and one end of the resistor R21 respectively, the other end of the capacitor C11 is used to input the clock signal CLK_IN, the other end of the resistor R21 is electrically connected to one end of the resistor R22 and one end of the resistor R10 electrically connected to the current source I1 respectively; the other end of the resistor R22 is electrically connected to the gate of the MOS transistor PM11, the gate of the MOS transistor PM12 and one end of the capacitor C12 respectively, the other end of the capacitor C12 is used to input the clock signal CLK_IP;

[0070] The drain of the MOS transistor PM10 is electrically connected to the drain of the MOS transistor PM11, one end of the capacitor C13, the drain of the MOS transistor NM20 and one end of the adjustable resistor respectively; the drain of the MOS transistor PM12 is electrically connected to the drain of the MOS transistor PM13, one end of the capacitor C14, one end of the adjustable resistor R24 ​​and one end of the capacitor C14 respectively; the other end of the capacitor C13 and the other end of the capacitor C14 are both electrically connected to the ground line CS; the other end of the adjustable resistor R23 is electrically connected to the gate of the MOS transistor NM20, the gate of the MOS transistor NM21, the gate of the MOS transistor NM22 and the other end of the adjustable resistor R24 ​​respectively; the source of the MOS transistor NM20, the source of the MOS transistor NM21, the source of the MOS transistor NM22 and the drain of the MOS transistor NM22 are all grounded.

[0071] In addition, MOS tubes PM10 to PM13 are all PMOS tubes, and MOS tubes NM20 to NM22 are all NMOS tubes.

[0072] In this embodiment, the sizes of the MOS transistor PM10 , the MOS transistor PM11 , the MOS transistor PM12 and the MOS transistor PM14 are the same, and the resistance values ​​of the resistor R21 and the resistor R22 are the same, so as to meet the requirements of differential output.

[0073] The mixer circuit and the voltage-to-current unit form a folded common-source common-gate structure. The single-ended output voltage swing of the voltage-to-current unit is as follows:

[0074] VDD-[(VGS-Vth) PM1 +(VGS-Vth) PM5 +(VGS-Vth) NM11 +(VGS-Vth) NM15 ];

[0075] Compared with the traditional sleeve-type structure, the voltage swing is increased, and a larger swing can be output even at a low power supply voltage, which can effectively reduce power consumption.

[0076] In addition, in this embodiment, the mixer circuit 3 and the low noise amplifier 1 both use adjustable resistors, which facilitates the AGC in the receiver module to adjust the gain.

[0077] The above is based on the present invention as an inspiration. Through the above description, relevant staff can make various changes and modifications without departing from the technical idea of ​​this invention. The technical scope of this invention is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A low noise amplifier, characterized in that: Including bias circuit and amplifier circuit; The bias circuit includes a MOS transistor NM4, a MOS transistor NM5, a capacitor C5, a capacitor C6, a resistor R1, a resistor R2, a resistor R3, a resistor R4, a resistor R5 and a resistor R6; The drain of the MOS tube NM4 is electrically connected to the gate of the MOS tube NM4 and one end of the resistor R1 respectively, the other end of the resistor R1 is electrically connected to one end of the resistor R2 and one end of the capacitor C5 respectively, the other end of the resistor R2 is electrically connected to one end of the resistor R3 and one end of the resistor R4 respectively, the other end of the resistor R3 is used to output the reference voltage VB_REF1, and the other end of the resistor R4 is used to output the reference voltage VB_REF2; The source of the MOS transistor NM4 is electrically connected to the drain of the MOS transistor NM5, the gate of the MOS transistor NM5, one end of the capacitor C6, one end of the resistor R5 and one end of the resistor R6 respectively; the other end of the resistor R5 is used to output the reference voltage VREF1, and the other end of the resistor R5 is used to output the reference voltage VREF2; the other end of the capacitor C5 and the other end of the capacitor C6 are both electrically connected to the ground line GS; The amplifying circuit includes a MOS tube NM0, a MOS tube NM1, a MOS tube NM2, a MOS tube NM3, a capacitor C1 and a capacitor C2; The drain of the MOS tube NM0 and the drain of the MOS tube NM1 are electrically connected to the power supply VS through the adjustable resistor RL_ADJ, and are two output terminals of the amplifier circuit; the gate of the MOS tube NM0 is electrically connected to the source of the MOS tube NM1, one end of the capacitor C4 and the drain of the MOS tube NM3 through the capacitor C2, and is used to input the reference voltage VB_REF2; the gate of the MOS tube NM1 is electrically connected to the source of the MOS tube NM0 and the drain of the MOS tube NM2 through the capacitor C1, and the gate of the MOS tube NM2 is electrically connected to the other end of the capacitor C3, and is used to input the reference voltage VREF2; the source of the MOS tube NM2 is electrically connected to one end of the capacitor C4, and is the input terminal of the amplifier circuit; the other end of the capacitor C4 is electrically connected to the input terminal of the MOS tube NM3, and is used to input the reference voltage VREF1; the source of the MOS tube NM3 is grounded.

2. A low noise amplifier according to claim 1, characterized in that: The MOS tubes NM0 to NM5 are all NMOS tubes.

3. A radio frequency front-end circuit, characterized in that: A low noise amplifier comprising any one of claims 1 to 2, further comprising a mixer circuit, wherein the mixer circuit comprises a voltage-to-current unit and two mixer units, wherein the voltage-to-current unit is electrically connected to the drain of the MOS tube NM0 and the drain of the MOS tube NM1, and is used to convert the voltage at the two output ends of the low noise amplifier into current, and the two mixer units are electrically connected to the two current output interfaces of the voltage-to-current unit.

4. A radio frequency front-end circuit according to claim 3, characterized in that: The voltage-to-current unit includes a first current mirror circuit, a second current mirror circuit, MOS transistors PM5-PM8, MOS transistors NM11-NM14, capacitors C10 to C13 and a resistor R10; The first current mirror circuit inputs current to the source of the MOS transistor PM5, the source of the MOS transistor PM6, the source of the MOS transistor PM7, and the source of the MOS transistor PM8 based on the input current I2; one end of the capacitor C10 is electrically connected to the gate of the MOS transistor PM5 and the gate of the MOS transistor PM7, respectively, and one end of the capacitor C11 is electrically connected to the gate of the MOS transistor PM6 and the gate of the MOS transistor PM8, respectively; the other end of the capacitor C10 is electrically connected to one end of the capacitor C12 and to the drain of the MOS transistor NM1, the other end of the capacitor C11 is electrically connected to one end of the capacitor C13 and to the drain of the MOS transistor NM0; the other end of the capacitor C12 is electrically connected to the gate of the MOS transistor NM11 and the gate of the MOS transistor NM13, respectively, and the other end of the capacitor C13 is electrically connected to the gate of the MOS transistor NM12 and the gate of the MOS transistor NM14, respectively; The drain of the MOS transistor PM5 is electrically connected to the drain of the MOS transistor NM11, the drain of the MOS transistor PM6 is electrically connected to the drain of the MOS transistor NM12, and the drain of the MOS transistor PM5 and the drain of the MOS transistor PM6 are the first current output interface of the voltage-to-current unit; The drain of the MOS transistor PM7 is electrically connected to the drain of the MOS transistor NM13, the drain of the MOS transistor PM8 is electrically connected to the drain of the MOS transistor NM14, and the drain of the MOS transistor PM7 and the drain of the MOS transistor PM8 are the second current output interface of the voltage-to-current unit; The current I1 is electrically connected to the second current mirror circuit through the resistor R10. The second current mirror circuit provides current to the source of the MOS transistors NM11, NM12, NM13 and NM14 based on the current I1.

5. A radio frequency front-end circuit according to claim 4, characterized in that: The first current mirror circuit includes a MOS transistor PM9, a MOS transistor PM1, a MOS transistor PM2, a MOS transistor PM3 and a MOS transistor PM4; The source of the MOS transistor PM9, the source of the MOS transistor PM1, the source of the MOS transistor PM2, the source of the MOS transistor PM3 and the source of the MOS transistor PM4 are all electrically connected to the power supply VS, and the gate of the MOS transistor PM9 is electrically connected to the gate of the MOS transistor PM1, the gate of the MOS transistor PM2, the gate of the MOS transistor PM3 and the gate of the MOS transistor PM4 respectively; the drain of the MOS transistor PM9 inputs the current I2, the drain of the MOS transistor PM1 and the drain of the MOS transistor PM2 are electrically connected to the source of the MOS transistor PM5 and the source of the MOS transistor PM6 respectively, and the drain of the MOS transistor PM3 and the drain of the MOS transistor PM4 are electrically connected to the source of the MOS transistor PM7 and the source of the MOS transistor PM8 respectively.

6. The radio frequency front-end circuit according to claim 5, characterized in that: The second current mirror circuit includes a MOS transistor NM15, a MOS transistor NM16, a MOS transistor NM17, a MOS transistor NM18 and a MOS transistor NM19; The current I1 is electrically connected to the drain of the MOS tube NM19 through the resistor R10, the drain of the MOS tube NM15 and the drain of the MOS tube NM16 are electrically connected to the source of the MOS tube NM11 and the source of the MOS tube NM12 respectively, the drain of the MOS tube NM17 and the drain of the MOS tube NM18 are electrically connected to the source of the MOS tube NM13 and the source of the MOS tube NM14 respectively; the gate of the MOS tube NM19 is electrically connected to the gate of the MOS tube NM15, the gate of the MOS tube NM16, the gate of the MOS tube NM17 and the gate of the MOS tube NM18 respectively; the source of the MOS tube NM19, the source of the MOS tube NM15, the source of the MOS tube NM16, the source of the MOS tube NM17 and the source of the MOS tube NM18 are all electrically connected to the ground line CS.

7. The radio frequency front-end circuit according to claim 6, characterized in that: The MOS tubes NM11 to NM19 are all NMOS tubes.

8. The radio frequency front-end circuit according to claim 6, characterized in that: The MOS tubes PM1 to PM9 are all PMOS tubes.

9. A radio frequency front-end circuit according to any one of claims 3 to 8, characterized in that: The frequency mixing unit includes a MOS transistor PM10, a MOS transistor PM11, a MOS transistor PM12 and a MOS transistor PM13; The source of the MOS transistor PM10 is electrically connected to the source of the MOS transistor PM12, the source of the MOS transistor PM11 is electrically connected to the source of the MOS transistor PM13, and the source of the MOS transistor PM10 and the source of the MOS transistor PM12 are electrically connected to a current output interface of the voltage-to-current unit; The gate of the MOS transistor PM10 is electrically connected to the gate of the MOS transistor PM13, one end of the capacitor C11 and one end of the resistor R21 respectively, the other end of the capacitor C11 is used to input the clock signal CLK_IN, the other end of the resistor R21 is electrically connected to one end of the resistor R22 and one end of the resistor R10 electrically connected to the current source I1 respectively; the other end of the resistor R22 is electrically connected to the gate of the MOS transistor PM11, the gate of the MOS transistor PM12 and one end of the capacitor C12 respectively, the other end of the capacitor C12 is used to input the clock signal CLK_IP; The drain of the MOS transistor PM10 is electrically connected to the drain of the MOS transistor PM11, one end of the capacitor C13, the drain of the MOS transistor NM20 and one end of the adjustable resistor respectively; the drain of the MOS transistor PM12 is electrically connected to the drain of the MOS transistor PM13, one end of the capacitor C14, one end of the adjustable resistor R24 ​​and one end of the capacitor C14 respectively; the other end of the capacitor C13 and the other end of the capacitor C14 are both electrically connected to the ground line CS; the other end of the adjustable resistor R23 is electrically connected to the gate of the MOS transistor NM20, the gate of the MOS transistor NM21, the gate of the MOS transistor NM22 and the other end of the adjustable resistor R24 ​​respectively; the source of the MOS transistor NM20, the source of the MOS transistor NM21, the source of the MOS transistor NM22 and the drain of the MOS transistor NM22 are all grounded.

10. The radio frequency front-end circuit according to claim 9, characterized in that: The MOS tubes PM10 to PM13 are all PMOS tubes, and the MOS tubes NM20 to NM22 are all NMOS tubes.

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