Rail-to-rail operational amplifier circuit with low offset voltage, low noise and high precision

Abstract

The invention discloses a rail-to-rail operational amplifier circuit with low offset voltage, low noise and high precision, and relates to the technical field of integrated circuits. The amplifying circuit comprises an input stage circuit, an intermediate stage circuit, a compensating circuit and an output stage circuit, the input stage circuit is used for realizing rail-to-rail input through a group of PMOS (P-channel Metal Oxide Semiconductor) and NMOS (N-channel Metal Oxide Semiconductor) differential pairs, the intermediate stage circuit is used for improving the precision and stabilizing a common mode through a pair of operational amplifier tubes, the compensation circuit is used for realizing voltage clamping of the circuit, and the output stage circuit is used for realizing rail-to-rail output and driving a load. According to the invention, the amplitude of input and output signals can basically reach a positive and negative power rail, the high current consumption caused by the conventional design is avoided in the design of the input stage, the precision of the circuit can be greatly improved by the design of the middle stage, and the circuit can be applied to a high-precision signal processing circuit.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a rail-to-rail operational amplifier circuit with low offset voltage, low noise and high precision. Background Art

[0002] A rail-to-rail operational amplifier is an amplifier that can reach the limits of the power supply voltage range at both the input and output ends. Traditional operational amplifiers usually cannot reach the power supply rail voltage at the input and output ends, while rail-to-rail operational amplifiers achieve input voltages close to the positive and negative power supply rails through a parallel complementary differential pair structure, and the output voltage can reach the requirements close to the power supply rail through a class AB output structure, thereby greatly expanding the dynamic range of the input and output swings of the operational amplifier, and enabling the input and output signals to cover the entire power supply voltage range, thereby improving the dynamic range and signal processing capabilities of the system. High-precision rail-to-rail operational amplifiers are widely used in sensor signal conditioning, power management, data acquisition systems, and medical equipment. In sensor signal conditioning, rail-to-rail operational amplifiers can process weak signals and amplify them to a wider dynamic range; in power management, their high-precision characteristics can improve power efficiency and stability; in data acquisition systems, rail-to-rail operational amplifiers can improve sampling accuracy and signal quality; in medical equipment, their high precision and low noise characteristics help improve the accuracy of detection and diagnosis. At the same time, in the application scenarios of operational amplifiers, offset is a key factor that cannot be ignored. The input offset voltage greatly affects the amplification accuracy of the operational amplifier, and reducing offset is an important part of operational amplifier design. Therefore, research on high-precision rail-to-rail operational amplifiers has become a hot topic in the current research field of operational amplifiers. Summary of the invention

[0003] The purpose of the present invention is to overcome the deficiencies of the prior art and provide a rail-to-rail operational amplifier circuit with low offset voltage, low noise and high precision.

[0004] The objective of the present invention is achieved through the following technical solutions: A rail-to-rail operational amplifier circuit with low offset voltage, low noise and high precision, comprising an input stage circuit, an intermediate stage circuit, a compensation circuit and an output stage circuit; The first output end of the input stage circuit is connected to the first input end of the intermediate stage circuit, the second output end of the input stage circuit is connected to the second input end of the intermediate stage circuit, the first output end of the intermediate stage circuit is connected to the first input end of the compensation circuit and the first input end of the output stage circuit, and the second output end of the intermediate stage circuit is connected to the second input end of the compensation circuit and the second input end of the output stage circuit; The input stage circuit is used to achieve rail-to-rail input through a group of PMOS and NMOS differential pairs, the intermediate stage circuit is used to improve accuracy and stabilize the common mode through a pair of operational amplifiers, the compensation circuit is used to achieve voltage clamping of the circuit, and the output stage circuit is used to achieve rail-to-rail output and drive the load.

[0005] Further, the input stage circuit includes a DC current source I, a first DC voltage source V1, a second DC voltage source V2, a third DC voltage source V3, a fourth DC voltage source V4, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, and a ninth NMOS tube N9; The first output terminal of the DC current source I is connected to the positive power supply voltage, the second output terminal of the DC current source I is connected to the drain of the seventh NMOS tube N7 and the source of the first and second PMOS tubes P1 and P2, the gate of the seventh NMOS tube N7 is connected to the second output terminal of the fourth DC voltage source V4, the source of the seventh NMOS tube N7 is connected to the gates of the eighth and ninth NMOS tubes N8 and N9 and the drain of the eighth NMOS tube N8, the drain of the ninth NMOS tube N9 is connected to the source of the first and second NMOS tubes N1 and N2, and the first The drain of the NMOS tube N1 is connected to the drain of the third PMOS tube P3 and the source of the fifth PMOS tube P5, the drain of the second NMOS tube N2 is connected to the drain of the fourth PMOS tube P4 and the source of the sixth PMOS tube P6, the sources of the third and fourth PMOS tubes P3 and P4 are connected to the positive power supply voltage, the drain of the first PMOS tube P1 is connected to the source of the fifth NMOS tube N5 and the drain of the third NMOS tube N3, the source of the second PMOS tube P2 is connected to the source of the sixth NMOS tube N6 and the source of the fourth NMOS The drain of the third PMOS tube N4 is connected, the gate of the third PMOS tube P3 and the gate of the fourth PMOS tube N4 are connected to the second output end of the first voltage source V1, the gate of the fifth PMOS tube P5 and the gate of the sixth PMOS tube P6 are connected to the second output end of the second voltage source V2, the gate of the fifth NMOS tube N5 and the gate of the sixth NMOS tube N6 are connected to the second output end of the third voltage source V3, the source of the eighth, ninth, third, and fourth NMOS tubes N8, N9, N3, and N4, the first, second, third, and fourth DC voltage sources V1, The first output terminals of V2, V3 and V4 are connected to the negative power supply voltage, the first input terminal VP is connected to the gates of the first NMOS tube N1 and the first PMOS tube P1, the second input terminal VN is connected to the gates of the second NMOS tube N2 and the second PMOS tube P2, the first output terminal VO1 is connected to the drains of the fifth PMOS tube P5 and the fifth NMOS tube N5, and the second output terminal VO2 is connected to the drains of the sixth PMOS tube P6 and the sixth NMOS tube N6, and the gates of the third NMOS tube N3 and the fourth NMOS tube N4.

[0006] Further, the intermediate stage circuit includes a first operational amplifier and a second operational amplifier; The inverting input terminal of the first operational amplifier is connected to the first output terminal VO1 of the input stage circuit, and the positive input terminal of the second operational amplifier is connected to the second output terminal VO2 of the input stage circuit; the positive input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier are both grounded (connected to the negative power supply voltage of the input stage circuit).

[0007] Further, the output stage circuit includes a seventh PMOS tube P7, an eighth PMOS tube P8, a ninth PMOS tube P9, a tenth PMOS tube P10, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a thirteenth NMOS tube N13, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; The gates of the seventh, eighth, ninth and tenth PMOS tubes P7, P8, P9 and P10 are connected to the first input terminal VIN1 of the output stage circuit, the gates of the tenth, eleventh, twelfth and thirteenth NMOS tubes N10, N11, N12 and N13 are connected to the second input terminal VIN2 of the output stage circuit, the sources of the seventh, eighth, ninth and tenth PMOS tubes are connected to the positive power supply voltage, the sources of the tenth, eleventh, twelfth and thirteenth NMOS tubes are connected to the negative power supply voltage, the first end of the first resistor R1 is connected to the seventh PMOS tube The drains of the S transistor P7 and the tenth NMOS transistor N10 are connected, the first end of the second resistor R2 is connected to the drains of the eighth PMOS transistor P8 and the eleventh NMOS transistor N11, the first end of the third resistor R3 is connected to the drains of the ninth PMOS transistor P9 and the twelfth NMOS transistor N12, the first end of the fourth resistor R4 is connected to the drains of the tenth PMOS transistor P10 and the thirteenth NMOS transistor N13, and the output terminal VOUT is connected to the second ends of the first, second, third, and fourth resistors R1, R2, R3, and R4; The first input terminal VIN1 of the output stage circuit is connected to the output terminal of the first operational amplifier of the intermediate stage circuit, and the second input terminal VIN2 is connected to the output terminal of the second operational amplifier of the intermediate stage circuit.

[0008] Further, the compensation circuit includes a second direct current source I2, a third direct current source I3, an eleventh PMOS tube P11, a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fourteenth NMOS tube N14, a fifteenth NMOS tube N15, a sixteenth NMOS tube N16, and a seventeenth NMOS tube N17; The source of the eleventh PMOS tube P11 is connected to the positive power supply voltage, the drain of the eleventh PMOS tube P11 is connected to the gate of the eleventh PMOS tube P11, the source of the twelfth PMOS tube P12, and the source of the fourteenth NMOS tube N14, the drain of the twelfth PMOS tube P12 is connected to the gate of the twelfth PMOS tube P12 and the source of the thirteenth PMOS tube P13, the gate of the thirteenth PMOS tube P13 is connected to the gate of the fourteenth NMOS tube N14, the drain of the fourteenth NMOS tube N14, and the second output end of the second direct current source I2, and the drain of the thirteenth PMOS tube P13 is connected to the first output end of the second direct current source I2 and the negative power supply voltage; The source of the fourteenth NMOS tube N14 is connected to the negative power supply voltage, the drain of the fourteenth NMOS tube N14 is connected to the gate of the fourteenth NMOS tube N14, the source of the fifteenth NMOS tube N15, and the source of the seventeenth NMOS tube N17, the drain of the fifteenth NMOS tube N15 is connected to the gate of the fifteenth NMOS tube N15 and the source of the sixteenth NMOS tube N16, the gate of the sixteenth NMOS tube N16 is connected to the gate of the seventeenth NMOS tube N17, the drain of the seventeenth NMOS tube N17, and the second output end of the third direct current source I3, the drain of the sixteenth NMOS tube N16 and the first output end of the third direct current source I3 are connected to the positive power supply voltage, the first input-output end IO1 is connected to the drain of the twelfth PMOS tube P12, and the second input-output end IO2 is connected to the drain of the fifteenth NMOS tube N15; The first input-output terminal IO1 of the compensation circuit is connected to the first input terminal VIN1 of the output stage circuit, and the second input-output terminal IO2 is connected to the second input terminal VIN2 of the output stage circuit.

[0009] The beneficial effects of the present invention are as follows: the present invention designs a low-noise, low-offset, high-precision rail-to-rail operational amplifier circuit, so that the input and output signal swings can basically reach the positive and negative power rails, and the higher current consumption caused by conventional designs is avoided in the design of the input stage. At the same time, the design of the intermediate stage can greatly increase the accuracy of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 is a circuit diagram of an input stage circuit in the present invention; Figure 2 is a circuit diagram of an output stage circuit in the present invention; Figure 3 is a circuit diagram of the compensation circuit in the present invention; Figure 4 It is a structural block diagram of the overall circuit in the present invention. DETAILED DESCRIPTION

[0011] The technical solution of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0012] See also Figure 1-Figure 4 , the present invention provides a technical solution: A low offset voltage, low noise, high precision rail-to-rail operational amplifier circuit, such as Figure 1 As shown, it includes an input stage circuit, an intermediate stage circuit, a compensation circuit and an output stage circuit connected in sequence; The input stage circuit is used to achieve rail-to-rail input through a group of PMOS and NMOS differential pairs, the intermediate stage circuit is used to improve accuracy and stabilize the common mode through a pair of five-tube operational amplifiers, the compensation circuit is used to achieve voltage clamping of the circuit, and the output stage circuit is used to achieve rail-to-rail output and drive the load.

[0013] Further, the input stage circuit includes a DC current source I, a first DC voltage source V1, a second DC voltage source V2, a third DC voltage source V3, a fourth DC voltage source V4, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, and a ninth NMOS tube N9; The first output terminal of the DC voltage source I is connected to the positive power supply voltage, the second output terminal is connected to the drain of the seventh NMOS tube N7, the source of the first and second PMOS tubes P1 and P2, the gate of the seventh NMOS tube N7 is connected to the second output terminal of the fourth DC voltage source V4, the source of the seventh NMOS tube N7 is connected to the gates of the eighth and ninth NMOS tubes N8 and N9, the drain of the eighth NMOS tube N8, the drain of the ninth NMOS tube N9 is connected to the source of the first and second NMOS tubes N1 and N2, the drain of the first NMOS tube N1 is connected to the gate of the eighth and ninth NMOS tubes N8 and N9, the drain of the eighth NMOS tube N8 is connected to the gate of the eighth and ninth NMOS tubes N8 and N9, the drain of the ninth NMOS tube N9 is connected to the source of the first and second NMOS tubes N1 and N2, the drain of the first NMOS tube N1 ... the drain of the first NMOS tube N1 is connected to the gate of the eighth and ninth NMOS tubes N8 and the drain of the first The drain of the first PMOS tube P1 is connected to the drain of the third PMOS tube P3 and the source of the fifth PMOS tube P5, the drain of the second NMOS tube N2 is connected to the drain of the fourth PMOS tube P4 and the source of the sixth PMOS tube P6, the sources of the third and fourth PMOS tubes P3 and P4 are connected to the power supply voltage, the drain of the first PMOS tube P1 is connected to the source of the fifth NMOS tube N5 and the drain of the third NMOS tube N3, the source of the second PMOS tube P2 is connected to the source of the sixth NMOS tube N6 and the drain of the fourth NMOS tube N4, and the drain of the third PMOS tube P1 is connected to the source of the fifth NMOS tube N5 and the drain of the third NMOS tube N3. The gate of the OS transistor P3 and the gate of the fourth PMOS transistor N4 are connected to the second output end of the first voltage source V1, the gate of the fifth PMOS transistor P5 and the gate of the sixth PMOS transistor P6 are connected to the second output end of the second voltage source V2, the gate of the fifth NMOS transistor N5 and the gate of the sixth NMOS transistor N6 are connected to the second output end of the third voltage source V3, and the sources of the eighth, ninth, third, and fourth NMOS transistors N8, N9, N3, and N4, the first output ends of the first, second, third, and fourth DC voltage sources V1, V2, V3, and V4 are connected to the negative The power supply voltage is connected, the sources of the third and fourth PMOS tubes P3 and P4 are connected to the positive power supply voltage, the input terminal VP is connected to the gates of the first NMOS tube N1 and the first PMOS tube P1, the input terminal VN is connected to the gates of the second NMOS tube N2 and the second PMOS tube P2, the output terminal VO1 is connected to the drains of the fifth PMOS tube P5 and the fifth NMOS tube N5, and the output terminal VO2 is connected to the drains of the sixth PMOS tube P6 and the sixth NMOS tube N6, and the gates of the third NMOS tube N3 and the fourth NMOS tube N4.

[0014] In this embodiment, when the input voltage (i.e., the common-mode input voltage) loaded on both ends of the input terminal VP and the input terminal VN is close to the negative power supply voltage rail, the first NMOS transistor N1 and the second NMOS transistor N2 are turned off, and only the first PMOS transistor P1 and the second PMOS transistor P2 work. At this time, the signal flows to the subsequent circuit through the first PMOS transistor P1, the second PMOS transistor P2, and the summing circuit composed of the third PMOS transistor P3, the fourth PMOS transistor P4, the fifth PMOS transistor P5, the sixth PMOS transistor P6, the third NMOS transistor N3, the fourth NMOS transistor N4, the fifth NMOS transistor N5, and the sixth NMOS transistor N6; When the input voltage is near the middle value of the positive and negative power supply voltages, the first NMOS transistor N1, the second NMOS transistor N2, the first PMOS transistor P1, and the second PMOS transistor P2 are all in the on state. However, since the two differential pairs use the same DC current source I, by reasonably selecting the value of the fourth DC voltage source V4, the current flowing through the PMOS differential pair and the current flowing through the NMOS differential pair are reasonably distributed, ensuring that the transconductance of the input stage is in a relatively constant region. When the input voltage is close to the positive power supply voltage rail, the first PMOS tube P1 and the second PMOS tube P2 are turned off, and only the first NMOS tube N1 and the second NMOS tube N2 are working. The current of the DC current source I flows through the first NMOS tube N1 and the second NMOS tube N2 through the current mirror composed of the seventh NMOS tube N7 and the eighth NMOS tube N8 and the ninth NMOS tube, and then flows to the subsequent circuit through the summing circuit composed of the third PMOS tube P3, the fourth PMOS tube P4, the fifth PMOS tube P5, the sixth PMOS tube P6, the third NMOS tube N3, the fourth NMOS tube N4, the fifth NMOS tube N5, and the sixth NMOS tube N6.

[0015] In this embodiment, Figure 2 The input stage circuit can meet the full swing of the input level between the positive power supply voltage rail and the negative power supply voltage rail, and compared with the commonly used constant span structure, only one current source is used for biasing in this embodiment, which reduces the power consumption of the input stage circuit.

[0016] Further, the intermediate stage circuit includes a first operational amplifier and a second operational amplifier; The inverting input terminal of the first operational amplifier is connected to the first output terminal VO1 of the input stage circuit, and the positive input terminal of the second operational amplifier is connected to the second output terminal VO2 of the input stage circuit; the positive input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier are both grounded (connected to the negative power supply voltage of the input stage circuit).

[0017] In this embodiment, the entire operational amplifier is connected to the closed-loop system. After the intermediate stage operational amplifier is connected, the voltages at the first output terminal VO1 and the second output terminal VO2 of the input stage circuit tend to be equal, and the entire circuit has better symmetry, thereby greatly improving the common mode rejection ratio of the circuit under DC input and improving the accuracy of the overall circuit.

[0018] In a specific embodiment, Figure 3, the output stage circuit includes a seventh PMOS tube P7, an eighth PMOS tube P8, a ninth PMOS tube P9, a tenth PMOS tube P10, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a thirteenth NMOS tube N13, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; The gates of the seventh, eighth, ninth and tenth PMOS tubes P7, P8, P9 and P10 are connected to the first input terminal VIN1 of the output stage circuit, the gates of the tenth, eleventh, twelfth and thirteenth NMOS tubes N10, N11, N12 and N13 are connected to the second input terminal VIN2 of the output stage circuit, the sources of the seventh, eighth, ninth and tenth PMOS tubes are connected to the positive power supply voltage, the sources of the tenth, eleventh, twelfth and thirteenth NMOS tubes are connected to the negative power supply voltage, the first end of the first resistor R1 is connected to the seventh PMOS tube The drains of the S transistor P7 and the tenth NMOS transistor N10 are connected, the first end of the second resistor R2 is connected to the drains of the eighth PMOS transistor P8 and the eleventh NMOS transistor N11, the first end of the third resistor R3 is connected to the drains of the ninth PMOS transistor P9 and the twelfth NMOS transistor N12, the first end of the fourth resistor R4 is connected to the drains of the tenth PMOS transistor P10 and the thirteenth NMOS transistor N13, and the output terminal VOUT is connected to the second ends of the first, second, third, and fourth resistors R1, R2, R3, and R4; The first input terminal VIN1 of the output stage circuit is connected to the output terminal of the first operational amplifier of the intermediate stage circuit, and the second input terminal VIN2 is connected to the output terminal of the second operational amplifier of the intermediate stage circuit.

[0019] In a specific embodiment, Figure 4 , the compensation circuit includes a second direct current source I2, a third direct current source I3, an eleventh PMOS tube P11, a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fourteenth NMOS tube N14, a fifteenth NMOS tube N15, a sixteenth NMOS tube N16, and a seventeenth NMOS tube N17; The source of the eleventh PMOS tube P11 is connected to the positive power supply voltage, the drain of the eleventh PMOS tube P11 is connected to the gate of the eleventh PMOS tube P11, the source of the twelfth PMOS tube P12, and the source of the fourteenth NMOS tube N14, the drain of the twelfth PMOS tube P12 is connected to the gate of the twelfth PMOS tube P12 and the source of the thirteenth PMOS tube P13, the gate of the thirteenth PMOS tube P13 is connected to the gate of the fourteenth NMOS tube N14, the drain of the fourteenth NMOS tube N14, and the second output end of the second direct current source I2, and the drain of the thirteenth PMOS tube P13 is connected to the first output end of the second direct current source I2 and the negative power supply voltage; The source of the fourteenth NMOS tube N14 is connected to the negative power supply voltage, the drain of the fourteenth NMOS tube N14 is connected to the gate of the fourteenth NMOS tube N14, the source of the fifteenth NMOS tube N15, and the source of the seventeenth NMOS tube N17, the drain of the fifteenth NMOS tube N15 is connected to the gate of the fifteenth NMOS tube N15 and the source of the sixteenth NMOS tube N16, the gate of the sixteenth NMOS tube N16 is connected to the gate of the seventeenth NMOS tube N17, the drain of the seventeenth NMOS tube N17, and the second output end of the third direct current source I3, the drain of the sixteenth NMOS tube N16 and the first output end of the third direct current source I3 are connected to the positive power supply voltage, the first input-output end IO1 is connected to the drain of the twelfth PMOS tube P12, and the second input-output end IO2 is connected to the drain of the fifteenth NMOS tube N15; The first input-output terminal IO1 of the compensation circuit is connected to the first input terminal VIN1 of the output stage circuit, and the second input-output terminal IO2 is connected to the second input terminal VIN2 of the output stage circuit.

[0020] In this embodiment, in order to prevent the output stage current from increasing due to process deviation, a compensation circuit is introduced to clamp the potential, thereby reducing the excessive current consumption caused by the process error, and at the same time providing a bias for the MOS tube in the output stage circuit. Figure 3 As shown, under normal circumstances, the twelfth PMOS transistor P12 and the second NMOS transistor N2 are turned off, and the current path only has two paths: the eleventh PMOS transistor P11, the fourteenth PMOS transistor P14, the second DC current source I2 and the fourteenth NMOS transistor N14, the seventeenth NMOS transistor N17, the third DC current source I3. When the potential of IO1 decreases, the twelfth PMOS transistor P12 is turned on. The circuit generates an additional current path. Since the gate potentials of the thirteenth PMOS tube P13 and the fourteenth PMOS tube P14 are the same and the source potential of the thirteenth PMOS tube P13 is lower than the source potential of the fourteenth PMOS tube P14, the current flowing through the thirteenth PMOS tube P13 is smaller than the current flowing through the fourteenth PMOS tube P14. However, since the width-to-length ratio of the twelfth PMOS tube P12 is very large, a larger current will be generated. Therefore, the excess current will flow out through the path of the first operational amplifier OP1 of the intermediate stage circuit, which will cause the currents of the left and right paths of the first operational amplifier OP1 of the intermediate stage circuit to be asymmetric. When the current flows entirely through one path of the first operational amplifier of the intermediate stage, the potential of IO1 at this time is the lowest potential that can be reached at this point. The same is true for the input and output terminal IO2. When the current flows entirely through one path of the second operational amplifier of the intermediate stage, the potential of IO2 at this time is the highest potential that can be reached at this point.

[0021] In this example, in order to achieve low noise of the operational amplifier, according to the flicker noise expression, a larger value is set for the width-length product W*L of the first PMOS tube P1 and the second PMOS tube P2 of the input stage circuit, and a larger value is also set for the width-length product W*L of the first NMOS tube N1 and the second NMOS tube N2 of the input stage, so that lower noise can be achieved. Since the operational amplifier of the intermediate stage in this example also generates a gain, the gain of the operational amplifier in this example is not particularly low.

[0022] In order to achieve low offset voltage of the operational amplifier, on the one hand, the sizes of the two pairs of tubes of the current mirror are increased proportionally to reduce the mismatch of the current mirror and achieve the purpose of low offset. On the other hand, a trimming circuit is set in the circuit. After the chip is produced, the current flowing into the summing circuit of the input stage pair of tubes is adjusted through trimming technology to further reduce the mismatch of the circuit.

[0023] The above is only a preferred embodiment of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, and should not be regarded as excluding other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge of the relevant field. The changes and modifications made by those skilled in the art shall not deviate from the spirit and scope of the present invention, and shall be within the scope of protection of the claims attached to the present invention.

Claims

1. A low offset voltage, low noise and high precision rail-to-rail operational amplifier circuit, characterized in that: It includes an input stage circuit, an intermediate stage circuit, a compensation circuit and an output stage circuit; The first output end of the input stage circuit is connected to the first input end of the intermediate stage circuit, the second output end of the input stage circuit is connected to the second input end of the intermediate stage circuit, the first output end of the intermediate stage circuit is connected to the first input end of the compensation circuit and the first input end of the output stage circuit, and the second output end of the intermediate stage circuit is connected to the second input end of the compensation circuit and the second input end of the output stage circuit; The input stage circuit is used to achieve rail-to-rail input through a group of PMOS and NMOS differential pairs, the intermediate stage circuit is used to improve accuracy and stabilize the common mode through a pair of operational amplifiers, the compensation circuit is used to achieve voltage clamping of the circuit, and the output stage circuit is used to achieve rail-to-rail output and drive the load.

2. The low offset voltage, low noise and high precision rail-to-rail operational amplifier circuit according to claim 1, characterized in that: The input stage circuit includes a DC current source I, a first DC voltage source V1, a second DC voltage source V2, a third DC voltage source V3, a fourth DC voltage source V4, a first PMOS tube P1, a second PMOS tube P2, a third PMOS tube P3, a fourth PMOS tube P4, a fifth PMOS tube P5, a sixth PMOS tube P6, a first NMOS tube N1, a second NMOS tube N2, a third NMOS tube N3, a fourth NMOS tube N4, a fifth NMOS tube N5, a sixth NMOS tube N6, a seventh NMOS tube N7, an eighth NMOS tube N8, and a ninth NMOS tube N9; The first output terminal of the DC current source I is connected to the positive power supply voltage, the second output terminal of the DC current source I is connected to the drain of the seventh NMOS tube N7 and the source of the first and second PMOS tubes P1 and P2, the gate of the seventh NMOS tube N7 is connected to the second output terminal of the fourth DC voltage source V4, the source of the seventh NMOS tube N7 is connected to the gates of the eighth and ninth NMOS tubes N8 and N9 and the drain of the eighth NMOS tube N8, the drain of the ninth NMOS tube N9 is connected to the source of the first and second NMOS tubes N1 and N2, and the first The drain of the NMOS tube N1 is connected to the drain of the third PMOS tube P3 and the source of the fifth PMOS tube P5, the drain of the second NMOS tube N2 is connected to the drain of the fourth PMOS tube P4 and the source of the sixth PMOS tube P6, the sources of the third and fourth PMOS tubes P3 and P4 are connected to the positive power supply voltage, the drain of the first PMOS tube P1 is connected to the source of the fifth NMOS tube N5 and the drain of the third NMOS tube N3, the source of the second PMOS tube P2 is connected to the source of the sixth NMOS tube N6 and the source of the fourth NMOS The drain of the third PMOS tube N4 is connected, the gate of the third PMOS tube P3 and the gate of the fourth PMOS tube N4 are connected to the second output end of the first voltage source V1, the gate of the fifth PMOS tube P5 and the gate of the sixth PMOS tube P6 are connected to the second output end of the second voltage source V2, the gate of the fifth NMOS tube N5 and the gate of the sixth NMOS tube N6 are connected to the second output end of the third voltage source V3, the source of the eighth, ninth, third, and fourth NMOS tubes N8, N9, N3, and N4, the first, second, third, and fourth DC voltage sources V1, The first output terminals of V2, V3 and V4 are connected to the negative power supply voltage, the first input terminal VP is connected to the gates of the first NMOS tube N1 and the first PMOS tube P1, the second input terminal VN is connected to the gates of the second NMOS tube N2 and the second PMOS tube P2, the first output terminal VO1 is connected to the drains of the fifth PMOS tube P5 and the fifth NMOS tube N5, and the second output terminal VO2 is connected to the drains of the sixth PMOS tube P6 and the sixth NMOS tube N6, and the gates of the third NMOS tube N3 and the fourth NMOS tube N4.

3. The low offset voltage, low noise and high precision rail-to-rail operational amplifier circuit according to claim 2, characterized in that: The intermediate stage circuit includes a first operational amplifier and a second operational amplifier; The inverting input terminal of the first operational amplifier is connected to the first output terminal VO1 of the input stage circuit, and the positive input terminal of the second operational amplifier is connected to the second output terminal VO2 of the input stage circuit; the positive input terminal of the first operational amplifier and the inverting input terminal of the second operational amplifier are both grounded (connected to the negative power supply voltage of the input stage circuit).

4. The low offset voltage, low noise and high precision rail-to-rail operational amplifier circuit according to claim 3, characterized in that: The output stage circuit includes a seventh PMOS tube P7, an eighth PMOS tube P8, a ninth PMOS tube P9, a tenth PMOS tube P10, a tenth NMOS tube N10, an eleventh NMOS tube N11, a twelfth NMOS tube N12, a thirteenth NMOS tube N13, a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4; The gates of the seventh, eighth, ninth and tenth PMOS tubes P7, P8, P9 and P10 are connected to the first input terminal VIN1 of the output stage circuit, the gates of the tenth, eleventh, twelfth and thirteenth NMOS tubes N10, N11, N12 and N13 are connected to the second input terminal VIN2 of the output stage circuit, the sources of the seventh, eighth, ninth and tenth PMOS tubes are connected to the positive power supply voltage, the sources of the tenth, eleventh, twelfth and thirteenth NMOS tubes are connected to the negative power supply voltage, the first end of the first resistor R1 is connected to the seventh PMOS tube The drains of the S transistor P7 and the tenth NMOS transistor N10 are connected, the first end of the second resistor R2 is connected to the drains of the eighth PMOS transistor P8 and the eleventh NMOS transistor N11, the first end of the third resistor R3 is connected to the drains of the ninth PMOS transistor P9 and the twelfth NMOS transistor N12, the first end of the fourth resistor R4 is connected to the drains of the tenth PMOS transistor P10 and the thirteenth NMOS transistor N13, and the output terminal VOUT is connected to the second ends of the first, second, third, and fourth resistors R1, R2, R3, and R4; The first input terminal VIN1 of the output stage circuit is connected to the output terminal of the first operational amplifier of the intermediate stage circuit, and the second input terminal VIN2 is connected to the output terminal of the second operational amplifier of the intermediate stage circuit.

5. The low offset voltage, low noise and high precision rail-to-rail operational amplifier circuit according to claim 4, characterized in that: The compensation circuit includes a second direct current source I2, a third direct current source I3, an eleventh PMOS tube P11, a twelfth PMOS tube P12, a thirteenth PMOS tube P13, a fourteenth PMOS tube P14, a fourteenth NMOS tube N14, a fifteenth NMOS tube N15, a sixteenth NMOS tube N16, and a seventeenth NMOS tube N17; The source of the eleventh PMOS tube P11 is connected to the positive power supply voltage, the drain of the eleventh PMOS tube P11 is connected to the gate of the eleventh PMOS tube P11, the source of the twelfth PMOS tube P12, and the source of the fourteenth NMOS tube N14, the drain of the twelfth PMOS tube P12 is connected to the gate of the twelfth PMOS tube P12 and the source of the thirteenth PMOS tube P13, the gate of the thirteenth PMOS tube P13 is connected to the gate of the fourteenth NMOS tube N14, the drain of the fourteenth NMOS tube N14, and the second output end of the second direct current source I2, and the drain of the thirteenth PMOS tube P13 is connected to the first output end of the second direct current source I2 and the negative power supply voltage; The source of the fourteenth NMOS tube N14 is connected to the negative power supply voltage, the drain of the fourteenth NMOS tube N14 is connected to the gate of the fourteenth NMOS tube N14, the source of the fifteenth NMOS tube N15, and the source of the seventeenth NMOS tube N17, the drain of the fifteenth NMOS tube N15 is connected to the gate of the fifteenth NMOS tube N15 and the source of the sixteenth NMOS tube N16, the gate of the sixteenth NMOS tube N16 is connected to the gate of the seventeenth NMOS tube N17, the drain of the seventeenth NMOS tube N17, and the second output end of the third direct current source I3, the drain of the sixteenth NMOS tube N16 and the first output end of the third direct current source I3 are connected to the positive power supply voltage, the first input-output end IO1 is connected to the drain of the twelfth PMOS tube P12, and the second input-output end IO2 is connected to the drain of the fifteenth NMOS tube N15; The first input-output terminal IO1 of the compensation circuit is connected to the first input terminal VIN1 of the output stage circuit, and the second input-output terminal IO2 is connected to the second input terminal VIN2 of the output stage circuit.

Images