DMA PMM for transmission groups

Abstract

The invention provides a method for managing transmission groups by using a hardware linked list at a DMA (Direct Memory Access) PMM (Platform Management Module), which comprises the following steps of: sequentially querying and updating the transmission state of each transmission group in a transmission group queue according to the priority of the transmission groups; configuring the transmission group queue according to the query result and the priority of the transmission group; and triggering the DMA to transmit the transmission group queue. According to the invention, priority management can be carried out on the transmission group used for communication between the chips without adding a hardware module, and the increase of the chip size and the manufacturing cost due to the addition of the hardware module is avoided. In addition, the DMA PMM provided by the invention can be flexibly applied to various different MCUs.

Description

Technical Field

[0001] The present invention generally relates to a microcontroller unit (MCU), and more particularly to a priority management module (PMM) in a microcontroller unit (MCU). Background Art

[0002] In automotive electronics, communication between multiple chips is widely used in electronic body stability systems ESP, Ibooster, IPB, DPB and other products.

[0003] To facilitate communication between chips, some existing microcontroller units (MCUs) include a dedicated hardware module: a Priority Management Module (PMM). Specifically, Figure 1 As shown, the MCU includes a direct memory access (DMA) 106, a PMM hardware module 104, and a serial data transmission module 102. The communication between chips (for example, between a host (such as an MCU) and a slave (such as an ASIC)) is divided into a plurality of transmission groups (abbreviated as TG) 105-1 to 105-8. The PMM hardware module 104 performs priority management on these transmission groups 105-1 to 105-8, and then configures the transmission groups 105-1 to 105-8 in the form of queues according to the priority order and transmits them to the serial data transmission module 102. Thus, the plurality of transmission groups 105-1 to 105-8 can be transmitted in sequence according to the priority order to avoid preemption and congestion of the transmission channel.

[0004] However, if the above MCU wants to omit the PMM hardware module to reduce the chip size and reduce the chip cost, it is necessary to implement the priority management function through other means. In addition, when it is necessary to use other MCUs different from the above MCU on other products (for example, ESP, IPB, etc.), these other MCUs currently lack the priority management module (PMM), and other MCUs need to add additional design and cost to implement the priority management function for the transmission group.

[0005] Therefore, it is expected that the MCU can perform priority management on the transmission group without the PMM hardware module and minimize the design and manufacturing costs. Summary of the invention

[0006] The following summary is provided to introduce selected concepts in a simplified form that are further described in the detailed description that follows. This summary is not intended to highlight key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter.

[0007] The present invention provides a DMAPMM, which is used to cache and prioritize transmission groups by configuring a hardware linked list (eg, a DMA linked list) by software on the DMA side, wherein the DMA linked list is a common hardware unit in an MCU.

[0008] According to one aspect of the present invention, a method for managing transmission groups by using a hardware linked list at a DMA PMM is provided, comprising: a query step: querying and updating the transmission status of each transmission group in a transmission group queue in turn according to the priority of the transmission group; a configuration step: configuring the transmission group queue according to the query result and the priority of the transmission group; and a triggering step: triggering DMA to transmit the transmission group queue.

[0009] According to one aspect of the present invention, a DMA PMM for managing transmission groups using a hardware linked list is provided, including: a query module, used to query and update the transmission status of each transmission group in a transmission group queue in turn according to the priority of the transmission group; a configuration module, used to configure the transmission group queue according to the query result and the priority of the transmission group; and a trigger module, used to trigger DMA to transmit the transmission group queue.

[0010] According to one aspect of the present invention, there is provided a device for transmitting a group, comprising: a microcontroller unit; and a memory storing machine executable instructions, which, when executed by the microcontroller unit, enable the microcontroller unit to perform the method described according to multiple aspects of the present invention.

[0011] According to one aspect of the present invention, a non-transitory machine-readable storage medium is provided, which stores machine-executable instructions. When the machine-executable instructions are executed by the microcontroller unit, the microcontroller unit executes the method described according to multiple aspects of the present invention.

[0012] The beneficial effects of the present invention include: even if the PMM hardware module is omitted, the MCU can still perform priority management on the SPI transmission group, thereby reducing the size of the MCU. In addition, for other MCUs that originally do not have the PMM hardware module, the present invention can also implement priority management on the transmission group without redesigning its hardware, avoiding the increase in chip size and manufacturing cost due to the addition of hardware modules. Moreover, the DMA PMM designed by the present invention can be applied to various different MCUs available on the market. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] By referring to the following drawings, a further understanding of the nature and advantages of the present invention can be achieved. For ease of understanding, similar components or features may have the same reference numerals in the accompanying drawings. It is expected that the elements disclosed in one aspect may be used in other aspects without special instructions. However, it should be noted that the accompanying drawings only illustrate certain typical aspects of the present invention and should not be considered as limiting its scope, because the specification may allow other equally effective aspects.

[0014] Figure 1 A block diagram of an MCU including a PMM hardware module in the prior art is shown.

[0015] Figure 2 A block diagram of a microcontroller unit (MCU) including a DMA PMM according to an embodiment of the present invention is shown.

[0016] Figure 3 A flow chart of performing priority management on a transmission group according to an embodiment of the present invention is shown.

[0017] Figure 4 A schematic diagram showing priority management of a transmission group by a DMA PMM according to an embodiment of the present invention is shown.

[0018] Figure 5 A schematic diagram showing a data structure in a DMA PMM according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0019] The following description provides an example of a DMA PMM and does not limit the scope, applicability or examples set forth in the claims. Without departing from the scope of the present invention, the functions and arrangements of the elements discussed may be changed. Various examples may omit, replace or add various processes or components as appropriate. For example, the method described may be performed in an order different from that described, and various steps may be added, omitted or combined. Moreover, the features described for some examples may be combined in some other examples. For example, any number of aspects set forth herein may be used to implement a method or device. In addition, the scope of the present invention is intended to cover such a device or method implemented using other structures, functions, or structures and functions that are supplementary or alternative to the various aspects of the present invention set forth herein. It should be understood that any aspect of the disclosure disclosed herein may be embodied by one or more elements of the claims. The word "exemplary" is used herein to mean "used as an example, instance or illustration". Any aspect described herein as "exemplary" need not be interpreted as being more preferred or advantageous than other aspects.

[0020] For ease of description, the following is an exemplary description of the application scenario of SPI communication. However, this is only an example and not a limitation. It should be understood that the present invention can also be applied to other serial communications (including but not limited to, for example, I 2 C, UART, etc.).

[0021] Figure 2 FIG. 2 is a block diagram of a microcontroller unit (MCU) 200 including a DMA PMM according to an embodiment of the present invention. The MCU 200 includes a SPI transmit (TX) module 202 , a DMA 206 , and a DMA PMM 208 .

[0022] The SPI communication between chips is divided into multiple transmission groups (TG for short).

[0023] and Figure 1 Similar to the function of the SPI PMM 104 in the DMA PMM 208, the DMA PMM 208 can perform priority management on multiple transmission groups. For example, when new TGs 105-1'~105-8' arrive, the DMA PMM 208 configures the new TGs 105-1'~105-8' into the queue of TGs105-1~105-8 in order of priority. The DMA PMM 208 includes a software program and a hardware linked list (e.g., a DMA linked list). The software program includes: querying and updating the transmission status of each transmission group in the transmission group queue in turn according to the priority of the transmission group (query module); configuring the transmission group queue according to the result of the query and the priority of the transmission group (configuration module); and triggering DMA to transmit the transmission group queue (trigger module). The completion of the transmission of one TG in the TG queue will trigger the next TG to start transmission.

[0024] In response to a hardware trigger request (eg, SPI request), DMA 206 automatically transfers the queue of TGs 105-1 to 105-8 from a source address to a target address in SPI transmit (TX) module 202 via a DMA channel. Each DMA channel has a hardware chain mode, also called a linked list mode.

[0025] Figure 3 FIG. 3 is a flowchart 300 for managing the priority of a transmission group according to an embodiment of the present invention. Figure 2 The DMAPMM 208 shown is implemented to include a plurality of steps 302-326.

[0026] In step 302, DMAPMM 208 receives a request for a new TG for SPI transfer.

[0027] In step 304, DMA PMM 208 starts an iterator. The iterator is used to record the transmission status of the TG in the current TG queue. The transmission status includes: completed transmission, transmitting, and not yet transmitted.

[0028] In step 306 , the DMA PMM 208 queries whether the DMA 206 is idle (ie, the DMA 206 is not transmitting TG). If the DMA 206 is not idle, the process proceeds to step 308 ; otherwise, the process proceeds to step 312 .

[0029] In step 312, DMA PMM 208 determines whether there is a next iterator, that is, whether there is a next TG in the current TG queue. If there is a next TG in the current TG queue, proceed to step 314; otherwise, proceed to step 316.

[0030] In step 314, DMA PMM 208 queries the transmission status of the next TG in the current TG queue, and then returns to step 306 to continue querying whether DMA 206 is idle.

[0031] The loop of steps 306, 312 and 314 enables the DMA PMM 208 to query and update the transmission status of each TG in the current TG queue in sequence according to the priority order (eg, completed transmission, transmitting, not yet transmitted).

[0032] In step 316, DMA PMM 208 determines that the TG queue has been completely transferred and DMA 206 is now in an idle state, so DMA PMM 208 can trigger DMA 206 to transfer the new TG, and then the process ends (step 326).

[0033] In step 308 , DMA PMM 208 determines whether a hardware linked list (hereinafter referred to as linked list) exists. If the linked list exists, the process proceeds to step 310 ; otherwise, the process proceeds to step 318 .

[0034] In step 310 , the DMA PMM 208 compares the priority of the new TG with the priorities of all TGs in the linked list and then proceeds to step 316 .

[0035] In step 316, DMAPMM 208 determines whether it is necessary to insert the new TG into the linked list according to the comparison result. Specifically, if the priority of the new TG is higher than the priority of one or more TGs in the linked list that have not yet been transmitted, then the process proceeds to step 320, DMA PMM 208 configures the new TG before the TG with a low priority that has not yet been transmitted and after the TG with a low priority that is being transmitted, then DMA PMM 208 updates the linked list information (step 324) and ends (step 326). If the priority of the new TG is lower than the priority of all TGs in the linked list, then the process proceeds to step 322, DMA PMM 208 configures the new TG after all TGs in the linked list, then DMA PMM 208 updates the linked list information (step 324) and ends (step 326).

[0036] In step 318, DMA PMM 208 directly configures the new TG into the linked list so as to transmit the new TG through DMA 206, and then updates the linked list information (step 324) and ends (step 326).

[0037] Figure 4 A schematic diagram 400 is shown of a DMA PMM performing priority management on a transmission group according to an embodiment of the present invention. The transmission group includes TG 401, TG 402, TG 403, and TG 404. The priorities from high to low are: TG 401>TG 402>TG 403>TG 404.

[0038] like Figure 4 As shown, first, DMA PMM simultaneously receives a transmission request for TG 401 (block 401-1) and a transmission request for TG 404 (block 404-1). Since the priority of TG 401 is higher than that of TG 404, TG 401 is transmitted first (block 401-2) and then TG 404 is transmitted (block 404-2).

[0039] While TG 404 is transmitting, DMA PMM receives a transmission request for TG 403 (block 403-1) and a transmission request for TG 402 (block 402-1) in succession. Although the priorities of TG 402 and TG 403 are both higher than the priority of TG 404 which is transmitting, the transmission of TG 404 (block 404-2) is not interrupted. DMA PMM configures TG 402 and TG 403 into a linked list in order of priority to wait for transmission.

[0040] After the transmission of TG 404 (block 404-2) is completed, TG 402 (block 402-2) and TG 403 (block 403-2) in the linked list are transmitted in sequence.

[0041] Figure 5 A schematic diagram 500 shows a data structure of a DMA PMM according to one embodiment of the present invention.

[0042] As described above, DMA PMM maintains the information and linked list of TG. The data structure of DMA PMM includes register 502 and linked list 504. For the sake of simplicity, it is only for example and not for limitation. Figure 5 The description is expanded as if the linked list length is 4.

[0043] like Figure 5 As shown, the DMA PMM includes a register 502 and a linked list 504. The linked list 504 includes a node 504-0, a node 504-1, a node 504-2, and a node 504-3.

[0044] First, DMA PMM initializes the linked list 504. Specifically, the source address and the target address in nodes 504-0 to 504-3 are set to dummy, and the LLI mode in nodes 504-0 to 504-3 is set to off to avoid source addresses and target addresses pointing to unknown areas and causing program errors. In addition, each node includes a bidirectional pointer (including: forward pointer *prev, backward pointer *next), which is used to point to the entry address of the previous node and the entry address of the next node respectively, so that nodes 504-0 to 504-3 are connected end to end to form a linked list 504. For example, in Figure 5 In the example, the forward pointer *prev in node 504-0 points to the entry address of node 504-3, and the backward pointer *next points to the entry address of node 504-1; the forward pointer *prev in node 504-1 points to the entry address of node 504-0, and the backward pointer *next points to the entry address of node 504-2; the forward pointer *prev in node 504-2 points to the entry address of node 504-1, and the backward pointer *next points to the entry address of node 504-3; the forward pointer *prev in node 504-3 points to the entry address of node 504-2, and the backward pointer *next points to the entry address of node 504-0.

[0045] Then, the DMA PMM can start to prioritize the received TGs.

[0046] When the DMA PMM receives the first frame TG 1, the DMA PMM directly loads the first frame TG 1 into the register 502 so that the DMA can transfer it to the SPI TX register. Specifically, the DMA PMM sets the source address in the register 502 to the source address of the first frame TG 1, sets the destination address in the register 502 to the address of the first frame TG 1 to be transferred to the SPI TX register, sets the LLI mode in the register 502 to on, and points the back pointer *next in the register 502 to the entry address of the node 504-0.

[0047] During the transmission of the first frame TG 1, if the DMA PMM receives the second frame TG 2, the DMA PMM configures the second frame TG 2 into the node 504-0 to wait for transmission. Specifically, the DMA PMM sets the source address in the node 504-0 to the source address of the second frame TG 2, sets the target address in the node 504-0 to the address of the first frame TG 2 to be transmitted to the SPITX register, and sets the LLI mode in the node 504-0 to be on.

[0048] After the transmission of the first frame TG 1 is completed, if the DMA PMM receives the second frame TG 2, the DMAPMM directly loads the second frame TG 2 into the register 502 so as to be transmitted to the SPI TX register by the DMA.

[0049] When the first frame TG 1 in the register 502 is being transmitted and the second frame TG 2 in the node 504-0 has not been transmitted, if the DMAPMM receives the third frame TG 3, the DMA PMM compares the priorities of the second frame TG 2 and the third frame TG 3. If the priority of the second frame TG 2 is higher than the priority of the third frame TG 3, the DMAPMM configures the third frame TG 3 into the node 504-1. If the priority of the second frame TG 2 is lower than the priority of the third frame TG 3, the DMA PMM will change the position of the second frame TG 2 in the linked list 504, that is, the DMA PMM moves the second frame TG 2 from the node 504-0 backward to the node 504-1 and configures the third frame TG 3 into the node 504-0.

[0050] When the first frame TG 1 in the register 502 has completed transmission and the second frame TG 2 in the node 504-0 is being transmitted, if the DMA PMM receives the third frame TG 3, even if the priority of the second frame TG 2 is lower than the priority of the third frame TG 3, the DMA PMM neither interrupts the transmission of the second frame TG 2 nor changes the position of the second frame TG 2 in the linked list 504, but configures the third frame TG 3 to the node 504-1.

[0051] When the first frame TG 1 in the register 502 has completed transmission, the second frame TG2 in the node 504-0 is being transmitted, and the third frame TG 3 in the node 504-1 has not yet been transmitted, if the DMA PMM receives the fourth frame TG 4, the DMA PMM compares the priorities of the third frame TG 3 and the fourth frame TG 4. If the priority of the third frame TG 3 is higher than the priority of the fourth frame TG 4, the DMAPMM configures the fourth frame TG 4 into the node 504-2. If the priority of the third frame TG 3 is lower than the priority of the fourth frame TG 4, the DMA PMM will change the position of the third frame TG 3 in the linked list 504, that is, move the third frame TG 3 backward from the node 504-1 to the node 504-2, and configure the fourth frame TG 4 into the node 504-1.

[0052] When the first frame TG 1 in the register and the second frame TG 2 in the node 504-0 have completed transmission, and the third frame TG 3 in the node 504-1 is being transmitted, if the DMA PMM receives the fourth frame TG 4, then even if the priority of the third frame TG 3 is lower than the priority of the fourth frame TG 4, the DMA PMM neither interrupts the transmission of the third frame TG 3 nor changes the position of the third frame TG 3 in the linked list 504, but configures the fourth frame TG 4 to the node 504-2.

[0053] Therefore, the priority management rule of DMA PMM for TGs is to configure a TG with a high priority before a TG with a low priority that has not yet transmitted and after a TG with a low priority that is currently transmitting.

[0054] Note that whenever a TG in a register or a node completes a transfer, the DMA PMM resets the source address and the destination address in the register or node where the TG is located to dummy, and resets the LLI mode to off to prevent the source address and the destination address from pointing to unknown areas and causing program errors.

[0055] After all TGs in register 502 and the entire linked list 504 have completed transmission, if DMA PMM receives a new TG, DMA PMM directly configures the new TG into register 502, and then configures the subsequently received TGs according to the above priority management rules to start a new round of SPI transmission.

[0056] It should be understood that Figure 5The modules or units shown in the figure are only exemplary. In practical applications, one or more modules or units may be added or reduced as needed. For example, the register 502 may be omitted, and the DMA PMM may configure the received new transmission group only in the linked list 504 according to the above-mentioned priority management rule to form a transmission group queue. In addition, the length of the linked list 504 is variable, that is, the number of nodes in the linked list 504 is variable.

[0057] The present invention also provides a device for transmitting a group (not shown), the device comprising a microcontroller unit and a memory, wherein the memory is used to store machine executable instructions, and when the machine executable instructions are executed by the microcontroller unit, the microcontroller unit executes the method for transmitting a group of the above-mentioned embodiments of the present invention.

[0058] The present invention further provides a non-transitory machine-readable storage medium storing machine-executable instructions. When the machine-executable instructions are executed by the microcontroller unit, the microcontroller unit executes the method for transmitting a group according to the above-mentioned embodiments of the present invention.

[0059] It should also be understood that all modules in the above described device can be implemented in various ways. These modules can be implemented as hardware, software, or a combination thereof. In addition, any module in these modules can be further divided into submodules or combined together functionally.

[0060] The specific embodiments described above in conjunction with the accompanying drawings describe exemplary embodiments, but do not represent all embodiments that can be implemented or fall within the scope of protection of the claims. The term "example" used throughout this specification may mean "used as an example, instance or illustration" and does not mean "preferred" or "having advantages" over other embodiments. For the purpose of providing an understanding of the described technology, the specific embodiments include specific details. However, these technologies can be implemented without these specific details. In some instances, in order to avoid making the concepts of the described embodiments difficult to understand, well-known structures and devices are shown in block diagram form.

[0061] The methods disclosed herein include one or more steps or actions for implementing these methods. It should be understood that all operations in the methods described above are merely exemplary, and the present invention is not limited to any operation in the method or the order of these operations, but should cover all other equivalent transformations under the same or similar conception. Without departing from the scope of the claims, the method steps and / or actions can be interchangeable with each other. In other words, unless the specific order of steps or actions is specified, the order and / or use of specific steps and / or actions can be modified without departing from the scope of the claims.

[0062] The above description of the present invention is provided to enable any person skilled in the art to make or use the present invention. Various modifications to the present invention will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of the present invention. Therefore, the present invention is not limited to the examples and designs described herein, but is consistent with the widest range of principles and novel features disclosed herein.

Claims

1. A method for managing a transfer group using a hardware linked list at a DMA PMM, comprising: Query step: query and update the transmission status of each transmission group in the transmission group queue in turn according to the priority of the transmission group; Configuration step: configuring the transmission group queue according to the query result and the priority of the transmission group; as well as Triggering step: triggering DMA to transfer the transfer group queue.

2. The method according to claim 1, wherein: The transmission status includes: completed transmission, transmitting, and not yet transmitted.

3. The method according to claim 1, wherein: When the state of the DMA is idle, the triggering step includes: triggering the DMA to directly transmit a new transmission group.

4. The method according to claim 1, wherein: When the state of the DMA is non-idle, the configuration step includes: configuring a new transmission group into the transmission group queue to wait for transmission.

5. The method according to claim 4, wherein: The configuration step includes: when the transmission group queue is empty, directly configuring a new transmission group into the transmission group queue to wait for transmission.

6. The method according to claim 4, wherein: The configuration steps include: When the transmission group queue is not empty, the order of the new transmission group in the transmission group queue is configured by comparing the priority of the new transmission group with the priorities of the transmission groups in the transmission group queue.

7. The method according to claim 6, wherein: The configuration steps include: In the transmission group queue, a transmission group with a high priority that has not been transmitted is arranged before a transmission group with a low priority that has not been transmitted.

8. The method according to claim 6, wherein: The configuration steps include: In the transmission group queue, a transmission group with a high priority that has not yet been transmitted is arranged after a transmission group with a low priority that is being transmitted.

9. The method according to claim 1, wherein: The triggering step includes: the completion of transmission of a transmission group in the transmission group queue will trigger the next transmission group to start transmission.

10. A DMA PMM for managing a transfer group using a hardware linked list, comprising: A query module, used to query and update the transmission status of each transmission group in the transmission group queue in turn according to the priority of the transmission group; A configuration module, configured to configure the transmission group queue according to the query result and the priority of the transmission group; as well as The trigger module is used to trigger the DMA to transfer the transfer group queue.

11. The DMA PMM according to claim 10, wherein: The transmission status includes: completed transmission, transmitting, and not yet transmitted.

12. The DMA PMM according to claim 10, wherein: When the state of the DMA is idle, the trigger module is used to trigger the DMA to directly transmit a new transmission group.

13. The DMA PMM according to claim 10, wherein: When the state of the DMA is non-idle, the configuration module is used to configure a new transmission group into the transmission group queue to wait for transmission.

14. The DMA PMM of claim 13, wherein: The configuration module is used to: When the transmission group queue is empty, a new transmission group is directly configured into the transmission group queue to wait for transmission.

15. The DMA PMM of claim 13, wherein: The configuration module is used to: When the transmission group queue is not empty, the order of the new transmission group in the transmission group queue is configured by comparing the priority of the new transmission group with the priorities of the transmission groups in the transmission group queue.

16. The DMA PMM of claim 15, wherein: The configuration module is used to: In the transmission group queue, a transmission group with a high priority that has not been transmitted is arranged before a transmission group with a low priority that has not been transmitted.

17. The DMA PMM of claim 15, wherein: The configuration module is used to: In the transmission group queue, a transmission group with a high priority that has not yet been transmitted is arranged after a transmission group with a low priority that is being transmitted.

18. The DMA PMM of claim 10, wherein: In the trigger module, the completion of transmission of one transmission group in the transmission group queue will trigger the next transmission group to start transmission.

19. An apparatus for transmitting a group, comprising: Microcontroller unit; as well as A memory storing machine executable instructions which, when executed by the microcontroller unit, cause the microcontroller unit to perform a method according to any one of claims 1 to 9.

20. A non-transitory machine-readable storage medium storing machine-executable instructions which, when executed by the microcontroller unit, cause the microcontroller unit to perform the method according to any one of claims 1 to 9.

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