Multi-layer wiring PCB (printed circuit board) and serial-parallel transceiver

Abstract

The embodiment of the invention provides a multi-layer wiring PCB (Printed Circuit Board) and a serial-parallel transceiver. The multi-layer wiring PCB comprises a first wiring layer and a second wiring layer, the first wiring layer is located above the second wiring layer; a first signal bonding pad is arranged on the upper surface layer of the PCB; a back-drilled signal through hole which is in the vertical direction and penetrates through the first signal bonding pad is formed in the PCB, so that the fan-out wire of the first wiring layer is connected with the first signal bonding pad through the back-drilled signal through hole; the back-drilled signal through hole is a signal through hole subjected to back-drilling processing; the back drilling signal through hole comprises a via hole stub which extends from the first wiring layer to the second wiring layer in the vertical direction and has a first height; the fan-out wires of the second wiring layer are arranged at the positions deviating from the projection area of the via hole stumps. The fan-out wire is arranged at the position deviating from the projection area of the via hole stub, the horizontal distance between the fan-out wire and the via hole stub of other signals is increased, and signal crosstalk between different wire layers is reduced on the basis that the number of stacked PCBs is not increased.

Description

Technical Field

[0001] The present application relates to the technical field of printed circuit boards, and in particular to a multi-layer wiring PCB board and a serial-parallel transceiver. Background Art

[0002] With the rapid development of information technology, high-speed serial communication technology has been widely used in various fields, such as data centers, cloud computing, communication base stations, etc. The requirements for data transmission rates in these applications are also increasing.

[0003] Taking Serdes (serial-to-parallel transceiver) as an example, the transmission rate of serial-to-parallel transceivers is constantly being refreshed. Currently, 56Gbps and 112Gbps Serdes are already widely used, and 224Gbps Serdes are also gradually beginning to be commercialized.

[0004] As the data transmission rate increases, the electromagnetic coupling effect between signals becomes more obvious, and the crosstalk problem becomes more prominent. Since the signal is affected by various factors during the transmission process, such as line impedance, signal attenuation, interference, etc., mutual interference between signals occurs, namely crosstalk. Crosstalk affects the transmission quality of the signal, resulting in data errors and reduced transmission performance. From the perspective of S parameters, when the crosstalk reaches -60dB, 1‰ of the signal energy is coupled to the adjacent signal line; when the crosstalk reaches -40dB, 1% of the signal energy is coupled to the adjacent signal line. For the current more mature 56Gbps Serdes design, the crosstalk on the signal line is required not to exceed -50dB, that is, the energy of crosstalk to the adjacent signal line cannot exceed 3‰.

[0005] Many products’ PCBs (Printed Circuit Boards) usually use through-hole designs for cost reasons. For high-speed PCBs, through-hole designs must include back drilling to increase signal transmission speed and reduce signal distortion. However, back drilling will leave a certain height of via stubs at the end of the signal vias, which may cause the via stubs to be close to the fan-out traces of another trace layer in space, resulting in electromagnetic coupling and signal crosstalk, which greatly affects system performance. Summary of the invention

[0006] The purpose of the embodiments of the present application is to provide a PCB board with multi-layer wiring and a serial-parallel transceiver, so as to reduce the crosstalk between the signal via stubs and the signal lines without increasing the number of stacking layers, thereby optimizing the bit error rate of the chip.

[0007] The specific technical solutions are as follows:

[0008] In a first aspect of the present application, a multi-layer wiring PCB board is provided, comprising:

[0009] A first routing layer and a second routing layer; the first routing layer is not adjacent to the second routing layer, and the first routing layer is located above the second routing layer;

[0010] The upper surface layer of the PCB board is provided with a first signal pad;

[0011] The PCB board is provided with a back-drilled signal via in a vertical direction and passing through the first signal pad, so that the fan-out routing of the first routing layer is connected to the first signal pad through the back-drilled signal via; the back-drilled signal via is a signal via that has been back-drilled; the back-drilled signal via includes: a via stub of a first height extending from the first routing layer to the second routing layer in a vertical direction;

[0012] The fan-out routing of the second routing layer is arranged at a position deviating from the projection area of ​​the via stub, so that the distance between the fan-out routing of the second routing layer and the projection area of ​​the via stub exceeds a preset threshold; wherein the projection area of ​​the via stub is the projection area of ​​the via stub on the second routing layer.

[0013] Optionally, a pad array including the first signal pad is provided on the upper surface layer of the PCB board;

[0014] For each pad, a through hole is arranged in the PCB board in a vertical direction and passes through the pad.

[0015] Optionally, the pad includes a signal pad and a ground pad;

[0016] The fan-out routing of the second routing layer is arranged in the routing channel at a position close to the ground via projection area and deviated from the signal via projection area; the ground via projection area is the projection area of ​​the via set for the ground pad on the second routing layer; the signal via projection area is the projection area of ​​the via set for the signal pad on the second routing layer.

[0017] Optionally, the through hole provided for each pad in the pad array is deviated from the center of the pad along a direction away from the routing channel.

[0018] Optionally, for each through hole, the distance deviating from the center of the corresponding pad is the radius of the pad.

[0019] Optionally, the first routing layer is used to transmit a first differential signal; the first differential signal includes a first differential sub-signal and a second differential sub-signal; the fan-out routing of the first routing layer includes: a first routing line for transmitting the first differential sub-signal, and a second routing line for transmitting the second differential sub-signal;

[0020] The first signal pad includes a first sub-pad and a second sub-pad, and the back-drilled signal via includes: a first back-drilled signal via passing through the first sub-pad and a second back-drilled signal via passing through the second sub-pad;

[0021] The first trace is connected to the first sub-pad through the first back-drilled signal via; and the second trace is connected to the second sub-pad through the second back-drilled via.

[0022] Optionally, the second routing layer is used to transmit a second differential signal; the second differential signal includes a third differential sub-signal and a fourth differential sub-signal; the fan-out routing of the second routing layer includes: a third routing for transmitting the third differential sub-signal, and a fourth routing for transmitting the fourth differential sub-signal;

[0023] The upper surface layer of the PCB board is provided with a second signal pad; the second signal pad includes a third sub-pad and a fourth sub-pad; the PCB board is provided with a third back-drilled signal through hole in a vertical direction and passing through the third sub-pad, and the PCB board is provided with a fourth back-drilled signal through hole in a vertical direction and passing through the fourth sub-pad;

[0024] The third routing line is connected to the third sub-pad through the third back-drilled signal via; and the fourth routing line is connected to the fourth sub-pad through the fourth back-drilled via.

[0025] Optionally, it also includes: a reference stratum and a medium layer;

[0026] The ground pad is connected to at least one reference ground layer through a ground via penetrating the ground pad.

[0027] A second aspect of the present application provides a serial-to-parallel transceiver, comprising: any one of the above-mentioned PCB boards.

[0028] A third aspect of the present application provides a chip, comprising: any one of the above-mentioned PCB boards.

[0029] Beneficial effects of the embodiments of the present application:

[0030] The PCB board with a multi-layer layout provided in an embodiment of the present application comprises: a first routing layer and a second routing layer; the first routing layer is not adjacent to the second routing layer, and the first routing layer is located above the second routing layer; a first signal pad is arranged on the upper surface of the PCB board; a back-drilled signal through hole is arranged in a vertical direction and passes through the first signal pad, so that a fan-out routing of the first routing layer is connected to the first signal pad through the back-drilled signal through hole; the back-drilled signal through hole is a signal through hole that has been back-drilled; the back-drilled signal through hole comprises: a via stub of a first height extending from the first routing layer to the second routing layer in a vertical direction; the fan-out routing of the second routing layer is arranged at a position deviating from a projection area of ​​the via stub, so that the distance between the fan-out routing of the second routing layer and the projection area of ​​the via stub exceeds a preset threshold; wherein the projection area of ​​the via stub is a projection area of ​​the via stub on the second routing layer.

[0031] By setting the fan-out routing at a position deviating from the projection area of ​​the via stub, the horizontal distance between the fan-out routing and the via stubs of other signals is increased, and the spatial distance between the fan-out routing and the via stubs is increased, thereby reducing the crosstalk of signals between different routing layers without increasing the number of PCB stacking.

[0032] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0034] Figure 1 It is a schematic diagram of the PCB stacking structure of the serial-parallel transceiver;

[0035] Figure 2 A schematic diagram of a pad array of a serial-to-parallel transceiver;

[0036] Figure 3 is a cross-sectional diagram of a serial-to-parallel transceiver;

[0037] Figure 4 This is a schematic diagram of fanning out differential signals at Layer 2;

[0038] Figure 5 A schematic diagram of a PCB stacking structure of a serial-to-parallel transceiver provided in an embodiment of the present application;

[0039] Figure 6 A schematic diagram of a cross section of a serial-to-parallel transceiver provided in an embodiment of the present application;

[0040] Figure 7 A schematic diagram of a routing channel provided in an embodiment of the present application;

[0041] Figure 8 A schematic diagram of an eccentric through hole provided in an embodiment of the present application;

[0042] Fig. 9 A schematic diagram of a fan-out routing provided in an embodiment of the present application. DETAILED DESCRIPTION

[0043] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0044] For high-speed PCBs, that is, PCBs that need to transmit high-frequency and high-speed signals, it is usually necessary to back-drill the signal vias to increase the signal transmission speed and reduce signal distortion. However, back-drilling will leave a certain height of via stubs at the end of the signal vias, which may cause the via stubs to be close to the fan-out traces of another routing layer in space, resulting in electromagnetic coupling and signal crosstalk, which greatly affects the performance of the system.

[0045] Among them, back drilling is a technology used to remove part of the unused through-hole from the through-hole of the electronic PCB. The back drilling process is also called PCB controlled depth drilling. In the back drilling process, the back drilling technology cannot completely remove the unused through-hole part to avoid affecting the through-hole part that needs to be used. Therefore, back drilling usually leaves residual via stumps.

[0046] To facilitate understanding, the causes of the above signal crosstalk are analyzed with reference to specific examples.

[0047] As an example, taking a serial-to-parallel transceiver as an example, see Figure 1 , which is a schematic diagram of the PCB stacking structure of the serial-parallel transceiver, such as Figure 1 As shown, Layer 1 and Layer 2 are used as routing layers for Serdes signals, in addition to a reference ground layer and a dielectric layer. Figure 1 The material and thickness of each layer are also shown, where IT968G is a dielectric material.

[0048] See also Figure 2 , is a schematic diagram of the pad array of the serial-parallel transceiver, and the pad array is arranged on the upper surface layer. Figure 2 As shown, there are 2 pairs of differential signals that need to be fanned out, one pair includes TXP (Transmit Positive, positive polarity at the transmitting end) signal and TXN (Transmit Negative, negative polarity at the transmitting end) signal; the other pair includes RXP (receive Positive, positive polarity at the receiving end) signal and RXN (receive Negative, negative polarity at the receiving end) signal.

[0049] Among them, differential transmission is a signal transmission technology. Different from the traditional method of one signal line and one ground line, differential transmission transmits signals on both lines. The two signals have the same amplitude and opposite phase. The signal transmitted on these two lines is a differential signal. The signal receiving end compares the difference between the two voltages to determine whether the sending end sends a logic 0 or a logic 1. On the circuit board, the differential traces must be two lines of equal length, equal width, close proximity, and on the same layer.

[0050] Figure 2 In the example shown, the TXP signal and the TXN signal are fanned out at Layer 1, and the RXP signal and the RXN signal are fanned out at Layer 2. Figure 2 TX_P and TX_N shown in the figure represent signal pads corresponding to the differential signals TXP and TXN, respectively. RX_P and RX_N represent signal pads corresponding to the differential signals RXP and RXN, respectively.

[0051] See also Figure 3 , is a cross-sectional diagram of a serial-to-parallel transceiver, as shown in Figure 3 As shown in the figure, in order to fan out differential signals on Layer 1, vias (Via) need to be drilled for the TX_P signal pad and the TX_N signal pad, including TXP Via and TXN Via. In order to increase signal transmission speed and reduce signal distortion, the signal vias need to be back-drilled. However, due to the process limitations of back-drilling, a certain height of via stubs (Via Stub) will be left at the end of the signal vias, which is about 8 mils. Figure 3 As shown, the generated Via Stub is very close to Layer 2 in vertical distance.

[0052] also, Figure 3 The through hole GND Via drilled for the GND pad, that is, the ground pad, is shown in FIG. 1 . There is no need to perform back drilling on the GND Via, so no via stump is generated. Figure 3The through holes for the RX_P signal pad and the RX_N signal pad are also shown, namely RXP Via and RXN Via. Since back drilling is also required, via stubs will also be generated. However, since the RXP signal and RXN signal are fanned out at Layer 2, the corresponding via stubs will not interfere with the fan-out signal at Layer 1.

[0053] See also Figure 4 , which is a schematic diagram of fanning out differential signals at Layer 2 in the related art. Since the pads are only set on the upper surface of the serial-to-parallel transceiver, Figure 4 The GND, TX_P, TX_N, RX_P and RX_N shown in the figure can be understood as the projection of the pad on Layer 2. Figure 4 The Via shown is the projection of the through hole on Layer 2, and the Via Stub is the projection of the via stub on Layer 2. Figure 4 As shown, when the fan-out routing is set in the middle area of ​​the routing channel, the horizontal distance between the signal through hole projection area (the dotted circle part) in the TX_P pad projection area and the signal through hole projection area in the TX_N pad projection area is very close.

[0054] Specifically, taking the more common 1mm Ball Pitch (solder ball spacing) / 0.6mm Ball Pad Diameter (solder ball diameter) as an example, the signal via diameter is 8mil, and the 90ohm differential signal is designed according to the 4mil line width and 3mil routing spacing.

[0055] according to Figure 4 In the conventional routing method shown, when the signal is routed out from the middle of the routing channel, the horizontal spacing Space1 between the fan-out routing and the TXP signal Via Stub and TXN signal Via Stub is 10.185 mil, and the calculation method is as follows:

[0056] Space1=(39.37-8-4-3-4)÷2=10.185mil

[0057] Among them, 39.37mil is equal to 1mm.

[0058] As mentioned above, since the via stub generated by back drilling in Layer 1 is very close to Layer 2 in vertical distance, and the above horizontal spacing is small, the spatial distance between the via stub and the fan-out routing in Layer 2 is very close, which makes it easy for electromagnetic coupling to occur, resulting in signal crosstalk, which greatly affects the performance of the system.

[0059] At present, in order to reduce the above signal crosstalk, the method generally adopted in the related art is to perform cross-layer processing on the routing of Serdes signals of adjacent layers. Figure 5 , is another schematic diagram of the PCB stacking structure of the serial-parallel transceiver, such as Figure 5 As shown in the figure, the routing layer is increased from two layers to three layers. Thus, the TXP signal and TXN signal can be fanned out at Layer 1, and the RXP signal and RXN signal can be fanned out at Layer 3.

[0060] See also Figure 6 , is another schematic diagram of the cross section of a serial-to-parallel transceiver, such as Figure 6 As shown, the Via Stub of the TXP signal and the Via Stub of the TXN signal are away from Layer 3 in the vertical direction, so that the vertical space between the fan-out routing of the RXP signal and the RXN signal and the Via Stub can be increased, thereby reducing the crosstalk between the two.

[0061] However, reducing crosstalk by increasing the number of stacked layers will bring new disadvantages. Specifically, they include: 1) Increasing the number of stacked layers will increase the cost. 2) Increasing the number of stacked layers will increase the overall thickness of the PCB, causing some assembly problems and not conducive to the miniaturization of electronic devices.

[0062] In order to solve the above technical problems, the embodiment of the present application designs a wiring method for fan-out traces, which increases the distance between the fan-out traces and the via stubs in the horizontal direction without increasing the number of stacking layers, so as to reduce signal crosstalk.

[0063] Specifically, an embodiment of the present application provides a multi-layer wiring PCB board, including:

[0064] The first routing layer and the second routing layer; the first routing layer and the second routing layer are not adjacent to each other, and the first routing layer is located above the second routing layer;

[0065] The upper surface layer of the PCB board is provided with a first signal pad;

[0066] The PCB board is provided with a back-drilled signal via in a vertical direction and passing through the first signal pad, so that the fan-out routing of the first routing layer is connected to the first signal pad through the back-drilled signal via; the back-drilled signal via is a signal via that has been back-drilled; the back-drilled signal via includes: a via stub of a first height extending from the first routing layer to the second routing layer in a vertical direction;

[0067] The fan-out routing of the second routing layer is arranged at a position deviating from the projection area of ​​the via stub, so that the distance between the fan-out routing of the second routing layer and the projection area of ​​the via stub exceeds a preset threshold; wherein the projection area of ​​the via stub is the projection area of ​​the via stub on the second routing layer.

[0068] It should be noted that the PCB board provided in the embodiment of the present application does not only include the first routing layer and the second routing layer. Those skilled in the art can understand that a dielectric layer and a reference ground layer are also required to be set in the PCB board, and the distribution of the dielectric layer and the reference ground layer is not limited.

[0069] In the embodiment of the present application, the first routing layer is located above the second routing layer, but the two are not adjacent to each other. For example, a dielectric layer and / or a reference ground layer are provided between the first routing layer and the second routing layer.

[0070] Those skilled in the art will appreciate that a pad is usually provided on the upper surface of a PCB board, and a through hole is provided passing through the pad, and the hole wall of the through hole is metallized, such as copper plating, so that the wiring inside the PCB board can be connected to the pad through the through hole.

[0071] In an embodiment of the present application, a first signal pad is provided on the upper surface layer of the PCB board, and the first signal pad needs to be connected to the fan-out routing of the first routing layer. A back-drilled signal via is provided in the PCB board in a vertical direction and passes through the first signal pad, so that the fan-out routing of the first routing layer is connected to the first signal pad through the back-drilled signal via. The back-drilled signal via refers to a signal via that has been back-drilled.

[0072] Specifically, back-drilling the signal via will generate via stubs of a certain height, and the via stubs extend from the first wiring layer to the second wiring layer in a vertical direction.

[0073] The projection area of ​​the via stub on the second routing layer is recorded as the via stub projection area. When setting the fan-out routing of the second routing layer, the fan-out routing is set at a position deviating from the via stub projection area, so that the distance between the fan-out routing of the second routing layer and the via stub projection area exceeds a preset threshold.

[0074] It can be seen that the multi-layer wiring PCB board provided in the embodiment of the present application, by setting the fan-out routing at a position deviating from the projection area of ​​the via stub, increases the horizontal distance between the fan-out routing and the via stub, and then increases the spatial distance between the fan-out routing and the via stub, thereby reducing the crosstalk of signals between different routing layers without increasing the number of PCB stacking layers.

[0075] In one embodiment of the present application, a pad array including a first signal pad is disposed on the upper surface layer of the PCB board; for each pad, a through hole is disposed in the PCB board in a vertical direction and passes through the pad.

[0076] Specifically, the pads disposed on the surface of the PCB are usually arranged regularly to form an array. Figure 2 , Figure 2 The 6×2 pad array shown here contains two rows and six columns of regularly arranged pads. For the same row, the distance between adjacent pads is fixed; for pad pairs contained in the same column, the distance between pads is also fixed.

[0077] For each pad, a through hole is provided in the PCB board in a vertical direction and passes through the pad, so that the traces of each layer can be connected to the pad of the PCB board through the through hole.

[0078] The pads specifically include signal pads and ground pads. Specifically, for the signal pads, the through holes provided are signal through holes, which are used to connect the fan-out traces of the trace layer and the signal pads on the upper surface layer of the PCB. For the ground pads, the through holes provided are ground through holes, which are used to connect the reference ground layer. For the ground through holes, back drilling is not required.

[0079] Correspondingly, the projection area of ​​the through hole set for the signal pad on the second routing layer is recorded as the signal through hole projection area, and the projection area of ​​the through hole set for the ground pad on the second routing layer is recorded as the ground through hole projection area.

[0080] Therefore, the fan-out routing of the second routing layer is arranged as close to the projection area of ​​the ground via in the routing channel as possible and away from the projection area of ​​the signal via.

[0081] The routing channel is the area in the routing layer of the PCB board used to set the fan-out routing. The fan-out routing cannot touch the through hole. As an example, see Figure 7 , Figure 7 The area range of the routing channel is shown. As long as the fan-out routing is arranged in this area, it will not contact the through hole.

[0082] In one embodiment of the present application, the through hole provided for each pad in the pad array is deviated from the center of the pad along a direction away from the routing channel.

[0083] Specifically, the through hole set for each pad is an eccentric through hole, that is, the center of the through hole is not aligned with the center of the pad, but deviates from the center of the pad in a direction away from the routing channel, thereby leaving a larger routing space.

[0084] According to current process capabilities, for each through hole, the maximum distance offset from the center of the corresponding pad is the radius of the pad.

[0085] As an example, see Figure 8 , the through hole is deviated from the center of the pad in the direction away from the routing channel, providing a larger routing range. Therefore, the fan-out routing can be set at a position farther away from the projection area of ​​the signal through hole, further reducing the crosstalk of signals between different routing layers.

[0086] As an example, see Fig. 9 , the signal via and GND via on both sides of the routing channel are offset to the sides of the routing channel. In this case, the ball pad is designed with a diameter of 0.6mm. Under normal processing technology, the eccentric hole design can be offset by 0.3mm. After the offset, the center spacing of the vias on both sides of the routing channel is 1.6mm, that is, 62.99mil.

[0087] In the through-hole board design, GND Via does not need to be back-drilled, so the distance between the signal trace and GND Via can be reduced. According to the current conventional processing technology, the distance between the signal trace and GND Via can be reduced to 7mil. The RXP / N signal is offset toward the GND Via according to the requirement of 7mil distance from the GND Via. At this time, the distance between the RXP / N signal and the TXP / N signal Via Stub can be increased to 36.99mil. The calculation method is as follows:

[0088] Space=62.99-8-4-3-4-7=36.99mil

[0089] It can be seen that through the combination of offsetting the via and offsetting the signal trace to the ground via, the horizontal distance between the fan-out trace and the via stub projection area is expanded from 10.185 mil to 36.99 mil, which significantly reduces the spatial distance between the fan-out trace and the via stub, thereby optimizing the signal crosstalk between the signal trace and the via stub in the fan-out area.

[0090] It should be noted that Fig. 9 The routing method shown is only an example and is not intended to limit the present application. As long as the fan-out routing is set away from the projection area of ​​the via stub in the routing channel so that the distance between the fan-out routing and the via stub area is greater than a preset threshold, it falls within the protection scope of the present application.

[0091] In addition, the embodiment of the present application does not limit the corners of the fan-out routing. Fig. 9 A 45-degree corner is shown, but arc corners, right-angle corners, etc. may also be used.

[0092] In one embodiment of the present application, the first routing layer is used to transmit a first differential signal; the first differential signal includes a first differential sub-signal and a second differential sub-signal; the fan-out routing of the first routing layer includes: a first routing line for transmitting the first differential sub-signal, and a second routing line for transmitting the second differential sub-signal;

[0093] The first signal pad includes a first sub-pad and a second sub-pad, and the back-drilled signal via includes: a first back-drilled signal via passing through the first sub-pad and a second back-drilled signal via passing through the second sub-pad;

[0094] The first trace is connected to the first sub-pad through the first back-drilled signal via; and the second trace is connected to the second sub-pad through the second back-drilled via.

[0095] Specifically, differential signaling is a signal transmission technology that works by transmitting signals on two wires with equal amplitudes and opposite phases. The signal receiving end determines whether the signal is a logic 0 or a logic 1 by comparing the difference between the two voltages. On a circuit board, differential traces must be two lines of equal length, width, close proximity, and on the same layer.

[0096] In this embodiment, the first routing layer is configured to transmit a first differential signal, which includes a first differential sub-signal and a second differential sub-signal; accordingly, the fan-out routing of the first routing layer includes: a first routing for transmitting the first differential sub-signal and a second routing for transmitting the second differential sub-signal.

[0097] Correspondingly, on the upper surface layer of the PCB, the first signal pad also includes two sub-pads, namely a first sub-pad and a second sub-pad, and the back-drilled signal via includes: a first back-drilled signal via passing through the first sub-pad and a second back-drilled signal via passing through the second sub-pad.

[0098] For each differential signal, a backdrilled signal via is used to connect the trace and the pad, that is, the first trace is connected to the first sub-pad through the first backdrilled signal via; the second trace is connected to the second sub-pad through the second backdrilled via.

[0099] Since the transmission rate of differential signals is relatively high and crosstalk is easily generated, the structure of the PCB board provided in the embodiment of the present application can increase the distance between the signal routing and other via stubs for each differential signal, thereby reducing signal crosstalk.

[0100] In one embodiment of the present application, the second routing layer is used to transmit a second differential signal; the second differential signal includes a third differential sub-signal and a fourth differential sub-signal; the fan-out routing of the second routing layer includes: a third routing line for transmitting the third differential sub-signal, and a fourth routing line for transmitting the fourth differential sub-signal;

[0101] The upper surface layer of the PCB board is provided with a second signal pad; the second signal pad includes a third sub-pad and a fourth sub-pad; the PCB board is provided with a third back-drilled signal through hole in a vertical direction and passing through the third sub-pad, and the PCB board is provided with a fourth back-drilled signal through hole in a vertical direction and passing through the fourth sub-pad;

[0102] The third routing line is connected to the third sub-pad through the third back-drilled signal via; and the fourth routing line is connected to the fourth sub-pad through the fourth back-drilled via.

[0103] Specifically, the second routing layer can also be used to transmit differential signals. Accordingly, the fan-out routing of the second routing layer includes: a third routing for transmitting a third differential sub-signal, and a fourth routing for transmitting the fourth differential sub-signal;

[0104] Correspondingly, the upper surface layer of the PCB board is also provided with a second signal pad, which includes a third sub-pad and a fourth sub-pad, and is connected to the fan-out trace of the second trace layer through back-drilled signal vias. The specific connection method is the same as that of the first trace layer, and will not be repeated.

[0105] In this embodiment, the routing layers all transmit differential signals, and the structure of this PCB board can be used to implement a serial-to-parallel transceiver. SerDes is the abbreviation of SERializer (serializer) / DESerializer (deserializer), which is a mainstream time-division multiplexing, point-to-point serial communication technology. The transmitting end converts multiple low-speed parallel signals into high-speed serial signals, and the high-speed serial signals are converted back into low-speed parallel signals at the receiving end through the transmission medium (optical cable or copper wire). This point-to-point serial communication technology makes full use of the channel capacity of the transmission medium, reduces the number of transmission channels and device pins required, and improves the signal speed, thereby greatly reducing the communication cost.

[0106] The present application also provides a serial-to-parallel transceiver, comprising any of the above-mentioned PCB boards.

[0107] The present application also provides a chip, comprising any of the above-mentioned PCB boards.

[0108] By adopting the serial-to-parallel transceiver and chip provided in the embodiments of the present application, the fan-out routing is set at a position deviating from the projection area of ​​the via stub, the horizontal distance between the fan-out routing and the via stubs of other signals is increased, and the spatial distance between the fan-out routing and the via stubs is increased, thereby reducing the crosstalk of signals between different routing layers without increasing the number of PCB stacking layers.

[0109] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium, for example, the computer instructions may be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium may be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0110] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0111] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0112] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A multi-layer wiring PCB board, characterized in that: include: A first routing layer and a second routing layer; the first routing layer is not adjacent to the second routing layer, and the first routing layer is located above the second routing layer; The upper surface layer of the PCB board is provided with a first signal pad; The PCB board is provided with a back-drilled signal via in a vertical direction and passing through the first signal pad, so that the fan-out routing of the first routing layer is connected to the first signal pad through the back-drilled signal via; the back-drilled signal via is a signal via that has been back-drilled; the back-drilled signal via includes: a via stub of a first height extending from the first routing layer to the second routing layer in a vertical direction; The fan-out routing of the second routing layer is arranged at a position deviating from the projection area of ​​the via stub, so that the distance between the fan-out routing of the second routing layer and the projection area of ​​the via stub exceeds a preset threshold; wherein the projection area of ​​the via stub is the projection area of ​​the via stub on the second routing layer.

2. The PCB board according to claim 1, characterized in that: The upper surface layer of the PCB board is provided with a pad array including the first signal pad; For each pad, a through hole is arranged in the PCB board in a vertical direction and passes through the pad.

3. The PCB board according to claim 2, characterized in that: The pads include a signal pad and a ground pad; The fan-out routing of the second routing layer is arranged in the routing channel at a position close to the ground via projection area and deviated from the signal via projection area; the ground via projection area is the projection area of ​​the via set for the ground pad on the second routing layer; the signal via projection area is the projection area of ​​the via set for the signal pad on the second routing layer.

4. The PCB board according to claim 2, characterized in that: The through hole arranged for each pad in the pad array is deviated from the center of the pad along a direction away from the routing channel.

5. The PCB board according to claim 4, characterized in that: For each through hole, the distance from the center of the corresponding pad is the radius of the pad.

6. The PCB board according to claim 1, characterized in that: The first routing layer is used to transmit a first differential signal; The first differential signal includes a first differential sub-signal and a second differential sub-signal; the fan-out routing of the first routing layer includes: a first routing for transmitting the first differential sub-signal, and a second routing for transmitting the second differential sub-signal; The first signal pad includes a first sub-pad and a second sub-pad, and the back-drilled signal via includes: a first back-drilled signal via passing through the first sub-pad and a second back-drilled signal via passing through the second sub-pad; The first trace is connected to the first sub-pad through the first back-drilled signal via; and the second trace is connected to the second sub-pad through the second back-drilled via.

7. The PCB board according to claim 6, characterized in that: The second routing layer is used to transmit a second differential signal; the second differential signal includes a third differential sub-signal and a fourth differential sub-signal; the fan-out routing of the second routing layer includes: a third routing line for transmitting the third differential sub-signal, and a fourth routing line for transmitting the fourth differential sub-signal; The upper surface layer of the PCB board is provided with a second signal pad; the second signal pad includes a third sub-pad and a fourth sub-pad; the PCB board is provided with a third back-drilled signal through hole in a vertical direction and passing through the third sub-pad, and the PCB board is provided with a fourth back-drilled signal through hole in a vertical direction and passing through the fourth sub-pad; The third routing line is connected to the third sub-pad through the third back-drilled signal via; and the fourth routing line is connected to the fourth sub-pad through the fourth back-drilled via.

8. The PCB board according to claim 1, characterized in that: Also includes: Reference strata and dielectric layers; The ground pad is connected to at least one reference ground layer through a ground via penetrating the ground pad.

9. A serial-to-parallel transceiver, characterized in that: include: A PCB board as claimed in any one of claims 1 to 8.

10. A chip, characterized in that: include: A PCB board as claimed in any one of claims 1 to 8.

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