Manufacturing method of three-dimensional memory, three-dimensional memory and memory system

Abstract

The embodiment of the invention provides a manufacturing method of a three-dimensional memory, the three-dimensional memory and a memory system. The manufacturing method of the three-dimensional memory comprises the steps that a semiconductor structure is provided, the semiconductor structure comprises a substrate, a sacrificial layer, a protective layer, a stack structure and a channel structure, the sacrificial layer, the protective layer and the stack structure are sequentially located on one side of the substrate, and the channel structure penetrates through the stack structure and extends into the substrate; the channel structure comprises a functional layer and a channel layer from outside to inside; forming an opening penetrating through the substrate to the sacrificial layer; removing the sacrificial layer through the opening to form a sacrificial gap; and removing a portion of the functional layer exposed to the sacrificial gap.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and more specifically, to a method for manufacturing a three-dimensional memory, a three-dimensional memory, and a memory system. Background Art

[0002] As the feature size of memory cells approaches the process lower limit, planar processes and manufacturing techniques become challenging and costly, causing the storage density of planar memories to approach an upper limit.

[0003] To overcome the limitations of planar memory, the industry has developed a memory with a three-dimensional structure (e.g., 3D NAND memory) to increase storage density by arranging memory cells three-dimensionally. At present, how to improve the dumping problem of the channel structure during the backside processing is one of the key technical problems in this field. Summary of the invention

[0004] The present application provides a method for manufacturing a three-dimensional memory, a three-dimensional memory, and a memory system that can at least partially solve the above-mentioned problems existing in the related art or other problems in the art.

[0005] In a first aspect, an embodiment of the present application provides a method for manufacturing a three-dimensional memory. The manufacturing method includes: providing a semiconductor structure, wherein the semiconductor structure includes a substrate, a sacrificial layer, a protective layer, a stacking structure, and a channel structure, wherein the sacrificial layer, the protective layer, and the stacking structure are sequentially located on one side of the substrate, the channel structure penetrates the stacking structure and extends into the substrate, and the channel structure includes a functional layer and a channel layer from outside to inside; forming an opening that penetrates the substrate to the sacrificial layer; removing the sacrificial layer through the opening to form a sacrificial gap; and removing the portion of the functional layer exposed to the sacrificial gap.

[0006] In some embodiments, after removing the portion of the functional layer exposed to the sacrificial gap, the manufacturing method further includes: removing the portion of the substrate and the channel structure protruding from the protective layer; and forming a first conductive layer covering the protective layer and the channel structure.

[0007] In some embodiments, removing the substrate and the portion of the channel structure protruding from the protective layer includes: exposing the channel layer of the remaining channel structure to the protective layer; and forming a first conductive layer covering the protective layer and the channel structure includes: forming a first conductive layer connected to the channel layer.

[0008] In some embodiments, removing the portion of the substrate and the channel structure protruding from the protective layer includes: removing the portion of the substrate and the channel structure protruding from the protective layer by a mechanical chemical polishing process.

[0009] In some embodiments, after removing the portion of the functional layer exposed to the sacrificial gap, the manufacturing method further includes: forming a second conductive layer in the sacrificial gap and the opening; and replacing the substrate with an insulating layer.

[0010] In some embodiments, removing the portion of the functional layer exposed to the sacrificial gap includes: exposing a channel layer of the channel structure to the sacrificial gap; and forming a second conductive layer in the sacrificial gap and the opening includes: forming a second conductive layer connected to the channel layer.

[0011] In some embodiments, after replacing the substrate with the insulating layer, the manufacturing method further includes: forming a pad connected to the second conductive layer.

[0012] In some embodiments, replacing the substrate with the insulating layer includes: removing the substrate by a wet etching process; and forming the insulating layer in the cavity formed after removing the substrate.

[0013] In some embodiments, before forming the opening penetrating the substrate to the sacrificial layer, the manufacturing method further includes: thinning the substrate.

[0014] In some embodiments, the material of the protection layer includes polysilicon, and the material of the sacrificial layer includes silicon oxide.

[0015] In some embodiments, the semiconductor structure further includes a gate line gap structure, which penetrates the stacked structure, wherein forming an opening that penetrates the substrate to the sacrificial layer includes: forming an opening that is at least partially aligned with the gate line gap structure.

[0016] In a second aspect, an embodiment of the present application provides a three-dimensional memory. The three-dimensional memory includes: a conductive layer; a stacked structure located on one side of the conductive layer; and a channel structure that penetrates the stacked structure and passes through the conductive layer, including a functional layer and a channel layer from the outside to the inside; wherein the conductive layer passes through the functional layer and contacts the channel layer, and the conductive layer has a protrusion on the side away from the stacked structure, and the protrusion is spaced apart from the channel structure.

[0017] In some embodiments, the material of the conductive layer includes polysilicon.

[0018] In some embodiments, the material of the conductive layer includes metal, and the three-dimensional memory further includes: a protection layer located between the conductive layer and the stacked structure, and the material of the protection layer includes polysilicon.

[0019] In some embodiments, the conductive layer and the protrusions are made of the same material.

[0020] In some embodiments, the functional layer surrounds the channel layer on a side of the conductive layer away from the stack structure.

[0021] In some embodiments, the three-dimensional memory further includes: a gate line gap structure penetrating the stacked structure; wherein the protrusion is at least partially aligned with the gate line gap structure.

[0022] In some embodiments, the three-dimensional memory further includes: an insulating layer located on a side of the conductive layer away from the stacked structure and surrounding the protrusion; wherein the channel structure extends into the insulating layer.

[0023] In some embodiments, the plurality of channel structures have different extension distances in the insulating layer.

[0024] In some embodiments, the three-dimensional memory further includes: a pad located on a side of the conductive layer away from the stacked structure and connected to the protrusion.

[0025] In a third aspect, an embodiment of the present application provides a memory system, which includes: at least one three-dimensional memory as mentioned in any of the above embodiments; and a controller coupled to the three-dimensional memory and used to control the three-dimensional memory to store data.

[0026] According to at least one embodiment of the present application, the manufacturing method of the three-dimensional memory, the three-dimensional memory and the memory system provided by the present application utilize openings penetrating the substrate and sacrificial gaps to remove part of the functional layer outside the channel structure, thereby exposing the channel layer. Retaining part of the substrate can provide support for the channel structure, effectively improve the problem of the channel structure tipping over, and improve the product yield. On the other hand, it can improve the tolerance of the channel structure's extension distance in the substrate, which is conducive to reducing the difficulty of manufacturing the channel structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings, in which:

[0028] Figures 1A to 1C is a cross-sectional schematic diagram of a three-dimensional memory device according to an exemplary embodiment of the present application during a manufacturing process;

[0029] Figure 2 is a flowchart of a method for manufacturing a three-dimensional memory according to another exemplary embodiment of the present application;

[0030] FIG. 3A to FIG. 3F A cross-sectional schematic diagram of a three-dimensional memory device during a manufacturing process according to another exemplary embodiment of the present application;

[0031] FIG. 4A to FIG. 4D A cross-sectional schematic diagram of a three-dimensional memory device during a manufacturing process according to another exemplary embodiment of the present application;

[0032] Figure 5 is a block diagram of a system having a memory system according to an exemplary embodiment of the present application; and

[0033] Fig. 6A and Figure 6B is a schematic diagram of a memory system according to an exemplary embodiment of the present application. DETAILED DESCRIPTION

[0034] In order to better understand the present application, a more detailed description will be made of various aspects of the present application with reference to the accompanying drawings. It should be understood that these detailed descriptions are only descriptions of exemplary embodiments of the present application, and are not intended to limit the scope of the present application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0035] It should be noted that in this specification, the expressions first, second, third, etc. are only used to distinguish one feature from another feature, and do not represent any limitation on the features, especially do not represent any order of precedence. Therefore, without departing from the teaching of this application, the first conductive layer discussed in this application may also be referred to as the second conductive layer, and vice versa.

[0036] In the drawings, the thickness, size and shape of the components have been slightly adjusted for ease of illustration. The drawings are for illustration only and are not drawn strictly to scale. As used herein, the terms "substantially," "approximately," and similar terms are used as terms of approximation, not as terms of degree, and are intended to account for the inherent deviations in measurements or calculations that would be recognized by one of ordinary skill in the art.

[0037] It should also be understood that expressions such as "include", "including", "have", "contain" and / or "comprising" are open rather than closed expressions in this specification, which indicate the presence of the stated features, elements and / or components, but do not exclude the presence of one or more other features, elements, components and / or combinations thereof. In addition, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features rather than just the individual elements in the list. In addition, when describing embodiments of the present application, "may" is used to mean "one or more embodiments of the present application". And, the term "exemplary" is intended to refer to an example or illustration.

[0038] Unless otherwise specified, all words (including engineering terms and scientific and technological terms) used in this article have the same meaning as those commonly understood by ordinary technicians in the field to which this application belongs. It should also be understood that, unless clearly stated in this application, words defined in common dictionaries should be interpreted as having the same meaning as their meaning in the context of the relevant technology, and should not be interpreted in an idealized or overly formal sense.

[0039] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments in this application can be combined with each other. In addition, unless explicitly limited or contradictory to the context, the specific steps included in the method recorded in this application are not necessarily limited to the recorded order, but can be performed in any order or in parallel.

[0040] In addition, in the present application, when “connected” or “coupled” is used, it may indicate direct contact or indirect contact between corresponding components, unless otherwise clearly defined or inferred from the context.

[0041] The present application will be described in detail below with reference to the accompanying drawings and in combination with embodiments.

[0042] It should be noted that in the following, the x-direction, y-direction, and z-direction in each figure show the spatial relationship of the components in the three-dimensional memory. For example, the z-direction is the stacking direction of the stacking structure, and the x-direction and the y-direction are two directions perpendicular to each other on a plane perpendicular to the stacking direction. The same concept will be used throughout this application to describe the spatial relationship of the components in the three-dimensional memory.

[0043] Figures 1A to 1C FIG. 1 is a cross-sectional schematic diagram of a three-dimensional memory device according to an exemplary embodiment of the present application during the manufacturing process. Figure 1A As shown, in the middle structure of the three-dimensional memory (i.e., the semiconductor structure 100a), the channel structure 131 penetrates the stacked structure 121 and extends into the substrate 111. The channel structure 131 may include a charge blocking layer 132, a charge trapping layer 133, a tunneling layer 134, a channel layer 135, and a first dielectric layer 136, which are sequentially arranged from the outside to the inside. Optionally, a first stop layer 112 and a second stop layer 113 may be sequentially arranged between the substrate 111 and the stacked structure 121.

[0044] like Figure 1A and 1B As shown, the substrate 111 may be removed by, for example, a wet etching process to expose the outermost charge blocking layer 132 of the channel structure 131. Figure 1B and Figure 1C As shown, for example, a dry etching process can be used to remove the charge blocking layer 132, the charge trapping layer 133 and the tunneling layer 134 that protrude from the second stop layer 113 and the first stop layer 112, respectively, to expose the channel layer 135. The charge blocking layer 132, the charge trapping layer 133 and the tunneling layer 134 can be referred to as functional layers.

[0045] In this embodiment, in the process of gradually removing the charge blocking layer 132, the charge trapping layer 133 and the tunneling layer 134 outside the channel structure 131, the portion of the channel structure 131 protruding from the stacked structure 121 (for example, protruding from the second stop layer 113) lacks structural support, and the ratio of the radial dimension to the axial dimension of this portion of the channel structure 131 gradually increases, causing this portion of the channel structure 131 to tip over. In particular, when the channel structure 131 extends a long distance on the substrate 111, the tipping problem is aggravated, thereby affecting the implementation of subsequent processes and causing yield loss.

[0046] In view of this, another exemplary embodiment of the present application provides a method for manufacturing a three-dimensional memory. Figure 2 FIG. 1 is a flowchart of a method for manufacturing a three-dimensional memory according to another exemplary embodiment of the present invention. Figure 2 As shown, a method 200 for manufacturing a three-dimensional memory (hereinafter referred to as manufacturing method 200 ) may include the following steps.

[0047] S110, providing a semiconductor structure, wherein the semiconductor structure includes a substrate, a sacrificial layer, a protective layer, a stacking structure and a channel structure, the sacrificial layer, the protective layer and the stacking structure are sequentially located on one side of the substrate, the channel structure penetrates the stacking structure and extends into the substrate, and the channel structure includes a functional layer and a channel layer from the outside to the inside.

[0048] S120 , forming an opening penetrating through the substrate to the sacrificial layer.

[0049] S130 , removing the sacrificial layer through the opening to form a sacrificial gap.

[0050] S140, removing the portion of the functional layer exposed in the sacrificial gap.

[0051] According to the manufacturing method of the three-dimensional memory provided in this embodiment, the opening penetrating the substrate and the sacrificial gap are used to remove part of the functional layer outside the channel structure, so that the channel layer is exposed. Retaining part of the substrate can provide support for the channel structure, effectively improve the problem of the channel structure tipping, and improve the product yield. On the other hand, it can improve the tolerance of the extension distance of the channel structure in the substrate, which is conducive to reducing the manufacturing difficulty of the channel structure.

[0052] FIG. 3A to FIG. 3F FIG. 1 is a cross-sectional schematic diagram of a three-dimensional memory according to another exemplary embodiment of the present application during the manufacturing process. For example, the three-dimensional memory in this embodiment can be manufactured according to Figure 2 The manufacturing method 200 shown is formed. FIG. 3A to FIG. 3F The above steps S210 to S240 are explained by way of example.

[0053] Step S210: providing a semiconductor structure.

[0054] In this step, if Figure 3A As shown, the semiconductor structure 300a may be an intermediate structure of the final three-dimensional memory in the manufacturing process. It should be noted that the semiconductor structure 300a may be formed by any process known in the art. In the semiconductor structure 300a, the sacrificial layer 315, the protective layer 316 and the stacked structure 321 are sequentially located on one side of the substrate 311.

[0055] In some embodiments, the substrate 311 may extend laterally in a plane perpendicular to the z-direction. The material of the substrate 311 may include, but is not limited to, silicon (e.g., single crystal silicon c-Si), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), or any other suitable material. For example, the substrate 311 may be a silicon substrate.

[0056] In some embodiments, the material of the sacrificial layer 315 and the material of the protective layer 316 may be different from each other. For example, the material of the sacrificial layer 315 may be silicon oxide or silicon nitride. The material of the protective layer 316 may be silicon (eg, polysilicon).

[0057] In some embodiments, the stacked structure 321 may include dielectric layers 322 and gate layers 323 alternately arranged in the z direction. The more stacked layers of the dielectric layer 322 and the gate layer 323, the higher the integration of the memory cell, that is, the greater the unit storage density. The material of the dielectric layer 322 may include silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. The material of the gate layer 323 may include tungsten, cobalt, copper, aluminum, polysilicon, titanium, titanium nitride, silicide, or any other suitable conductive material. For example, the material of the dielectric layer 322 is silicon oxide. For example, the gate layer 323 may include a gate barrier layer, an adhesive layer, and a metal layer (not shown) arranged in sequence from the outside to the inside.

[0058] The channel structure 331 penetrates the stacked structure 321 and extends into the substrate 311. In other words, the channel structure 331 sequentially penetrates the stacked structure 321, the protective layer 316 and the sacrificial layer 315 and extends into the substrate 311. For example, the channel structure 331 may be a substantially columnar structure. The channel structure 331 may include a functional layer 337 and a channel layer 335 sequentially arranged from the outside to the inside. Exemplarily, the functional layer 337 may include a charge blocking layer 332, a charge trapping layer 333 and a tunneling layer 334 sequentially arranged from the outside to the inside. For example, the materials of the charge blocking layer 332, the charge trapping layer 333 and the tunneling layer 334 may be silicon oxide, silicon nitride and silicon oxide in sequence. For example, the material of the channel layer 335 may include single crystal silicon, polycrystalline silicon, amorphous silicon or any other appropriate semiconductor material. Optionally, a first dielectric layer 336 may be arranged inside the channel layer 335. An air gap may be provided inside the first dielectric layer 336. For example, the material of the first dielectric layer 336 may include but is not limited to silicon oxide. It should be noted that, due to the limitation of the manufacturing process of the channel structure 331 , the extension distances of the plurality of channel structures 331 in the substrate 311 are not the same.

[0059] In some embodiments, a portion of the channel structure 331 surrounded by a gate layer 323 and a portion of the gate layer 323 constitute a memory cell MC. A plurality of memory cells MC are arranged in series along the extension direction (e.g., z direction) of the channel structure 331 to constitute a memory string, and share the channel layer 335. The remaining portion of the gate layer 323 can be used as a word line connecting a plurality of memory cells MC at the same height in different memory strings. For example, in the memory cell MC, by applying a voltage to the gate layer 323, the charge in the channel layer 335 can be made to enter the charge capture layer 333, or the charge in the charge capture layer 333 can be made to retreat to the channel layer 335, so that the memory cell MC is in a programmed state or an erased state (unprogrammed state). For example, in the case where the charge is an electron, a hole can be made to enter the charge capture layer 333 to neutralize the electron, so that the memory cell MC is in an erased state (unprogrammed state).

[0060] In some embodiments, the semiconductor structure 300a may further include a gate line gap structure 341 that penetrates the stacked structure 321 to the protective layer 316. For example, the gate line gap structure 341 is a wall-like structure extending along the y direction. For example, the gate line gap structure 341 may be used as an insulating boundary of a memory block. In some examples, the gate line gap structure 341 may include a second dielectric layer 342 and a polysilicon layer 343 that are sequentially arranged from the outside to the inside. In other examples, the gate line gap structure 341 may be composed of at least one dielectric material (not shown).

[0061] Step S220 , forming an opening penetrating the substrate to the sacrificial layer.

[0062] In this step, if Figure 3A and Figure 3B As shown, an opening 351 penetrating the substrate 311 to the sacrificial layer 315 may be formed from the side of the substrate 311 away from the stacked structure 321 (i.e., the back side of the substrate 311). In some embodiments, the opening 351 and the gate line gap structure 341 may be at least partially aligned. For example, the opening 351 may be a groove extending along the x-direction. Since the gate line gap structure 341 penetrates the stacked structure 321 to the protective layer 316, aligning the opening 351 with the gate line gap structure 341 at least partially can prevent the opening 351 from causing damage to other components (e.g., the channel structure 331) extending into the substrate 311.

[0063] In some embodiments, the opening 351 may be formed by the process described below. First, a mask layer 301 may be formed on the back side of the substrate 311. For example, the material of the mask layer 301 may be photoresist. Then, a photolithography process is used to transfer the pattern for forming the opening 351 to the mask layer 301. Then, the substrate 311 is etched (for example, dry etching) using the mask layer 301 to form the opening 351. In the case where the substrate 311 is a silicon substrate and the material of the sacrificial layer 315 is silicon oxide or silicon nitride, the sacrificial layer 315 may serve as a stop layer for etching the substrate 311.

[0064] In some embodiments, before forming the opening 351, the substrate 311 may be thinned by, for example, a chemical mechanical polishing (CMP) process. When the substrate 311 is thin, the difficulty of controlling the process of etching the substrate 311 to form the opening 351 can be reduced.

[0065] In step S230 , the sacrificial layer is removed through the opening to form a sacrificial gap.

[0066] In this step, if Figure 3B and Figure 3C As shown, the sacrificial layer 315 may be removed through the opening 351 by an etching process to form a sacrificial gap 352. The functional layer 337 is exposed in the sacrificial gap 352.

[0067] In some embodiments, when the substrate 311 is a silicon substrate, the material of the sacrificial layer 315 is silicon oxide, and the material of the protective layer 316 is polysilicon, hydrofluoric acid can be used as an etchant and introduced into the opening 351, thereby selectively removing the sacrificial layer 315 without damaging the silicon substrate 311 and the protective layer 316 made of polysilicon. As another option, the material of the sacrificial layer 315 can be silicon nitride, and the etchant introduced into the opening 351 can be phosphoric acid.

[0068] Step S240 , removing the portion of the functional layer exposed to the sacrificial gap.

[0069] In this step, if Figure 3C and Figure 3D As shown, an etching process may be used to remove the portion of the functional layer 337 exposed to the sacrificial gap 352 through the opening 351 and the sacrificial gap 352, thereby exposing the channel layer 335. For example, after removing part of the functional layer 337, the channel structure 331 may have an annular groove 353.

[0070] It should be noted that, generally speaking, one end of each channel layer 335 in a plurality of channel structures 331 in the same memory block (not shown) is electrically connected to each other to meet the electrical performance requirements of the three-dimensional memory. Therefore, the channel layer 335 of the channel structure 331 is exposed so that each channel layer 335 in the plurality of channel structures 331 can be connected to each other in subsequent processes.

[0071] In some embodiments, when the functional layer 337 includes a charge blocking layer 332, a charge capture layer 333, and a tunneling layer 334, and the materials are silicon oxide, silicon nitride, and silicon oxide, respectively, hydrofluoric acid and / or phosphoric acid can be used as an etchant and introduced into the opening 351 and the sacrificial gap 352, thereby selectively removing the portion of the functional layer 337 exposed to the sacrificial gap 352.

[0072] It should be noted that, when the materials of the sacrificial layer 315 and the functional layer 337 are silicon oxide and silicon nitride, the etchant may be introduced into the opening 351 at one time to form the sacrificial gap 352 and remove part of the functional layer 337 .

[0073] In this embodiment, the opening 351 penetrating the substrate 311 and the sacrificial gap 352 are used to remove part of the functional layer 337 outside the channel structure 331, so as to expose the channel layer 335. Retaining part of the substrate 311 can provide support for the channel structure 331, effectively improve the problem of the channel structure 331 tipping over, and improve the product yield. On the other hand, the tolerance of the extension distance of the channel structure 331 in the substrate 311 can be improved, which is conducive to reducing the manufacturing difficulty of the channel structure 331.

[0074] In some embodiments, the manufacturing method 200 may further include the following steps.

[0075] S251, removing the substrate and the portion of the channel structure protruding from the protective layer.

[0076] S252, forming a first conductive layer covering the protection layer and the channel structure.

[0077] In step S251, Figure 3D and 3EAs shown, the CMP process can be used to remove the portion of the substrate 311 and the channel structure 331 protruding from the protective layer 316. In other words, the intermediate structure 300d is planarized using the protective layer 316 as a stop layer. In this way, the end faces of the functional layer 337, the channel layer 335, and the first dielectric layer 336 in the channel structure 331 are roughly flush with the surface of the protective layer 316 away from the stacked structure 321, and the retained channel layer 335 has an exposed end face relative to the protective layer 316. Under the physical action of a stress process such as CMP, the substrate 311 and the portion of the channel structure 331 protruding from the protective layer 316 are removed as a whole, which can avoid the introduction of etching materials (for example, etchants or etching gases), thereby avoiding damage to the portion of the channel structure 331 that does not need to be removed by the etching materials.

[0078] In step S252, if Figure 3E and Figure 3F As shown, a first conductive layer 361 covering the protective layer 316 and the channel structure 331 may be formed by a thin film deposition process of physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD) or any combination thereof. The first conductive layer 361 may be connected to the channel layer 335 (e.g., physically and electrically connected). Each channel layer 335 in the plurality of channel structures 331 may be connected to each other through the first conductive layer 361. For example, the material of the first conductive layer 361 may include tungsten, cobalt, copper, aluminum, titanium or any other appropriate metal material. For another example, the first conductive layer 361 may include a semiconductor material (e.g., doped or undoped polysilicon).

[0079] FIG. 4A to FIG. 4D A cross-sectional schematic diagram of a three-dimensional memory device in a manufacturing process according to another exemplary embodiment of the present application. For the purpose of brevity, the present application will not repeat the same contents as the previous embodiment.

[0080] In some embodiments, after removing the portion of the functional layer 337 exposed to the sacrificial gap 352 (see Figure 3D ), the manufacturing method 200 may further include the following steps.

[0081] S261, forming a second conductive layer in the sacrificial gap and the opening.

[0082] S262, replacing the substrate with an insulating layer.

[0083] S263, forming a pad connected to the second conductive layer.

[0084] Combine the following FIG. 4A to FIG. 4DThe above steps S261 to S263 are explained by way of example.

[0085] In step S261, if Figure 4A As shown, a thin film deposition process such as PVD, CVD, ALD or any combination thereof may be used to deposit the sacrificial gap 352 and the opening 351 (see Figure 3D ) to form a second conductive layer 471. The second conductive layer 471 is exposed to the sacrificial gap 352 (reference Figure 3D ) is connected (e.g., physically and electrically connected) to the channel layer 435 of the second conductive layer 471. For example, the material of the second conductive layer 471 may include tungsten, cobalt, copper, aluminum, titanium, or any other appropriate metal material. For another example, the material of the second conductive layer 471 may be a semiconductor material (e.g., doped or undoped polysilicon).

[0086] In step S262, if Figure 4A and Figure 4C As shown, the substrate 411 can be replaced by the insulating layer 413 by etching and thin film deposition process. For example, first, as Figure 4A and Figure 4B As shown, a wet etching process can be used to remove the substrate 411 by selecting an etchant, while retaining the second conductive layer 471 and the portion of the channel structure 431 protruding from the second conductive layer 471, thereby forming a cavity 412. Then, as shown in FIG. Figure 4B and Figure 4C As shown, a thin film deposition process such as PVD, CVD, ALD or any combination thereof may be used to form an insulating layer 413 in the cavity 412. The material of the insulating layer 413 may include silicon oxide, silicon nitride, silicon oxynitride or any other appropriate insulating material.

[0087] In step S263, an etching and thin film deposition process may be used to form a pad 481 connected (e.g., physically and electrically connected) to the second conductive layer 471. For example, the material of the pad 481 may include tungsten, cobalt, copper, aluminum, titanium, or any other appropriate metal material. For example, the pad 481 may be used to lead out the second conductive layer 471 and may be used to receive an external signal.

[0088] In this embodiment, after removing the substrate 411, on the one hand, the second conductive layer 471 can provide support for the portion of the channel structure 431 protruding from the stacked structure 421. On the other hand, since the portion of the functional layer 437 protruding from the second conductive layer 471 is not removed, this portion of the channel structure 431 maintains the original radial dimension and is not prone to tipping, thereby improving structural stability and yield.

[0089] The present application also provides a three-dimensional memory. Figure 4DAs shown, the three-dimensional memory 400d includes a conductive layer (for example, the conductive layer may be the second conductive layer 471 described above), a stacked structure 421 and a channel structure 431 .

[0090] The stacked structure 421 is located on one side of the second conductive layer 471. In some embodiments, the stacked structure 421 may include dielectric layers 422 and gate layers 423 alternately arranged in the z direction. The more stacked layers of the dielectric layer 422 and the gate layer 423, the higher the integration of the memory cell, that is, the greater the unit storage density. The material of the dielectric layer 422 may include silicon oxide, silicon nitride, silicon oxynitride, or any other suitable insulating material. The material of the gate layer 423 may include tungsten, cobalt, copper, aluminum, polysilicon, titanium, titanium nitride, silicide, or any other suitable conductive material. For example, the material of the dielectric layer 423 is silicon oxide. For example, the gate layer 423 may include a gate barrier layer, an adhesive layer, and a metal layer (not shown) arranged in sequence from the outside to the inside.

[0091] The channel structure 431 penetrates the stacked structure 421 and the second conductive layer 471, and extends out of the second conductive layer 471. The channel structure 431 includes a functional layer 437 and a channel layer 435 arranged from the outside to the inside. For example, the channel structure 431 may be a substantially columnar structure and have an annular groove 453 exposing the channel layer 435. In some embodiments, the functional layer 437 may include a charge blocking layer 432, a charge trapping layer 433, and a tunneling layer 434 arranged in sequence from the outside to the inside. For example, the materials of the charge blocking layer 432, the charge trapping layer 433, and the tunneling layer 434 may be silicon oxide, silicon nitride, and silicon oxide in sequence. For example, the material of the channel layer 435 may include single crystal silicon, polycrystalline silicon, amorphous silicon, or any other appropriate semiconductor material. Optionally, a first dielectric layer 436 may be disposed inside the channel layer 435. The inside of the first dielectric layer 436 may have an air gap. For example, the material of the first dielectric layer 436 may include, but is not limited to, silicon oxide.

[0092] In some embodiments, the second conductive layer 471 may have a raised portion 4712 and a flat portion 4711. The raised portion 4712 is located on a side of the flat portion 4711 away from the stacked structure 421, and is spaced apart from a portion of the channel structure 431 protruding from the flat portion 4711. For example, the flat portion 4711 extends laterally on a plane perpendicular to the z-direction. For example, the raised portion 4712 may extend along the y-direction. Exemplarily, the flat portion 4711 and the raised portion 4712 are an integral structure. When the material of the flat portion 4711 and the raised portion 4712 is the same, the two do not have an obvious interface. For example, the material of the second conductive layer 471 may include tungsten, cobalt, copper, aluminum, titanium, or any other suitable metal material. For another example, the material of the second conductive layer 471 may be a semiconductor material (e.g., doped or undoped polysilicon).

[0093] In some embodiments, the flat plate portion 4711 in the second conductive layer 471 passes through the functional layer 437 and contacts the channel layer 435. For example, the flat plate portion 4711 extends into the annular groove 453 of the channel structure 431. In the portion of the channel structure 431 located on both sides of the flat plate portion 4711, the functional layer 437 surrounds the channel layer 435. The flat plate portion 4711 in the second conductive layer 471 may pass through each functional layer 437 in the plurality of channel structures 431 and contact each channel layer 435. Each channel layer 435 in the plurality of channel structures 431 may be connected to each other through the second conductive layer 471.

[0094] In some embodiments, the three-dimensional memory 400d may further include a protective layer 416. The protective layer 416 is located between the second conductive layer 471 and the stacked structure 421. For example, the material of the protective layer 416 may be polysilicon. In this case, when the material of the second conductive layer 471 is also polysilicon, there is no obvious interface between the second conductive layer 471 and the protective layer 416, and the two may be an integrated structure.

[0095] In some embodiments, the three-dimensional memory 400d may further include a gate line gap structure 441 that penetrates the stacked structure 421 to the protective layer 416. For example, the gate line gap structure 441 is a wall-like structure extending along the y direction. For example, the gate line gap structure 441 can be used as an insulating boundary of a memory block. In some examples, the gate line gap structure 441 may include a second dielectric layer 442 and a polysilicon layer 443 that are sequentially arranged from the outside to the inside. In other examples, the gate line gap structure 441 may be composed of at least one dielectric material (not shown). The protrusion 4712 may be at least partially aligned with the gate line gap structure 441, so that the protrusion 4712 can be prevented from causing damage to other components (e.g., the channel structure 431) in the stacked structure 421 during the formation process.

[0096] In some embodiments, the three-dimensional memory 400d may further include an insulating layer 413. The insulating layer 413 is located on a side of the second conductive layer 471 away from the stacked structure 421 and surrounds the protrusion 4712. The portion of the channel structure 431 extending from the second conductive layer 471 may be located in the insulating layer 413. It should be noted that, for example, due to limitations on the manufacturing process of the channel structure 431, the extension distances of the multiple channel structures 431 in the insulating layer 413 are not the same.

[0097] In some embodiments, the three-dimensional memory 400d may further include a pad 481. The pad 481 is located on a side of the second conductive layer 471 away from the stack structure 421 and is connected to the protrusion 4712 (eg, physically and electrically connected).

[0098] Since the contents and structures involved in the above description of the preparation method 200 can be fully or partially applied to the three-dimensional memory described here, the related or similar contents will not be described in detail.

[0099] An embodiment of the present application also provides a memory system. Figure 5 is a block diagram of a system having a memory system according to an exemplary embodiment of the present application.

[0100] The system 11 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device (the electronic device has the memory system 12 located therein). Figure 5 As shown, the system 11 may include a host 18 and a memory system 12, the memory system 12 having one or more three-dimensional memories 14 and a controller 16. The host 18 may be a processor of an electronic device, such as a central processing unit (CPU), or may be a system-on-chip (SoC), such as an application processor (AP). The host 18 may be configured to send or receive data to or from the three-dimensional memory 14.

[0101] The three-dimensional memory 14 may be any of the three-dimensional memory described in the above embodiments. For example, Figure 4D400d is shown. According to some embodiments, the controller 16 is coupled to the three-dimensional memory 14 and the host 18, and is configured to control the three-dimensional memory 14. The controller 16 can manage data stored in the three-dimensional memory 14 and communicate with the host 18. In some embodiments, the controller 16 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact Flash (CF) card, a universal serial bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 16 is designed to operate in a high duty cycle environment, such as an SSD or an embedded multi-media-card (eMMC) used as a data storage device for mobile devices, and an enterprise storage array, and the mobile device is a smart phone, a tablet computer, a laptop computer, etc. The controller 16 can be configured to control the operation of the three-dimensional memory 14, such as read, erase, and program operations. The controller 16 may also be configured to manage various functions related to data stored in or to be stored in the three-dimensional memory 14, including but not limited to bad block management, garbage collection, logical to physical address conversion, wear leveling, etc. In some embodiments, the controller 16 is further configured to process error correction code (ECC) related to data read from or written to the three-dimensional memory 14. Any other appropriate functions may also be performed by the controller 16, for example, formatting the three-dimensional memory 14. The controller 16 may communicate with an external device (e.g., a host 18) according to a specific communication protocol. For example, the controller 16 may communicate with an external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnect (PCI) protocol, a high-speed PCI (PCI-express, PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a Firewire protocol, etc.

[0102] The controller 16 and the one or more three-dimensional memories 14 may be integrated into various types of memory systems, for example, included in the same package (such as a universal flash storage (UFS) package or an eMMC package). That is, the memory system 12 may be implemented and packaged into different types of final electronic products. Fig. 6AIn one example shown in FIG, the controller 16 and the single three-dimensional memory 14 may be integrated into a memory card 22. The memory card 22 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 22 may further include a memory card 22 that connects to a host (e.g., Figure 5 The host 18 in the memory card connector 24 is coupled. Figure 6B In another example shown in FIG. 1 , the controller 16 and the plurality of three-dimensional memories 14 may be integrated into the SSD 26. The SSD 26 may further include a processor that connects the SSD 26 to a host (e.g., Figure 5 In some embodiments, the storage capacity and / or operating speed of the SSD 26 is higher than the storage capacity and / or operating speed of the memory card 22.

[0103] The above description is only an implementation method of the present application and an explanation of the technical principles used. Those skilled in the art should understand that the scope of protection involved in the present application is not limited to the technical solution formed by a specific combination of the above technical features, but should also cover other technical solutions formed by any combination of the above technical features or their equivalent features without departing from the technical concept. For example, the above features are replaced with (but not limited to) technical features with similar functions disclosed in this application.

Claims

1. A method for manufacturing a three-dimensional memory, characterized in that: include: A semiconductor structure is provided, wherein the semiconductor structure comprises a substrate, a sacrificial layer, a protective layer, a stack structure and a channel structure, wherein the sacrificial layer, the protective layer and the stack are sequentially located on one side of the substrate, the channel structure penetrates the stack structure and extends into the substrate, and the channel structure comprises a functional layer and a channel layer from outside to inside; forming an opening penetrating through the substrate to the sacrificial layer; removing the sacrificial layer through the opening to form a sacrificial gap; and A portion of the functional layer exposed to the sacrificial gap is removed.

2. The manufacturing method according to claim 1, wherein: After removing the portion of the functional layer exposed to the sacrificial gap, the method further comprises: removing the substrate and the portion of the channel structure protruding from the protective layer; and A first conductive layer covering the protection layer and the channel structure is formed.

3. The manufacturing method according to claim 2, wherein: Removing the substrate and the portion of the channel structure protruding from the protective layer includes: exposing the remaining channel layer of the channel structure to the protective layer; and Forming a first conductive layer covering the protection layer and the channel structure includes: The first conductive layer connected to the channel layer is formed.

4. The manufacturing method according to claim 2, wherein: Removing the substrate and the portion of the channel structure protruding from the protective layer includes: The substrate and the portion of the channel structure protruding from the protection layer are removed by a mechanical chemical polishing process.

5. The manufacturing method according to claim 1, wherein: After removing the portion of the functional layer exposed to the sacrificial gap, the method further comprises: forming a second conductive layer in the sacrificial gap and the opening; and The substrate is replaced with an insulating layer.

6. The manufacturing method according to claim 5, wherein: Removing the portion of the functional layer exposed to the sacrificial gap comprises: exposing a channel layer of the channel structure to the sacrificial gap; and Forming a second conductive layer in the sacrificial gap and the opening includes: The second conductive layer connected to the channel layer is formed.

7. The manufacturing method according to claim 5, wherein: After replacing the substrate with an insulating layer, the method further comprises: A pad connected to the second conductive layer is formed.

8. The manufacturing method according to claim 5, wherein: Replacing the substrate with an insulating layer comprises: removing the substrate by a wet etching process; and The insulating layer is formed in a cavity formed after removing the substrate.

9. The manufacturing method according to any one of claims 1 to 8, wherein: Before forming an opening that penetrates the substrate to the sacrificial layer, the method further includes: The substrate is thinned.

10. The manufacturing method according to any one of claims 1 to 8, wherein: The material of the protection layer includes polysilicon, and the material of the sacrificial layer includes silicon oxide.

11. The manufacturing method according to any one of claims 1 to 8, wherein: The semiconductor structure further includes a gate line gap structure, and the gate line gap structure penetrates the stacked structure, wherein forming an opening penetrating the substrate to the sacrificial layer includes: The opening is formed to be at least partially aligned with the gate line gap structure.

12. A three-dimensional memory, characterized in that: include: Conductive layer; A stacked structure located on one side of the conductive layer; as well as A channel structure, which runs through the stacked structure and the conductive layer, and includes a functional layer and a channel layer from outside to inside; The conductive layer passes through the functional layer and contacts the channel layer. The conductive layer has a protrusion on a side away from the stacking structure. The protrusion is spaced apart from the channel structure.

13. The three-dimensional memory according to claim 12, wherein: The material of the conductive layer includes polysilicon.

14. The three-dimensional memory according to claim 12, wherein: The material of the conductive layer includes metal, and the three-dimensional memory further includes: The protection layer is located between the conductive layer and the stacked structure, and the material of the protection layer includes polysilicon.

15. The three-dimensional memory according to claim 12, wherein: The conductive layer and the protrusion are made of the same material.

16. The three-dimensional memory according to claim 12, wherein: The functional layer surrounds the channel layer on a side of the conductive layer away from the stacked structure.

17. The three-dimensional memory according to any one of claims 12 to 16, wherein: Also includes: A gate line gap structure, penetrating the stacked structure; Wherein, the protrusion is at least partially aligned with the gate line gap structure.

18. The three-dimensional memory according to any one of claims 12 to 16, wherein: Also includes: an insulating layer, located on a side of the conductive layer away from the stacked structure and surrounding the protruding portion; Wherein, the channel structure extends into the insulating layer.

19. The three-dimensional memory according to claim 18, wherein: The plurality of channel structures have different extension distances in the insulating layer.

20. The three-dimensional memory according to any one of claims 12 to 16, wherein: Also includes: The pad is located on a side of the conductive layer away from the stacking structure and is connected to the protruding portion.

21. A memory system, characterized in that: include: At least one three-dimensional memory as claimed in any one of claims 12 to 20; as well as The controller is coupled to the three-dimensional memory to control the three-dimensional memory to store data.

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