Gallium nitride HEMT device structure and manufacturing method

Abstract

The invention relates to a gallium nitride HEMT device structure and a manufacturing method. The device comprises a substrate; the composite layer is arranged on the substrate, the composite layer comprises an Al < y > Ga < 1-y > N layer with high Al component doping and an Al < x > Ga < 1-x > N layer with low Al component doping, and at least one Al < x > Ga < 1-x > N layer is embedded into the Al < y > Ga < 1-y > N layer; the GaN buffer layer is arranged on the composite layer; the GaN channel layer is arranged on the GaN buffer layer; the AlN space layer is arranged on the GaN channel layer; the two-dimensional electron gas layer is formed in the GaN channel layer and is close to an interface of the GaN channel layer and the AlN space layer; the AlGaN potential barrier layer is arranged on the AlN space layer; an insulating layer is arranged between the gate electrode and the AlGaN barrier layer, and the source electrode and the drain electrode respectively extend into the AlN space layer or the surface of the AlGaN barrier layer from the upper side of the insulating layer. According to the invention, the AlyGa1-yN layer highly doped with the Al component is combined with the AlxGa1-xN embedded layer low doped with the Al component, so that the electric field distribution can be improved, the charge accumulation problem can be reduced, the breakdown voltage can be improved, the structural stress can be improved, and the probability of fragmentation can be reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a gallium nitride HEMT device structure and a manufacturing method thereof. Background Art

[0002] GaN has excellent electron transmission performance, high breakdown electric field and fast electron saturation velocity, which makes it show great development potential in microwave / millimeter wave high-power devices and power electronics. However, in conventional GaN HEMT (High Electron Mobility Transistor) devices, due to the uneven distribution of the electric field in the channel layer, the charge tends to concentrate on the edge of the gate, thus limiting the improvement of the breakdown voltage. Summary of the invention

[0003] Therefore, the technical problem to be solved by the present invention is to overcome the problem in the prior art that the electric field distribution in the channel layer of the gallium nitride HEMT device is uneven, which limits the improvement of the breakdown voltage.

[0004] In order to solve the above technical problems, the present invention provides a gallium nitride HEMT device structure, comprising: substrate; A composite layer is arranged on the substrate, and the composite layer includes Al with a high Al doping component. y Ga 1-y N layer and low Al-doped Al x Ga 1-x N layer, at least one of the Al x Ga 1-x The N layer is embedded in the Al y Ga 1-y In the N layer; A GaN buffer layer, disposed on the composite layer; A GaN channel layer is disposed on the GaN buffer layer; An AlN space layer is disposed on the GaN channel layer; A two-dimensional electron gas layer, wherein the two-dimensional electron gas layer is formed in the GaN channel layer and is close to an interface between the GaN channel layer and the AlN space layer; An AlGaN barrier layer is disposed on the AlN space layer; A source electrode, a gate electrode and a drain electrode, wherein an insulating layer is provided between the gate electrode and the AlGaN barrier layer, and the source electrode and the drain electrode extend from the upper side of the insulating layer to the inside of the AlN space layer or the surface of the AlGaN barrier layer respectively; Among them, the Al x Ga 1-xThe N layer is arranged on one side and / or both sides of the gate electrode, and a gap is left between the bottom end of the N layer and the bottom end of the gate electrode in the device width direction.

[0005] In one embodiment of the present invention, the device structure includes a first p-GaN layer and a recessed gate hole, and the insulating layer includes a first insulating layer and a second insulating layer; The first p-GaN layer is disposed on the AlGaN barrier layer and a step is formed therebetween, and the concave gate hole sequentially penetrates the first p-GaN layer, the AlGaN barrier layer, the AlN space layer and the two-dimensional electron gas layer, and then extends into the GaN channel layer; The first insulating layer covers the surfaces of the AlGaN barrier layer and the first p-GaN layer and the inner surface of the recessed gate hole; The gate electrode extends into the recessed gate hole and contacts the first insulating layer on the inner surface of the recessed gate hole and a portion of the first p-GaN layer respectively; The second insulating layer is disposed on the first insulating layer and extends to a side end of the gate electrode; The dielectric constant of the first insulating layer is greater than the dielectric constant of the second insulating layer; The source electrode and the drain electrode are respectively arranged at two ends of the device and extend from the upper side of the second insulating layer to the AlN space layer.

[0006] In one embodiment of the present invention, the device structure includes a second p-GaN layer, and the insulating layer includes a third insulating layer; The second p-GaN layer is disposed on the AlGaN barrier layer to form a step therebetween, the third insulating layer covers the respective surfaces of the AlGaN barrier layer and the second p-GaN layer, and the gate electrode penetrates the third insulating layer and contacts the second p-GaN layer; The source electrode and the drain electrode are respectively arranged at two ends of the device and extend from the upper side of the third insulating layer to the AlN space layer.

[0007] In one embodiment of the present invention, the device structure includes a third p-GaN layer, and the insulating layer includes a fourth insulating layer; The third p-GaN layer is disposed on the AlGaN barrier layer and a step is formed therebetween, the fourth insulating layer covers the respective surfaces of the AlGaN barrier layer and the third p-GaN layer, and the gate electrode penetrates the fourth insulating layer and contacts the third p-GaN layer; The source electrode and the drain electrode are respectively disposed at two ends of the device and are in contact with the AlGaN barrier layer.

[0008] In one embodiment of the present invention, in the Al y Ga 1-y The N layer and the Al x Ga 1-x In the N layer, y>x, 0.1≤y≤0.4, 0.01≤x≤0.2.

[0009] In one embodiment of the present invention, the Al closest to the gate electrode x Ga 1-x The distance between the bottom end of the N layer and the bottom end of the gate electrode is 0.01-0.2 of the device width.

[0010] In one embodiment of the present invention, each of the Al x Ga 1-x The bottom width of the N layer accounts for 0.1~0.5 of the device width.

[0011] In one embodiment of the present invention, the Al x Ga 1-x The shape of the N layer includes a quadrilateral or an inverted trapezoid.

[0012] In one embodiment of the present invention, the Al x Ga 1-x N can be set from 1 to 5.

[0013] The present invention also provides a method for manufacturing a gallium nitride HEMT device structure, comprising: providing a substrate; Depositing Al with high Al doping content on the substrate y Ga 1-y N, forming Al y Ga 1-y N layers; An epitaxial inhibition layer is formed on the surface and a template is prepared. y Ga 1-y Etching is performed on the N layer to form a groove; Selective deposition of low Al-doped Al on devices x Ga 1-x N, forming at least one Al embedded in the groove y Ga 1-y Al in N layer x Ga 1-x N layer, forming a composite layer; A GaN buffer layer, a GaN channel layer, an AlN space layer, an AlGaN barrier layer and a p-GaN layer are sequentially formed on the composite layer, and a two-dimensional electron gas layer is formed between the GaN channel layer and the AlN space layer; Etching a source region and a drain region on the device, and making a source electrode and a drain electrode in the source region and the drain region respectively, and forming an ohmic contact by high temperature alloy treatment; Etching the p-GaN layer to form a gate step structure; Etching a concave gate hole that sequentially penetrates the p-GaN layer, the AlGaN barrier layer, the AlN space layer, and the two-dimensional electron gas layer and extends into the GaN channel layer; Manufacturing a first insulating layer, wherein the first insulating layer covers the surfaces of the AlGaN barrier layer and the p-GaN layer and the inner surface of the recessed gate hole; Forming a second insulating layer on the surface of the first insulating layer, and partially exposing the first insulating layer, wherein the partially exposing first insulating layer includes the inner surface area of ​​the recessed gate hole and the partial area extending to the p-GaN layer; A gate electrode is manufactured, wherein the gate electrode is in contact with the partially leaked first insulating layer.

[0014] The above technical solution of the present invention has the following advantages compared with the prior art: The present invention discloses a GaN HEMT device structure and a manufacturing method, using a highly Al-doped Al y Ga 1-y N layer and Al with low Al doping content x Ga 1-x Combined with the N embedded layer, it can improve the electric field distribution, reduce the charge accumulation problem, increase the breakdown voltage, and improve the structural stress to reduce the chance of fragmentation. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to make the contents of the present invention more clearly understood, the present invention is further described in detail below based on specific embodiments of the present invention in conjunction with the accompanying drawings.

[0016] Figure 1 It is a schematic diagram of the structure of a gallium nitride HEMT device according to Example 1 of the present invention.

[0017] Figure 2 It is a schematic diagram of the structure of a gallium nitride HEMT device according to Example 2 of the present invention.

[0018] Figure 3 It is a schematic diagram of the structure of a gallium nitride HEMT device according to Example 3 of the present invention.

[0019] Figure 4 It is a schematic diagram of the structure of a gallium nitride HEMT device according to Example 4 of the present invention.

[0020] Figure 5 It is a schematic diagram of the structure of a gallium nitride HEMT device according to Example 5 of the present invention.

[0021] Figure 6 It is a schematic diagram of the structure of a gallium nitride HEMT device according to Example 6 of the present invention.

[0022] Figure 7 Schematic diagram of a method for manufacturing a gallium nitride HEMT device according to Embodiment 7 of the present invention Figure 1 .

[0023] Figure 8 Schematic diagram of a method for manufacturing a gallium nitride HEMT device according to Embodiment 7 of the present invention Figure 2 .

[0024] Fig. 9 Schematic diagram of a method for manufacturing a gallium nitride HEMT device according to Embodiment 7 of the present invention Figure 3 .

[0025] Fig.10 Schematic diagram of a method for manufacturing a gallium nitride HEMT device according to Embodiment 7 of the present invention Figure 4 .

[0026] Fig.11 Schematic diagram of a method for manufacturing a gallium nitride HEMT device according to Embodiment 7 of the present invention Figure 5 .

[0027] Fig.12 Schematic diagram of a method for manufacturing a gallium nitride HEMT device according to Embodiment 7 of the present invention Figure 6 .

[0028] Fig.13 Schematic diagram of a method for manufacturing a gallium nitride HEMT device according to Embodiment 7 of the present invention Figure 7 .

[0029] Fig.14 Schematic diagram of a method for manufacturing a gallium nitride HEMT device according to Embodiment 7 of the present invention Figure 8 .

[0030] Fig.15 Schematic diagram of a method for manufacturing a gallium nitride HEMT device according to Embodiment 7 of the present invention Figure 9 .

[0031] Fig.16 Schematic diagram of a method for manufacturing a gallium nitride HEMT device according to Embodiment 7 of the present invention Figure 10 .

[0032] Description of the Figures in the Specification: 10. Substrate; 20. Composite layer; 21. Al y Ga 1-y N layer; 22, Al x Ga 1-x N layer; 210, groove; 30. GaN buffer layer; 40. GaN channel layer; 50. Two-dimensional electron gas layer; 60. AlN space layer; 70. AlGaN barrier layer; 81. source electrode; 82. gate electrode; 83. drain electrode; 91, a first insulating layer; 92, a second insulating layer; 93, a third insulating layer; 94, a fourth insulating layer; 100, p-GaN layer; 101, first p-GaN layer; 102, second p-GaN layer; 103, third p-GaN layer. DETAILED DESCRIPTION

[0033] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0034] In the present invention, if directions (up, down, left, right, front and back) are described, it is only for the convenience of describing the technical solution of the present invention, and does not indicate or imply that the technical features referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, it cannot be understood as a limitation of the present invention.

[0035] In the present invention, "several" means one or more, "multiple" means more than two, "greater than", "less than", "exceed" and the like are understood to exclude the number itself; "above", "below", "within" and the like are understood to include the number itself. In the description of the present invention, if there is a description of "first" or "second", it is only used for the purpose of distinguishing technical features, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0036] In the present invention, unless otherwise clearly defined, the words "set", "install", "connect" and the like should be understood in a broad sense, for example, they can be directly connected or indirectly connected through an intermediate medium; they can be fixedly connected or detachably connected or integrally formed; they can be mechanically connected or electrically connected or able to communicate with each other; they can be the internal connection of two elements or the interaction relationship between two elements. Those skilled in the art can reasonably determine the specific meanings of the above words in the present invention in combination with the specific content of the technical solution.

[0037] Example 1 Reference Figure 1 As shown, this embodiment provides a GaN HEMT device structure, including: Substrate 10; The composite layer 20 is disposed on the substrate 10, and the composite layer 20 includes Al with a high Al doping component. y Ga 1-y N layer 21 and Al with low Al doping content x Ga 1-x N layer 22, at least one of the Al x Ga 1-x The N layer 22 is embedded in the Al y Ga 1-y In the N layer 21; y Ga 1-y The N layer 21 and the Al x Ga 1-x In the N layer 22, y>x, 0.1≤y≤0.4, 0.01≤x≤0.2; A GaN buffer layer 30, disposed on the composite layer 20; A GaN channel layer 40 is disposed on the GaN buffer layer 30; The AlN space layer 60 is disposed on the GaN channel layer 40 A two-dimensional electron gas layer 50, wherein the two-dimensional electron gas layer 50 is formed in the GaN channel layer 40 and is close to the interface between the GaN channel layer 40 and the AlN space layer 60; An AlGaN barrier layer 70 is disposed on the AlN space layer 60; A source electrode 81, a gate electrode 82 and a drain electrode 83, an insulating layer is provided between the gate electrode 82 and the AlGaN barrier layer 70, and the source electrode 81 and the drain electrode 83 extend from the upper side of the insulating layer to the AlN space layer 60 respectively. x Ga 1-x A gap is left between the bottom end of the N layer 22 and the bottom end of the gate electrode 82 in the device width direction.

[0038] By using Al with high Al doping y Ga 1-y N layer 21 and Al with low Al doping content x Ga 1-x Combined with the N embedded layer, it can improve the electric field distribution, reduce the charge accumulation problem, increase the breakdown voltage, and improve the structural stress to reduce the chance of fragmentation.

[0039] Specifically, the device structure includes a first p-GaN layer 101 and a recessed gate hole, and the insulating layer includes a first insulating layer 91 and a second insulating layer 92; The first p-GaN layer 101 is disposed on the AlGaN barrier layer 70 and a step is formed therebetween. The recessed gate hole sequentially penetrates the first p-GaN layer 101, the AlGaN barrier layer 70, the AlN space layer 60 and the two-dimensional electron gas layer 50, and then extends into the GaN channel layer 40. The first insulating layer 91 covers the surfaces of the AlGaN barrier layer 70 and the first p-GaN layer 101 and the inner surface of the recessed gate hole; The gate electrode 82 extends into the recessed gate hole and contacts the first insulating layer 91 on the inner surface of the recessed gate hole and a portion of the first p-GaN layer 101 respectively; The second insulating layer 92 is disposed on the first insulating layer 91 and extends to the side end of the gate electrode 82; The dielectric constant (κ value) of the first insulating layer 91 is greater than the dielectric constant of the second insulating layer 92; the first insulating layer 91 is a dense high dielectric constant insulating layer, made of materials such as Al2O3\HfO2\AlN\TiN; the second insulating layer 92 is made of SiN x , Al2O3, SiO2, etc.; The source electrode 81 and the drain electrode 83 are respectively disposed at two ends of the device and extend from the upper side of the second insulating layer 92 to the inside of the AlN space layer 60 .

[0040] The provision of a double insulating layer (the first and second insulating layers 92 ), especially the design of different dielectric constants, helps to optimize the electric field distribution and reduce the parasitic capacitance between the gate and the drain. At the same time, the insulating layer protects the recessed gate hole region.

[0041] Specifically, the Al x Ga 1-x The N layer 22 is located on both sides of the gate electrode 82 and is provided with at least 1 to 5 N layers. x Ga 1-x The shape of the N layer 22 is a quadrilateral or an inverted trapezoid.

[0042] Specifically, the Al2O3 electrode closest to the gate electrode 82 x Ga 1-x The distance between the bottom of the N layer 22 and the bottom of the gate electrode 82 is 0.01-0.2 of the device width. x Ga 1-x The width of the bottom end of the N layer 22 (ie, the end in contact with the substrate 10 ) accounts for 0.1 to 0.5 of the width of the device.

[0043] For example, the device is provided with 4 Al x Ga 1-xN layer 22 (embedded block), and one and three are respectively distributed on both sides of the gate electrode 82, and Al x Ga 1-x The shape of the N layer 22 is an inverted trapezoid, the width of the bottom end is L2, the width of the top end is L3, L3 / L2 is between 1 and 1.5, and the Al closest to the gate electrode 82 is x Ga 1-x The distance between the bottom end of the N layer 22 and the bottom end of the gate electrode 82 is L1, the device width is L0, L1 / L0 is between 0.01 and 0.2, and L2 / L0 is between 0.1 and 0.5.

[0044] Example 2 Reference Figure 2 As shown, in this embodiment, the difference from embodiment 1 is that Al x Ga 1-x The N layer 22 is rectangular in shape, and the device is provided with 4 Al x Ga 1-x N layer 22, and one and three Al x Ga 1-x The width of the bottom of the N layer is L2, and the width of the top is L3, L3 / L2=1, and the Al closest to the gate electrode 82 x Ga 1-x The distance between the bottom end of the N layer 22 and the bottom end of the gate electrode 82 is L1, the device width is L0, L1 / L0 is between 0.01 and 0.2, and L2 / L0 is between 0.1 and 0.5.

[0045] The rest of the structure is the same as that of Example 1.

[0046] Example 3 Reference Figure 3 As shown, in this embodiment, unlike embodiment 2, only one Al x Ga 1-x The N layer 22 is at a certain distance from the edge of the device, and the rest of the structure is the same as that of the first embodiment.

[0047] This embodiment is compared with Al in Example 1. x Ga 1-x The N-layer alternating design has a simpler structure, is easier to implement, and is suitable for low-cost manufacturing processes. At the same time, it can still effectively improve the uniformity of the electric field distribution and the stability of the device.

[0048] Example 4 Reference Figure 4 As shown, in this embodiment, unlike embodiment 3, an Al x Ga 1-x N layer 22 is formed and filled on one side of the device. The rest of the structure is the same as that of embodiment 3.

[0049] The Al in the composite layer in the GaN HEMT device structure of this embodiment x Ga 1-x The N layer accounts for a higher proportion, the overall structural stress of the device is lower, and the probability of wafer breakage during the manufacturing process is lower.

[0050] Example 5 Reference Figure 5 As shown, this embodiment is a D-mode (depletion mode) HEMT device. Different from the embodiment 4, the device structure includes a second p-GaN layer 102, and the insulating layer includes a third insulating layer 93; the third insulating layer 93 is made of SiNx, Al2O3, SiO2, etc.; The second p-GaN layer 102 is disposed on the AlGaN barrier layer 70 and a step is formed therebetween. The third insulating layer 93 covers the surfaces of the AlGaN barrier layer 70 and the second p-GaN layer 102. The gate electrode 82 penetrates the third insulating layer 93 and contacts the second p-GaN layer 102. The source electrode 81 and the drain electrode 83 are respectively disposed at two ends of the device and extend from the upper side of the third insulating layer 93 to the inside of the AlN space layer 60 .

[0051] The rest of the structure is the same as that of Example 4.

[0052] Example 6 Reference Figure 6 As shown, in this embodiment, different from the embodiment 5, the device structure includes a third p-GaN layer 103, and the insulating layer includes a fourth insulating layer 94; the fourth insulating layer 94 is made of SiN x , Al2O3, SiO2, etc.; The third p-GaN layer 103 is disposed on the AlGaN barrier layer 70 and a step is formed therebetween. The fourth insulating layer 94 covers the surfaces of the AlGaN barrier layer 70 and the third p-GaN layer 103. The gate electrode 82 penetrates the fourth insulating layer 94 and contacts the third p-GaN layer 103. The source electrode 81 and the drain electrode 83 are respectively disposed at two ends of the device and are in contact with the AlGaN barrier layer 70 .

[0053] The remaining structures are the same as those in Example 5. The etching damage of the gallium nitride HEMT device structure in this embodiment is small, and the process stability is better.

[0054] Example 7 This embodiment provides a method for manufacturing the gallium nitride HEMT device structure in Embodiment 1, comprising the following steps: S1, providing a substrate 10, such as sapphire, SiC, etc.; S2, depositing Al with high Al doping component on the substrate 10 y Ga 1-y N, forming Al y Ga 1-y N layer 21; reference Figure 7 As shown; S3, making an epitaxial inhibition layer on the surface and making a template, y Ga 1-y Etching is performed on the N layer 21 to form a groove 210; Figure 8 As shown; S4. Selectively deposit low Al-doped Al on the device x Ga 1-x N, at least one Al embedded in the groove 210 is formed y Ga 1-y Al in N layer 21 x Ga 1-x N layer 22, forming a composite layer 20; Fig. 9 As shown; S5, sequentially fabricating a GaN buffer layer 30, a GaN channel layer 40, an AlN space layer 60, an AlGaN barrier layer 70 and a p-GaN layer 100 on the composite layer 20, and forming a two-dimensional electron gas layer 50 between the GaN channel layer 40 and the AlN space layer 60; Fig.10 As shown; S6, etching the source region and the drain region on the device, and making the source electrode 81 and the drain electrode 83 in the source region and the drain region respectively, forming an ohmic contact by high temperature alloy treatment, the alloy temperature is 650-900°C, nitrogen (N2) or argon (Ar) atmosphere, the alloy time is 30-120s, and the heating rate is 5-15°C / s; refer to Fig.11 As shown; S7, etching the p-GaN layer 100 to form a gate step structure; Fig.12 As shown; S8, etching a concave gate hole that sequentially penetrates the p-GaN layer 100, the AlGaN barrier layer 70, the AlN space layer 60 and the two-dimensional electron gas layer 50 and extends to the GaN channel layer 40; Fig.13 As shown; S9, manufacturing a first insulating layer 91, wherein the first insulating layer 91 covers the surfaces of the AlGaN barrier layer 70 and the p-GaN layer 100 and the inner surface of the recessed gate hole; Fig.14 As shown; S10, forming a second insulating layer 92 on the surface of the first insulating layer 91, and making the first insulating layer 91 partially leak out, wherein the partially leaked first insulating layer 91 includes the inner surface area of ​​the recessed gate hole and the partial area extending to the p-GaN layer 100; Fig.15 As shown; S11, manufacturing a gate electrode 82, wherein the gate electrode 82 contacts the partially leaked first insulating layer 91, referring to Fig.16 As shown, the device structure is finally formed.

[0055] The design of the composite layer 20 with high and low Al doping components optimizes the electric field distribution and reduces the charge accumulation problem at the gate edge, thereby improving the breakdown voltage. The multi-layer structure design (such as the double insulating layer and the p-GaN layer 100) improves the gate's control over the channel layer, helps reduce leakage current and parasitic capacitance, and enhances the high-voltage stability and high-frequency performance of the device. The ohmic contact formed by high-temperature alloy treatment effectively reduces the contact resistance, improves the current injection efficiency and transmission efficiency, and is suitable for high-power applications.

[0056] Finally, it should be noted that the above specific implementation methods are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the spirit and scope of the technical solution of the present invention, which should be included in the scope of the claims of the present invention.

Claims

1. A gallium nitride HEMT device structure, characterized in that: include: Substrate (10); A composite layer (20) is arranged on the substrate (10), wherein the composite layer (20) comprises Al with a high Al doping component. y Ga 1-y N layer (21) and Al with low Al doping content x Ga 1-x N layer (22), at least one Al x Ga 1-x The N layer (22) is embedded in the Al y Ga 1-y In the N layer (21); A GaN buffer layer (30) disposed on the composite layer (20); A GaN channel layer (40) is disposed on the GaN buffer layer (30); An AlN space layer (60) is disposed on the GaN channel layer (40) A two-dimensional electron gas layer (50), wherein the two-dimensional electron gas layer (50) is formed in the GaN channel layer (40) and is close to an interface between the GaN channel layer (40) and the AlN space layer (60); An AlGaN barrier layer (70) is disposed on the AlN space layer (60); A source electrode (81), a gate electrode (82) and a drain electrode (83), wherein an insulating layer is provided between the gate electrode (82) and the AlGaN barrier layer (70), and the source electrode (81) and the drain electrode (83) respectively extend from the upper side of the insulating layer to the inside of the AlN space layer (60) or the surface of the AlGaN barrier layer (70); Among them, the Al x Ga 1-x The N layer (22) is arranged on one side and / or both sides of the gate electrode (82), and a gap is left between the bottom end of the N layer and the bottom end of the gate electrode (82) in the device width direction.

2. A gallium nitride HEMT device structure according to claim 1, characterized in that: The device structure comprises a first p-GaN layer (101) and a recessed gate hole, and the insulating layer comprises a first insulating layer (91) and a second insulating layer (92); The first p-GaN layer (101) is arranged on the AlGaN barrier layer (70) and a step is formed between the two; the concave gate hole sequentially penetrates the first p-GaN layer (101), the AlGaN barrier layer (70), the AlN space layer (60) and the two-dimensional electron gas layer (50), and then extends into the GaN channel layer (40); The first insulating layer (91) covers the surfaces of the AlGaN barrier layer (70) and the first p-GaN layer (101) and the inner surface of the recessed gate hole; The gate electrode (82) extends into the recessed gate hole and contacts the first insulating layer (91) on the inner surface of the recessed gate hole and part of the first p-GaN layer (101) respectively; The second insulating layer (92) is arranged on the first insulating layer (91) and extends to the side end of the gate electrode (82); The dielectric constant of the first insulating layer (91) is greater than the dielectric constant of the second insulating layer (92); The source electrode (81) and the drain electrode (83) are respectively arranged at two ends of the device and respectively extend from the upper side of the second insulating layer (92) into the AlN space layer (60).

3. A gallium nitride HEMT device structure according to claim 1, characterized in that: The device structure comprises a second p-GaN layer (102), and the insulating layer comprises a third insulating layer (93); The second p-GaN layer (102) is arranged on the AlGaN barrier layer (70) to form a step between the two, the third insulating layer (93) covers the respective surfaces of the AlGaN barrier layer (70) and the second p-GaN layer (102), and the gate electrode (82) penetrates the third insulating layer (93) and contacts the second p-GaN layer (102); The source electrode (81) and the drain electrode (83) are respectively arranged at two ends of the device and respectively extend from the upper side of the third insulating layer (93) into the AlN space layer (60).

4. The gallium nitride HEMT device structure according to claim 1, characterized in that: The device structure comprises a third p-GaN layer (103), and the insulating layer comprises a fourth insulating layer (94); The third p-GaN layer (103) is arranged on the AlGaN barrier layer (70) and forms a step between the two, the fourth insulating layer (94) covers the respective surfaces of the AlGaN barrier layer (70) and the third p-GaN layer (103), and the gate electrode (82) penetrates the fourth insulating layer (94) and contacts the third p-GaN layer (103); The source electrode (81) and the drain electrode (83) are respectively arranged at two ends of the device and are in contact with the AlGaN barrier layer (70).

5. The gallium nitride HEMT device structure according to claim 1, characterized in that: In the Al y Ga 1-y N layer (21) and the Al x Ga 1-x In layer N (22), y > x , 0.1≤ y ≤0.4,0.01≤ x ≤0.

2.

6. The gallium nitride HEMT device structure according to claim 1, characterized in that: The Al2O3 closest to the gate electrode (82) x Ga 1-x The distance between the bottom end of the N layer (22) and the bottom end of the gate electrode (82) accounts for 0.01 to 0.2 of the width of the device.

7. A gallium nitride HEMT device structure and manufacturing method according to claim 1, characterized in that: Each of the Al x Ga 1-x The bottom width of the N layer (22) accounts for 0.1 to 0.5 of the width of the device.

8. A gallium nitride HEMT device structure and manufacturing method according to claim 1, characterized in that: The Al x Ga 1-x The shape of the N layer (22) includes a quadrilateral or an inverted trapezoid.

9. A gallium nitride HEMT device structure and manufacturing method according to claim 1, characterized in that: The Al x Ga 1-x N can be set from 1 to 5.

10. A method for manufacturing a gallium nitride HEMT device structure, characterized in that: include: Providing a substrate (10); Depositing Al with a high Al doping component on the substrate (10) y Ga 1-y N, forming Al y Ga 1-y N layer (21); An epitaxial inhibition layer is formed on the device surface and a template is prepared. y Ga 1-y Etching is performed on the N layer (21) to form a groove (210); Selective deposition of low Al-doped Al on devices x Ga 1-x N, forming at least one Al embedded in the groove (210) y Ga 1-y Al in N layer (21) x Ga 1-x N layer (22), forming a composite layer (20); A GaN buffer layer (30), a GaN channel layer (40), an AlN space layer (60), an AlGaN barrier layer (70) and a p-GaN layer (100) are sequentially fabricated on the composite layer (20), and a two-dimensional electron gas layer (50) is formed between the GaN channel layer (40) and the AlN space layer (60); Etching a source region and a drain region on the device, and manufacturing a source electrode (81) and a drain electrode (83) in the source region and the drain region respectively, and forming an ohmic contact by high-temperature alloy treatment; Etching the p-GaN layer (100) to form a gate step structure; Etching a concave gate hole which sequentially penetrates the p-GaN layer (100), the AlGaN barrier layer (70), the AlN space layer (60) and the two-dimensional electron gas layer (50) and then extends into the GaN channel layer (40); Manufacturing a first insulating layer (91), wherein the first insulating layer (91) covers respective surfaces of the AlGaN barrier layer (70) and the p-GaN layer (100) and the inner surface of the recessed gate hole; A second insulating layer (92) is formed on the surface of the first insulating layer (91), and the first insulating layer (91) is partially exposed, wherein the partially exposed first insulating layer (91) includes an inner surface area of ​​the recessed gate hole and a partial area thereof extending onto the p-GaN layer (100); A gate electrode (82) is manufactured, wherein the gate electrode (82) is in contact with the partially leaked first insulating layer (91).

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