Double-channel enhanced GaN power device

Abstract

The utility model relates to the technical field of gallium nitride power devices, in particular to a double-channel enhanced GaN power device, which comprises a substrate, a nucleating layer, a buffer layer, a lower channel layer, a first barrier layer, an upper channel layer, a second barrier layer and an insulating medium layer which are sequentially arranged from bottom to top. The device further comprises a first source-drain electrode group, a second source-drain electrode group, a first grid electrode and a second grid electrode. The structure is provided with two channels, two source electrodes, two grid electrodes and two drain electrodes, the on-resistance of the channels is reduced by adding one conducting channel, and the ohmic contact resistance of the source electrodes is reduced by forming ohmic contact between the two source electrodes and the two channels respectively. The ohmic contact resistance of the drain electrodes is reduced by forming ohmic contact between the two drain electrodes and the two channels respectively, so that the on resistance of the whole device is reduced under the condition that the chip area is not increased, and finally the chip size and the chip cost are reduced. In addition, the design of the two grid electrodes can ensure the control capability of the grid electrodes on the two channels.

Description

Technical Field

[0001] The utility model relates to the technical field of gallium nitride power devices, and in particular to a dual-channel enhancement-mode GaN power device. Background Art

[0002] Third-generation semiconductor materials such as GaN and SiC have a larger bandgap width than traditional Si materials, and thus have a higher critical breakdown electric field strength. GaN has another advantage over SiC, that is, GaN / can form an AlGaN / GaN heterojunction with AlGaN. Due to the spontaneous polarization and piezoelectric polarization effect of GaN, a high concentration of two-dimensional electron gas (2DEG) will be formed at the interface of the AlGaN / GaN heterojunction. 2DEG is not affected by surface scattering, so it has a higher electron mobility. Therefore, GaN power devices based on AlGaN / GaN heterojunctions have higher breakdown voltages and lower on-resistance than traditional Si MOS power devices. In addition, since GaN power devices are single-carrier conductive, there is no reverse recovery charge, so their switching speed is also much higher than traditional Si MOS power devices.

[0003] Because of the existence of two-dimensional electron gas at the interface of AlGaN / GaN heterojunction, the most primitive GaN power device is a depletion-mode device, that is, the threshold voltage Vth<0V. In order to make the device work safely and simplify the design of the driving circuit, GaN power devices need to achieve enhancement mode. At present, the PGaN gate structure is one of the effective methods to achieve enhancement mode, and it has been commercially applied on a large scale. The groove gate structure is another technical solution to achieve enhancement mode, which achieves enhancement mode by partially or completely etching the AlGaN layer under the gate. Although GaN power devices have obvious advantages over Si MOS, the advantages of GaN power devices are not prominent enough in practice, especially the on-resistance and breakdown voltage of the device are still far from the theoretical values. Utility Model Content

[0004] The utility model aims to provide a dual-channel enhanced GaN power device to solve the problem that the on-resistance and breakdown voltage of the device in the prior art are still far from the theoretical values.

[0005] The embodiments of the present invention are implemented by the following technical solutions:

[0006] A double-channel enhancement-mode GaN power device comprises a substrate, a nucleation layer, a buffer layer, a lower channel layer, a first barrier layer, an upper channel layer, a second barrier layer and an insulating dielectric layer arranged in sequence from bottom to top;

[0007] A first source-drain electrode group and a second source-drain electrode group are respectively disposed on both sides of the upper portion of the first barrier layer and both sides of the upper portion of the second barrier layer, and the first source-drain electrode group and the second source-drain electrode group form ohmic contacts with the first barrier layer and the second barrier layer respectively;

[0008] A first gate and a second gate are respectively disposed on the upper portions of the insulating dielectric layer and the second barrier layer.

[0009] In one embodiment of the present invention, the first source-drain electrode group includes a first source electrode and a first drain electrode, and the first source electrode and the first drain electrode pass through the upper channel layer, the second barrier layer and the insulating dielectric layer to form an ohmic contact with the first barrier layer;

[0010] The second source-drain electrode group includes a second source electrode and a second drain electrode, and the first source electrode and the first drain electrode pass through the insulating dielectric layer to form an ohmic contact with the second barrier layer.

[0011] In an embodiment of the present invention, the insulating dielectric layer where the first gate is disposed is sunken and disposed above the upper channel layer.

[0012] In an embodiment of the present invention, a PGaN layer is disposed at the bottom of the second gate, the second gate forms a Schottky contact with the PGaN layer, and the PGaN layer is disposed on the upper portion of the second barrier layer.

[0013] In an embodiment of the present invention, the first source and the second source are interconnected outside the active region, the first drain and the second drain are interconnected outside the active region, and the first gate and the second gate are interconnected outside the active region.

[0014] In one embodiment of the present invention, the nucleation layer is an AlN nucleation layer, the upper channel layer and the lower channel layer are both GaN layers, and the first barrier layer and the second barrier layer are both AlGaN barrier layers.

[0015] The technical solution of the embodiment of the utility model has at least the following advantages and beneficial effects:

[0016] The structure provided by the utility model mainly includes a substrate, a nucleation layer, a buffer layer, a lower channel layer, a first barrier layer, an upper channel layer, a second barrier layer and an insulating dielectric layer arranged in sequence from bottom to top; and also includes a first source-drain electrode group, a second source-drain electrode group, a first gate and a second gate. In this structure, there are two channels, two sources, two gates and two drains. The structure reduces the channel on-resistance by adding a conductive channel, reduces the source ohmic contact resistance by forming ohmic contacts with the two channels by two sources, and reduces the drain ohmic contact resistance by forming ohmic contacts with the two channels by two drains, thereby reducing the on-resistance of the entire device without increasing the chip area, and ultimately reducing the chip size and chip cost. In addition, the design of the two gates can ensure the control ability of the gate over the two channels. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions of the embodiments of the utility model, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the utility model and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other relevant drawings can be obtained based on these drawings without paying creative work.

[0018] Figure 1 It is a schematic diagram of the structure of the utility model;

[0019] 1-substrate, 2-nucleation layer, 3-buffer layer, 4-lower channel layer, 5-first barrier layer, 6-upper channel layer, 7-second barrier layer, 8-insulating dielectric layer, 9-first source, 10-second source, 11-first gate, 12-second gate, 13-PGaN layer, 14-second drain, 15-first drain. DETAILED DESCRIPTION

[0020] In order to make the purpose, technical scheme and advantages of the embodiments of the utility model clearer, the technical scheme in the embodiments of the utility model will be clearly and completely described below in conjunction with the drawings in the embodiments of the utility model. Obviously, the described embodiments are part of the embodiments of the utility model, not all of the embodiments. Generally, the components of the embodiments of the utility model described and shown in the drawings here can be arranged and designed in various different configurations.

[0021] Please refer to Figure 1 The utility model provides a double-channel enhancement-mode GaN power device, comprising a substrate 1, a nucleation layer 2, a buffer layer, a lower channel layer 4, a first barrier layer 5, an upper channel layer 6, a second barrier layer 7 and an insulating dielectric layer 8 arranged in sequence from bottom to top;

[0022] In this embodiment, the nucleation layer 2 is an AlN nucleation layer 2, the upper channel layer 6 and the lower channel layer 4 are both GaN layers, and the first barrier layer 5 and the second barrier layer 7 are both AlGaN barrier layers.

[0023] A first source-drain electrode group is disposed on both sides of the upper portion of the first barrier layer 5, and a second source-drain electrode group is disposed on both sides of the upper portion of the second barrier layer 7. The first source-drain electrode group forms an ohmic contact with the first barrier layer 5, and the second source-drain electrode group forms an ohmic contact with the second barrier layer 7.

[0024] Specifically, in this embodiment, the first source-drain electrode group includes a first source electrode 9 and a first drain electrode 15, and the first source electrode 9 and the first drain electrode 15 pass through the upper channel layer 6, the second barrier layer 7 and the insulating dielectric layer 8 to form an ohmic contact with the first barrier layer 5;

[0025] The second source-drain electrode group includes a second source electrode 10 and a second drain electrode 14 . The first source electrode 9 and the first drain electrode 15 pass through the insulating dielectric layer 8 to form an ohmic contact with the second barrier layer 7 .

[0026] Secondly, a first gate 11 and a second gate 12 are respectively disposed on the upper portions of the insulating dielectric layer 8 and the second barrier layer 7 .

[0027] The insulating dielectric layer 8 where the first gate 11 is disposed is sunken and disposed on the upper portion of the upper channel layer 6 .

[0028] More specifically, a PGaN layer 13 is disposed at the bottom of the second gate 12 , the second gate 12 forms a Schottky contact with the PGaN layer 13 , the PGaN layer 13 is disposed on the second barrier layer 7 , and insulating dielectric layers 8 are disposed on both sides of the PGaN layer 13 and the second gate 12 .

[0029] In an exemplary embodiment of the present invention, the first source 9 and the second source 10 are interconnected outside the active region, the first drain 15 and the second drain 14 are interconnected outside the active region, and the first gate 11 and the second gate 12 are interconnected outside the active region.

[0030] The structure provided by the utility model mainly includes a substrate 1, a nucleation layer 2, a buffer layer, a lower channel layer 4, a first barrier layer 5, an upper channel layer 6, a second barrier layer 7 and an insulating dielectric layer 8 arranged in sequence from bottom to top; and also includes a first source-drain electrode group, a second source-drain electrode group, a first gate 11 and a second gate 12. In this structure, there are two channels, two sources, two gates and two drains. The structure reduces the channel on-resistance by adding a conductive channel, reduces the source ohmic contact resistance by forming ohmic contacts with the two channels respectively by two sources, and reduces the drain ohmic contact resistance by forming ohmic contacts with the two channels respectively by two drains, thereby reducing the on-resistance of the entire device without increasing the chip area, and ultimately reducing the chip size and chip cost. In addition, the design of the two gates can ensure the control ability of the gate over the two channels.

[0031] The preparation method of the present invention comprises:

[0032] PGaN is etched on the GaN epitaxy to form a PGaN layer 13, the Al GaN barrier layer under the first gate 11 is etched, an insulating dielectric layer 8 is grown, the insulating dielectric layer 8 is etched, a gate metal is deposited and etched to form a first gate 11 and a second gate 12, the Al GaN barrier layer and the GaN layer are etched, a source-drain ohmic contact metal is deposited and etched to form a first source 9, a second source 10, a first drain 15 and a second drain 14, and the device is rapidly thermally annealed to form an ohmic contact between the source and drain metals.

[0033] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A dual-channel enhancement-mode GaN power device, characterized in that: It comprises a substrate (1), a nucleation layer (2), a buffer layer, a lower channel layer (4), a first barrier layer (5), an upper channel layer (6), a second barrier layer (7) and an insulating dielectric layer (8) which are arranged in sequence from bottom to top; A first source-drain electrode group and a second source-drain electrode group are respectively arranged on both sides of the upper part of the first barrier layer (5) and on both sides of the upper part of the second barrier layer (7), and the first source-drain electrode group and the second source-drain electrode group form ohmic contacts with the first barrier layer (5) and the second barrier layer (7) respectively; A first gate (11) and a second gate (12) are respectively arranged on the upper parts of the insulating dielectric layer (8) and the second barrier layer (7).

2. A dual-channel enhancement-mode GaN power device according to claim 1, characterized in that: The first source-drain electrode group comprises a first source electrode (9) and a first drain electrode (15), wherein the first source electrode (9) and the first drain electrode (15) pass through the upper channel layer (6), the second barrier layer (7) and the insulating dielectric layer (8) to form an ohmic contact with the first barrier layer (5); The second source-drain electrode group comprises a second source electrode (10) and a second drain electrode (14); the first source electrode (9) and the first drain electrode (15) pass through the insulating dielectric layer (8) to form an ohmic contact with the second barrier layer (7).

3. A dual-channel enhancement-mode GaN power device according to claim 1, characterized in that: The insulating dielectric layer (8) is sunken at the top of the upper channel layer (6) where the first gate (11) is arranged.

4. A dual-channel enhancement-mode GaN power device according to claim 1, characterized in that: A PGaN layer (13) is arranged at the bottom of the second gate (12), the second gate (12) forms a Schottky contact with the PGaN layer (13), and the PGaN layer (13) is arranged on the upper part of the second barrier layer (7).

5. A dual-channel enhancement-mode GaN power device according to claim 2, characterized in that: The first source electrode (9) and the second source electrode (10) are interconnected outside the active region, the first drain electrode (15) and the second drain electrode (14) are interconnected outside the active region, and the first gate electrode (11) and the second gate electrode (12) are interconnected outside the active region.

6. A dual-channel enhancement-mode GaN power device according to claim 1, characterized in that: The nucleation layer (2) is an AlN nucleation layer (2), the upper channel layer (6) and the lower channel layer (4) are both GaN layers, and the first barrier layer (5) and the second barrier layer (7) are both AlGaN barrier layers.

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