Super junction device terminal structure and preparation method thereof

Abstract

The invention relates to a super junction device terminal structure and a preparation method thereof. The terminal structure comprises at least one first P-type epitaxial layer, a plurality of N-type doped regions, a first N-type epitaxial layer and a plurality of second P-type epitaxial layers, the at least one first P-type epitaxial layer and the first N-type epitaxial layer are stacked in sequence; the plurality of N-type doped regions extend from the first surface of the first P-type epitaxial layer to the second surface of the first P-type epitaxial layer; the N-type doped regions located in the transition region and the terminal region are distributed at intervals, and the N-type doped regions in every two adjacent first P-type epitaxial layers make contact with each other. The plurality of second P-type epitaxial layers are distributed in the first N-type epitaxial layer at intervals, the plurality of second P-type epitaxial layers of the active region are in contact with the N-type doped regions, and the second P-type epitaxial layers of the transition region and the terminal region are located between two adjacent N-type doped regions and are in contact with the first P-type epitaxial layer. The structure solves the problem that the withstand voltage of the terminal region and the transition region is lower than that of the active region.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor technology, and in particular relates to a super junction device terminal structure and a preparation method thereof. Background Art

[0002] The super junction is composed of alternating P-type thin layers and N-type thin layers formed on a semiconductor substrate. The depletion layer formed by matching the P-type thin layer, namely the P-pillar, and the N-type thin layer, namely the N-pillar, is used to withstand reverse voltage. Compared with the traditional vertical double diffused metal-oxide semiconductor field effect transistor (VDMOS), the on-resistance of the super junction device is significantly reduced under the same withstand voltage specification.

[0003] The terminal structure of the existing deep trench super junction device mainly includes: active area, transition area and terminal area. Among them, the trench depths of the active area, transition area and terminal area are the same. At the charge balance point concentration, the withstand voltage of the three areas is not much different. If the concentration of the N-type column is greater than that of the P-type column, the withstand voltage of the terminal area and the transition area will be lower than that of the active area. When the device undergoes avalanche breakdown, the current will be concentrated in the area with lower withstand voltage: the terminal area and the transition area, which will cause thermal damage due to current concentration. Super junction devices have very high process requirements. Under the condition of no process error, the withstand voltage of the terminal of the super junction power device is about 99.5% of the withstand voltage of the active area. However, in the actual processing process, due to the fluctuation of process parameters, the terminal withstand voltage of the super junction device can easily drop to less than 96% of the active area. After the withstand voltage of the terminal area and the transition area is lower than that of the active area, the device breakdown position is likely to occur in the terminal area or the transition area, resulting in a decrease in the device's avalanche resistance.

[0004] Therefore, the existing deep trench super junction device has the problem that the withstand voltage of the terminal region and the transition region is lower than that of the active region, resulting in low avalanche resistance of the device. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a super junction device terminal structure and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions: An embodiment of the present invention provides a super junction device terminal structure, comprising: at least one first P-type epitaxial layer, a plurality of N-type doped regions, a first N-type epitaxial layer and a plurality of second P-type epitaxial layers, wherein: The at least one first P-type epitaxial layer and the first N-type epitaxial layer are stacked in sequence from bottom to top; The plurality of N-type doped regions extend from the first surface to the second surface of each of the first P-type epitaxial layers; the N-type doped regions located in the active region form an integral region; the plurality of N-type doped regions located in the transition region and the terminal region are distributed at intervals, and the N-type doped regions in two adjacent first P-type epitaxial layers are in contact; The plurality of second P-type epitaxial layers are spaced apart inside the first N-type epitaxial layer, the plurality of second P-type epitaxial layers in the active area are in contact with the N-type doped area, and the second P-type epitaxial layers in the transition area and the terminal area are located between two adjacent N-type doped areas and in contact with the first P-type epitaxial layer.

[0006] In one embodiment of the present invention, in the transition region and the terminal region, a boundary line between the first P-type epitaxial layer and the N-type doped region is a curve.

[0007] In one embodiment of the present invention, along the direction from the first surface to the second surface of the first P-type epitaxial layer, the width of the N-type doping region first gradually increases and then gradually decreases.

[0008] In one embodiment of the present invention, the depth of the second P-type epitaxial layer is greater than or equal to the thickness of the first N-type epitaxial layer, and when the depth of the second P-type epitaxial layer is greater than the thickness of the first N-type epitaxial layer, the depth of the second P-type epitaxial layer extending into the top layer of the first P-type epitaxial layer is less than or equal to half the thickness of the top layer of the first P-type epitaxial layer.

[0009] In one embodiment of the present invention, the total thickness of the at least one first P-type epitaxial layer is 3-10 μm, and the doping concentration of the first P-type epitaxial layer is 5e15-2e16 cm -3 ; The total thickness of the contacting N-type doping regions in the transition region and the terminal region is 3-10 μm; the doping concentration of the N-type doping region is 5e15-2e16 cm -3 ; The doping concentration of the first N-type epitaxial layer is 5e15-2e16cm -3 ; The width of the second P-type epitaxial layer is 3.8-4.5 μm, and the doping concentration is 5e15-2e16 cm -3 .

[0010] In one embodiment of the present invention, it also includes: an N-type substrate, a second N-type epitaxial layer, a plurality of P-type body regions, an oxide layer, a plurality of first gate oxide layers, a plurality of first gates, a second gate, a plurality of first N-type source regions, an interlayer insulating medium, a plurality of through-hole metals, a first source metal, a second source metal and a drain metal, wherein: The second N-type epitaxial layer, the N-type substrate, and the drain metal are sequentially stacked from top to bottom on the second surface of the first P-type epitaxial layer at the bottom; The plurality of P-type body regions extend from the first surface of the first N-type epitaxial layer to the interior of the first N-type epitaxial layer, the plurality of P-type body regions of the active region correspond to and contact the plurality of second P-type epitaxial layers one by one, and the P-type body regions of the transition region form an integral region and contact the plurality of second P-type epitaxial layers; The plurality of first gate oxide layers are distributed on the surface of the first N-type epitaxial layer, and an end of each first gate oxide layer spans two adjacent P-type body regions. The plurality of first gate electrodes are arranged on the surfaces of the plurality of first gate oxide layers in a one-to-one correspondence. The plurality of first N-type source regions are distributed in the plurality of P-type body regions of the active region, and each first N-type source region contacts an end of each first gate oxide layer. The oxide layer covers the surface of the first N-type epitaxial layer and the surfaces of the plurality of second P-type epitaxial layers in the terminal region, and one end extends to a partial surface of the P-type body region in the transition region; the second gate is located on the surface of the oxide layer; The interlayer insulating dielectric covers the P-type body region, the oxide layer, the first gate, the second gate and the first N-type source region; The plurality of through-hole metals penetrate through the interlayer insulating medium; The first source metal is connected to the first N-type source region and the P-type body region of the transition region through the through-hole metal; the second source metal is connected to the second gate through the through-hole metal.

[0011] In one embodiment of the present invention, the present invention further comprises: a second gate oxide layer, a third gate, a second N-type source region and a third source metal, wherein: The second gate oxide layer is located on the surface of the first N-type epitaxial layer and contacts the other end of the oxide layer, the third gate is located on the first surface of the second gate oxide layer and extends to the surface of the oxide layer, the second N-type source region is located in the first N-type epitaxial layer and contacts the second surface of the second gate oxide layer; the third source metal is connected to the third gate through the through-hole metal, and is connected to the second N-type source region and the first N-type epitaxial layer through the through-hole metal.

[0012] Another embodiment of the present invention provides a method for preparing a super junction device terminal structure, comprising the steps of: growing a first P-type epitaxial layer; Performing ion implantation in the first P-type epitaxial layer to form a plurality of N-type doped regions penetrating the first P-type epitaxial layer, wherein the N-type doped regions located in the active region form an integral region, and the plurality of N-type doped regions located in the transition region and the terminal region are distributed at intervals; Growing a first N-type epitaxial layer on a first surface of the first P-type epitaxial layer; Etching a plurality of trenches distributed at intervals in the first N-type epitaxial layer until the first N-type epitaxial layer is penetrated, wherein the plurality of trenches in the transition region and the terminal region are located between two adjacent N-type doped regions; A second P-type epitaxial layer is filled in the plurality of trenches, wherein the second P-type epitaxial layer in the active area contacts the N-type doped area, and the second P-type epitaxial layer in the transition area and the terminal area contacts the first P-type epitaxial layer.

[0013] In one embodiment of the present invention, before growing the first P-type epitaxial layer, the method further includes: A second N-type epitaxial layer is grown on the N-type substrate, and the first P-type epitaxial layer is located on the second N-type epitaxial layer.

[0014] In one embodiment of the present invention, after the second P-type epitaxial layer is filled in the plurality of trenches, the method further comprises: Ion implantation is performed on the first N-type epitaxial layer to form a P-type body region extending into the first N-type epitaxial layer, wherein the P-type body regions of the active region correspond to the second P-type epitaxial layers one by one and contact each other, and the P-type body regions of the transition region form an integral region and contact the second P-type epitaxial layers; An oxide layer is formed on the surface of the first N-type epitaxial layer in the terminal region, the surfaces of the plurality of second P-type epitaxial layers, and a portion of the surface of the P-type body region in the transition region; Preparing a plurality of first gate oxide layers and second gate oxide layers on the surface of the first N-type epitaxial layer, wherein an end of each of the first gate oxide layers spans two adjacent P-type body regions, and the second gate oxide layer contacts an end of the oxide layer; A first gate is formed on the surface of each of the first gate oxide layers, a second gate is formed on the surface of the oxide layer, and a third gate is formed on the surface of the second gate oxide layer and extends to the surface of the oxide layer; Ion implantation is performed in the P-type body region of the active region to form a plurality of first N-type source regions, each of the first N-type source regions is in contact with an end of each first gate oxide layer, and ion implantation is performed in the first N-type epitaxial layer under the second gate oxide layer to form a second N-type source region; Depositing an interlayer insulating dielectric on the surfaces of the P-type body region, the oxide layer, the second gate oxide layer, the first gate, the second gate, the third gate and the first N-type source region; Forming a plurality of through holes in the interlayer insulating medium, and filling metal in the through holes to form a plurality of through hole metals; Preparing a first source metal, a second source metal and a third source metal on the interlayer insulating medium, wherein the first source metal is connected to the first N-type source region and the P-type body region of the transition region through the through-hole metal, the second source metal is connected to the second gate through the through-hole metal, the third source metal is connected to the third gate through the through-hole metal, and is connected to the second N-type source region and the first N-type epitaxial layer through the through-hole metal; A drain metal is prepared on the lower surface of the N-type substrate.

[0015] Compared with the prior art, the present invention has the following beneficial effects: 1. The present invention forms a plurality of N-type doped regions in the first P-type epitaxial layer, and a plurality of second P-type epitaxial layers in the active region are in contact with the N-type doped regions, the second P-type epitaxial layer in the transition region and the terminal region are in contact with the first P-type epitaxial layer, the second P-type epitaxial layer in the active region forms a P-type column, the first N-type epitaxial layer forms an N-type column, the second P-type epitaxial layer in the transition region and the terminal region and the first P-type epitaxial layer form a P-type column, the first N-type epitaxial layer and the N-type doped region form an N-type column, so that the depth of the P-type column in the terminal region and the transition region is deeper than that in the active region, so that the withstand voltage of the terminal region and the transition region is higher than that of the active region, which solves the problem that the withstand voltage of the terminal region and the transition region is lower than that of the active region, and in the reverse withstand voltage state, the device preferentially breaks down the active region, so that the device has a higher avalanche resistance; 2. The boundary line between the first P-type epitaxial layer and the N-type doped region of the present invention is curved, so that the contact area between the P-type column and the N-type column is larger than the planar contact area, thereby improving the device's anti-electronic interference capability and increasing the device's charge balance fault tolerance. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 A schematic structural diagram of a first super junction device terminal structure provided by an embodiment of the present invention; Figure 2 A schematic structural diagram of a second super junction device terminal structure provided by an embodiment of the present invention; Figure 3 A schematic structural diagram of a third super junction device terminal structure provided by an embodiment of the present invention; Figure 4 A schematic structural diagram of a fourth super junction device terminal structure provided by an embodiment of the present invention; Figure 5 A schematic structural diagram of a fifth super junction device terminal structure provided by an embodiment of the present invention; Figure 6 It is a simulation diagram of the existing deep trench terminal structure under the reverse withstand voltage state; Figure 7 This is a simulation diagram of the terminal structure of the super junction device in this embodiment under the reverse withstand voltage state; Figure 8 The withstand voltage values ​​of the existing deep trench terminal structure and the super junction device terminal structure of this embodiment under different process conditions; Figure 9a-9n A schematic diagram of a process of preparing a super junction device terminal structure provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0017] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0018] Embodiment 1 See also Figure 1 , Figure 1 A schematic diagram of the structure of the first superjunction device terminal structure provided by an embodiment of the present invention. The superjunction device terminal structure includes: at least one first P-type epitaxial layer 1, a plurality of N-type doped regions 2, a first N-type epitaxial layer 3, and a plurality of second P-type epitaxial layers 4. Among them, at least one first P-type epitaxial layer 1 and a first N-type epitaxial layer 3 are stacked in sequence from bottom to top; a plurality of N-type doped regions 2 extend from the first surface of each first P-type epitaxial layer 1 to the second surface; the N-type doped regions 2 located in the active region form an integral region; a plurality of N-type doped regions 2 located in the transition region and the terminal region are distributed at intervals, and the N-type doped regions 2 in two adjacent first P-type epitaxial layers 1 are in contact; a plurality of second P-type epitaxial layers 4 are distributed at intervals inside the first N-type epitaxial layer 3, a plurality of second P-type epitaxial layers 4 in the active region are in contact with the N-type doped regions 2, and the second P-type epitaxial layers 4 in the transition region and the terminal region are located between two adjacent N-type doped regions 2 and in contact with the first P-type epitaxial layer 1.

[0019] Specifically, the number of the first P-type epitaxial layer 1 can be one layer or multiple layers. When the first P-type epitaxial layer 1 is one layer, the N-type doping region 2 in the active region extends from the first surface to the second surface of the first P-type epitaxial layer 1 as a whole, and the plurality of N-type doping regions 2 in the transition region and the terminal region are distributed at intervals and extend from the first surface to the second surface of the first P-type epitaxial layer 1. When the first P-type epitaxial layer 1 is multiple layers, the N-type doping region 2 in each layer of the first P-type epitaxial layer 1 extends from the first surface to the second surface of the first P-type epitaxial layer 1, and the N-type doping region 2 in the active region forms an overall N-type region. In the transition region and the terminal region, the N-type doping regions 2 distributed at intervals in two adjacent layers of the first P-type epitaxial layer 1 are aligned vertically and in contact with each other, forming a vertically continuous N-type region, such as Figure 2 As shown, Figure 2 A schematic structural diagram of a second super junction device terminal structure provided in an embodiment of the present invention.

[0020] Further, in the active area, the second P-type epitaxial layer 4 forms a P-type column, and the first N-type epitaxial layer 3 forms an N-type column; in the terminal area and the transition area, the contacting second P-type epitaxial layer 4 and at least one first P-type epitaxial layer 1 form a P-type column together, and the contacting first N-type epitaxial layer 3 and the multi-layer N-type doping region 2 form an N-type column together. Therefore, the depth of the P-type column in the terminal area and the transition area is deeper than that in the active area, and the depth difference depends on the total thickness of at least one first P-type epitaxial layer. Exemplarily, the total thickness of at least one first P-type epitaxial layer 1 is 3~10μm, and the total thickness of the contacting N-type doping region 2 is 3~10μm, that is, the P-type column in the terminal area and the transition area is 3~10μm deeper than the P-type column in the active area.

[0021] The active area usually accounts for more than 85% of the chip area and has a stronger avalanche current resistance than the terminal area and the transition area. In this embodiment, since the depth of the P-type column in the terminal area and the transition area is deeper than that in the active area, the withstand voltage of the transition area and the terminal area is higher than that of the active area, which solves the problem that the withstand voltage of the terminal area and the transition area is lower than that of the active area. In the reverse withstand voltage state, the device breaks down the active area first, so that the device has a higher avalanche resistance.

[0022] In a specific embodiment, in the transition region and the terminal region, the boundary between the first P-type epitaxial layer 1 and the N-type doped region 2 is distributed in a curved line.

[0023] Specifically, in the transition region and the terminal region, since the boundary of the formed N-type doped region 2 is a curve, the boundary line between the first P-type epitaxial layer 1 and the N-type doped region 2 is a curve. Further, when the first P-type epitaxial layer 1 is multi-layered, the boundary line between the multi-layer N-type doped region 2 and the multi-layer first P-type epitaxial layer 1 is a superposition of multiple curves.

[0024] Exemplarily, along the direction from the first surface to the second surface of the first P-type epitaxial layer 1 , the width of the N-type doping region 2 first gradually increases and then gradually decreases, so that the boundary of the N-type doping region 2 forms an arc.

[0025] In this embodiment, the boundary line between the first P-type epitaxial layer and the N-type doped region is curved, so that the contact area between the P-type column and the N-type column is larger than the planar contact area, thereby improving the device's anti-electronic interference capability, increasing the device's charge balance tolerance, and increasing the device's process window.

[0026] In a specific embodiment, the depth of the second P-type epitaxial layer 4 is greater than or equal to the thickness of the first N-type epitaxial layer 3, and when the depth of the second P-type epitaxial layer 4 is greater than the thickness of the first N-type epitaxial layer 3, the depth of the second P-type epitaxial layer 4 extending into the top-layer first P-type epitaxial layer 1 is less than or equal to half the thickness of the top-layer first P-type epitaxial layer 1.

[0027] Specifically, the depth of the second P-type epitaxial layer 4 may be equal to the thickness of the first N-type epitaxial layer 3, or may be greater than the thickness of the first N-type epitaxial layer 3. When the first P-type epitaxial layer 1 is one layer and the depth of the second P-type epitaxial layer 4 is greater than the thickness of the first N-type epitaxial layer 3, the second P-type epitaxial layer 4 extends into the first P-type epitaxial layer 1, and the depth of the extended portion is less than or equal to half the thickness of the first P-type epitaxial layer 1, such as Figure 3 As shown, Figure 3 A schematic diagram of the structure of the third super junction device terminal structure provided by an embodiment of the present invention; when the first P-type epitaxial layer 1 is multi-layered and the depth of the second P-type epitaxial layer 4 is greater than the thickness of the first N-type epitaxial layer 3, the second P-type epitaxial layer 4 extends into the top first P-type epitaxial layer 1, and the depth of the extended portion is less than or equal to half the thickness of the top first P-type epitaxial layer 1, such as Figure 4 As shown, Figure 4 A schematic structural diagram of a fourth super junction device terminal structure provided in an embodiment of the present invention.

[0028] In this embodiment, the depth of the second P-type epitaxial layer extending into the top-layer first P-type epitaxial layer is less than or equal to half the thickness of the top-layer first P-type epitaxial layer. On the one hand, the preparation process is relatively stable. On the other hand, if the depth of the second P-type epitaxial layer is too deep, the depth difference between the P-type column in the active area and the P-type column in the transition area and the terminal area will become smaller, which will eventually lead to a smaller gap between the breakdown voltage of the active area and the breakdown voltage of the transition area and the terminal; if the extension depth of the second P-type epitaxial layer is equal to the depth of the first P-type epitaxial layer, the depths of the P-type columns in the active area, the transition area and the terminal area are the same, and the effect of the breakdown voltage of the terminal area and the transition area being greater than the breakdown voltage of the active area cannot be achieved.

[0029] In a specific embodiment, the doping concentration of the first P-type epitaxial layer 1 is 5e15-2e16cm -3 ; The doping concentration of N-type doping region 2 is 5e15-2e16cm -3 ; The doping concentration of the first N-type epitaxial layer 3 is 5e15-2e16cm -3 ; The doping concentration of the second P-type epitaxial layer 4 is 5e15-2e16cm -3 .

[0030] Specifically, the width of the second P-type epitaxial layer 4 is 3.8-4.5 μm. The widths of the second P-type epitaxial layer 4 in the active region and the transition region are the same, and the same here can be understood as the width difference is within 0.3 μm; the widths of the second P-type epitaxial layer 4 in the terminal region can be the same or different.

[0031] Exemplarily, the number of the second P-type epitaxial layers 4 in the terminal region is between 10 and 18, and the number of the second P-type epitaxial layers 4 in the transition region is between 3 and 7.

[0032] In a specific embodiment, the materials of the first P-type epitaxial layer 1 , the first N-type epitaxial layer 3 , and the second P-type epitaxial layer 4 all include silicon.

[0033] See also Figure 5 , Figure 5 A schematic diagram of the structure of the fifth super junction device terminal structure provided by an embodiment of the present invention. The super junction device terminal structure includes: at least one first P-type epitaxial layer 1, a plurality of N-type doped regions 2, a first N-type epitaxial layer 3 and a plurality of second P-type epitaxial layers 4, an N-type substrate 5, a second N-type epitaxial layer 6, a plurality of P-type body regions 7, an oxide layer 8, a plurality of first gate oxide layers 91, a plurality of first gates 101, a second gate 102, a plurality of first N-type source regions 111, an interlayer insulating dielectric 12, a plurality of through-hole metals 13, a first source metal 141, a second source metal 142 and a drain metal 15.

[0034] The relative positional relationship among the at least one first P-type epitaxial layer 1 , the plurality of N-type doped regions 2 , the first N-type epitaxial layer 3 and the plurality of second P-type epitaxial layers 4 can be found in the above-mentioned embodiment.

[0035] The second N-type epitaxial layer 6, the N-type substrate 5, and the drain metal 15 are stacked in sequence from top to bottom on the second surface of the bottom first P-type epitaxial layer 1. A plurality of P-type body regions 7 extend from the first surface of the first N-type epitaxial layer 3 to the inside of the first N-type epitaxial layer 3. The plurality of P-type body regions 7 in the active region correspond to and contact the plurality of second P-type epitaxial layers 4 one by one. The P-type body regions 7 in the transition region form an integral region and contact the plurality of second P-type epitaxial layers 4. A plurality of first gate oxide layers 91 are distributed on the surface of the first N-type epitaxial layer 3, and the end of each first gate oxide layer 91 spans two adjacent P-type body regions 7. A plurality of first gate electrodes 101 are arranged on the surface of the plurality of first gate oxide layers 91 in one by one correspondence. A plurality of first N-type source regions 111 are distributed in the plurality of P-type body regions 7 in the active region, and each first N-type source region 111 contacts the end of each first gate oxide layer 91, that is, two first N-type source regions 111 are distributed in each P-type body region 7 in the active region. The oxide layer 8 covers the surface of the first N-type epitaxial layer 3 and the surfaces of the second P-type epitaxial layers 4 in the terminal region, and one end extends to a part of the surface of the P-type body region 7 in the transition region. The second gate 102 is located on the surface of the oxide layer 8. The interlayer insulating dielectric 12 covers the P-type body region 7, the oxide layer 8, the first gate 101, the second gate 102 and the first N-type source region 111. Several through-hole metals 13 penetrate the interlayer insulating dielectric 12. The first source metal 141 is connected to the first N-type source region 111 and the P-type body region 7 in the transition region through the through-hole metal 13; it can be understood that each first N-type source region 111 is connected to the first source metal 141 through a through-hole metal 13, and the P-type body region 7 in the transition region can be connected to the first source metal 141 through two through-hole metals 13. The second source metal 142 is connected to the second gate 102 through the through-hole metal 13. Exemplarily, the second source metal 142 may be connected to the second gate 102 through two through-hole metals 13 .

[0036] In a specific embodiment, the super junction device terminal structure further includes: a second gate oxide layer 92 , a third gate 103 , a second N-type source region 112 and a third source metal 143 .

[0037] Specifically, the second gate oxide layer 92 is located on the surface of the first N-type epitaxial layer 3 and contacts the other end of the oxide layer 8. The third gate 103 is located on the first surface of the second gate oxide layer 92 and extends to the upper surface of the oxide layer 8, and the second N-type source region 112 is located in the first N-type epitaxial layer 3 and contacts the second surface of the second gate oxide layer 92. The third source metal 143 is connected to the third gate 103 through the through-hole metal 13, and is connected to the second N-type source region 112 and the first N-type epitaxial layer 3 through the through-hole metal 13.

[0038] Exemplarily, the third source metal 143 can be connected to the third gate 103 through two through-hole metals 13, wherein one through-hole metal 13 is connected to the portion of the third gate 103 located on the upper surface of the oxide layer 8, and the other through-hole metal 13 is connected to the portion of the third gate 103 located on the upper surface of the second gate oxide layer 92. The through-hole metal 13 connecting the second N-type source region 112 and the first N-type epitaxial layer 3 penetrates the interlayer insulating dielectric 12, the second gate oxide layer 92, the second N-type source region 112, and extends to the interior of the first N-type epitaxial layer 3.

[0039] In this embodiment, a second N-type source region 112 is disposed at the outer edge of the terminal region. The second N-type source region 112 can serve as a cutoff protection ring to block external ion intrusion.

[0040] In a specific embodiment, the material of the N-type substrate 5 includes silicon, and the doping concentration is 3.5e19-9.6e19cm -3 , exemplarily, the thickness of the N-type substrate 5 is 725 μm. The material of the second N-type epitaxial layer 6 includes silicon, the thickness is 2-4 μm, and the doping concentration is 4e16-8e16 cm -3 The doping concentration of the P-type body region 7 is 3e16-1e17cm -3 The doping concentration of the first N-type source region 111 and the second N-type source region 112 is 8e19-2e20cm -3 .

[0041] In this embodiment, the N-type doping ions include phosphorus ions, arsenic ions or nitrogen ions, and the P-type doping ions include boron ions.

[0042] This embodiment Figure 5 The super junction device terminal structure shown in the figure and the existing deep trench terminal structure are simulated under reverse withstand voltage conditions. The simulation results are shown in Figure 6 , Figure 7 and Figure 8 As shown, Figure 6 This is a simulation diagram of the existing deep trench terminal structure under reverse withstand voltage state. Figure 7 is a simulation diagram of the terminal structure of the super junction device in this embodiment under the reverse withstand voltage state, Figure 8 1 and 2 are the withstand voltage values ​​of the existing deep trench terminal structure and the super junction device terminal structure of this embodiment under different process conditions.

[0043] Depend on Figure 6 It can be seen that the maximum impact ionization rate of the existing deep trench terminal structure occurs on the surface of the first P-type column in the terminal area, and the avalanche current occurs in the transition area and the terminal area, among which the transition area bears more avalanche current. The transition area occupies a small proportion of the chip area, has a relatively weak ability to resist avalanche current, and is prone to heat and burnout.

[0044] Depend on Figure 7It can be seen that the maximum impact ionization rate of the terminal structure of this embodiment occurs inside the active area, and the avalanche current occurs in the active area and the transition area, among which the active area bears more avalanche current, the active area accounts for a larger proportion of the chip area, and the ability to resist avalanche current is relatively strong.

[0045] Figure 8 In the figure, Terminal A_BV represents the withstand voltage of the existing deep trench terminal structure under different second P-type silicon epitaxial layer concentrations, Cell_BV represents the withstand voltage of the active area under different second P-type silicon epitaxial layer concentrations, and Terminal B_BV represents the withstand voltage of the super junction device terminal structure of this embodiment under different second P-type silicon epitaxial layer concentrations. Figure 8 It can be seen that the withstand voltage Terminal A_BV of the existing deep trench terminal structure at different second P-type silicon epitaxial layer concentrations is lower than the withstand voltage Cell_BV of the active region, while the withstand voltage Terminal B_BV of the super junction device terminal structure of this embodiment at different second P-type silicon epitaxial layer concentrations is higher than the withstand voltage Cell_BV of the active region and the withstand voltage Terminal A_BV of the existing deep trench terminal structure. The breakdown of the super junction device terminal structure of this embodiment is not likely to occur in the active region, which improves the process window of the device.

[0046] Embodiment 2 Based on Example 1, see Figure 9a-9n , Figure 9a-9n A schematic diagram of a process of preparing a super junction device terminal structure provided by an embodiment of the present invention. The method of preparing the super junction device terminal structure comprises the following steps: S1, growing a second N-type epitaxial layer 6 on an N-type substrate 5, such as Figure 9a shown.

[0047] Specifically, a heavily doped N-type substrate 5 is selected as a part of the drain, and the material of the N-type substrate 5 is silicon. Then, a lightly doped second N-type epitaxial layer 6 is epitaxially grown on the N-type substrate 5. Then, the epitaxial wafer is cleaned.

[0048] S2, growing a first P-type epitaxial layer 1 on the second N-type epitaxial layer 6, such as Figure 9b shown.

[0049] S3, performing ion implantation in the first P-type epitaxial layer 1 to form a plurality of N-type doping regions 2 penetrating the first P-type epitaxial layer 1, wherein the N-type doping regions 2 located in the active region form an integral region, and the plurality of N-type doping regions 2 located in the transition region and the terminal region are distributed at intervals, such as Fig.9c shown.

[0050] Specifically, an oxide layer is first deposited on the second N-type epitaxial layer 6 to prevent subsequent ion implantation from damaging the N-type substrate 5 and to prevent tunneling in the N-type substrate 5 during the ion implantation process. Then, an ion implantation window is formed by photolithography using photoresist, and phosphorus ions are selectively implanted to form the N-type doped region 2. The energy of the ion implantation is 50-500 KeV. Finally, the photoresist and the oxide layer are removed.

[0051] In another embodiment, steps S2 and S3 may be repeated to perform multiple epitaxial growth and ion implantation on the first P-type epitaxial layer 1 to form multiple layers of the first P-type epitaxial layer 1 and multiple N-type doped regions 2 distributed in the first P-type epitaxial layer 1 .

[0052] S4, growing a lightly doped first N-type epitaxial layer 3 on the first surface of the first P-type epitaxial layer 1 by an epitaxial process, such as Figure 9d shown.

[0053] S5, etching a plurality of grooves distributed at intervals in the first N-type epitaxial layer 3 until penetrating the first N-type epitaxial layer 3, wherein the plurality of grooves in the transition region and the terminal region are located between two adjacent N-type doped regions 2, such as Fig.9e shown.

[0054] Specifically, a thick oxide layer is deposited on the first N-type epitaxial layer 3 as a hard mask for photolithography, a deep trench is etched through photolithography and etching processes, and the hard mask is removed.

[0055] In another embodiment, the deep trench may also extend into the first P-type epitaxial layer 1 , and the depth of the deep trench extending into the first P-type epitaxial layer 1 is less than or equal to half of the thickness of the first P-type epitaxial layer 1 .

[0056] S6, filling a second P-type epitaxial layer 4 in a plurality of trenches, wherein the second P-type epitaxial layer 4 in the active region contacts the N-type doping region 2, and the second P-type epitaxial layer 4 in the transition region and the terminal region contacts the first P-type epitaxial layer 1, as shown in FIG. Figure 9f shown.

[0057] Specifically, first, a sacrificial oxide layer is formed inside the deep trench, and then the oxide layer inside the deep trench is completely removed with acid, thereby removing the etching damage. Then, the second P-type epitaxial layer 4 is filled with a reduced pressure epitaxial process, so that the second P-type epitaxial layer 4 in the active area contacts the N-type doped area 2, and the second P-type epitaxial layer 4 in the transition area and the terminal area contacts the first P-type epitaxial layer 1.

[0058] S7, ion implantation is performed on the first N-type epitaxial layer 3 to form a P-type body region 7 extending into the first N-type epitaxial layer 3, wherein the P-type body regions 7 in the active region correspond to the second P-type epitaxial layers 4 one by one and contact each other, and the P-type body regions 7 in the transition region form an integral region and contact the second P-type epitaxial layers 4, such as Figure 9g shown.

[0059] Specifically, an oxide layer is deposited on the first N-type epitaxial layer 3, an ion implantation window is formed by photolithography, boron ions are selectively implanted to form the P-type body region 7, the energy of the ion implantation is 80-350 KeV, and then the oxide layer is removed.

[0060] S8, forming an oxide layer 8 on the surface of the first N-type epitaxial layer 3 in the terminal region, the surfaces of the second P-type epitaxial layers 4, and a portion of the surface of the P-type body region 7 in the transition region, such as Figure 9h shown.

[0061] Specifically, a thick oxide layer is grown on the surface of the epitaxial wafer, and the active area is etched out through photolithography and etching processes to obtain an oxide layer 8 that covers the surface of the first N-type epitaxial layer 3 in the terminal area, the surfaces of several second P-type epitaxial layers 4, and one end of which extends to a portion of the surface of the P-type body region 7 in the transition area.

[0062] S9, a plurality of first gate oxide layers 91 and second gate oxide layers 92 are formed on the surface of the first N-type epitaxial layer 3, wherein the end of each first gate oxide layer 91 spans two adjacent P-type body regions 7, and the second gate oxide layer 92 is located at the end of the oxide layer 8, such as Figure 9i shown.

[0063] Specifically, an oxide layer is deposited on the first N-type epitaxial layer 3, and a plurality of first gate oxide layers 91 and second gate oxide layers 92 are simultaneously formed by a furnace thermal oxidation process.

[0064] S10, prepare a first gate 101 on the surface of each first gate oxide layer 91, prepare a second gate 102 on the surface of the oxide layer 8, and prepare a third gate 103 extending to the surface of the oxide layer 8 on the surface of the second gate oxide layer 92, such as Figure 9j shown.

[0065] Specifically, polysilicon is grown on the surface of the epitaxial wafer by low pressure chemical vapor deposition, and then the first gate 101, the second gate 102 and the third gate 103 are simultaneously formed by photolithography and etching processes.

[0066] S11, ion implantation is performed in the P-type body region 7 of the active region to form a plurality of first N-type source regions 111, each of the first N-type source regions 111 is in contact with the end of each first gate oxide layer 91, and ion implantation is performed in the first N-type epitaxial layer 3 under the second gate oxide layer 92 to form a second N-type source region 112, such as Figure 9k shown.

[0067] Specifically, an ion implantation window is formed on the first N-type epitaxial layer 3 by a photolithography process, and arsenic ions are selectively implanted into the P-type body region 7 of the active region and the first N-type epitaxial layer 3 under the second gate oxide layer 92. The energy of the ion implantation is 40-150 KeV, and a plurality of heavily doped first N-type source regions 111 and second N-type source regions 112 are simultaneously formed.

[0068] S12, depositing an interlayer insulating dielectric 12 on the surfaces of the P-type body region 7, the oxide layer 8, the second gate oxide layer 92, the first gate 101, the second gate 102, the third gate 103 and the first N-type source region 111, such as Figure 9l shown.

[0069] Specifically, the interlayer insulating dielectric 12 is formed on the surface of the epitaxial wafer by chemical vapor deposition.

[0070] S13, forming a plurality of through holes in the interlayer insulating medium 12, and filling the through holes with metal to form a plurality of through hole metals 13, such as Figure 9m shown.

[0071] Specifically, through holes are formed in the interlayer insulating medium 12 by photolithography and etching processes, and metal aluminum or metal tungsten is filled in the through holes to form a plurality of through-hole metals 13 .

[0072] S14, prepare a first source metal 141, a second source metal 142 and a third source metal 143 on the interlayer insulating dielectric 12, and prepare a drain metal 15 on the lower surface of the N-type substrate 5. The first source metal 141 is connected to the first N-type source region 111 and the P-type body region 7 of the transition region through the through-hole metal 13, the second source metal 142 is connected to the second gate 102 through the through-hole metal 13, the third source metal 143 is connected to the third gate 103 through the through-hole metal 13, and is connected to the second N-type source region 112 and the first N-type epitaxial layer 3 through the through-hole metal 13, as shown in FIG. Figure 9n shown.

[0073] In this embodiment, the P-type columns in the transition zone and the terminal zone are formed by a first P-type epitaxial layer grown in a planar manner and a second P-type epitaxial layer filled with a deep trench technology. The P-type columns grown in a planar manner are doped uniformly and the concentration control is relatively precise. The active area forms an N-type doped region by ion implantation, and the concentration of the N-type doped region can be adjusted as needed, which is beneficial to the device performance regulation.

[0074] This embodiment combines at least one epitaxial implantation and deep trench technology to make the P-type columns in the transition area and the terminal area deeper, solving the problem that the withstand voltage of the terminal area and the transition area is lower than that of the active area, improving the process window and reducing the cost.

[0075] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A super junction device terminal structure, characterized in that: include: At least one first P-type epitaxial layer (1), a plurality of N-type doped regions (2), a first N-type epitaxial layer (3) and a plurality of second P-type epitaxial layers (4), wherein: The at least one first P-type epitaxial layer (1) and the first N-type epitaxial layer (3) are stacked in sequence from bottom to top; The plurality of N-type doping regions (2) extend from the first surface to the second surface of each of the first P-type epitaxial layers (1); the N-type doping regions (2) located in the active region form an integral region; the plurality of N-type doping regions (2) located in the transition region and the terminal region are distributed at intervals, and the N-type doping regions (2) in two adjacent first P-type epitaxial layers (1) are in contact with each other; The plurality of second P-type epitaxial layers (4) are spaced apart and distributed inside the first N-type epitaxial layer (3); the plurality of second P-type epitaxial layers (4) in the active region are in contact with the N-type doped region (2); and the second P-type epitaxial layers (4) in the transition region and the terminal region are located between two adjacent N-type doped regions (2) and in contact with the first P-type epitaxial layer (1).

2. The super junction device terminal structure according to claim 1, characterized in that: In the transition region and the terminal region, a boundary line between the first P-type epitaxial layer (1) and the N-type doped region (2) is a curve.

3. The super junction device terminal structure according to claim 2, characterized in that: Along the direction from the first surface to the second surface of the first P-type epitaxial layer (1), the width of the N-type doping region (2) first gradually increases and then gradually decreases.

4. The super junction device terminal structure according to claim 1, characterized in that: The depth of the second P-type epitaxial layer (4) is greater than or equal to the thickness of the first N-type epitaxial layer (3), and when the depth of the second P-type epitaxial layer (4) is greater than the thickness of the first N-type epitaxial layer (3), the depth to which the second P-type epitaxial layer (4) extends into the top layer, the first P-type epitaxial layer (1), is less than or equal to half the thickness of the top layer, the first P-type epitaxial layer (1).

5. The super junction device terminal structure according to claim 1, characterized in that: The total thickness of the at least one first P-type epitaxial layer (1) is 3-10 μm, and the doping concentration of the first P-type epitaxial layer (1) is 5e15-2e16 cm -3 ; In the transition region and the terminal region, the total thickness of the contacting N-type doping region (2) is 3-10 μm; the doping concentration of the N-type doping region (2) is 5e15-2e16 cm -3 ; The doping concentration of the first N-type epitaxial layer (3) is 5e15-2e16cm -3 ; The width of the second P-type epitaxial layer (4) is 3.8-4.5 μm, and the doping concentration is 5e15-2e16 cm -3 .

6. The super junction device terminal structure according to claim 1, characterized in that: Also includes: N-type A substrate (5), a second N-type epitaxial layer (6), a plurality of P-type body regions (7), an oxide layer (8), a plurality of first gate oxide layers (91), a plurality of first gate electrodes (101), a second gate electrode (102), a plurality of first N-type source regions (111), an interlayer insulating medium (12), a plurality of through-hole metals (13), a first source metal (141), a second source metal (142) and a drain metal (15), wherein: The second N-type epitaxial layer (6), the N-type substrate (5), and the drain metal (15) are stacked in sequence from top to bottom on the second surface of the first P-type epitaxial layer (1); The plurality of P-type body regions (7) extend from the first surface of the first N-type epitaxial layer (3) to the interior of the first N-type epitaxial layer (3), the plurality of P-type body regions (7) in the active region correspond to the plurality of second P-type epitaxial layers (4) one by one and contact each other, and the P-type body regions (7) in the transition region form an integral region and contact the plurality of second P-type epitaxial layers (4); The plurality of first gate oxide layers (91) are distributed on the surface of the first N-type epitaxial layer (3), and the end of each first gate oxide layer (91) straddles two adjacent P-type body regions (7); the plurality of first gate electrodes (101) are arranged one by one on the surface of the plurality of first gate oxide layers (91); the plurality of first N-type source regions (111) are distributed in the plurality of P-type body regions (7) of the active region, and each first N-type source region (111) is in contact with the end of each first gate oxide layer (9); The oxide layer (8) covers the surface of the first N-type epitaxial layer (3) and the surfaces of the plurality of second P-type epitaxial layers (4) in the terminal region, and one end extends to a portion of the surface of the P-type body region (7) in the transition region; the second gate (102) is located on the surface of the oxide layer (8); The interlayer insulating medium (12) covers the P-type body region (7), the oxide layer (8), the first gate (101), the second gate (102) and the first N-type source region (111); The plurality of through-hole metals (13) penetrate the interlayer insulating medium (12); The first source metal (141) is connected to the first N-type source region (111) and the P-type body region (7) of the transition region through the through-hole metal (13); and the second source metal (142) is connected to the second gate (102) through the through-hole metal (13).

7. The super junction device terminal structure according to claim 6, characterized in that: Also includes: Second grid An oxide layer (92), a third gate (103), a second N-type source region (112) and a third source metal (143), wherein: The second gate oxide layer (92) is located on the surface of the first N-type epitaxial layer (3) and is in contact with the other end of the oxide layer (8); the third gate electrode (103) is located on the first surface of the second gate oxide layer (92) and extends to the surface of the oxide layer (8); the second N-type source region (112) is located in the first N-type epitaxial layer (3) and is in contact with the second surface of the second gate oxide layer (92); the third source metal (143) is connected to the third gate electrode (103) through the through-hole metal (13), and is connected to the second N-type source region (112) and the first N-type epitaxial layer (3) through the through-hole metal (13).

8. A method for preparing a super junction device terminal structure, characterized in that: Includes steps: Growing a first P-type epitaxial layer (1); Ion implantation is performed in the first P-type epitaxial layer (1) to form a plurality of N-type doped regions (2) penetrating the first P-type epitaxial layer (1), wherein the N-type doped regions (2) located in the active region form an integral region, and the plurality of N-type doped regions (2) located in the transition region and the terminal region are distributed at intervals; Growing a first N-type epitaxial layer (3) on a first surface of the first P-type epitaxial layer (1); Etching a plurality of grooves distributed at intervals in the first N-type epitaxial layer (3) until the first N-type epitaxial layer (3) is penetrated, wherein the plurality of grooves in the transition region and the terminal region are located between two adjacent N-type doped regions (2); A second P-type epitaxial layer (4) is filled in the plurality of trenches, wherein the second P-type epitaxial layer (4) in the active region is in contact with the N-type doped region (2), and the second P-type epitaxial layer (4) in the transition region and the terminal region is in contact with the first P-type epitaxial layer (1).

9. The method for preparing a super junction device terminal structure according to claim 8, characterized in that: Before growing the first P-type epitaxial layer (1), the method further comprises: A second N-type epitaxial layer (6) is grown on an N-type substrate (5), and the first P-type epitaxial layer (1) is located on the second N-type epitaxial layer (6).

10. The method for preparing a super junction device terminal structure according to claim 9, characterized in that: After the second P-type epitaxial layer (4) is filled in the plurality of trenches, the method further comprises: Ion implantation is performed on the first N-type epitaxial layer (3) to form a P-type body region (7) extending into the first N-type epitaxial layer (3), wherein the plurality of P-type body regions (7) in the active region correspond to and contact the plurality of second P-type epitaxial layers (4) one by one, and the P-type body regions (7) in the transition region form an integral region and contact the plurality of second P-type epitaxial layers (4); An oxide layer (8) is prepared on the surface of the first N-type epitaxial layer (3) in the terminal region, the surfaces of a plurality of second P-type epitaxial layers (4), and a portion of the surface of the P-type body region (7) in the transition region; A plurality of first gate oxide layers (91) and second gate oxide layers (92) are prepared on the surface of the first N-type epitaxial layer (3), wherein the end of each first gate oxide layer (91) bridges two adjacent P-type body regions (7), and the second gate oxide layer (92) is in contact with the end of an oxide layer (8); A first gate electrode (101) is prepared on the surface of each of the first gate oxide layers (91), a second gate electrode (102) is prepared on the surface of the oxide layer (8), and a third gate electrode (103) extending to the surface of the oxide layer (8) is prepared on the surface of the second gate oxide layer (92); Ion implantation is performed in the P-type body region (7) of the active region to form a plurality of first N-type source regions (111), each first N-type source region (111) is in contact with the end of each first gate oxide layer (91), and ion implantation is performed in the first N-type epitaxial layer (3) under the second gate oxide layer (92) to form a second N-type source region (112); Depositing an interlayer insulating dielectric (12) on the surfaces of the P-type body region (7), the oxide layer (8), the second gate oxide layer (92), the first gate (101), the second gate (102), the third gate (103) and the first N-type source region (111); Forming a plurality of through holes in the interlayer insulating medium (12), and filling the through holes with metal to form a plurality of through hole metals (13); A first source metal (141), a second source metal (142) and a third source metal (143) are prepared on the interlayer insulating medium (12), wherein the first source metal (141) is connected to the first N-type source region (111) and the P-type body region (7) of the transition region through the through-hole metal (13), the second source metal (142) is connected to the second gate (102) through the through-hole metal (13), the third source metal (143) is connected to the third gate (103) through the through-hole metal (13), and is connected to the second N-type source region (112) and the first N-type epitaxial layer (3) through the through-hole metal (13); A drain metal (15) is prepared on the lower surface of the N-type substrate (5).

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