AI accelerator card based on FPGA

Abstract

The invention provides an AI accelerator card based on an FPGA, and belongs to the technical field of FPGA and AI computing. According to the technical scheme, the system comprises a data processing module which adopts an FPGA chip VU47P and an HBM on a 16GB chip and provides a bandwidth of at least 460GB / s; the control module adopts an ESP32-H2 chip to realize an IPMI protocol and BMC (Baseboard Management Controller) control; the power supply voltage stabilizing module is used for carrying out voltage reduction processing on 12V input and generating required voltage; and the clock module comprises an OSC clock and a PLL chip, and provides a reference clock of the FPGA and a Kernel standby clock. By adopting the FPGA chip VU47P and combining the HBM2 high-speed cache in the chip, the scheme can provide the bandwidth as high as 460GB / s, and the requirement of high-performance AI calculation is met. And meanwhile, the typical power consumption is only 80W, so that the combination of high performance and low power consumption is realized.

Description

Technical Field

[0001] The present invention relates to an AI acceleration card based on FPGA, and belongs to the technical field of FPGA and AI computing. Background Art

[0002] With the rapid development of artificial intelligence (AI) technology, the popularity of AI computing continues to rise. In this context, how to improve computing efficiency and promote the further development of AI technology has become an important research direction. As a key component to improve computing efficiency, accelerator cards are widely used in various artificial intelligence applications due to their high performance and high concurrency to shorten model training time and handle large-scale computing tasks.

[0003] Currently, AI accelerator cards on the market are mainly divided into three categories: GPU, FPGA and ASIC. ASIC chips are specially designed chips with high specificity and relatively high cost, which limits their flexibility and economy in some application scenarios. GPUs are favored for their powerful parallel processing capabilities, but they are relatively expensive, and the market is basically dominated by a few companies such as NVIDIA. In contrast, FPGA-type accelerator cards have become a competitive choice with their relatively low cost and high flexibility.

[0004] FPGA (Field Programmable Gate Array) has the dual advantages of programmability and high-performance computing capabilities, and can be flexibly configured according to different application requirements to achieve customized acceleration solutions. FPGA-based AI acceleration cards can use these features of FPGA to provide efficient and flexible computing acceleration capabilities to meet the needs of various AI application scenarios.

[0005] However, in the current AI accelerator card market, there is a relative lack of AI accelerator card design solutions for FPGAs, which to some extent limits the application and development of FPGAs in the field of AI computing. Therefore, developing an FPGA-based AI accelerator card hardware design solution can not only enrich the market options for AI accelerator cards, but also promote the widespread application and further development of FPGAs in the field of AI computing. Summary of the invention

[0006] The purpose of the present invention is to provide an FPGA-based AI acceleration card that meets the requirements of high performance, high bandwidth, low power consumption, and low latency AI computing acceleration scenarios.

[0007] In order to achieve the above object, the present invention is implemented through the following technical solutions: The data processing module uses the FPGA chip VU47P and 16GB on-chip HBM, providing a bandwidth of at least 460GB / s; The control module uses the ESP32-H2 chip to implement IPMI protocol and BMC control; The power supply voltage regulator module steps down the 12V input to generate the required voltage; The clock module, including the OSC clock and PLL chip, provides the FPGA reference clock and the Kernel backup clock.

[0008] Preferably, 2. The FPGA-based AI acceleration card according to claim 1, wherein the data processing module supports: External 3-channel 64-bit data and 8-bit parity DDR4 SDRAM, supporting up to 24GB onboard memory; System interface, supports PCIe Gen4.0, X16 Lane, connected to external server via gold finger; High-speed network, supports two-channel QSFP, compatible with 100GE / 40GE / 4*25GE.

[0009] Preferably, the data processing module also includes an external debugging interface, supporting JTAG or USB interface debugging; supporting one 1Gb QSPI serial NorFlash for Active Serial configuration of FPGA.

[0010] Preferably, the control module is capable of: Collect the Alert alarm signal and PGood signal of the power module; As an I2C MASTER, it controls PLL, EEPROM, QSFP28, and POWER devices.

[0011] Preferably, the control module supports reading the FPGA chip temperature, board temperature and whole board power consumption; supports one onboard 512Kb EEPROM for storing the PN and SN information of the board.

[0012] Preferably, the PLL chip in the clock module adopts Renesas' 8A34004 chip, which outputs 4-channel LVDS, LVPECL, and CML differential clocks.

[0013] Preferably, the power supply voltage stabilization module adopts the form of PCIE slot 12V@75W power supply and external Aux power supply 12V@75W.

[0014] Preferably, the BMC control is managed by the SMBUS system.

[0015] The advantages of the present invention are: by using the FPGA chip VU47P and combining it with the HBM2 cache on the chip, the solution can provide a bandwidth of up to 460GB / s, meeting the needs of high-performance AI computing. At the same time, the typical power consumption is only 80W, achieving a combination of high performance and low power consumption.

[0016] Utilizing FPGA chips and their peripheral configurations, this solution is particularly suitable for AI computing scenarios that require high bandwidth and low latency, such as large-scale data processing and real-time response applications.

[0017] The hardware design scheme of the present invention has simple circuits and is easy to implement and maintain. At the same time, its modular design enables the scheme to flexibly adapt to different customer needs and facilitates transplantation and application on different platforms.

[0018] The control module uses Espressif's ESP32-H2 chip, implements the IPMI protocol and BMC management functions, and can monitor and control various board states in real time, including temperature, power consumption, PN / SN information, etc., improving the reliability and maintainability of the system.

[0019] The system interface supports PCIe Gen4.0 and high-speed network (QSFP), ensuring good compatibility with other devices and future scalability. In addition, it supports JTAG or USB interface debugging, providing developers with convenient debugging tools. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0021] Figure 1 The figure is a schematic diagram of the hardware structure of the FPGA acceleration card of the present invention.

[0022] Figure 2 This is the SMBUS system management diagram of the present invention. DETAILED DESCRIPTION

[0023] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0024] In view of the lack of AI acceleration card design solutions in the field of FPGA acceleration card design, the present invention proposes an FPGA-based AI acceleration card, including a data processing module, a control module, a power supply voltage stabilization module, and a clock module.

[0025] (1) Data processing module: This embodiment uses the FPGA chip VU47P as the core processing unit. The chip integrates 16GB of on-chip HBM (high bandwidth memory), which can provide up to 460GB / s of bandwidth to meet the needs of high-performance computing. In addition, the data processing module also supports external 3-channel 64-bit data and 8-bit check DDR4 SDRAM, and supports up to 24GB of onboard memory, further enhancing data processing capabilities.

[0026] In terms of system interface, the module supports PCIe Gen4.0 and is connected to an external server through the X16 Lane gold finger to achieve high-speed data transmission. At the same time, it supports two-channel QSFP interface and is compatible with 100GE / 40GE / 4*25GE high-speed networks, meeting the needs of large-scale data transmission and remote access. The external debugging interface supports JTAG or USB interface debugging, which is convenient for developers to debug and troubleshoot boards.

[0027] To support FPGA configuration and program loading, the data processing module also integrates a 1Gb QSPI serial NorFlash, through which users can load configuration data into the FPGA.

[0028] (2) Control module: The control module uses Espressif's ESP32-H2 chip as a microcontroller, which is responsible for the intelligent management of the entire accelerator board. The module implements the IPMI protocol and can perform BMC (baseboard management controller) control, including monitoring the board status, controlling the LED status on the baffle side, etc. At the same time, the ESP32-H2 chip, as an I2C MASTER, can control devices such as PLL, EEPROM, QSFP28, POWER, etc., to achieve coordinated work of various components inside the board.

[0029] The ESP32-H2 chip also has the function of reading the FPGA chip temperature, board temperature and the power consumption of the entire board, providing important data support for system monitoring and optimization. In addition, the control module also integrates a 512Kb EEPROM to store the board's PN (product number) and SN (serial number) information for easy device management and tracking.

[0030] (3) Power supply voltage regulator module: The power supply voltage regulator module is responsible for stepping down the input 12V voltage to generate various voltages required by chips such as FPGA, DDR, MCU, etc. This embodiment adopts the form of PCIE slot 12V@75W power supply and external Aux power supply 12V@75W to ensure that the board can be stably powered when running under high load.

[0031] During the voltage conversion process, it is first protected by the hot-swap isolation module MP5023, and then processed by the step-down module MPQ8633 and MSN12AD60 and other devices to generate a voltage value that meets the requirements of each chip. This design not only ensures the reliability of power supply, but also improves the safety of the system.

[0032] (4) Clock module: The clock module includes an OSC clock and a PLL chip. The OSC clock provides two clock sources: single-ended and differential. The single-ended 100MHz crystal oscillator is used as the reference clock of the FPGA, and the differential 100MHz crystal oscillator is used as the kernel backup clock of the FPGA. The PLL chip uses the Renesas 8A34004 chip, which has low jitter performance (150fs RMS) and can output 4 LVDS, LVPECL, and CML differential clocks.

[0033] In this embodiment, the 300MHz clock output by the 8A34004 PLL is used as the reference clock of the DDR, and the 322.265625MHz output is used as the reference clock of the optical module. This clock configuration scheme not only ensures the synchronization and stability of data transmission, but also improves the overall performance of the system.

[0034] As a refinement of the above embodiment, BMC control is implemented through BMC management, which adopts SMBUS system management as follows Figure 2 As shown. PCIe SMBUS connects FPGA and MCU. Both FPGA and MCU are I2C slave devices. The addresses can be customized as long as there is no conflict. In addition, MCU is the master device and connects to each I2C_SLAVE to read information such as board temperature, power consumption, board PN, SN, etc. I2C_SLAVE includes hot-swappable isolation module MP5023, optical module, temperature sensor SHTC3, power module, EPPROM and PLL module.

[0035] As a refinement of the above embodiment, the power supply adopts PCIE slot 12V@75W power supply + external Aux power supply 12V@75W. After entering, 12V first passes through the hot-swap isolation module MP5023, and then is processed by the step-down module MPQ8633 and MSN12AD60 to generate various voltages required by the chip.

[0036] It should be noted that the FPGA-based AI acceleration card hardware design of the present invention shows significant advantages in terms of cost, performance, power consumption, latency, design simplicity, system management, scalability and compatibility, which can meet the diverse needs of different customers and promote the further development of AI technology.

[0037] In summary, the embodiments of the present invention achieve a high-performance, low-cost FPGA-based AI acceleration card hardware design solution by optimizing the design of the data processing module, control module, power supply voltage regulator module and clock module. This solution has the advantages of strong flexibility, easy expansion and transplantation, and can meet the needs of different customers.

[0038] Finally, it should be noted that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art can still modify the technical solutions described in the aforementioned embodiments or replace some of the technical features therein by equivalents. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. An FPGA-based AI accelerator card, characterized in that: include: The data processing module uses the FPGA chip VU47P and 16GB on-chip HBM, providing a bandwidth of at least 460GB / s; The control module uses the ESP32-H2 chip to implement IPMI protocol and BMC control; The power supply voltage regulator module steps down the 12V input to generate the required voltage; The clock module, including the OSC clock and PLL chip, provides the FPGA reference clock and the Kernel backup clock.

2. The FPGA-based AI acceleration card according to claim 1, characterized in that: Data processing module supports: External 3-channel 64-bit data and 8-bit parity DDR4 SDRAM, supporting up to 24GB onboard memory; System interface, supports PCIe Gen4.0, X16 Lane, connected to external server via gold finger; High-speed network, supports two-channel QSFP, compatible with 100GE / 40GE / 4*25GE.

3. The FPGA-based AI acceleration card as claimed in claim 2, characterized in that: The data processing module also includes an external debugging interface that supports JTAG or USB interface debugging; it supports one 1Gb QSPI serial NorFlash for ActiveSerial configuration of the FPGA.

4. The FPGA-based AI acceleration card according to claim 1, characterized in that: The control module can: Collect the Alert alarm signal and PGood signal of the power module; As an I2C MASTER, it controls PLL, EEPROM, QSFP28, and POWER devices.

5. The FPGA-based AI acceleration card as claimed in claim 4, characterized in that: The control module supports reading FPGA chip temperature, board temperature and whole board power consumption; supports 1 onboard 512Kb EEPROM for storing the PN and SN information of the board.

6. The FPGA-based AI acceleration card according to claim 1, characterized in that: The PLL chip in the clock module uses Renesas' 8A34004 chip, which outputs 4 LVDS, LVPECL, and CML differential clocks.

7. The FPGA-based AI acceleration card according to claim 1, characterized in that: The power supply voltage regulator module adopts the form of PCIE slot 12V@75W power supply and external Aux power supply 12V@75W.

8. The FPGA-based AI acceleration card according to claim 1, characterized in that: BMC control is managed by SMBUS system.

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