Target architecture extension instruction-oriented node merging, compiling and optimizing system and method

Abstract

The invention belongs to the technical field of compiler optimization, and discloses a node merging, compiling and optimizing system and method for a target architecture extension instruction, and the system comprises a node checking module, a node merging module, an instruction selection module and an error processing module; according to the instruction selection optimization method, operation nodes such as addition and displacement can be effectively recognized and combined, and the operation nodes are converted into the user-defined extension instruction nodes and finally mapped into the target machine instruction. By optimizing the node merging process in the Selection DAG, the number of generated instructions can be reduced, the execution performance of a program can be improved, and particularly for a SumerCore processor architecture depending on a user-defined instruction set, the hardware utilization efficiency can be remarkably improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of compiler optimization, and in particular relates to a node merging compilation optimization system and method for target architecture extension instructions. Background Art

[0002] With the development of modern computer architecture, the improvement of processor performance no longer depends solely on hardware improvements, and the role of compilers in optimizing code generation has become increasingly important. Compilers need to efficiently convert high-level language code into the instruction set of the target machine to make full use of hardware resources. A key step in the code generation process is instruction selection, which is mapping the intermediate representation (IR) to the specific instruction set of the target machine. In this process, modern compilers such as LLVM use a structure based on selection DAG (Selection Directed Acyclic Graph, Selection DAG) to optimize code generation. Selection DAG represents operands and instructions in the form of nodes, which provides the basis for compilers to optimize code generation. In this structure, the connection relationship between nodes describes the dependency of instructions, and the compiler can optimize the final generated machine code by reordering and merging the operations of these nodes.

[0003] However, as modern processors introduce more and more custom extended instructions (such as hardware instructions for accelerating specific calculations), the traditional instruction selection mechanism faces new challenges. Compilers usually generate multiple independent general instructions when processing complex operations (such as a combination of addition and shift). For some architectures with extended instructions for fast implementation of complex operations, this redundant instruction generation method leads to an increase in the number of instructions, which not only increases the execution time of the program, but also occupies more processor resources and memory bandwidth, thus affecting the overall performance of the program.

[0004] As the industry's leading compiler infrastructure, the LLVM compilation framework's instruction selector is mainly based on the SelectionDAG structure. LLVM divides instruction selection into multiple stages, including the Legalize and Combine stages. In the Legalize stage, SelectionDAG converts instructions or types that are not supported by the target machine to meet the instruction set requirements of the target processor. In the Combine stage, the compiler detects node dependencies in the DAG and tries to combine nodes that can be merged, thereby reducing the number of instructions and optimizing the generated code. For the SummerCore digital signal processor of the RISC-V architecture, the processor introduces custom extended instructions sadd and ssub. These two instructions can combine addition or subtraction and shift operations into a single instruction, and the instruction overhead is consistent with a single addition, subtraction or shift, so they can effectively reduce the number of instructions and improve program performance. However, the existing LLVM instruction selector cannot automatically identify and process these custom extended instructions, resulting in the inability to fully utilize the processor's expansion capabilities. This phenomenon is also common in other processor architectures that use custom instruction set extensions.

[0005] Therefore, the existing compiler optimization technology has the following problems: when facing a custom instruction set, the instruction selector lacks an effective node merging mechanism, resulting in a large number of instructions generated by compilation and low execution efficiency, making it difficult to maximize the potential of the processor hardware. Therefore, how to optimize the merging of nodes in the instruction selection stage, especially the support for specific extended instructions, has become an urgent problem to be solved. Summary of the invention

[0006] In order to solve the above technical problems, the present invention provides a node merging compilation optimization system and method for target architecture extension instructions, so as to reduce the number of generated instructions and improve the execution performance of the program.

[0007] To achieve the above object, the technical solution of the present invention is as follows:

[0008] A node merging compilation optimization system for target architecture extension instructions, comprising a node checking module, a node merging module, an instruction selection module and an error handling module;

[0009] The node checking module is responsible for checking the ADD / SUB nodes and the types of their operands, and screening out the nodes that meet the conditions to enter the merging process;

[0010] The node merging module is responsible for merging the qualified ADD / SUB nodes with the shift nodes SRA / SHL. The module checks the shift amount and node usage and generates a custom compound instruction node.

[0011] The instruction selection module is responsible for mapping the compound instruction node to the specific machine instruction sadd / ssub supported by the target processor after the node merging is completed, so as to ensure the optimization effect at the hardware level;

[0012] The error handling module is responsible for detecting and handling potential errors during node checking, node merging and instruction selection. If an illegal operation is detected or the conditions are not met, the error handling module will safely roll back the merge operation to avoid compilation errors and ensure compiler stability.

[0013] In the above scheme, the node checking module includes a data type checking unit, an operand type checking unit, a node usage checking unit, a shift operation checking unit, a shift amount checking unit, and a shift node type checking unit;

[0014] The data type checking unit is used to confirm whether the data type currently being processed is a 32-bit integer;

[0015] The operand type checking unit is used to check whether the ADD node operand is a register type rather than an immediate type;

[0016] The node usage checking unit is used to check whether the result of the ADD node has only one user node;

[0017] The shift operation checking unit is used to check whether the ADD node is a shift operation SRA or SHL;

[0018] The shift amount checking unit is used to check whether the shift amount of the shift operation does not exceed 3;

[0019] The shift node type checking unit is used to determine whether the specific type of the shift node is SRA or SHL.

[0020] A node merging compilation optimization method for target architecture extension instructions adopts the node merging compilation optimization system for target architecture extension instructions as described above, and comprises the following steps:

[0021] (1) When the system input is an ADD node, the node check module will call the performADDCombine function to analyze the operands and usage nodes of the addition node to determine whether there is a merge opportunity. Before merging, the data type check unit confirms whether the currently processed data type is a 32-bit integer through the getValueType() interface. If the data type does not meet the requirements, the error handling module will directly end the merge process.

[0022] (2) The operand type checking unit checks the operand type of the ADD node to ensure that the operand is a register type rather than an immediate type. If the operand type is not satisfied, the error handling module will return directly without proceeding to the subsequent process. Otherwise, it will proceed to the next step.

[0023] (3) The node use check unit checks whether the result of the ADD node has only one user node through the hasOneUse() interface. If the result is used by multiple nodes, the error handling module will end the merging logic, otherwise proceed to the next step;

[0024] (4) After the unique use condition is met, the shift operation check unit obtains the node and checks whether the node is a shift operation SRA or SHL. If it does not belong to these two types of nodes, the merging process ends;

[0025] (5) If the node meets the merging condition, the shift value checking unit will further obtain the shift value ShiftValue of the shift operation and check whether it is within a reasonable range, that is, ShiftValue≤3; if the shift value does not meet the requirement, the error handling module will end the merging process, otherwise proceed to the next step;

[0026] (6) The shift node type check unit determines the specific type of the shift node: If it is SRA, the node merging module directly calls the DAG.getNode() function to create a custom SelectionDAG node SADD. The three input operands of the SADD node are the two input operands of the ADD node and the shift operand of SRA. If it is SHL, the node merging module needs to first add 4 to the ShiftValue and convert it into a constant node type before creating the SADD node.

[0027] (7) After the merge is completed, the node merge module deletes the shifted node through the DCI.CombineTo interface and points all its references to the newly created SADD node; if the original ADD node is accidentally deleted, the error handling module will issue an assertion error and no other processing is required;

[0028] (8) After completing the above merging logic, when it is detected in the node merging stage that the ADD node is followed by a shift node and meets the merging requirements, the node merging module will merge the two nodes into one node;

[0029] (9) The instruction selection module maps the merged nodes to specific instructions of the target architecture through the Select function. When traversing to the SADD node, the system will check the operands again. If the third operand is not a constant, the error handling module will trigger an assertion error. After that, the instruction selection module will establish a machine node bound to the machine instruction sadd. Finally, the machine node will replace the previous SADD node to achieve the final instruction mapping.

[0030] In the above scheme, when the system input is a SUB node, the node merging module directly calls combineSUBShift to create a custom SelectionDAG node SSUB, and the rest are the same as the addition node, and finally realizes the generation of the ssub instruction.

[0031] Through the above technical solution, the node merging compilation optimization system and method for target architecture extension instructions provided by the present invention have the following beneficial effects:

[0032] 1. The number of instructions is significantly reduced, and the execution efficiency is improved. Existing compilers usually generate multiple independent instructions for addition and shift operations, while the present invention automatically identifies and merges addition (or subtraction) and shift nodes, converting them into custom extended instructions sadd and ssub, thereby effectively reducing the number of instructions generated. By reducing redundant instructions, the present invention significantly improves the execution efficiency of the program, especially in the scenario of processing a large number of addition and shift combinations, the performance improvement is particularly obvious.

[0033] 2. Make full use of the extended instructions of the processor to improve the utilization rate of hardware resources. Many modern processors, such as SummerCore digital signal processors, have specific extended instruction sets (such as sadd, ssub), which can complete the functions of multiple general instructions without increasing overhead. However, the traditional LLVM compiler cannot automatically recognize these custom instructions, resulting in the compilation result being unable to make full use of the hardware capabilities of the processor. The present invention can automatically generate and utilize these extended instructions by introducing node merging and instruction selection mechanisms for custom instructions, giving full play to the hardware potential of the processor and improving overall performance.

[0034] 3. The compilation process is more efficient and reduces compilation time. The present invention simplifies the processing logic of the instruction selection stage by introducing automated pattern recognition and instruction merging in the merging stage of SelectionDAG, reduces the complex instruction generation steps and the subsequent optimization process of redundant nodes. Compared with the traditional compilation process, the present invention can merge nodes in advance in the optimization stage, reducing the complexity of subsequent instruction selection and mapping, thereby shortening the compilation time and improving the overall efficiency of the compiler.

[0035] 4. Enhanced compiler stability and robustness. The present invention provides a complete node legalization and error handling mechanism to ensure that when an illegal operation is encountered during instruction merging or selection, it can safely fall back to the original instruction and maintain the normal working process of the compiler. This design improves the robustness of the compiler, avoids unpredictable errors in the process of generating custom instructions, and ensures the correctness and stability of the generated code. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art are briefly introduced below.

[0037] Figure 1 Diagram of the flow of selecting and mapping target architecture machine instructions from LLVM IR to completion instructions in the LLVM backend.

[0038] Figure 2 A schematic diagram of a node merging and compiling optimization system for target architecture extension instructions provided by the present invention;

[0039] Figure 3 Check module composition graph for nodes;

[0040] Figure 4 A flow chart of a node merging and compiling optimization method for target architecture extension instructions provided by the present invention;

[0041] Figure 5 A schematic diagram of the SADD node for merging the ADD and SRA nodes to generate the SummerCore architecture;

[0042] Figure 6 The performance improvement ratio diagram brought by the present invention in some digital signal processing test cases;

[0043] Figure 7 The present invention brings about a reduction in the number of instructions in some digital signal processing test cases. DETAILED DESCRIPTION

[0044] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the accompanying drawings in the embodiments of the present invention.

[0045] The entire LLVM compilation framework is divided into the front-end, middle-end, and back-end. In the front-end, the compiler compiles the high-level language into LLVM IR (Intermediate Representation, IR) that is independent of the target architecture; in the back-end, code generation and optimization for the target architecture are completed. Figure 1As shown in the figure: This figure describes the entire process from the intermediate representation to the final instruction selection in the LLVM compiler. In this process, the system will merge the directed acyclic graph (DAG) nodes multiple times. Each merge includes the merging of nodes that are irrelevant to the target architecture and the merging of nodes that are relevant to the target architecture, as well as the legalization of types and operations. Finally, the mapping of specific machine instructions on the target architecture is implemented through the Select function.

[0046] The sadd and ssub instructions in the present invention are unique extended instructions in the SummerCore architecture, and their overhead is the same as the standard add or srai instructions. Therefore, the present invention chooses to implement the merging logic of these extended instructions in the node merging interface of the target architecture. In the PerformDAGCombine function of the SummerCorep1p0IselLowering.cpp file of the llvm target backend, when traversing each node in the SelectionDAG, the system will check and judge the node according to the predetermined merging conditions. If the node meets the merging conditions, the system will execute the corresponding merging logic.

[0047] The present invention provides a node merging compilation optimization system for target architecture extension instructions, such as Figure 2 As shown, it includes a node checking module, a node merging module, an instruction selection module and an error handling module.

[0048] The node check module is responsible for checking the ADD / SUB nodes and the types of their operands, and screening out qualified nodes to enter the merging process;

[0049] The node merging module is responsible for merging the qualified ADD / SUB nodes with the shift nodes SRA / SHL. The module checks the shift amount and node usage and generates a custom compound instruction node.

[0050] The instruction selection module is responsible for mapping the compound instruction nodes to specific machine instructions sadd / ssub supported by the target processor after the node merging is completed, ensuring the optimization effect at the hardware level;

[0051] The error handling module is responsible for detecting and handling potential errors during node checking, node merging, and instruction selection. If an illegal operation is detected or the conditions are not met, the error handling module will safely roll back the merge operation to avoid compilation errors and ensure compiler stability.

[0052] Specifically, Figure 3As shown, the node checking module includes a data type checking unit, an operand type checking unit, a node usage checking unit, a shift operation checking unit, a shift amount checking unit, and a shift node type checking unit.

[0053] The data type checking unit is used to confirm whether the data type currently being processed is a 32-bit integer;

[0054] The operand type checking unit is used to check whether the operand of the ADD node is a register type rather than an immediate type;

[0055] The node usage check unit is used to check whether the result of the ADD node has only one user node;

[0056] The shift operation checking unit is used to check whether the ADD node is a shift operation SRA or SHL;

[0057] The shift amount checking unit is used to check whether the shift amount of the shift operation does not exceed 3;

[0058] The shift node type checking unit is used to determine whether the specific type of the shift node is SRA or SHL.

[0059] A node merging compilation optimization method for target architecture extension instructions, using a node merging compilation optimization system for target architecture extension instructions as above, such as Figure 4 As shown, the following steps are included:

[0060] (1) When the system input is an ADD node, the node check module calls the performADDCombine function, which is located in the SummerCorep1p0IselLowering.cpp file of the llvm target backend and is specifically used to process the merging logic of the addition node. By calling this function, the node check module analyzes the operands and usage nodes of the addition node and determines whether there is a merging opportunity. The innovation of the present invention is to insert the logic of merging the addition node and the shift node to generate a custom node in the function interface, and implement this logic in the custom function combineADDShift. The implementation of the custom function is also located in the SummerCorep1p0IselLowering.cpp file. Since the target architecture SummerCore only supports 32-bit data types, and the ADD node can only process integer data, before merging, the data type check unit confirms whether the currently processed data type is a 32-bit integer (MVT::i32) through the getValueType() interface. If the data type does not meet the requirements, the error handling module will directly end the merging process and return to the correct position without affecting the normal compilation process, otherwise proceed to the next step.

[0061] (2) Considering that the ADD node may be mapped to two machine instructions, add or addi, and sadd does not support addition of immediate type, the present invention checks the operand type of the ADD node through an operand type checking unit to ensure that the operand is a register type rather than an immediate type; if it is not satisfied, the error handling module will directly return without performing the subsequent process, otherwise it will proceed to the next step;

[0062] (3) The node use check unit checks whether the result of the ADD node has only one user node through the hasOneUse() interface. If the result is used by multiple nodes, the error handling module will end the merging logic, otherwise proceed to the next step;

[0063] (4) After the unique use condition is met, the shift operation check unit will obtain the node and check whether the node is a shift operation SRA or SHL. If it does not belong to these two types of nodes, the merging process will end. It should be noted that for the right shift operation, there are two types of nodes: arithmetic right shift (SRA) and logical right shift (SRL). The sadd instruction regards the input operand as a signed number during calculation, so it can only be merged with the SRA node.

[0064] (5) If the node meets the merging condition, the shift amount checking unit will further obtain the shift amount ShiftValue of the shift operation. Since the sadd machine instruction can only perform a maximum of three-digit left or right shift, it is also necessary to check whether it is within a reasonable range, that is, ShiftValue≤3; if the shift amount does not meet the requirements, the error handling module will end the merging process, otherwise it will proceed to the next step;

[0065] (6) After the previous series of checks are completed, the shift node type check unit determines the specific type of the shift node: if it is SRA, the node merging module directly calls the DAG.getNode() function to create a custom SelectionDAG node SADD. The three input operands of the SADD node are the two input operands of the ADD node and the shift operand of SRA. If it is SHL, the node merging module needs to first add 4 to ShiftValue and convert it to a constant node type before creating the SADD node. The reason is that if sadd performs a left shift operation, the highest bit of the third immediate value uimm3 is used as a flag bit and needs to be marked as 1, while the lower two bits determine the shift size. Therefore, the value of the ShiftValue operand needs to be adjusted before creating the node.

[0066] (7) After the merge is completed, the node merge module deletes the shifted node through the DCI.CombineTo interface and points all its references to the newly created SADD node. If the original ADD node is accidentally deleted, the error handling module will issue an assertion error and no other processing is required. Because the original ADD node will be marked as a "deleted node" in the subsequent process of LLVM, no other processing is required.

[0067] (8) After completing the above merging logic, when it is detected in the node merging stage that the ADD node is followed by a shift node and meets the merging requirements, the node merging module will merge the two nodes into one node, such as Figure 5 As shown;

[0068] (9) However, at this time, the SADD node still belongs to the SelectionDAGNode of a higher abstract level. After completing a series of node merging and type legalization operations, in order to achieve the final machine instruction selection, the instruction selection module maps the merged node to the specific instruction of the target architecture through the Select function. There are two ways to implement this process: one is to manually implement it through C++ code, and the other is to implement it through the Pat template in the .td file. Considering the flexibility of the C++ language, the present invention chooses the former, which is manually implemented in the Select function in the instruction selection module. The implementation of the Select function is located in the SummerCorep1p0DAGToDAG.cpp file. The Select function will traverse the SelectionDAG nodes after a series of optimizations. When traversing to the SADD node, the system will check the operands again. If the third operand is not a constant, the error handling module will trigger an assertion error; then, the instruction selection module will establish a machine node (SummerCorep1p0::SADD) bound to the machine instruction sadd, which is defined in the .td file. Finally, the machine node will replace the previous SADD node to achieve the final instruction mapping.

[0069] In the above scheme, when the system input is a SUB node, the node merging module directly calls combineSUBShift to create a custom SelectionDAG node SSUB, and the rest are the same as the addition node, and finally realizes the generation of the ssub instruction.

[0070] The above are the main steps in the execution process of the present invention. The compiler optimized by the present invention can directly generate sadd and ssub machine instructions of the SummerCore architecture when encountering a specific node, effectively improving the execution efficiency of the processor.

[0071] The following is a specific case and test results to illustrate the performance improvement brought by the present invention in the SummerCore processor: In the actual C / C++ code writing process, division operations such as int c=a / 4 are often encountered. This line of code will be compiled by clang into four assembly instructions for the SummerCore architecture: srai a4,a5,31, andi a4,a4,3, add a5,a4,a5, and srai a5,a5,2. Since the overhead of division operations is usually high in most architectures, compilers often optimize division in specific scenarios. In particular, when the divisor is a power of 2 (such as 2, 4, 8, 16, etc.), the compiler usually replaces the division with a more efficient displacement operation (such as srai) to reduce execution time. At the same time, in order to ensure that the division of signed numbers can be executed correctly, the compiler must process the sign bit. In the SummerCore architecture, the division of signed integers requires the addition of a sign bit compensation operation to ensure that the result is still correct when the operand is a negative number. In some specific processor architectures (such as SummerCore), custom extended instructions sadd and ssub are introduced. The two instructions add a5,a4,a5 and srai a5,a5,2 can be merged into one sadd a5,a4,a5,2. Therefore, in the SummerCore architecture, when clang compiles codes like int c=a / 4;, it can be further optimized to the sadd instruction. The sadd instruction not only performs addition operations, but also handles shift operations at the same time, thereby greatly improving processing efficiency and reducing instruction overhead.

[0072] The present invention improves the performance of SummerCore processors in some digital signal processing benchmarks. Figure 6 and Figure 7As shown. The test case is mainly the calculation of fast Fourier transform. cfft_i32_calc is a fixed-point benchmark for testing discrete complex fast Fourier transform (CFFT). In the field of signal processing, CFFT is widely used to convert signals from time domain to frequency domain. This test specifically evaluates the performance of CFFT operation on 32-bit integer data, and evaluates the processing ability of the processor when performing complex number operations. rfft_i32_calc is a fixed-point benchmark for evaluating real fast Fourier transform (RFFT). Unlike CFFT, RFFT processes real input signals. In many practical applications, such as audio signal processing or vibration analysis, the fast conversion of real signals is crucial to the overall performance of the system. This benchmark evaluates the RFFT operation on 32-bit integers, and tests the speed and efficiency of the processor when performing real FFT. rfft_i32_split is a special step in the real fast Fourier transform (RFFT), which splits the real signal for processing, further improving the efficiency of FFT processing. This benchmark evaluates the processor's processing capabilities during the RFFT decomposition phase, especially its performance when handling transformation operations with higher complexity. Figure 6 and Figure 7 It can be seen that the optimization method provided by the present invention performs well in the face of computationally intensive signal processing tasks, and can provide significant performance improvement and power consumption optimization for SummerCore digital signal processors. Therefore, the use of these extended instructions can be widely used in modern processors, especially in application scenarios that require high-performance computing (such as digital signal processing, audio processing, etc.), to improve hardware resource utilization and reduce computing delays and power consumption.

[0073] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A node merging compilation optimization system for target architecture extension instructions, characterized in that: It includes a node checking module, a node merging module, an instruction selection module and an error handling module; The node checking module is responsible for checking the ADD / SUB nodes and the types of their operands, and screening out the nodes that meet the conditions to enter the merging process; The node merging module is responsible for merging the qualified ADD / SUB nodes with the shift nodes SRA / SHL. The module checks the shift amount and node usage and generates a custom compound instruction node. The instruction selection module is responsible for mapping the compound instruction node to the specific machine instruction sadd / ssub supported by the target processor after the node merging is completed, so as to ensure the optimization effect at the hardware level; The error handling module is responsible for detecting and handling potential errors during node checking, node merging and instruction selection. If an illegal operation is detected or the conditions are not met, the error handling module will safely roll back the merge operation to avoid compilation errors and ensure compiler stability.

2. A node merging and compiling optimization system for target architecture extension instructions according to claim 1, characterized in that: The node checking module includes a data type checking unit, an operand type checking unit, a node usage checking unit, a shift operation checking unit, a shift amount checking unit, and a shift node type checking unit; The data type checking unit is used to confirm whether the data type currently being processed is a 32-bit integer; The operand type checking unit is used to check whether the ADD node operand is a register type rather than an immediate type; The node usage checking unit is used to check whether the result of the ADD node has only one user node; The shift operation checking unit is used to check whether the ADD node is a shift operation SRA or SHL; The shift amount checking unit is used to check whether the shift amount of the shift operation does not exceed 3; The shift node type checking unit is used to determine whether the specific type of the shift node is SRA or SHL.

3. A node merging compilation optimization method for target architecture extension instructions, using a node merging compilation optimization system for target architecture extension instructions as claimed in claim 2, characterized in that: The steps include: (1) When the system input is an ADD node, the node check module will call the performADDCombine function to analyze the operands and usage nodes of the addition node to determine whether there is a merge opportunity. Before merging, the data type check unit confirms whether the currently processed data type is a 32-bit integer through the getValueType() interface. If the data type does not meet the requirements, the error handling module will directly end the merge process. (2) The operand type checking unit checks the operand type of the ADD node to ensure that the operand is of register type rather than immediate type; If not, the error handling module will return directly without proceeding to the next step; otherwise, it will proceed to the next step; (3) The node use check unit checks whether the result of the ADD node has only one user node through the hasOneUse() interface. If the result is used by multiple nodes, the error handling module will end the merging logic, otherwise proceed to the next step; (4) After the unique use condition is met, the shift operation check unit obtains the node and checks whether the node is a shift operation SRA or SHL. If it does not belong to these two types of nodes, the merging process ends; (5) If the node meets the merging condition, the shift value checking unit will further obtain the shift value ShiftValue of the shift operation and check whether it is within a reasonable range, that is, ShiftValue≤3; if the shift value does not meet the requirement, the error handling module will end the merging process, otherwise proceed to the next step; (6) The shift node type check unit determines the specific type of the shift node: If it is SRA, the node merging module directly calls the DAG.getNode() function to create a custom SelectionDAG node SADD. The three input operands of the SADD node are the two input operands of the ADD node and the shift operand of SRA. If it is SHL, the node merging module needs to first add 4 to the ShiftValue and convert it into a constant node type before creating the SADD node. (7) After the merge is completed, the node merge module deletes the shifted node through the DCI.CombineTo interface and points all its references to the newly created SADD node; If the original ADD node is accidentally deleted, the error handling module will issue an assertion error and no other processing is required; (8) After completing the above merging logic, when it is detected in the node merging stage that the ADD node is followed by a shift node and meets the merging requirements, the node merging module will merge the two nodes into one node; (9) The instruction selection module maps the merged nodes to specific instructions of the target architecture through the Select function. When traversing to the SADD node, the system will check the operands again. If the third operand is not a constant, the error handling module will trigger an assertion error. After that, the instruction selection module will establish a machine node bound to the machine instruction sadd. Finally, the machine node will replace the previous SADD node to achieve the final instruction mapping.

4. The node merging and compiling optimization method for target architecture extension instructions according to claim 3, characterized in that: When the system input is a SUB node, the node merging module directly calls combineSUBShift to create a custom SelectionDAG node SSUB, and the rest are the same as the addition node, finally realizing the generation of the ssub instruction.

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