Flash memory read error correction method, solid-state storage device, and firmware program product

Abstract

A flash memory read error correction method, a solid-state storage device, and a firmware program product, which can realize error correction based on a reread action while realizing data compression. The flash memory read error correction method includes: correcting the user data read from the flash memory unit based on the default read voltage through an ECC circuit; and rereading the flash memory unit based on a pre-stored reread voltage code when the number of error bits of the user data exceeds a specified number of bits, so that the number of error bits of the user data reaches less than the specified number of bits, and the specified number of bits is the number of bits that the ECC circuit can correct errors. The reread voltage code is composed of a sign field and an offset field, and a reread voltage is formed according to the sign field and the offset field of the reread voltage code, and the reread voltage is applied to the flash memory unit to perform the rereading.

Description

Technical Field

[0001] The present application relates to the field of flash memory and solid-state storage, and in particular to a flash memory read error correction method, a solid-state storage device, and a firmware program product. Background Art

[0002] At present, solid-state storage devices (commonly known as "solid-state drives", or SSDs) have replaced traditional mechanical hard disks (or HDDs) to become the most mainstream storage devices due to their advantages such as good performance, low power consumption, shock and drop resistance, low noise, and small size. Unlike traditional mechanical hard disks that use a mechanical structure of "head + motor + disk", solid-state drives use a semiconductor storage chip structure of "flash memory media + master control". As its storage medium, flash memory is a non-volatile memory. Even if power is lost, the data stored in the flash memory will not be lost. Taking NAND flash memory as an example, an example of a basic storage unit (cell) of NAND flash memory is a floating gate transistor similar to NMOS. A floating gate for storing electrons is formed on a semiconductor where current is unidirectionally conducted between the source and the drain. The floating gate uses a conductive material and is surrounded by an insulating layer above and below. The electrons stored in the floating gate will not disappear due to power failure. Regarding the storage information, for example, the state where there are no electrons in the floating gate can be set to "1", and the state where a certain amount of electrons are stored can be set to "0". This kind of flash memory that stores 1 bit of data in one storage unit is called SLC (Single Level Cell). On the other hand, in order to further increase the popularity of flash memory as a storage medium for SSDs, high-density storage and low bit cost have always been the development direction of flash memory technology. One way to increase the density of flash memory is the logical method, that is, to allow a storage unit to store more bits of data. At present, in the process of using the logical method to increase storage density, MLC, TLC, and QLC types of flash memory have appeared on the basis of SLC. Among them, a flash memory that stores 2 bits of data in one storage unit is called MLC (Multiple Level Cell), a flash memory that stores 3 bits of data in one storage unit is called TLC (Triple Level Cell), and a flash memory that stores 4 bits of data in one storage unit is called QLC (Quad Level Cell), and so on. For any of the above types of flash memory, a storage unit of the flash memory is divided into multiple states according to the number of injected electrons, so as to achieve the purpose of storing a specific number of bits of data. Taking MLC as an example, assuming that a storage unit can inject up to 100 electrons, then 0~5 electrons, 20~40 electrons, 50~70 electrons, and 80~100 electrons injected represent 4 states respectively, and each state is encoded with 2 bits. Thus, the MLC can store data in four states, namely, "00", "01", "10" and "11".Figure 1 The figure shows the threshold voltage distribution diagram of MLC flash memory. From the perspective of flash memory organization, the low-order data and high-order data of 2-bit data are stored in different flash memory pages, and these two flash memory pages share a word line (Write Line). When reading low-order data, only a voltage (usually also called reference voltage) V is applied to the control electrode. A That is, when reading high-bit data, a voltage V needs to be applied to the control electrode. B and V C .observe Figure 1 It can be seen that each reference voltage is located between two adjacent threshold voltage distributions, and a certain width of spacing is formed between the two adjacent threshold voltage distributions. The width of the spacing represents the level of fault tolerance of the flash memory. Specifically, the wider the spacing, the more accidental loss or injection of electrons is allowed, and the better the fault tolerance of the flash memory.

[0003] However, as the flash memory is used continuously, the number of erase and write cycles (PEC) of the memory cell increases, and the degree of wear increases, which can cause a portion or all of the threshold voltage distribution in the threshold voltage distribution diagram to shift. In addition, during the use of the flash memory, as the number of times the flash memory block is read increases, more and more electrons may enter the floating gate transistor, which can also cause the threshold voltage distribution to shift (that is, read interference can also cause the threshold voltage distribution to shift). As a result, in Figure 1 In the figure, the threshold voltage distribution shifts from the original state shown in the implementation to the state shown in the dotted line. At this time, the reference voltage may partially overlap with a certain threshold voltage distribution, which may cause data reading errors. In addition, even if the flash memory is not used for a long time, the electrons stored in the floating gate will escape through the insulating layer under the action of the intrinsic electric field over time. In other words, data retention problems can also cause the threshold voltage distribution to shift.

[0004] In order to avoid the above situation, some measures need to be taken on the SSD software and hardware at the system level to solve the data unreliability problem of flash memory to ensure the reliability of user data. Generally speaking, the controller of the flash memory will first use the ECC (Error Correction Code) error correction engine to correct the error bits of the flash memory data. Specifically, before writing the user data A to the flash memory, it is first ECC-encoded, and the generated check data A is connected to the user data and written to the flash memory together. Then, after the data is stored in the flash memory, the data is bit-flipped due to factors such as read interference or data retention, so that the user data A becomes user data B. In this case, when the data is read, the user data B and the check data B pass through the ECC error correction engine. If the number of bits where the data is flipped does not exceed the error correction capability of ECC, the data obtained after ECC error correction is the original user data A. If the number of data error bits exceeds the error correction capability of ECC, the decoding will fail. Therefore, in the case where the number of data error bits exceeds the error correction capability of ECC, other error correction measures need to be further adopted.

[0005] As a means, rereading (also called read retry or read retry) is usually used. Specifically, when the number of error bits in user data exceeds the error correction capability of ECC, the firmware rereads the user data by changing the read voltage applied to the control electrode. On the other hand, since there are many factors that cause bit flipping, the distribution of threshold voltage in actual scenarios is not limited to Figure 1 Therefore, a reread table (Read Retry Table) is usually stored in the memory of the solid-state drive, and the reread table stores at least one set of reread voltage codes. A set of reread voltage codes can be used to form a set of reread voltages.

[0006] Figure 2 FIG. 2 shows a schematic diagram of a reread table used in the prior art for an MLC cell. Figure 2 As shown, the reread table stores three groups of reread voltage codes, each group of reread voltage codes includes three offset fields, which are respectively related to the above three reference voltages V A 、V B and V C In order to realize the error correction function, Figure 2 As shown in FIG. 1 , each offset field occupies 1 byte, so each group of reread voltage codes occupies 3 bytes, and three groups of reread voltage codes occupy a total of 9 bytes. Figure 2The reread operation performed by the reread table shown in the figure is explained. Taking the second group of reread voltage codes as an example, its first offset field records "00h", so the default read voltage corresponding to the first offset field does not shift. On the other hand, in the second group of reread voltage codes, the second offset field records "FDh". At this time, the firmware will compare "FDh" with "FFh" to obtain the difference, that is, "02h", and shift the default read voltage corresponding to the second offset field to the left or right by the amount corresponding to "02h". In addition, in the third group of reread voltage codes, the third offset field records "03h". At this time, the firmware will compare "03h" with "00h" to obtain the difference, that is, "03h", and shift the default read voltage corresponding to the third offset field to the right or left by the amount corresponding to "03h".

[0007] However, as the number of product layers increases and more complex scenarios are considered, the number of groups of reread voltage codes required also increases, resulting in insufficient on-chip SRAM storage space for the controller. In addition, too many reread voltage codes require longer traversal time, which will cause the product to respond to read commands with greater delays. Therefore, how to store fewer reread voltage codes and how to find the most appropriate reread voltage code in a shorter time becomes very important. Summary of the invention

[0008] The present application is formed to solve the above technical problems, and its purpose is to provide a flash memory read error correction method, which can realize error correction based on rereading action while realizing data compression. On this basis, the present application further provides a solid-state storage device and a firmware program product that can realize the above flash memory read error correction method.

[0009] A technical solution of the present application provides a flash memory read error correction method, comprising:

[0010] Correcting errors of user data read from the flash memory cell based on a default read voltage by an ECC circuit; and

[0011] When the number of error bits of the user data exceeds a specified number of bits, the flash memory cell is reread based on a pre-stored reread voltage code so that the number of error bits of the user data is less than the specified number of bits, wherein the specified number of bits is the number of bits that the ECC circuit can correct errors.

[0012] in,

[0013] The reread voltage code is composed of a sign field and an offset field.

[0014] A reread voltage is formed according to the sign field and the offset field of the reread voltage code, and the reread voltage is applied to the flash memory cell for the rereading.

[0015] According to the flash memory read error correction method described in the technical solution, unlike the prior art which uses a reread voltage code consisting of only a number of offset fields, in the technical solution, the reread voltage code consists of two types of fields, namely a sign field and an offset field, and a set of reread voltages is not determined only according to the offset field, but is determined according to both the sign field and the offset field. In other words, in the prior art, each reread voltage field of each set of reread voltage codes in the reread table uses an absolute value of the offset, while in the present application, a relative value of the offset is used. In this way, the reread voltage for rereading can be determined while occupying fewer bits compared to the prior art, thereby achieving data compression and saving memory storage space of the solid-state storage device.

[0016] Optionally, the offset field includes offset subfields whose number is the same as the number of the default read voltages, and the sign field includes bits corresponding to each of the offset subfields.

[0017] According to the flash memory read error correction method described in the technical solution, the re-read voltage can be determined while occupying fewer bits.

[0018] Optionally, one of the bit values ​​of the bit positions of the sign field corresponding to each of the offset subfields indicates that the default read voltage corresponding to each of the offset subfields is shifted in one direction by an amount corresponding to the offset subfield. The other of the bit values ​​of the bit positions of the sign field corresponding to each of the offset subfields indicates that the default read voltage corresponding to each of the offset subfields is shifted in another direction by an amount corresponding to the offset subfield.

[0019] According to the flash memory read error correction method described in the present technical solution, by making the default read voltage shift in a certain direction by a specified amount according to the bit value in the sign field, the reread voltage can be accurately determined while reducing the bits occupied by the reread voltage code.

[0020] Optionally, the flash memory cell is an MLC cell. The number of the offset subfields is three. The number of bits of each offset subfield in the reread voltage code is four. The number of bits of the sign field is four.

[0021] According to the flash memory read error correction method described in the technical solution, compared with the prior art where a set of reread voltage codes occupies 3 bytes, since a set of reread voltage codes in the technical solution only occupies 2 bytes, data compression can be achieved and memory space can be saved. In addition, by setting the bit of the sign field to four bits, data storage and intermediate implementation of the code are facilitated.

[0022] Optionally, the flash memory cell is a TLC cell. The number of the offset subfields is seven. The number of bits of each offset subfield in the reread voltage code is four. The number of bits of the sign field is eight.

[0023] According to the flash memory read error correction method described in the technical solution, compared with the prior art where a set of reread voltage codes occupies 7 bytes, since a set of reread voltage codes in the technical solution only occupies 4.5 bytes, data compression can be achieved and memory space can be saved. In addition, by setting the bit of the sign field to eight bits, data storage and intermediate implementation of the code are facilitated.

[0024] Optionally, the flash memory cell is a QLC cell. The number of the offset subfields is fifteen. The number of bits of each offset subfield in the reread voltage code is four. The number of bits of the sign field is sixteen.

[0025] According to the flash memory read error correction method described in the technical solution, compared with the prior art where a set of reread voltage codes occupies 15 bytes, since a set of reread voltage codes in the technical solution only occupies 9.5 bytes, data compression can be achieved and memory space can be saved. In addition, by setting the bits of the sign field to sixteen bits, data storage and intermediate implementation of the code are facilitated.

[0026] In addition, the present application also provides a solid-state storage device, which includes a memory, a control unit with a processor, and a firmware program stored in the memory, wherein the firmware program is executed by the processor to implement the flash memory read error correction method described in any of the above technical solutions.

[0027] In addition, the present application also provides a firmware program product, which includes a firmware program, and is characterized in that when the firmware program is executed by a processor, the flash memory read error correction method described in any of the above technical solutions is implemented.

[0028] According to the flash memory read error correction method described in the present application, by redesigning the data structure of the reread voltage code so that it includes a sign field for indicating the offset direction and an offset field for indicating the offset degree, it is possible to implement data error correction based on rereading while occupying fewer storage resources than the prior art, thereby saving memory space of the solid-state drive. In addition, since the reread voltage code described in the present application occupies fewer bits than the prior art, the RRT traversal time is also shortened accordingly, which can shorten the delay in responding to the read command. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Schematic diagram showing the threshold voltage distribution of MLC flash memory.

[0030] Figure 2 is a schematic diagram showing a re-read table used in the prior art for an MLC cell.

[0031] Figure 3 It is a schematic diagram showing an electronic system including a host device and a solid-state storage device connected to each other, and components not related to the present application are omitted.

[0032] Figure 4 It is a schematic diagram showing an example of a hardware structure for implementing a reread operation in a flash memory read error correction method according to an embodiment of the present application.

[0033] Figure 5 Detailed description of the invention The invention is a flowchart of a flash memory read error correction method according to an embodiment of the present application.

[0034] Figure 6 1 is a schematic diagram showing a first example of a reread table used in a flash memory read error correction method according to an embodiment of the present application.

[0035] Figure 7 1 is a schematic diagram showing a second example of a reread table used in the flash memory read error correction method according to an embodiment of the present application.

[0036] Figure 8 1 is a schematic diagram showing a third example of a reread table used in the flash memory read error correction method according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] Below, first refer to Figure 3 , the main architecture of the electronic system to which the flash memory read error correction method described in this application is applied is described. It should be noted that the architecture of the electronic system described here is only an example, and other types of architectures may also be used, or appropriate changes may be made based on the architecture.

[0038] like Figure 3As shown, the electronic system S mainly includes a host device 100, an external bus 110 and a solid-state storage device 120. The host device 100 mainly includes a host-side processor 101 and a host-side memory 102. Through the cooperation of the host-side processor 101 and the host-side memory 102, specific functions can be realized. In addition, according to actual needs, the host device 100 may also include a host-side controller (not shown in the figure). For example, through the cooperation of the host-side processor 101 and the host-side memory 102, the host device 100 can have the function of sending various commands (or requests) to the solid-state storage device 120 to access the flash memory array 123 in the solid-state storage device 120. The external bus 110 is used to connect the host device 100 and the solid-state storage device 120. Generally speaking, the external bus 110 is, for example, a USB bus, a SATA bus or a PCIe bus. The solid-state storage device 120 mainly includes a main control unit 121, a memory unit 122 and a flash memory array 123. The main control unit 121 is communicatively connected to the memory unit 122 and the flash array 123. The main control unit 121 is configured to receive commands sent from the host device 100 via the external bus 110 and communicate with the flash array 123 based on these commands, and enable the flash array 123 to perform corresponding actions according to the received commands. For example, the host device 100 can send commands such as write, read, and erase to the main control unit 121 of the solid-state storage device 120, and the main control unit 121 enables the flash array 123 to perform corresponding actions after receiving these commands. From a macroscopic perspective, the flash array 123 includes one or more Dies (or LUNs), each Die includes one or more Planes (sometimes called planes), each Plane includes one or more Blocks (also called flash blocks), each Block includes multiple Pages (also called flash pages), each Page corresponds to a word line (Write Line) and is composed of a large number of basic storage units. The Die or LUN of the flash array 123 is the basic unit for receiving or executing commands. Different Dies or LUNs can receive or execute different commands at the same time, but in a Die or LUN, only one command can be executed independently at a time. That is to say, while a write operation is being performed on a flash memory page in a Die or LUN, other flash memory pages cannot be read. In the current mainstream flash memory units, each Die can include four or six Planes, each Plane has its own independent registers (flash memory registers and page registers), and the size of each page register is equal to the size of a flash memory page. They are RAM inside the flash memory, which is used to cache data to be written to the flash memory array (Array) or read from the flash memory array. As explained above, the basic operations of flash memory are writing, reading and erasing. The smallest unit for writing and reading is a flash memory page, and the smallest unit for erasing is a flash memory block.

[0039] Figure 4 FIG. 3 is a schematic diagram showing an example of a hardware structure 300 for implementing a reread operation in a flash memory read error correction method according to an embodiment of the present application. Figure 4 As shown, the hardware structure 300 for implementing the reread operation includes, for example, a plurality of (three in this embodiment) offset field registers 301-303, a sign field register 310, and a read voltage generating circuit 320. It should be noted that the hardware structure 300 of this example is designed on the premise that the flash memory cell is an MLC. Since the number of reference voltages of the MLC is three, the hardware structure 300 is configured with offset field registers 301-303 corresponding to each of the three reread voltages, and each offset field register 301-303 is used to cache each offset sub-field of the offset field in a set of reread voltage codes. In addition, the sign field register 310 is used to cache the sign field for indicating the offset direction of the offset voltage corresponding to each offset sub-field. When a reread operation is to be performed, each offset subfield of the offset field in a group of reread voltage codes stored in the reread table of the memory unit 122 of the solid-state storage device 120 is cached to the offset field registers 301-303, and the sign field in the group of reread voltage codes is cached to the sign field register 310. Then, the sign field is input to the read voltage generation circuit 320, and each offset subfield is sequentially input to the read voltage generation circuit 320. Then, the read voltage generation circuit 320 calculates the reread voltage according to the input offset subfield and the value of the bit corresponding to the offset subfield in the sign field, and applies the reread voltage to the control electrode of the storage unit of the flash memory to perform the reread operation. The specific composition of the above-mentioned reread voltage code and the flash memory read error correction method implemented based on the reread voltage code will be described in detail later. It should be noted here that the above-mentioned hardware structure 300 for implementing the reread operation is only an example and is not limited to this. As long as the reread operation can be implemented, any suitable hardware structure can also be used.

[0040] Figure 5A flow chart of a flash memory read error correction method according to an embodiment of the present application is shown. First, in step ST1, the user data read from the flash memory unit based on the default read voltage is corrected by the ECC circuit (i.e., the ECC error correction engine). Specifically, the memory unit 122 of the solid-state storage device 120 pre-stores a default read voltage corresponding to the basic storage unit in the flash memory array 123. For example, in the case where the flash memory is an MLC unit, three default read voltages for reading low-order data and high-order data are pre-stored in the memory unit 122. In the case where the user performs an operation corresponding to a read request through the operating system of the host device 100, the file system converts the read request into a corresponding read command via the driver. That is, in response to a read request at the operating system level, a read instruction pre-stored in the host-side memory 102 is sent to the host-side processor 101, and then sent to the solid-state storage device 120 via the external bus 102. After receiving the above-mentioned read instruction, the main control unit 121 of the solid-state storage device 120 finds the corresponding default read voltage from the memory unit 122 according to the read instruction, and applies the default read voltage to the control electrode of each basic storage unit connected to the word line via the corresponding word line to obtain the required user data. For the obtained user data, in order to test the reliability of the user data, the main control unit 120 uses the ECC circuit (ECC error correction engine) to correct the above-mentioned user data read from the flash memory array 123 based on the above-mentioned default read voltage.

[0041] Then, in step ST2, it is determined whether the number of error bits of the user data exceeds the error correction capability of the ECC circuit. If the number of error bits of the user data does not exceed the error correction capability of the ECC circuit, the user data is output to the host device 100 (step STA). On the other hand, if the number of error bits of the user data exceeds the error correction capability of the ECC circuit, the process proceeds to step ST3.

[0042] In step ST3, when it is determined that the number of error bits of the above-mentioned user data exceeds the specified number of bits, that is, exceeds the error correction capability of the ECC circuit, the flash memory array 123 is reread based on a pre-stored reread voltage code so that the number of error bits of the user data finally output does not exceed the error correction capability of the ECC circuit.

[0043] Here, for ease of understanding, the types of flash memory are MLC, TLC, and QLC as examples and combined with Figure 6~Figure 8 The actions of this step are described in detail.

[0044] Figure 6 FIG. 4 is a schematic diagram showing an example of a reread table designed for MLC flash memory. Figure 6As shown, the reread table pre-stores three groups of reread voltage codes, and each group of reread voltage codes is composed of a sign field and an offset field. Specifically, in each group of reread voltage codes, the sign field occupies four bits, i.e., 0.5 bytes, and the offset field includes three offset subfields, each of which occupies four bits, i.e., 0.5 bytes. In addition, each offset subfield represents a voltage offset relative to one of the three default read voltages, and is a scalar. On the other hand, in each group of reread voltage codes, three bits of the four bits of the sign field correspond to each offset subfield, respectively. Regarding the corresponding method, for example, it can be corresponded from a low bit to a high bit, or it can be corresponded from a high bit to a low bit. The value of the bit corresponding to each offset subfield in the sign field represents the offset direction of the default read voltage corresponding to the offset subfield. Specifically, for example, if the value of the above-mentioned bit of the sign field is 0, it means that the default read voltage corresponding to the offset subfield corresponding to the bit is offset in one direction by an amount corresponding to the offset subfield. If the value of the above-mentioned bit of the sign field is 1, it means that the default read voltage corresponding to the offset subfield corresponding to the bit is offset in another direction by an amount corresponding to the offset subfield. Here, it can be assumed that "offset in one direction" is "offset to the left" and "offset in another direction" is "offset to the right", but it is not limited to this and can be designed according to the specific situation of the flash memory. Below, for ease of understanding, an explanation is given based on each group of reread voltage codes in the reread table. In the first group of reread voltage codes, the value of each offset subfield is "0000", indicating that the read voltage does not produce an offset. In the second group of reread voltage codes, the value of the first offset subfield is "0000", indicating that the corresponding read voltage does not generate an offset, while the values ​​of the second offset subfield and the third offset subfield are "0010" and "0011", respectively, indicating that the corresponding default read voltage generates an offset corresponding to "0010" and "0011", but the offset direction cannot be determined based on the information of these two offset subfields alone. On the other hand, in the second group of reread voltage codes, the value of the sign field is "0010". Assuming that the correspondence is performed from the lower bit to the higher bit, the lowest bit "0" corresponds to the first offset subfield, the second bit "1" from the right corresponds to the second offset subfield, and the third bit "0" from the right corresponds to the third offset subfield. It can be seen that the default read voltage corresponding to the first offset subfield does not generate an offset, the default read voltage corresponding to the second offset subfield is offset to the right by an amount corresponding to "0010", and the default read voltage corresponding to the third offset subfield is offset to the left by an amount corresponding to "0011". In addition, in the third group of re-read voltage codes, the value of the sign field is "0111".Assuming that the correspondence is performed from the lower bit to the higher bit, the lowest bit "1" corresponds to the first offset subfield, the second bit "1" from the right corresponds to the second offset subfield, and the third bit "1" from the right corresponds to the third offset subfield. It can be seen that the default read voltage corresponding to the first offset subfield is shifted to the right by an amount corresponding to "0001", the default read voltage corresponding to the second offset subfield is shifted to the right by an amount corresponding to "0001", and the default read voltage corresponding to the third offset subfield is shifted to the right by an amount corresponding to "0101".

[0045] Figure 7 FIG. 2 is a schematic diagram showing an example of a reread table designed for TLC flash memory. Figure 7 As shown, the reread table also pre-stores three groups of reread voltage codes, and each group of offset voltage codes is also composed of a sign field and an offset field. Specifically, in each group of reread voltage codes, the sign field occupies eight bits, i.e., 1 byte, and the offset field includes seven offset subfields, each of which occupies four bits, i.e., 0.5 bytes. Due to other conventions and Figure 6 The conventions in the reread table shown for the MLC flash memory design are the same and repeated descriptions are omitted here.

[0046] Figure 8 FIG. 1 is a schematic diagram showing an example of a reread table designed for QLC flash memory. Figure 8 As shown, the reread table also pre-stores three groups of reread voltage codes, and each group of offset voltage codes is also composed of a sign field and an offset field. Specifically, in each group of reread voltage codes, the sign field occupies sixteen bits, i.e., 2 bytes, and the offset field includes fifteen offset subfields, each of which occupies four bits, i.e., 0.5 bytes. Due to other conventions and Figure 6 The conventions in the reread table shown for the MLC flash memory design are the same and repeated descriptions are omitted here.

[0047] The flash memory read error correction method described in this embodiment is different from the prior art in which the reread table records the absolute value of the offset of the default read voltage in that, in this application, the composition of the reread voltage code recorded in the reread table is improved, and the reread voltage code consisting only of the offset field is improved to a reread voltage code consisting of both the sign field and the offset field. In this way, while the reread operation can still be realized, the number of bits occupied by the reread voltage code is reduced, thereby reducing the storage space occupied by the reread table in the memory unit of the solid-state storage device, realizing data compression and saving the storage space of the solid-state storage device.

[0048] It should be understood that the present invention is not limited to the exact construction that has been described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the present invention is limited only by the appended claims.

Claims

1. A flash memory read error correction method, comprising: Correcting errors of user data read from the flash memory cell based on a default read voltage by an ECC circuit; as well as When the number of error bits of the user data exceeds a specified number of bits, the flash memory unit is reread based on a pre-stored reread voltage code so that the number of error bits of the user data is less than the specified number of bits, wherein the specified number of bits is the number of bits that the ECC circuit can correct errors. It is characterized in that The reread voltage code is composed of a sign field and an offset field. The offset field includes the same number of offset subfields as the number of the default read voltages, The sign field includes bits corresponding to each of the offset subfields, The value of the bit corresponding to each offset subfield in the sign field indicates the offset direction of the default read voltage corresponding to the offset subfield. A reread voltage is formed according to the sign field and the offset field of the reread voltage code, and the reread voltage is applied to the flash memory cell for the rereading.

2. The flash memory read error correction method according to claim 1, wherein: One of the bit values ​​of the bit positions corresponding to each offset subfield of the sign field indicates that the default read voltage corresponding to each offset subfield is shifted in one direction by an amount corresponding to the offset subfield. The other of the bit values ​​of the bits of the sign field corresponding to the offset subfields indicates that the default read voltage corresponding to the offset subfield is shifted in the other direction by an amount corresponding to the offset subfield.

3. The flash memory read error correction method according to claim 2, characterized in that: The flash memory cell is an MLC cell, The number of the offset subfields is three, The number of bits of each offset subfield in the re-read voltage code is four bits. The sign field has four bits.

4. The flash memory read error correction method according to claim 2, wherein: The flash memory cell is a TLC cell, The number of the offset subfields is seven. The number of bits of each offset subfield in the re-read voltage code is four bits. The sign field has eight bits.

5. The flash memory read error correction method according to claim 2, wherein: The flash memory cell is a QLC cell, The number of the offset subfields is fifteen, The number of bits of each offset subfield in the re-read voltage code is four bits. The sign field has sixteen bits.

6. A solid-state storage device, comprising a memory, a control unit having a processor, and a firmware program stored in the memory, characterized in that: The firmware program is executed by the processor to implement the flash memory read error correction method according to any one of claims 1 to 5.

7. A firmware program product, comprising a firmware program, characterized in that: When the firmware program is executed by a processor, the flash memory read error correction method according to any one of claims 1 to 5 is implemented.

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