RISC-V vector optimization method, device and equipment based on thread scheduling

Abstract

The invention discloses an RISC-V vector optimization method, device and equipment based on thread scheduling, relates to the field of digital integrated circuit design, and is used for solving the problems of operation resource waste, relatively low operation efficiency and performance reduction caused by memory access performance limitation in the prior art. Comprising the following steps: acquiring an RISC-V vector instruction, extracting decoding information from the RISC-V vector instruction, and acquiring register configuration information in a vector state; determining thread scheduling information according to the decoding information, the register configuration information, the current thread execution state and hardware configuration; executing a corresponding thread task according to the thread scheduling information; after execution is finished, if the thread task of the current instruction is executed, updating the state and delivering the current instruction; otherwise, updating the state and executing the next thread task until all the thread tasks are executed, writing back the data, completing instruction delivery and ending the instruction cycle. According to the method, the vector instruction execution performance under memory access performance limitation can be effectively improved, and the overall operation performance is improved.

Description

Technical Field

[0001] The present invention relates to the field of digital integrated circuit design, and in particular to a RISC-V vector optimization method, device and equipment based on thread scheduling. Background Art

[0002] Digital integrated circuit chips are widely used in server high-performance computing, mobile portable devices and other fields. In recent years, with the development of artificial intelligence and the emergence of the Internet of Things, the demand for the computing power and efficiency of digital chips has continued to grow. Artificial intelligence applications usually involve the processing of large-scale data and the calculation of complex models, while the Internet of Things involves the collection and processing of a large amount of sensor data. These application scenarios have put forward higher and higher requirements on the computing power and speed of chips. SIMD (Single Instruction Multiple Data) technology is a parallel computing technology that allows multiple data to be operated under a single instruction to improve computing efficiency. This technical background originated from the continuous exploration and optimization of computer architecture. In traditional computer architecture, the processor can only execute one instruction at a time, while SIMD technology realizes parallel computing by operating multiple data elements simultaneously under a single instruction. This parallel computing is particularly suitable for some situations where the same operation needs to be performed on large-scale data, such as image processing, signal processing, scientific computing and other fields. Through SIMD technology, these data can be distributed in parallel to multiple processing units for calculation, thereby significantly improving the computing speed and efficiency.

[0003] RISC-V is an open source, reduced instruction set architecture known for its flexibility, scalability, and openness. As a general instruction set architecture, RISC-V can be widely used in various computing devices and fields, providing users with free and flexible choices. Combining the RISC-V architecture and SIMD technology, efficient parallel computing can be achieved on RISC-V processors. However, the existing RISC-V vector implementation method is prone to affect the overall computing performance due to insufficient memory access performance and cause waste of computing resources.

[0004] Therefore, there is an urgent need to provide a more reliable RISC-V vector optimization solution based on thread scheduling. Summary of the invention

[0005] The purpose of the present invention is to provide a RISC-V vector optimization method, device and equipment based on thread scheduling, which is used to solve the problems of waste of computing resources, low computing efficiency and performance degradation caused by insufficient memory access performance in the prior art.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] In a first aspect, the present invention provides a RISC-V vector optimization method based on thread scheduling, the method comprising:

[0008] Obtain a RISC-V vector instruction, extract decoding information from the RISC-V vector instruction, and obtain register configuration information of a vector state;

[0009] Determine thread scheduling information according to the decoding information, the register configuration information, the current thread execution state and the hardware configuration;

[0010] Execute corresponding thread tasks according to the thread scheduling information;

[0011] After the current thread task is executed, the scheduling judgment is made according to the thread status. If the thread task of the current instruction is executed, the status is updated and the current instruction is delivered; if there are still thread tasks that have not been executed for the current instruction, the status is updated and the next thread task is executed until all thread tasks are executed, the data is written back, the instruction delivery is completed, and the instruction cycle ends.

[0012] Optionally, the thread scheduling information includes allowing thread scheduling, not allowing thread scheduling, single thread scheduling or multi-thread scheduling;

[0013] The determining thread scheduling information according to the decoding information, the register configuration information, the current thread execution state and the hardware configuration specifically includes:

[0014] Perform scheduling judgment according to the decoding information and the current thread execution state to obtain a first judgment result;

[0015] If the first judgment result indicates that thread scheduling is allowed, thread scheduling is performed;

[0016] Perform judgment according to the hardware configuration and register configuration information to obtain a second judgment result;

[0017] If the second judgment result indicates that the current instruction task can be completed in a single thread, single thread scheduling is performed;

[0018] If the second judgment result indicates that the current instruction task cannot be completed in a single thread, multi-thread scheduling is performed.

[0019] Optionally, performing scheduling judgment according to the decoding information and the current thread execution state to obtain a first judgment result includes:

[0020] Perform scheduling judgment based on the decoding information and the current thread execution state to determine whether thread scheduling can be performed;

[0021] When there is no pipeline blockage, the memory access unit and the computing unit are both in the ready state, and the thread scheduling of any instruction is performed at this time;

[0022] When there is a pipeline blockage, determine the current instruction type and check whether the corresponding read / write / calculation module is in an idle state;

[0023] If the execution module corresponding to the current instruction type is in an idle state, a correlation determination is performed;

[0024] If there is no data dependency, the pipeline is switched and thread scheduling is performed for the current instruction.

[0025] Optionally, performing a judgment according to the hardware configuration and the register configuration information to obtain a second judgment result includes:

[0026] When it is determined that the current conditions allow thread scheduling, it is determined whether to perform multi-thread scheduling on the current instruction;

[0027] For memory access instructions, if the bus width of the memory access resource is greater than the product of the number of vector registers and the bit width of the vector register, it is determined that the current instruction can be executed in a single thread and single-thread scheduling is performed; otherwise, multi-thread scheduling is performed, the current instruction task is decomposed into multiple thread tasks, and the first thread task is thread scheduled in the current cycle;

[0028] For operation instructions, if the number of operation units of the operation resources is greater than the number of vector elements, it is determined that the current instruction can be executed within a single thread and single-thread scheduling is performed; otherwise, multi-thread scheduling is performed, and the current instruction task is decomposed into multiple thread tasks, and the first thread task is scheduled in the current cycle.

[0029] Optionally, executing the corresponding thread task according to the thread scheduling information includes:

[0030] When there is a memory access task that needs to be executed, the thread memory access module is enabled, generates addresses and processes data according to the configuration information provided by the thread scheduling module, and realizes data transmission with the memory through the bus interface;

[0031] When there is a computing task that needs to be executed, the thread computing module is enabled, and a corresponding number of computing units are enabled according to the configuration information provided by the thread scheduling module, the corresponding computing type is executed, and the result is written back to the register.

[0032] Optionally, for the single-thread scheduling, the thread scheduling module dispatches the current instruction task to the corresponding execution unit;

[0033] For the multi-thread scheduling, the thread scheduling module divides the instruction task into a plurality of sub-thread tasks, and the sub-thread tasks can be executed and completed at one time;

[0034] The first thread task in the sub-thread tasks is dispatched, the thread tasks other than the first thread task in the sub-thread tasks are cached, and the thread status is updated each time the thread execution is completed until all threads are executed.

[0035] Optionally, updating the thread state includes updating the thread execution state and the data correlation queue state;

[0036] After the current thread task is executed, a scheduling judgment is performed according to the thread state. If the thread task of the current instruction is executed, the state is updated and the current instruction is delivered, including:

[0037] For a single-thread instruction, after the thread task is completed, it is assumed that the instruction has been executed, and the thread execution state and data correlation state monitoring of the instruction are canceled. The thread scheduling module is responsible for delivering the current instruction and writing back the result.

[0038] For multi-threaded instructions, the thread scheduling module updates the thread execution status and data correlation status of the instruction, and determines whether the current thread is the last thread of the instruction. If so, the thread execution status and data correlation status monitoring of the instruction are canceled, and the thread scheduling module is responsible for delivering the current instruction and writing back the result when necessary; otherwise, the next thread task of the instruction is dispatched until all thread tasks are executed.

[0039] Compared with the prior art, the present invention provides a RISC-V vector optimization method based on thread scheduling. It includes: obtaining RISC-V vector instructions, extracting decoding information from RISC-V vector instructions, and obtaining register configuration information of vector status; determining thread scheduling information according to decoding information, register configuration information, current thread execution status and hardware configuration; executing corresponding thread tasks according to thread scheduling information; after the current thread task is executed, scheduling judgment is made according to the thread status, if the thread task of the current instruction is executed, the status is updated and the current instruction is delivered; if there are still unexecuted thread tasks in the current instruction, the status is updated and the next thread task is executed until all thread tasks are executed, data is written back, instruction delivery is completed, and the instruction cycle is ended. The present invention executes RISC-V vector instructions in a time-sharing manner, optimizes the pipeline arrangement problem of the traditional single instruction multiple data execution structure, and conceals pipeline blocking by multi-thread interleaved execution, which can effectively improve the execution performance of vector instructions under memory access performance restrictions, improve overall computing performance, and realize a low-cost and high-performance RISC-V vector processor.

[0040] In a second aspect, the present invention provides a RISC-V vector optimization device based on thread scheduling, the device comprising:

[0041] Instruction decoding module, thread scheduling module, thread memory access module and thread operation module;

[0042] The instruction decoding module is used to obtain RISC-V vector instructions, extract decoding information from the RISC-V vector instructions, and obtain register configuration information of the vector state;

[0043] The thread scheduling module is used to determine thread scheduling information according to the decoding information, the register configuration information, the current thread execution state and the hardware configuration;

[0044] The thread operation module is used to execute the corresponding thread task according to the thread scheduling information;

[0045] The thread memory access module is used to execute corresponding memory access tasks according to thread scheduling information, and write the results back to the vector register or memory after all thread tasks are executed.

[0046] Compared with the prior art, the present invention provides a RISC-V vector optimization device based on thread scheduling, which introduces a thread scheduling module. Through thread scheduling, RISC-V vector instructions are executed in a time-sharing manner, thereby optimizing the pipeline scheduling problem of the traditional single instruction multiple data execution structure, masking pipeline blockage through multi-threaded interleaved execution, improving the overall computing performance, reducing computing hardware overhead, and realizing a low-cost and high-performance RISC-V vector processor.

[0047] In a third aspect, the present invention provides a RISC-V vector optimization device based on thread scheduling, the device comprising:

[0048] A memory, a processor, and a communication interface coupled to the processor; the memory stores a computer program that can be executed by the processor; when the processor runs the computer program, it executes the above-mentioned RISC-V vector optimization method based on thread scheduling.

[0049] In a fourth aspect, the present invention provides a computer storage medium, wherein instructions are stored in the computer storage medium, and when the instructions are executed, the above-mentioned RISC-V vector optimization method based on thread scheduling is implemented.

[0050] The technical effects achieved by the device type solution provided in the third aspect and the computer storage medium solution provided in the fourth aspect are the same as those of the method type solution provided in the first aspect, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0052] Figure 1 A schematic flow chart of a RISC-V vector optimization method based on thread scheduling provided by the present invention;

[0053] Figure 2 A schematic diagram of a thread scheduling workflow of a RISC-V vector optimization method based on thread scheduling provided by the present invention;

[0054] Figure 3 A signal interface diagram of a RISC-V vector optimization device based on thread scheduling provided by the present invention;

[0055] Figure 4 It is a schematic diagram of hardware pipeline arrangement;

[0056] Figure 5 A schematic diagram of a RISC-V vector optimization device based on thread scheduling provided by the present invention.

[0057] Reference numerals:

[0058] 310 - instruction decoding module, 320 - thread scheduling module, 330 - thread memory access module, 340 - thread operation module. DETAILED DESCRIPTION

[0059] In order to clearly describe the technical solutions of the embodiments of the present invention, in the embodiments of the present invention, words such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions and effects. For example, the first threshold and the second threshold are only used to distinguish different thresholds, and their order is not limited. Those skilled in the art can understand that words such as "first" and "second" do not limit the quantity and execution order, and words such as "first" and "second" do not necessarily limit them to be different.

[0060] It should be noted that, in the present invention, words such as "exemplary" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "exemplary" or "for example" in the present invention should not be interpreted as being more preferred or more advantageous than other embodiments or designs. Specifically, the use of words such as "exemplary" or "for example" is intended to present related concepts in a specific way.

[0061] In the present invention, "at least one" means one or more, and "plurality" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the associated objects before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, the combination of a and b, the combination of a and c, the combination of b and c, or the combination of a, b and c, where a, b, c can be single or multiple.

[0062] In the prior art, the existing P extension instruction set and vector extension instruction set of RISC-V can support the SIMD instruction set by extending the RISC-V instruction set, and can meet the needs of parallel computing on the RISC-V processor, thereby improving computing efficiency and performance. However, the existing RISC-V vector manual is still imperfect, and there is a lot of room for optimization when it comes to hardware implementation. For example, the RISC-V vector extension does not specify the hardware behavior of memory access instructions when the bus interface width is limited and multiple handshakes are required to complete data transmission. This situation will cause excessive pipeline blocking and lead to unnecessary performance loss; in addition, the RISC-V vector extension defaults to aligning vector operations within one cycle, which will cause the computing components to be valid only in some cycles, resulting in a waste of computing resources, low computing efficiency, and poor computing performance.

[0063] In order to solve the problems in the prior art, the present invention provides a RISC-V vector optimization method, device and apparatus based on thread scheduling. Next, the scheme provided by the embodiment of this specification is described in conjunction with the accompanying drawings:

[0064] like Figure 1 As shown, the process may include the following steps:

[0065] Step 110: Obtain a RISC-V vector instruction, extract decoding information from the RISC-V vector instruction, and obtain register configuration information of the vector state.

[0066] RISC-V is an open source instruction set architecture (ISA) designed to support a wide range of devices from the smallest embedded processors to high-performance computing (HPC) systems. RISC-V defines multiple extensions, some of which support SIMD operations, such as the "V" extension, which provides support for vector processing. RISC-V processors can be configured to support SIMD operations to improve performance when processing large data sets. The RISC-V vector extension (RVV) is a part of the RISC-V instruction set architecture that is specifically designed to support vector computing. The design goal of RVV is to provide an efficient and scalable vector processing capability.

[0067] Step 110 is implemented by the instruction decoding module responsible for instruction decoding and caching: the instruction decoding module caches and decodes the obtained instructions. If the instruction is identified as a RISC-V vector instruction, relevant configuration information is extracted, including the instruction operation type and data type obtained from the instruction decoding, as well as the default vector element width SEW, the number of vector registers LUML, the vector start index VSTART, etc. obtained from the vector status register.

[0068] Step 120: Determine thread scheduling information according to the decoding information, the register configuration information, the current thread execution state and the hardware configuration.

[0069] The decoding information may include instruction operation type, data type, etc. The register configuration information may include default vector element width SEW, vector register number LUML, vector start index VSTART, etc.

[0070] Thread scheduling information may include whether to schedule, single-thread scheduling, and multi-thread scheduling.

[0071] Step 130: Execute the corresponding thread task according to the thread scheduling information.

[0072] Step 140: After the current thread task is executed, the scheduling judgment is performed according to the thread status. If the thread task of the current instruction is executed, the status is updated and the current instruction is delivered; if there is still an unfinished thread task of the current instruction, the status is updated and the next thread task is executed until all thread tasks are executed, the data is written back, the instruction delivery is completed, and the instruction cycle ends.

[0073] Figure 1The method in the invention obtains RISC-V vector instructions, extracts decoding information from RISC-V vector instructions, obtains register configuration information of vector state; determines thread scheduling information according to decoding information, register configuration information, current thread execution state and hardware configuration; executes corresponding thread tasks according to thread scheduling information; after the current thread task is executed, performs scheduling judgment according to thread state, if the thread task of the current instruction is executed, updates the state and delivers the current instruction; if the current instruction still has uncompleted thread tasks, updates the state and executes the next thread task, until all thread tasks are executed, writes back data, completes instruction delivery, and ends instruction cycle. The present invention executes RISC-V vector instructions in a time-sharing manner, optimizes the pipeline arrangement problem of traditional single instruction multiple data execution structure, and covers pipeline blocking by multi-thread interleaved execution, which can effectively improve the vector instruction execution performance under memory access performance limitation, improve overall computing performance, and realize a low-cost and high-performance RISC-V vector processor.

[0074] The present invention mainly aims at the problems of computing resource waste and performance degradation caused by memory access performance bottleneck. By performing fine-grained multi-thread scheduling through the scheduling module, vector parallel computing can be realized with the lowest possible hardware resources and the overall computing performance can be improved. In addition, the parameters of the present invention can be customized and adjusted, and the architecture parameters can be adjusted according to the actual situation of memory access capability and task requirements. The degree of liberalization is high and hardware redundancy can be avoided.

[0075] based on Figure 1 The method, the embodiments of this specification also provide some specific implementation methods of the method, which are described below.

[0076] In step 120, when determining thread scheduling information and executing corresponding thread tasks based on the thread scheduling information, the corresponding thread scheduling process can refer to Figure 2 To explain:

[0077] like Figure 2 As shown, a scheduling judgment is made based on the decoding information and the current thread execution state to determine whether the thread can be scheduled;

[0078] When there is no pipeline blocking, the memory access unit and the computing unit are both in the ready state, and the thread scheduling of any instruction can be performed at this time;

[0079] When there is a pipeline blockage, that is, there is an execution still in progress, determine the current instruction type and check whether the corresponding read / write / calculation module is in an idle state. If the execution module corresponding to the current instruction type is in an idle state, perform a correlation judgment;

[0080] If there is no data dependency, the pipeline can be switched and the thread scheduling can be performed on the current instruction.

[0081] In the above steps, the pipeline switching implemented by the thread scheduling module allows multi-threaded execution to be interleaved, without having to wait for a RISC-V vector instruction to be fully executed before executing the next RISC-V vector instruction. This masks the memory access bottleneck during program execution, solves the pipeline scheduling problem, and improves the overall computing performance.

[0082] Furthermore, if Figure 2 As shown, when the thread scheduling module determines that the current conditions allow thread scheduling, it will further determine whether multi-thread scheduling is required for the current instruction;

[0083] For memory access instructions, if the bus width of the memory access resource is greater than the number of vector registers LUML*vector register bit width VLEN;

[0084] For operation instructions, if the number of operation units of the operation resources is greater than the number of vector elements, it is considered that the current instruction can be executed in a single thread and single-thread scheduling is performed; otherwise, multi-thread scheduling is required, and the current instruction task is decomposed into multiple thread tasks, and the first thread task is scheduled in the current cycle.

[0085] Specifically, the thread scheduling module can convert instruction tasks into thread tasks through thread segmentation, reducing the requirements of vector implementation on hardware memory access and computing capabilities, and alleviating the memory access bottleneck and computing hardware overhead during program execution.

[0086] Furthermore, in step 130, when there is a memory access task that needs to be executed, the thread memory access module will be enabled, and an address will be generated according to the configuration information provided by the thread scheduling module, and data will be processed, and data transmission with the memory will be realized through the bus interface; when there is a computing task that needs to be executed, the thread computing module will be enabled, and a corresponding number of computing units will be enabled according to the configuration information provided by the thread scheduling module, the corresponding computing type will be executed, and the result will be directly written back to the register.

[0087] Furthermore, the thread scheduling module updates the thread execution status and the correlation dependency status each time the thread task is executed, and performs additional judgments.

[0088] If the current instruction is a single-threaded task, then determine whether the instruction has been executed, deliver the current instruction and write back the result; if the current instruction is a multi-threaded task, then determine whether the current executing thread is the last thread. If so, then determine whether the instruction has been executed, deliver the current instruction and write back the result. If not, then determine that the instruction is still being executed, block this type of pipeline, and execute the next thread task of the current instruction instead, until all thread tasks are executed.

[0089] Next, in order to explain the implementation scheme of the present application in more detail, a specific example is given. Figure 1 The steps are described in detail:

[0090] Regarding step 110, the instruction is decoded after being received, and once the instruction is identified as a RISC-V vector extension instruction, decoding information extraction begins.

[0091] The decoding information may include the source register index rs, the destination register index vd, the vector mask flag vm, the vector operation functions funct6, funct3 obtained from the instruction decoding, and the memory access element width eew, the read / write type mew, the addressing mode mop, etc. for special configuration instructions and memory access instructions. It may also include the vector register number LUML, the default element width SEW, the starting element index VSTART, the number of elements VL, etc. obtained from the vector status register.

[0092] Regarding step 120, the present invention has a thread scheduling module for thread scheduling, and the thread scheduling module makes a judgment based on the current instruction type and the current execution state. If there is no currently executing thread, thread scheduling of the input instruction is allowed. If there is currently an executing thread, it is determined whether the input instruction occupies the same execution component as the executing thread. If they are different, thread scheduling of the input instruction is allowed in the absence of data correlation conflict.

[0093] Taking the input of an instruction to read memory as an example, if there are currently threads that are writing and threads that are calculating, since there is no resource conflict between the instruction to read memory and them, a data dependency conflict is determined. If there is no data dependency conflict between the thread that needs to read memory and them, thread scheduling of the input instruction is allowed.

[0094] If the above conditions are not met, the pipeline is substantially blocked and thread scheduling of input instructions is not accepted until the executing thread is completed and the status is updated and the above judgment is performed again.

[0095] The pipeline switching implemented by the thread scheduling module allows multi-threaded execution in an interleaved manner, without having to wait for a RISC-V vector instruction to be fully executed before executing the next RISC-V vector instruction. This masks the memory access bottleneck during program execution, solves the pipeline scheduling problem, and improves the overall computing performance.

[0096] Regarding step 130, a judgment is made based on the hardware configuration and instruction configuration information to initiate single-thread scheduling or multi-thread scheduling.

[0097] This step is also implemented by the thread scheduling module responsible for thread scheduling. The thread scheduling module receives the configuration information of the thread operation module and the thread memory access module. When the input instruction needs to be conditionally judged, if the instruction is a memory access instruction, the thread scheduling module determines whether the bus width of the thread memory access module can complete data reading and writing at one time; if the instruction is an operation instruction, the thread scheduling module determines whether the operation resources of the thread memory access module can complete data operation at one time. If yes, single-thread scheduling is performed; otherwise, multi-thread scheduling is performed.

[0098] Taking memory access instructions as an example, if the bus length is greater than or equal to the number of vector registers LMUL configured by the vector register multiplied by the vector register bit width VLEN, it means that data reading and writing can be completed at one time; taking operation instructions as an example, if the number of thread operation units is greater than or equal to the vector elements vl, it means that data operation can be completed at one time.

[0099] For single-threaded scheduling, the thread scheduling module only needs to dispatch the current instruction task as a thread task to the corresponding execution unit; for multi-threaded scheduling, the thread scheduling module needs to first divide the instruction task into multiple thread tasks that can be executed at one time, and then dispatch the first thread task, cache the subsequent thread tasks, and update the thread status each time the thread is executed until all threads are executed.

[0100] For example: the present invention specifies that the vector register width VLEN is 32 bits and the bus width is 128 bits. When performing thread scheduling of read and write instructions, if the LUML saved in the current vector status register is 4, it means that the current instruction needs to use 4 vector registers, and the read and write data width will not exceed the bus width, then the task can be directly dispatched to the execution unit.

[0101] For example: if the LUML saved in the current vector status register is 16, it means that the current instruction needs to use 16 vector registers v0~v15, the total data read and write width is 512bit, and the bus interface needs four times to complete the data read and write. At this time, the thread scheduling unit will decompose the instruction task into 4 thread tasks, each thread task will complete the reading and writing of the 4 vector registers v0~v3, v4~v7, v8~v11 and v12~v15, and dispatch the first thread task to the execution unit at the same time, and dispatch the next thread task when each execution unit feedbacks the completion of execution.

[0102] The thread scheduling module converts instruction tasks into thread tasks through thread segmentation, reducing the demand for hardware memory access and computing capabilities for vector implementation, and alleviating the memory access bottleneck and computing hardware overhead during program execution.

[0103] The execution unit executes the corresponding thread task, that is, the computing unit and the memory access unit of the processor execute the corresponding computing / memory access task according to the signal sent by the thread scheduling module, and feed back to the thread scheduling module after the execution is completed.

[0104] Regarding step 140: updating the thread status, if the current instruction thread is completely completed, then the scheduling of the current instruction is terminated.

[0105] This step is implemented by the thread scheduling module. Updating the thread status includes updating the thread execution status and data dependency queue status. For single-threaded instructions, after the thread task is completed, it is assumed that the instruction has been executed, and the thread execution status and data dependency status monitoring of the instruction are canceled. The thread scheduling module is responsible for delivering the current instruction and writing back the result when needed.

[0106] For multi-threaded instructions, the thread scheduling module will first update the thread execution status and data dependency status of the instruction, and then determine whether the current thread is the last thread of the instruction. If so, the thread execution status and data dependency status monitoring of the instruction will be canceled, and the thread scheduling module will be responsible for delivering the current instruction and writing back the result when necessary; otherwise, the next thread task of the instruction will be dispatched until all thread tasks are executed. Delivering the instruction and writing back the result completes the execution cycle of the instruction.

[0107] Based on the same idea, the present invention also provides a RISC-V vector optimization device based on thread scheduling, such as Figure 3 As shown, the device may include:

[0108] Instruction decoding module 310, thread scheduling module 320, thread memory access module 330 and thread operation module 340;

[0109] The instruction decoding module 310 is used to obtain the RISC-V vector instruction, extract the decoding information from the RISC-V vector instruction, and obtain the register configuration information of the vector state;

[0110] The thread scheduling module 320 is used to determine thread scheduling information according to the decoding information, the register configuration information, the current thread execution state and the hardware configuration;

[0111] The thread operation module 340 is used to execute the corresponding thread task according to the thread scheduling information;

[0112] The thread memory access module 330 is used to execute corresponding memory access tasks according to thread scheduling information, and write the results back to the vector register or memory after all thread tasks are executed.

[0113] based on Figure 3 The device in the embodiment corresponds to the following process when it is implemented:

[0114] Optionally, the instruction decoding module 310 receives and decodes instructions, the thread scheduling module 320 performs thread scheduling based on the decoding information and the register configuration information of the vector state, and assigns thread tasks to the thread memory access module 330 and the thread operation module 340; the two execute corresponding thread tasks and store the results in the vector registers; after all threads are executed, the instruction delivery module is responsible for delivering the instructions and writing back the results.

[0115] The instruction decoding module 310 is responsible for caching the acquired instructions and decoding the instructions. If the instruction is identified as a RISC-V vector instruction, the decoding information and the register configuration information of the vector state are extracted.

[0116] The thread scheduling module 320 is responsible for receiving the register configuration information of the decoding information and the vector status, performing thread scheduling according to the current thread execution status, controlling the thread memory access module 330 to perform memory access tasks and the thread operation module 340 to perform operation tasks, and is responsible for the delivery of instructions and the writing back of results when the instructions are executed.

[0117] The thread memory access module 330 is controlled by the thread scheduling module 320, exposes its own state to the thread scheduling module 320, receives thread scheduling information issued by the thread scheduling module 320, performs corresponding memory access tasks according to the thread scheduling information, and writes the results back to the vector register or memory.

[0118] The thread operation module 340 is controlled by the thread scheduling module 320, exposes its own state to the thread scheduling module 320, receives thread scheduling information issued by the thread scheduling module 320, performs corresponding operation tasks according to the thread scheduling information, and writes the results back to the vector register.

[0119] The vector register is independent of the general register and is used specifically to store the results of RISC-V vector instructions. It can be written back and accessed by the thread operation module 340 and the thread memory access module 330.

[0120] Furthermore, the thread scheduling module 320 includes a thread allocation control unit, a thread cache unit and a correlation determination unit.

[0121] The thread allocation control unit will make thread scheduling judgments based on the decoding information, register configuration information of the vector state, the current execution state and the data correlation state. When there is no pipeline blockage or the read / write / operation module corresponding to the current instruction type is in an idle state and there is no correlation dependency, thread scheduling is performed to control the thread memory access module 330 and the thread operation module 340 to perform corresponding tasks. At the end of the thread task, the instruction delivery judgment is performed. If the current instruction is a single-threaded task or the current execution thread is the last thread, the instruction delivery module is controlled to write back the instruction.

[0122] The thread cache unit records the thread scheduling information and current execution status of the executing instruction, and processes the thread information of the instruction in a first-in-first-out queue each time the thread task of the instruction is assigned and the instruction is delivered. The thread information of the instruction is internally updated at the end of each thread execution of the instruction without changing the queue status. The thread cache unit provides information to assist the operation of the thread allocation control unit.

[0123] The correlation judgment unit is a first-in-first-out queue that records the index of data that has not yet been written back. When there is a data correlation conflict, the corresponding enable signal will be pulled low to prevent the scheduling of the current thread.

[0124] Furthermore, the thread memory access module 330 includes an address generation unit, a data processing unit and a bus interface unit.

[0125] The address generation unit is responsible for receiving thread allocation information and calculating the actual target address for use by the bus interface unit when there is a memory access task.

[0126] The data processing unit is responsible for receiving thread allocation information, converting vector element data and bus read / write data when there is a memory access task, and writing data that needs to be written into the vector register.

[0127] The bus interface unit is responsible for receiving thread allocation information, and when there is a memory access task, it implements data transmission with the memory through the valid-ready handshake protocol. The length of the bus interface allows custom configuration and is exposed to the thread scheduling module 320 for thread scheduling.

[0128] Furthermore, the thread operation module 340 is an operation array composed of a plurality of operation units, which can execute vector tasks in parallel. The number of operation units allows for custom configuration and is exposed to the thread scheduling module 320 for thread scheduling.

[0129] In the actual implementation process, the number of thread operation units can be traded off between the bus width / VLEN and the maximum value of LUML. The more thread operation units there are, the stronger the single-thread operation performance can be supported, which is suitable for programs with low memory access density and high operation density; the fewer thread operation units there are, the higher the hardware utilization of the operation components, reducing unnecessary overhead, which is suitable for programs with high memory access density and low operation density.

[0130] The present invention avoids the problem of memory access bottleneck leading to waste of computing resources and performance degradation faced by traditional hardware parallel computing architecture by introducing a thread scheduling module. Fine-grained multi-thread scheduling is used to decompose instruction tasks that cannot be completed at one time into thread tasks that can be completed at one time, and multi-thread interleaved execution is achieved through hardware pipeline arrangement, avoiding the limitation of computing power by memory access capacity, and can effectively improve the execution performance of vector instructions under the limitation of memory access performance, thereby improving the overall computing performance.

[0131] The beneficial effects that can be achieved by the present invention may at least include:

[0132] 1) The biggest problem faced by traditional hardware parallel computing architecture is the memory access performance bottleneck. The computing power is limited by the slow memory access speed, resulting in a waste of computing resources and performance degradation. The present invention introduces a thread scheduling module, which decomposes instruction tasks that cannot be completed at one time into thread tasks that can be completed at one time through fine-grained multi-thread scheduling, and implements multi-thread interleaved execution through hardware pipeline arrangement, avoiding the limitation of computing power by memory access capacity, and can effectively improve the execution performance of vector instructions under the limitation of memory access performance, thereby improving the overall computing performance.

[0133] 2) The present invention is flexible to use. Since it is not necessary to perform operations on all elements of a vector at a time, the maximum number of processing elements of a single thread can be customized, and then the number of computing units in the computing hardware can be customized. By limiting the hardware scale, the hardware redundancy problem is reduced most of the time, thereby achieving resource conservation and power consumption reduction.

[0134] 3) Compared with the traditional implementation, the present invention only adds a thread scheduling module, does not require major changes to the hardware architecture, has low implementation difficulty and low cost, conforms to the flexible and low-cost characteristics of the RISC-V architecture itself, and has high scalability.

[0135] The following diagram illustrates the beneficial effects of shared memory in this solution:

[0136] like Figure 4As shown in the figure, in the case of memory access performance bottleneck, the ordinary vector implementation architecture needs to wait for the data to be fully prepared after multiple memory access requests are completed, and then send the data to the operation unit; in the case of the existence of a thread scheduling module, hardware pipeline arrangement can be implemented, and the instruction tasks that cannot be completed at one time are decomposed into thread tasks that can be completed at one time through fine-grained multi-thread scheduling. After the data of a single thread task is completed, the operation can be performed immediately without waiting for all the data to be prepared. This greatly improves the operation efficiency in the case of complex operation tasks; taking the bus width of 128bit, the access cycle of 10clks, the multiplication operation cycle of 4clks, and 16 32-bit vector multiplication and addition operations as an example, the ordinary vector implementation architecture needs to complete the data reading at the 40th clk, and the 45th clk can accept new operation requests; while the hardware pipeline arrangement solution can complete the first step of data reading at the 10th clk, and accept new operation requests at the 15th clk; this greatly improves the hardware utilization and actual operation performance.

[0137] The present invention provides a RISC-V vector optimization method and device based on thread scheduling, introduces a thread scheduling module between a decoding module and an execution unit, executes RISC-V vector instructions in a time-sharing manner through thread scheduling, optimizes the pipeline arrangement problem of a traditional single instruction multiple data execution structure, masks pipeline blockage through multi-thread interleaved execution, improves overall computing performance, reduces computing hardware overhead, and implements a low-cost, high-performance RISC-V vector processor, which is essentially a balance between performance and area. While other alternatives require a larger area overhead while providing the same parallel computing capability, the present invention can maximize the use of hardware resources under the same area to achieve higher performance.

[0138] Based on the same idea, the embodiment of this specification also provides a RISC-V vector optimization device based on thread scheduling. Figure 5 As shown, the device includes:

[0139] A memory, a processor, and a communication interface coupled to the processor; the memory stores a computer program that can be executed by the processor; when the processor runs the computer program, it executes the aforementioned RISC-V vector optimization method based on thread scheduling.

[0140] like Figure 5As shown, the processor may be a general-purpose central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present invention. The communication interface may be one or more. The communication interface may use any transceiver-like device for communicating with other devices or communication networks.

[0141] like Figure 5 As shown, the terminal device may further include a communication line. The communication line may include a path to transmit information between the components.

[0142] Optional, such as Figure 5 As shown, the terminal device may further include a memory. The memory stores a computer program executable by the processor; when the processor executes the computer program, the method provided by the embodiment of the present invention is implemented.

[0143] like Figure 5 As shown, the memory may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory may exist independently and be connected to the processor through a communication line. The memory may also be integrated with the processor.

[0144] Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in the embodiment of the present invention.

[0145] In a specific implementation, as an example, Figure 5 As shown, the processor may include one or more CPUs, such as Figure 5 CPU0 and CPU1 in.

[0146] In a specific implementation, as an example, Figure 5 As shown, the terminal device may include multiple processors, such as Figure 5 Each of these processors can be a single-core processor or a multi-core processor.

[0147] Based on the same idea, the embodiments of this specification also provide a computer storage medium corresponding to the above embodiments, and the computer storage medium stores instructions, and when the instructions are executed, the method in the above embodiments is implemented.

[0148] The above mainly introduces the solution provided by the embodiment of the present invention from the perspective of the interaction between the various modules. It is understandable that, in order to realize the above functions, each module includes a hardware structure and / or software unit corresponding to the execution of each function. It should be easily appreciated by those skilled in the art that, in combination with the units and algorithm steps of each example described in the embodiments disclosed herein, the present invention can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0149] The embodiment of the present invention can divide the functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present invention is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0150] The processor in this specification may also have the function of a memory. The memory is used to store computer-executable instructions for executing the solution of the present invention, and the execution is controlled by the processor. The processor is used to execute the computer-executable instructions stored in the memory, thereby implementing the method provided by the embodiment of the present invention.

[0151] The memory may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), a compact disc read-only memory (CD-ROM) or other optical disc storage, optical disc storage (including compressed optical disc, laser disc, optical disc, digital versatile disc, Blu-ray disc, etc.), a magnetic disk storage medium or other magnetic storage device, or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory may exist independently and be connected to the processor through a communication line. The memory may also be integrated with the processor.

[0152] Optionally, the computer-executable instructions in the embodiment of the present invention may also be referred to as application program codes, which is not specifically limited in the embodiment of the present invention.

[0153] The method disclosed in the above embodiment of the present invention can be applied to a processor or implemented by a processor. The processor may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in the processor or an instruction in the form of software. The above processor may be a general-purpose processor, a digital signal processor (digital signal processing, DSP), an ASIC, a field-programmable gate array (field-programmable gate array, FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. The methods, steps and logic block diagrams disclosed in the embodiments of the present invention can be implemented or executed. The general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc. The steps of the method disclosed in the embodiment of the present invention can be directly embodied as being executed by a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a mature storage medium in the field such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in the memory, and the processor reads the information in the memory and completes the steps of the above method in combination with its hardware.

[0154] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "one" or "an" does not exclude multiple situations. A single processor or other unit may implement several functions listed in the claims. Certain measures are recorded in different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0155] Although the present invention has been described in conjunction with specific features and embodiments thereof, it is apparent that various modifications and combinations may be made thereto without departing from the spirit and scope of the present invention. Accordingly, this specification and the accompanying drawings are merely exemplary illustrations of the present invention as defined by the appended claims and are deemed to cover any and all modifications, variations, combinations or equivalents within the scope of the present invention. Obviously, those skilled in the art may make various modifications and variations to the present invention without departing from the spirit and scope of the present invention. Thus, the present invention is intended to include such modifications and variations if they fall within the scope of the claims of the present invention and their equivalents.

Claims

1. A RISC-V vector optimization method based on thread scheduling, characterized in that the method include: Obtain a RISC-V vector instruction, extract decoding information from the RISC-V vector instruction, and obtain register configuration information of a vector state; Determine thread scheduling information according to the decoding information, the register configuration information, the current thread execution state and the hardware configuration; Execute corresponding thread tasks according to the thread scheduling information; After the current thread task is executed, the scheduling judgment is made according to the thread status. If the thread task of the current instruction is executed, the status is updated and the current instruction is delivered; if there are still thread tasks that have not been executed for the current instruction, the status is updated and the next thread task is executed until all thread tasks are executed, the data is written back, the instruction delivery is completed, and the instruction cycle ends.

2. The RISC-V vector optimization method based on thread scheduling according to claim 1, characterized in that: The thread scheduling information includes allowing thread scheduling, not allowing thread scheduling, single thread scheduling or multi-thread scheduling; The determining thread scheduling information according to the decoding information, the register configuration information, the current thread execution state and the hardware configuration specifically includes: Perform scheduling judgment according to the decoding information and the current thread execution state to obtain a first judgment result; If the first judgment result indicates that thread scheduling is allowed, thread scheduling is performed; Perform judgment according to the hardware configuration and register configuration information to obtain a second judgment result; If the second judgment result indicates that the current instruction task can be completed in a single thread, single thread scheduling is performed; If the second judgment result indicates that the current instruction task cannot be completed in a single thread, multi-thread scheduling is performed.

3. The RISC-V vector optimization method based on thread scheduling according to claim 2 is characterized in that: Performing a scheduling judgment according to the decoding information and the current thread execution state to obtain a first judgment result includes: Perform scheduling judgment based on the decoding information and the current thread execution state to determine whether thread scheduling can be performed; When there is no pipeline blockage, the memory access unit and the computing unit are both in the ready state, and the thread scheduling of any instruction is performed at this time; When there is a pipeline blockage, determine the current instruction type and check whether the corresponding read / write / calculation module is in an idle state; If the execution module corresponding to the current instruction type is in an idle state, a correlation determination is performed; If there is no data dependency, the pipeline is switched and thread scheduling is performed for the current instruction.

4. The RISC-V vector optimization method based on thread scheduling according to claim 2, characterized in that: The second judgment result is obtained by judging according to the hardware configuration and the register configuration information, including: When it is determined that the current conditions allow thread scheduling, it is determined whether to perform multi-thread scheduling on the current instruction; For memory access instructions, if the bus width of the memory access resource is greater than the product of the number of vector registers and the bit width of the vector register, it is determined that the current instruction can be executed in a single thread and single-thread scheduling is performed; otherwise, multi-thread scheduling is performed, the current instruction task is decomposed into multiple thread tasks, and the first thread task is thread scheduled in the current cycle; For operation instructions, if the number of operation units of the operation resources is greater than the number of vector elements, it is determined that the current instruction can be executed within a single thread and single-thread scheduling is performed; otherwise, multi-thread scheduling is performed, and the current instruction task is decomposed into multiple thread tasks, and the first thread task is scheduled in the current cycle.

5. The RISC-V vector optimization method based on thread scheduling according to claim 2, characterized in that: The executing the corresponding thread task according to the thread scheduling information includes: When there is a memory access task that needs to be executed, the thread memory access module is enabled, generates addresses and processes data according to the configuration information provided by the thread scheduling module, and realizes data transmission with the memory through the bus interface; When there is a computing task that needs to be executed, the thread computing module is enabled, and a corresponding number of computing units are enabled according to the configuration information provided by the thread scheduling module, the corresponding computing type is executed, and the result is written back to the register.

6. The RISC-V vector optimization method based on thread scheduling according to claim 5, characterized in that: For the single-thread scheduling, the thread scheduling module dispatches the current instruction task to the corresponding execution unit; For the multi-thread scheduling, the thread scheduling module divides the instruction task into a plurality of sub-thread tasks, and the sub-thread tasks can be executed and completed at one time; The first thread task in the sub-thread tasks is dispatched, the thread tasks other than the first thread task in the sub-thread tasks are cached, and the thread status is updated each time the thread execution is completed until all threads are executed.

7. The RISC-V vector optimization method based on thread scheduling according to claim 6, characterized in that: The updating of the thread status includes updating the thread execution status and the data correlation queue status; After the current thread task is executed, a scheduling judgment is performed according to the thread state. If the thread task of the current instruction is executed, the state is updated and the current instruction is delivered, including: For a single-thread instruction, after the thread task is completed, it is assumed that the instruction has been executed, and the thread execution status and data correlation status monitoring of the instruction are canceled. The thread scheduling module is responsible for delivering the current instruction and writing back the result; For multi-threaded instructions, the thread scheduling module updates the thread execution status and data correlation status of the instruction, and determines whether the current thread is the last thread of the instruction. If so, the thread execution status and data correlation status monitoring of the instruction are canceled, and the thread scheduling module is responsible for delivering the current instruction and writing back the result when necessary; otherwise, the next thread task of the instruction is dispatched until all thread tasks are executed.

8. A RISC-V vector optimization device based on thread scheduling, characterized in that: The device includes: Instruction decoding module, thread scheduling module, thread memory access module and thread operation module; The instruction decoding module is used to obtain RISC-V vector instructions, extract decoding information from the RISC-V vector instructions, and obtain register configuration information of the vector state; The thread scheduling module is used to determine thread scheduling information according to the decoding information, the register configuration information, the current thread execution state and the hardware configuration; The thread operation module is used to execute the corresponding thread task according to the thread scheduling information; The thread memory access module is used to execute corresponding memory access tasks according to thread scheduling information, and write the results back to the vector register or memory after all thread tasks are executed.

9. A RISC-V vector optimization device based on thread scheduling, characterized in that the device include: A memory, a processor, and a communication interface coupled to the processor; The memory stores a computer program executable by the processor; When the processor runs the computer program, it executes the RISC-V vector optimization method based on thread scheduling as described in any one of claims 1 to 7.

10. A computer storage medium, characterized in that: The computer storage medium stores instructions, and when the instructions are executed, the RISC-V vector optimization method based on thread scheduling described in any one of claims 1 to 7 is implemented.

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