Method, device and equipment for configuring FPGA (Field Programmable Gate Array) and storage medium

Abstract

The invention provides a method, a device and equipment for configuring an FPGA (Field Programmable Gate Array) and a storage medium. The method comprises the following steps: acquiring an initial configuration parameter set; configuring the ith FPGA based on the ith initial configuration parameter to obtain an ith first intermediate FPGA; the ith first intermediate FPGA is used for executing the function of the ith preset module; operating each first intermediate FPGA to obtain a first original time delay; the first original time delay indicates a first critical path; adjusting the first database time delay to obtain a first adjustment time delay; adjusting the second database time delay to obtain a second adjustment time delay; and based on the first adjustment time delay, the second adjustment time delay and the i-th initial configuration parameter, configuring the i-th first intermediate FPGA to obtain the i-th first target FPGA. According to the technical scheme of the invention, the invalid time of workers can be shortened, and the verification efficiency of the SoC is improved.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a method, device, equipment and storage medium for configuring an FPGA. Background Art

[0002] When verifying a SoC (System on Chip) based on a Field Programmable Gate Array (FPGA), the complete SoC is usually divided into multiple modules and deployed on multiple FPGAs due to the resource limitations of the FPGA.

[0003] In the related art, in the process of dividing the SoC into multiple modules and deploying them on multiple FPGAs, it is completely dependent on automatic segmentation tools and comprehensive implementation software for planning and completing tasks such as synthesis, segmentation, layout, and routing.

[0004] However, automatic segmentation tools usually need to combine various synthesis, placement, and routing strategies, and execute them through iteration until a certain strategy combination meets expectations; therefore, automatic segmentation tools need to iterate countless times to find the optimal timing strategy, and thus cannot quickly find the best solution. Each iteration requires recompiling the netlist, which will waste a lot of ineffective time for the staff and reduce verification efficiency. Summary of the invention

[0005] The embodiment of the present application provides a method, device, equipment and storage medium for configuring an FPGA, which can shorten the ineffective time of staff and thus improve the verification efficiency. The technical solution is as follows:

[0006] According to a first aspect of an embodiment of the present application, a method for configuring an FPGA is provided, characterized by comprising:

[0007] Acquire an initial configuration parameter set; the initial configuration parameter set includes a plurality of initial configuration parameters; the initial configuration parameters correspond one-to-one to the preset modules in the SoC; the initial configuration parameters describe the function and timing of the preset modules;

[0008] The i-th FPGA is configured based on the i-th initial configuration parameter to obtain the i-th first intermediate FPGA; the i-th first intermediate FPGA is used to execute the function of the i-th preset module; i is an integer greater than or equal to 1;

[0009] Run each of the first intermediate FPGAs to obtain a first original delay; the first original delay indicates a first critical path; the first critical path indicates the kth first intermediate FPGA and the fth first intermediate FPGA; the first original delay includes a first database delay and a second database delay; the first database delay indicates the delay of the kth first intermediate FPGA transmitting data; the second database delay indicates the delay of the fth first intermediate FPGA transmitting the data; k, f are integers greater than or equal to 1, and k is not equal to f;

[0010] Adjusting the first database delay to obtain a first adjusted delay; and adjusting the second database delay to obtain a second adjusted delay;

[0011] Based on the first adjustment delay, the second adjustment delay, and the i-th initial configuration parameter, the i-th first intermediate FPGA is configured to obtain the i-th first target FPGA.

[0012] In a possible implementation, obtaining the initial configuration parameter set includes:

[0013] The code file of the SoC is divided to obtain the initial configuration parameter set; each of the initial configuration parameters includes a code block of the code file.

[0014] In a possible implementation, the first database delay indicates the delay of the data being transmitted between a first target database trigger and a first target input / output pin; the second database delay indicates the delay of the data being transmitted between a second target database trigger and a second input / output pin;

[0015] The database trigger is generated based on the code; the first target input and output pins are set in the kth first intermediate FPGA; the second target input and output pins are set in the fth first intermediate FPGA.

[0016] In a possible implementation, the first original delay further includes a board-level delay; the board-level delay indicates the delay of transmitting the data between the first target input / output pin and the second target input / output pin.

[0017] In a possible implementation, the adjusting the first database delay to obtain a first adjusted delay; and adjusting the second database delay to obtain a second adjusted delay include:

[0018] Taking the ratio between the first database delay and the second database delay as the target ratio;

[0019] The difference between the preset delay and the board-level delay is used as the target difference;

[0020] Based on the target ratio and the target difference, the first adjustment delay and the second adjustment delay are obtained; the ratio of the first adjustment delay and the second adjustment delay is the target ratio; and the sum of the first adjustment delay and the second adjustment delay is the target difference.

[0021] In a possible implementation, the method further includes:

[0022] Get trigger parameters;

[0023] The i-th FPGA is configured based on the trigger parameters and the i-th initial configuration parameters to obtain the i-th second intermediate FPGA; the input-output unit in the second intermediate FPGA is provided with a plurality of physical triggers and a plurality of input-output pins; the input-output pins correspond one-to-one to the physical triggers; i is an integer greater than or equal to 1.

[0024] In a possible implementation, each of the second intermediate FPGAs is run to obtain a second original delay; the second original delay indicates a second critical path; the second critical path indicates the mth second intermediate FPGA and the nth second intermediate FPGA; the second original delay includes a first physical delay and a second physical delay;

[0025] The first physical delay indicates the delay of the data being transmitted between the first target physical trigger and the first target input / output pin; the second physical delay indicates the delay of the data being transmitted between the second target physical trigger and the fourth input / output pin;

[0026] The first target physical trigger and the first target input-output pin are set in the mth second intermediate FPGA; the second target physical trigger and the fourth input-output pin are set in the nth second intermediate FPGA; m, n are integers greater than or equal to 1, and m is not equal to n.

[0027] In a possible implementation, the method further includes:

[0028] Adjusting the first physical delay to obtain a third adjusted delay; and adjusting the second physical delay to obtain a fourth adjusted delay;

[0029] Based on the third adjustment delay, the fourth adjustment delay and the i-th initial configuration parameter, the i-th second intermediate FPGA is configured to obtain the i-th second target FPGA.

[0030] According to a second aspect of an embodiment of the present application, a device for configuring an FPGA is provided, the device comprising:

[0031] An acquisition module, used to acquire an initial configuration parameter set; the initial configuration parameter set includes a plurality of initial configuration parameters; the initial configuration parameters correspond one-to-one to the preset modules in the SoC; the initial configuration parameters describe the function and timing of the preset modules;

[0032] A first configuration module, configured to configure an i-th FPGA based on the i-th initial configuration parameter to obtain an i-th first intermediate FPGA; the i-th first intermediate FPGA is used to execute the function of the i-th preset module; i is an integer greater than or equal to 1;

[0033] An operation module is used to operate each of the first intermediate FPGAs to obtain a first original delay; the first original delay indicates a first critical path; the first critical path indicates the kth first intermediate FPGA and the fth first intermediate FPGA; the first original delay includes a first database delay and a second database delay; the first database delay indicates the delay of the kth first intermediate FPGA transmitting data; the second database delay indicates the delay of the fth first intermediate FPGA transmitting the data; k, f are integers greater than or equal to 1, and k is not equal to f;

[0034] An adjustment module, configured to adjust the first database delay to obtain a first adjusted delay; and adjust the second database delay to obtain a second adjusted delay;

[0035] The second configuration module is used to configure the i-th first intermediate FPGA based on the first adjustment delay, the second adjustment delay and the i-th initial configuration parameter to obtain the i-th first target FPGA.

[0036] According to a third aspect of an embodiment of the present application, a computer device is provided, comprising a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor and executes the method for configuring an FPGA as described above.

[0037] According to a fourth aspect of an embodiment of the present application, a computer-readable storage medium is provided, wherein at least one program is stored in the computer-readable storage medium, and the at least one program is loaded and executed by a processor to implement the method for configuring an FPGA as described above.

[0038] In an embodiment of the present application, an embodiment of the present application provides a method for configuring an FPGA, configuring the FPGA based on initial configuration parameters to obtain a first intermediate FPGA; the first intermediate FPGA is used to execute the function of a preset module of the SoC; running each first intermediate FPGA to obtain a first original delay; the first original delay indicates a first critical path; adjusting the first database delay to obtain a first adjusted delay; and adjusting the second database delay to obtain a second adjusted delay; configuring the first intermediate FPGA based on the first adjusted delay, the second adjusted delay and the initial configuration parameters to obtain a first target FPGA. The above technical solution can quickly find the first critical path, shorten the delay of the first critical path, and obtain the optimal strategy, greatly reducing the number of iterations, thereby reducing the number of times the netlist is compiled, thereby greatly shortening the ineffective time of the staff and improving the verification efficiency of the SoC. In addition, the technical solution of the present application sets timing constraints, reduces delays, and thereby improves the performance of the prototype verification system. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0040] Figure 1 is a schematic diagram of an implementation environment provided according to an embodiment of the present application;

[0041] Figure 2 It is a flowchart of a first method for configuring an FPGA provided in an embodiment of the present application;

[0042] Figure 3 is a schematic diagram of a first original delay provided according to an embodiment of the present application;

[0043] Figure 4 is a flow chart of step 204 provided according to an embodiment of the present application;

[0044] Figure 5 It is a flowchart of a second method for configuring an FPGA provided in an embodiment of the present application;

[0045] Figure 6 It is a structural schematic diagram of a device for configuring FPGA provided according to an embodiment of the present application;

[0046] Figure 7 is a schematic diagram of the structure of a terminal provided according to an embodiment of the present application;

[0047] Figure 8It is a structural diagram of a server provided according to an embodiment of the present application. DETAILED DESCRIPTION

[0048] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0049] Here, exemplary embodiments are described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0050] In this application, the terms "first", "second", etc. are used to distinguish between identical or similar items with substantially the same effects and functions. It should be understood that there is no logical or temporal dependency between "first", "second", and "nth", nor is there a limitation on the quantity and execution order. It should also be understood that although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms.

[0051] These terms are only used to distinguish one element from another element. For example, without departing from the scope of various examples, a first action can be referred to as a second action, and similarly, a second action can also be referred to as a first action. Both the first action and the second action can be actions, and in some cases, can be separate and different actions.

[0052] Here, at least one means one or more than one, for example, at least one action can be one action, two actions, three actions, or any other action that is an integer greater than or equal to one. And multiple means two or more than two, for example, multiple actions can be two actions, three actions, or any other action that is an integer greater than or equal to two.

[0053] Figure 1 It is a schematic diagram of an implementation environment provided according to an embodiment of the present application, and the implementation environment may include a terminal 101 and a server 102.

[0054] A preset tool is provided in the terminal 101. The preset tool is used to divide the code file of the SoC into multiple code blocks.

[0055] The terminal 101 may be a smart phone with preset tools, a wearable device, a personal computer, a laptop, a tablet computer, a smart TV, a car terminal, etc.

[0056] The server 102 may be a single server, a server cluster consisting of multiple servers, or a cloud processing center.

[0057] The terminal 101 is connected to the server 102 via a wired or wireless network.

[0058] In some embodiments, the wireless network or wired network uses standard communication technology and / or protocol. The network is usually the Internet, but it can also be any network, including but not limited to any combination of local area network (LAN), metropolitan area network (MAN), wide area network (WAN), mobile, wired or wireless network, private network or virtual private network. In some embodiments, the data exchanged through the network is represented by technology and / or format including HyperText Mark-up Language (HTML), Extensible Markup Language (XML), etc. In addition, conventional encryption technologies such as Secure Socket Layer (SSL), Transport Layer Security (TLS), Virtual Private Network (VPN), Internet Protocol Security (IPsec) can also be used to encrypt all or some links. In other embodiments, customized and / or dedicated data communication technology can also be used to replace or supplement the above data communication technology.

[0059] In the related art, since the resources of an FPGA are limited and cannot carry all the functions of a complete SoC, in the process of verifying the SoC, due to the resource limitations of the FPGA, it is usually chosen to divide the complete SoC into multiple modules and deploy them on multiple FPGAs. The multiple deployed FPGAs are run to realize the simulation of the SoC; the multiple deployed FPGAs can represent the verification system.

[0060] In the process of splitting SoC into multiple modules and deploying them on multiple FPGAs, we completely rely on automatic segmentation tools and comprehensive implementation software for planning and completing tasks such as synthesis, segmentation, layout, and routing. However, automatic segmentation tools usually need to combine various synthesis, layout, and routing strategies, and execute them through traversal until a certain strategy combination meets expectations. Therefore, the automatic segmentation tool needs to iterate countless times to find the optimal strategy, and thus cannot quickly find the best solution. Each iteration requires recompiling the netlist, which will cost the staff a lot of ineffective time and reduce verification efficiency. Or it will result in low FPGA resource utilization and poor operating performance. Simulating SoC based on FPGAs with low operating performance often affects subsequent verification convergence tasks and may even prevent software development work from proceeding smoothly.

[0061] In addition, if the SoC is divided into multiple modules and deployed on multiple FPGAs by manual settings, that is, the SoC is divided manually and detailed timing constraints are set for the data path on each independent FPGA. However, the manual method increases the workload and is prone to errors during the setting process.

[0062] In order to solve the above technical problem, an embodiment of the present application provides a method for configuring an FPGA.

[0063] Figure 2 is a flowchart of a first method for configuring an FPGA according to an embodiment of the present application, such as Figure 2 As shown, in the embodiment of the present application, the method is described by taking application on a terminal with a preset tool as an example. The method comprises the following steps:

[0064] In step 201, the terminal obtains an initial configuration parameter set; the initial configuration parameter set includes a plurality of initial configuration parameters; the initial configuration parameters correspond one-to-one to the preset modules in the SoC; the initial configuration parameters describe the functions and timing of the preset modules.

[0065] Among them, timing can be understood as the layout and wiring of preset modules.

[0066] In some embodiments, the SoC may include multiple modules such as a CPU (Central Processing Unit) and an NPU (Neural Processing Unit).

[0067] It should be noted that the initial configuration parameters also describe other conventional features of the preset module, which will not be described in detail in the embodiments of the present application.

[0068] In some embodiments, the above step 201 can be implemented as follows:

[0069] The code file of the SoC is divided to obtain an initial configuration parameter set; each initial configuration parameter includes a code block of the code file.

[0070] It is important to understand that the code file includes multiple lines of code, and running these multiple lines of code can realize all the functions of the SoC.

[0071] In some embodiments, the code file is divided into code blocks, each of which is used to describe the function and timing of a preset module.

[0072] In one example, the code file of the SoC is segmented based on a preset tool. The preset tool is a tool with a function of segmenting the code file. It should be noted that the preset tool can be obtained from the relevant technology, and the embodiments of the present application will not be described in detail.

[0073] In one example, each segmentation position of the code file may be determined manually to obtain multiple code blocks.

[0074] For example, a code block of multiple lines of code is used to describe the function and timing of a CPU (Central Processing Unit).

[0075] For another example, a preset configuration parameter may also be used to describe a portion of the functions and timing of a CPU, where a portion of the CPU is a preset module in the SoC.

[0076] In other words, the functions carried by each preset module can be divided according to actual needs.

[0077] In step 202, the terminal configures the i-th FPGA based on the i-th initial configuration parameter to obtain the i-th first intermediate FPGA; the i-th first intermediate FPGA is used to execute the function of the i-th preset module; i is an integer greater than or equal to 1.

[0078] In some embodiments, the initial configuration parameter set is compiled into an FPGA netlist based on a compilation tool, and the compilation tool transmits the FPGA netlist to each FPGA; each FPGA completes configuration based on the FPGA netlist to obtain multiple first intermediate FPGAs. For example, the compilation tool is EDA (Electronic Design Automation).

[0079] It is important to understand that a netlist is a file that describes the connections between circuit elements. It is a blueprint or framework for a logic circuit, usually consisting of a series of interconnected gates (such as AND gates, OR gates, NOT gates, etc.) and basic logic units such as triggers. This netlist file is usually a text file that follows a preset tag syntax and is used to guide subsequent layout and routing processes.

[0080] In some embodiments, after each FPGA is configured, the internal layout and routing, as well as the layout and routing between each first intermediate FPGA are automatically completed based on the timing-related parameters of each preset module, thereby completing the mapping of various functions of the SoC to multiple FPGAs.

[0081] Figure 3 This is a schematic diagram of a first original delay provided according to an embodiment of the present application.

[0082] Combine the following Figure 3 The first original delay is exemplarily described.

[0083] In step 203, the terminal runs each first intermediate FPGA to obtain a first original delay; the first original delay indicates a first critical path; the first critical path indicates the kth first intermediate FPGA and the fth first intermediate FPGA; the first original delay includes a first database delay and a second database delay; the first database delay indicates the delay of the kth first intermediate FPGA transmitting data; the second database delay indicates the delay of the fth first intermediate FPGA transmitting data; k, f are integers greater than or equal to 1, and k is not equal to f.

[0084] Here, the path can also be understood as a circuit.

[0085] In some embodiments, after powering on multiple first intermediate FPGAs, each first intermediate FPGA can simulate corresponding functions in the SoC based on the configured initial configuration parameters, thereby simulating all functions of the SoC, and further verifying the complete SoC based on multiple FPGAs.

[0086] In some embodiments, the first database latency indicates a latency for data to be transmitted between a first target database trigger and a first target input / output pin; the second database latency indicates a latency for data to be transmitted between a second target database trigger and a second input / output pin;

[0087] The database trigger is generated based on the code; the first target input and output pins are set in the kth first intermediate FPGA; and the second target input and output pins are set in the fth first intermediate FPGA.

[0088] The code file includes a BLE (Basic Logic Element), which includes multiple database triggers, some of which are related to input and output pins, that is, these database triggers are used to interact with the input and output pins for data.

[0089] For example, BLE includes 1000 database triggers, of which 100 database triggers are used to interact with input and output pins for data.

[0090] In some embodiments, the first original delay further includes a board-level delay; the board-level delay indicates the delay of data transmission between the first target input / output pin and the second target input / output pin.

[0091] It should be understood that when configuring the i-th FPGA based on the i-th initial configuration parameters, no timing constraints are imposed, so when running multiple first intermediate FPGAs, the database trigger in the first intermediate FPGA randomly selects a data transmission path when interacting with the input and output pins. Therefore, there may be a long delay, which will seriously reduce the performance of the prototype verification system.

[0092] In some embodiments, during the operation of multiple first intermediate FPGAs, multiple data transmission paths are included; each path has a delay in transmitting data. Multiple paths are included inside the first intermediate FPGA, and multiple paths also exist when data is transmitted between different first intermediate FPGAs. The first critical path is the path with the largest combinational logic delay in the synchronous logic circuit. That is, the first original delay corresponding to the first critical path is the largest compared to the delays of all other paths. Therefore, the first critical path has a decisive influence on the performance of the prototype verification system.

[0093] In one example, a group of input / output pins and a database trigger in a first intermediate FPGA are used as an example for explanation. Specifically, since there is no timing constraint, the preset tool defaults that the time between data transmission from the input / output pin to the database trigger is one clock cycle on the path. After the first intermediate FPGA is powered on, data will be exchanged between the input / output pin and the database trigger, but the input / output pin may randomly select a path to interact with the database trigger as long as the data transmission is completed within one clock cycle; but in fact, for some paths, the time required for data transmission from the input / output pin to the database trigger is much less than one clock cycle, so the default time of the preset tool will limit the performance of the prototype system.

[0094] It is understandable that the first critical path is generally used for the transmission of data across FPGAs. That is, one end of the first critical path is the first target database trigger, and the other end of the first critical path is the second target database trigger. In the kth first intermediate FPGA, the first target database trigger interacts with the first target input and output pin. In the fth first intermediate FPGA, the second database trigger interacts with the second target input and output pin. Between the kth first intermediate FPGA and the fth first intermediate FPGA, the first target input and output pin interacts with the second target input and output pin.

[0095] In order to improve the performance of the prototype verification system, the embodiment of the present application reduces the delay inside the first intermediate FPGA by setting timing constraints. That is, for the inside of the first intermediate FPGA, the delay between data transmission from the input and output pins to the database trigger is shortened, which can shorten the verification time, thereby improving the verification efficiency and further improving the overall performance of the prototype verification system.

[0096] It can be understood that since the data transmission rate in the path is known, the length of the path, that is, the physical length of the wiring, is also known. Therefore, the first database delay, the second database delay, and the board-level delay can all be calculated. Among them, the data transmission rate is the number of bits transmitted in the path per second.

[0097] For example: data transmission delay = path length / data transmission rate.

[0098] Based on the above formula, the preset tool can calculate the first database delay, the second database delay and the board-level delay.

[0099] In addition, through the analysis of the above step 203, it can be known that the embodiment of the present application can quickly determine the first critical path without multiple iterations, thereby greatly reducing the number of times the netlist is compiled, thereby greatly reducing the workload of the staff and improving verification efficiency.

[0100] In step 204, the terminal adjusts the first database delay to obtain a first adjusted delay; and adjusts the second database delay to obtain a second adjusted delay.

[0101] It should be understood that since the board-level delay is the delay for data to reach the second target input / output pin of the f-th first intermediate FPGA from the first target input / output pin of the k-th first intermediate FPGA. The wiring and layout between FPGAs are fixed, so the board-level delay is fixed, so the embodiment of the present application does not adjust the board-level delay. The first database delay and the second database delay are both the delays for transmitting data between the input / output pins inside the first intermediate FPGA and the database trigger, so they can be adjusted. Therefore, the embodiment of the present application chooses to adjust the second database delay and the second database delay, thereby shortening the first original delay.

[0102] Figure 4 It is a flowchart of step 204 provided according to an embodiment of the present application.

[0103] Combine the following Figure 4 Step 204 is exemplarily described.

[0104] It should be understood that the distribution of the total allowed path delay among the first intermediate FPGAs is proportional to the share of each first intermediate FPGA in the total path delay. Therefore, if a first intermediate FPGA accounts for a larger share of the total path delay, the layout and routing of the first intermediate FPGA should also be subject to looser constraints, that is, the first intermediate FPGA should be allocated more delay during the delay adjustment process.

[0105] In some embodiments, the above step 204 includes the following steps 2041 to 2043:

[0106] In step 2041, the terminal uses the ratio between the first database delay and the second database delay as a target ratio.

[0107] In step 2042, the terminal uses the difference between the preset delay and the board-level delay as the target difference.

[0108] In step 2043, the terminal obtains a first adjustment delay and a second adjustment delay based on the target ratio and the target difference; the ratio of the first adjustment delay and the second adjustment delay is the target ratio; and the sum of the first adjustment delay and the second adjustment delay is the target difference.

[0109] The preset delay is set according to actual needs, and the preset delay is smaller than the first original delay. For example, the preset delay is 100 ns.

[0110] In some embodiments, the target difference is allocated based on the target ratio to obtain a first adjustment delay and a second adjustment delay. The timing is constrained by the first adjustment delay and the second adjustment delay, thereby shortening the internal delay of the kth first intermediate FPGA and the internal delay of the fth first intermediate FPGA.

[0111] For example, the first original delay is 150ns, wherein the first database delay is 80ns, the second database delay is 20ns, and the board-level delay is 50ns.

[0112] The preset delay is 100ns, the board-level delay is fixed; the target ratio is 4:1; the target difference is 50ns. Therefore, the first adjusted delay is 40ns, the second adjusted delay is 10ns, and the preset delay is 100ns. That is, the preset delay is less than the first original delay.

[0113] The clock period corresponding to the first original delay is 1 / 150ns=6.67MHz;

[0114] The clock period corresponding to the preset delay is 1 / 100ns=10MHz.

[0115] Through the analysis of the above step 204, it can be known that the optimal timing strategy, or the timing strategy actually required, can be obtained by simply determining the first critical path, then adding timing constraints, and shortening the first original delay. After shortening the first original delay, the clock cycle becomes faster, which improves the verification efficiency and the overall performance of the prototype verification system.

[0116] In step 205, the terminal configures the i-th first intermediate FPGA based on the first adjustment delay, the second adjustment delay, and the i-th initial configuration parameter to obtain the i-th first target FPGA.

[0117] That is, the i-th first target FPGA includes timing constraints.

[0118] In some embodiments, for the first target database trigger and the first target input and output pin, when data is transmitted, due to the constraint of the first adjustment delay, a shorter path will be selected for data transmission, thereby reducing the delay inside the kth first target FPGA.

[0119] For the second target database trigger and the second target input and output pin, when data is transmitted, due to the constraint of the second adjustment delay, a shorter path will be selected for data transmission, thereby reducing the delay inside the f-th first target FPGA.

[0120] In the embodiment of the present application, the FPGA is configured based on the initial configuration parameters to obtain the first intermediate FPGA; the first intermediate FPGA is used to execute the function of the preset module of the SoC; each first intermediate FPGA is run to obtain the first original delay; the first original delay indicates the first critical path; the first database delay is adjusted to obtain the first adjusted delay; and the second database delay is adjusted to obtain the second adjusted delay; based on the first adjusted delay, the second adjusted delay and the initial configuration parameters, the first intermediate FPGA is configured to obtain the first target FPGA. The above technical solution can quickly find the first critical path, shorten the delay of the first critical path, and obtain the optimal strategy, which greatly reduces the number of iterations, thereby reducing the number of times the netlist is compiled, thereby greatly shortening the ineffective time of the staff and improving the verification efficiency of the SoC. In addition, the technical solution of the present application sets timing constraints, reduces delays, and thereby improves the performance of the prototype verification system.

[0121] Figure 5 is a flow chart of a second method for configuring an FPGA according to an embodiment of the present application, such as Figure 5 As shown, in the embodiment of the present application, the method is described by taking application on a terminal with a preset tool as an example. The method comprises the following steps:

[0122] In step 501, the terminal obtains an initial configuration parameter set; the initial configuration parameter set includes a plurality of initial configuration parameters; the initial configuration parameters correspond one-to-one to the preset modules in the SoC; the initial configuration parameters describe the functions and timing of the preset modules.

[0123] In step 502, the terminal obtains trigger parameters.

[0124] It can be understood that an input-output unit is provided in the FPGA, and a plurality of physical triggers are provided in the input-output unit, that is, these physical triggers are part of the FPGA and are hardware.

[0125] However, when the database trigger is called, these physical triggers will be put on hold, that is, these physical triggers will not be used, thus causing the physical trigger resources to be wasted.

[0126] Therefore, by adding trigger parameters, the database triggers related to the input and output pins are mapped to these physical triggers, that is, these physical triggers are used to interact with the input and output pins in the input and output units for data, thereby improving the resource utilization of the FPGA.

[0127] In one example, the trigger parameters may be obtained from a data sheet. Alternatively, the trigger parameters may be added manually.

[0128] For example, the trigger parameter is define_global_attribute{syn_useioff}{true}. This trigger parameter is used to map the database trigger to the physical trigger of the input and output unit; and these physical triggers correspond to the input and output pins one by one.

[0129] It should be noted that each preset module needs to include a database trigger before it can be divided into an independent module. If a module does not include a database trigger, the module needs to be mapped to a second intermediate FPGA together with other modules including a database trigger, and the database trigger will be mapped to the physical trigger of the second intermediate FPGA, thereby improving the resource utilization of the second intermediate FPGA.

[0130] In one example, a group of input / output pins and a physical trigger are used as an example to explain data interaction. Specifically, the input / output pin obtains data, sends the data to the physical trigger, and the physical trigger stores the data. Or the input / output pin obtains data from the physical trigger and then outputs the data.

[0131] In step 503, the terminal configures the i-th FPGA based on the trigger parameters and the i-th initial configuration parameters to obtain the i-th second intermediate FPGA; the input and output unit in the second intermediate FPGA is provided with multiple physical triggers and multiple input and output pins; the input and output pins correspond one-to-one to the physical triggers; i is an integer greater than or equal to 1.

[0132] In the above step 503, by adding trigger parameters, there is no need to manually configure each physical trigger in the FPGA one by one, which greatly simplifies the configuration process of the physical trigger.

[0133] In step 504, the terminal runs each second intermediate FPGA to obtain a second original delay; the second original delay indicates a second critical path; the second critical path indicates the mth second intermediate FPGA and the nth second intermediate FPGA; the second original delay includes a first physical delay and a second physical delay; the first physical delay indicates the delay for data to be transmitted between a first target physical trigger and a first target input / output pin; the second physical delay indicates the delay for data to be transmitted between a second target physical trigger and a fourth input / output pin; the first target physical trigger and the first target input / output pin are set in the mth second intermediate FPGA; the second target physical trigger and the fourth input / output pin are set in the nth second intermediate FPGA; m, n are integers greater than or equal to 1, and m is not equal to n.

[0134] In step 505, the terminal adjusts the first physical delay to obtain a third adjusted delay; and adjusts the second physical delay to obtain a fourth adjusted delay.

[0135] In step 506, the terminal configures the i-th second intermediate FPGA based on the third adjustment delay, the fourth adjustment delay, and the i-th initial configuration parameter to obtain the i-th second target FPGA.

[0136] The above steps 504 to 506 are similar to steps 203 to 205, and will not be described in detail in the embodiments of the present application.

[0137] In the embodiment of the present application, the FPGA is configured based on the initial configuration parameters to obtain the first intermediate FPGA; the first intermediate FPGA is used to execute the function of the preset module of the SoC; each first intermediate FPGA is run to obtain the first original delay; the first original delay indicates the first critical path; the first database delay is adjusted to obtain the first adjusted delay; and the second database delay is adjusted to obtain the second adjusted delay; based on the first adjusted delay, the second adjusted delay and the initial configuration parameters, the first intermediate FPGA is configured to obtain the first target FPGA. The above technical solution can quickly find the first critical path, shorten the delay of the first critical path, and obtain the optimal strategy, which greatly reduces the number of iterations, thereby reducing the number of times the netlist is compiled, thereby greatly shortening the ineffective time of the staff and improving the verification efficiency of the SoC. In addition, the technical solution of the present application sets timing constraints, reduces delays, and thereby improves the performance of the prototype verification system.

[0138] Figure 6 6 is a schematic diagram of a structure of a device 600 for configuring an FPGA according to an embodiment of the present application, the device comprising:

[0139] The acquisition module 601 is used to acquire an initial configuration parameter set; the initial configuration parameter set includes a plurality of initial configuration parameters; the initial configuration parameters correspond to the preset modules in the SoC one by one; the initial configuration parameters describe the functions and timing of the preset modules;

[0140] The first configuration module 602 is used to configure the i-th FPGA based on the i-th initial configuration parameter to obtain the i-th first intermediate FPGA; the i-th first intermediate FPGA is used to perform the function of the i-th preset module; i is an integer greater than or equal to 1;

[0141] The operation module 603 is used to operate each first intermediate FPGA to obtain a first original delay; the first original delay indicates a first critical path; the first critical path indicates the kth first intermediate FPGA and the fth first intermediate FPGA; the first original delay includes a first database delay and a second database delay; the first database delay indicates a delay for the kth first intermediate FPGA to transmit data; the second database delay indicates a delay for the fth first intermediate FPGA to transmit data; k, f are integers greater than or equal to 1, and k is not equal to f;

[0142] An adjustment module 604 is configured to adjust the first database delay to obtain a first adjusted delay; and adjust the second database delay to obtain a second adjusted delay;

[0143] The second configuration module 605 is used to configure the i-th first intermediate FPGA based on the first adjustment delay, the second adjustment delay and the i-th initial configuration parameter to obtain the i-th first target FPGA.

[0144] In some embodiments, the apparatus is further configured to:

[0145] The code file of the SoC is divided to obtain an initial configuration parameter set; each initial configuration parameter includes a code block of the code file.

[0146] In some embodiments, the first database latency indicates a latency for data to be transmitted between a first target database trigger and a first target input / output pin; the second database latency indicates a latency for data to be transmitted between a second target database trigger and a second input / output pin;

[0147] The database trigger is generated based on the code; the first target input and output pins are set in the kth first intermediate FPGA; and the second target input and output pins are set in the fth first intermediate FPGA.

[0148] In some embodiments, the first original delay further includes a board-level delay; the board-level delay indicates the delay of data transmission between the first target input / output pin and the second target input / output pin.

[0149] In some embodiments, the apparatus is further configured to:

[0150] The ratio between the first database delay and the second database delay is used as a target ratio;

[0151] The difference between the preset delay and the board-level delay is used as the target difference;

[0152] Based on the target ratio and the target difference, a first adjustment delay and a second adjustment delay are obtained; the ratio of the first adjustment delay and the second adjustment delay is the target ratio; and the sum of the first adjustment delay and the second adjustment delay is the target difference.

[0153] In some embodiments, the apparatus is further configured to:

[0154] Get trigger parameters;

[0155] The i-th FPGA is configured based on the trigger parameters and the i-th initial configuration parameters to obtain the i-th second intermediate FPGA; the input-output unit in the second intermediate FPGA is provided with a plurality of physical triggers and a plurality of input-output pins; the input-output pins correspond one-to-one to the physical triggers; i is an integer greater than or equal to 1.

[0156] In some embodiments, the apparatus is further configured to:

[0157] Run each second intermediate FPGA to obtain a second original delay; the second original delay indicates a second critical path; the second critical path indicates the mth second intermediate FPGA and the nth second intermediate FPGA; the second original delay includes a first physical delay and a second physical delay;

[0158] The first physical delay indicates the delay of data being transmitted between the first target physical trigger and the first target input / output pin; the second physical delay indicates the delay of data being transmitted between the second target physical trigger and the fourth input / output pin;

[0159] The first target physical trigger and the first target input-output pin are set in the mth second intermediate FPGA; the second target physical trigger and the fourth input-output pin are set in the nth second intermediate FPGA; m, n are integers greater than or equal to 1, and m is not equal to n.

[0160] In some embodiments, the apparatus is further configured to:

[0161] Adjusting the first physical delay to obtain a third adjusted delay; and adjusting the second physical delay to obtain a fourth adjusted delay;

[0162] Based on the third adjustment delay, the fourth adjustment delay, and the i-th initial configuration parameter, the i-th second intermediate FPGA is configured to obtain the i-th second target FPGA.

[0163] It should be noted that: the device for configuring FPGA provided in the above embodiment only uses the division of the above functional modules as an example when executing the corresponding steps. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the device is divided into different functional modules to complete all or part of the functions described above. In addition, the device for configuring FPGA provided in the above embodiment and the method embodiment for configuring FPGA belong to the same concept. The specific implementation process is detailed in the method embodiment and will not be repeated here.

[0164] In the embodiment of the present application, the FPGA is configured based on the initial configuration parameters to obtain the first intermediate FPGA; the first intermediate FPGA is used to execute the function of the preset module of the SoC; each first intermediate FPGA is run to obtain the first original delay; the first original delay indicates the first critical path; the first database delay is adjusted to obtain the first adjusted delay; and the second database delay is adjusted to obtain the second adjusted delay; based on the first adjusted delay, the second adjusted delay and the initial configuration parameters, the first intermediate FPGA is configured to obtain the first target FPGA. The above technical solution can quickly find the first critical path, shorten the delay of the first critical path, and obtain the optimal strategy, which greatly reduces the number of iterations, thereby reducing the number of times the netlist is compiled, thereby greatly shortening the ineffective time of the staff and improving the verification efficiency of the SoC. In addition, the technical solution of the present application sets timing constraints, reduces delays, and thereby improves the performance of the prototype verification system.

[0165] An embodiment of the present application further provides a computer device, including a processor, a memory, and a computer program stored in the memory and configured to be executed by the processor, and the processor implements the above method when executing the computer program.

[0166] Taking computer equipment as the terminal as an example, Figure 7 This is a schematic diagram of the structure of a terminal provided in an embodiment of the present application, see Figure 7 The terminal 700 may be a smart phone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III), an MP4 player (Moving Picture Experts Group Audio Layer IV), a laptop computer or a desktop computer. The terminal 700 may also be called a user device, a portable terminal, a laptop terminal, a desktop terminal or other names.

[0167] Typically, the terminal 700 includes a processor 701 and a memory 702 .

[0168] The processor 701 may include one or more processing cores, such as a 4-core processor, a 5-core processor, etc. The processor 701 may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor 701 may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor 701 may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content to be displayed on the display screen. In some embodiments, the processor 701 may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0169] The memory 702 may include one or more computer-readable storage media, which may be non-transitory. The memory 702 may also include a high-speed random access memory, and a non-volatile memory, such as one or more disk storage devices, flash memory storage devices. In some embodiments, the non-transitory computer-readable storage medium in the memory 702 is used to store at least one program code, which is used to be executed by the processor 701 to implement the process provided by the method embodiment of the present application for the terminal execution in the above method.

[0170] In some embodiments, the terminal 700 may further optionally include: a peripheral device interface 703 and at least one peripheral device. The processor 701, the memory 702 and the peripheral device interface 703 may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface 703 via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a display screen 704, a camera assembly 705, an audio circuit 706 and a power supply 707.

[0171] The peripheral device interface 703 may be used to connect at least one peripheral device related to I / O (Input / Output) to the processor 701 and the memory 702. In some embodiments, the processor 701, the memory 702, and the peripheral device interface 703 are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor 701, the memory 702, and the peripheral device interface 703 may be implemented on a separate chip or circuit board, which is not limited in the embodiments of the present application.

[0172] The display screen 704 is used to display the UI (User Interface). The UI may include graphics, text, icons, videos, and any combination thereof. When the display screen 704 is a touch display screen, the display screen 704 also has the ability to collect touch signals on the surface or above the surface of the display screen 704. The touch signal can be input to the processor 701 as a control signal for processing. At this time, the display screen 704 can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen 704 can be one, set on the front panel of the terminal 700; in other embodiments, the display screen 704 can be at least two, respectively set on different surfaces of the terminal 700 or in a folding design; in other embodiments, the display screen 704 can be a flexible display screen, set on the curved surface or folding surface of the terminal 700. Even, the display screen 704 can also be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen 704 can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode, organic light-emitting diode).

[0173] The camera assembly 705 is used to capture images or videos. In some embodiments, the camera assembly 705 includes a front camera and a rear camera. Typically, the front camera is disposed on the front panel of the terminal, and the rear camera is disposed on the back of the terminal. In some embodiments, there are at least two rear cameras, which are any one of a main camera, a depth of field camera, a wide-angle camera, and a telephoto camera, so as to realize the fusion of the main camera and the depth of field camera to realize the background blur function, the fusion of the main camera and the wide-angle camera to realize the panoramic shooting and VR (Virtual Reality) shooting function or other fusion shooting functions. In some embodiments, the camera assembly 705 may also include a flash. The flash can be a monochrome temperature flash or a dual-color temperature flash. A dual-color temperature flash refers to a combination of a warm light flash and a cold light flash, which can be used for light compensation at different color temperatures.

[0174] The audio circuit 706 may include a microphone and a speaker. The microphone is used to collect sound waves from the user and the environment, and convert the sound waves into electrical signals and input them into the processor 701 for processing. For the purpose of stereo acquisition or noise reduction, there may be multiple microphones, which are respectively arranged at different parts of the terminal 700. The microphone may also be an array microphone or an omnidirectional acquisition microphone. The speaker is used to convert the electrical signal from the processor 701 into sound waves. The speaker may be a traditional film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, it can not only convert the electrical signal into sound waves audible to humans, but also convert the electrical signal into sound waves inaudible to humans for purposes such as ranging. In some embodiments, the audio circuit 706 may also include a headphone jack.

[0175] The power supply 707 is used to power various components in the terminal 700. The power supply 707 can be an alternating current, a direct current, a disposable battery, or a rechargeable battery. When the power supply 707 includes a rechargeable battery, the rechargeable battery can support wired charging or wireless charging. The rechargeable battery can also be used to support fast charging technology.

[0176] Those skilled in the art will understand that Figure 7 The structure shown in the figure does not constitute a limitation on the terminal 700, and the terminal 700 may include more or less components than those shown in the figure, or combine some components, or adopt a different component arrangement.

[0177] Take the computer device as a server as an example. Figure 8 It is a structural diagram of a server provided in an embodiment of the present application. The server 800 may have relatively large differences due to different configurations or performances, and may include one or more processors (Central Processing Units, CPU) 801 and one or more memories 802, wherein the one or more memories 802 store at least one computer program, and the at least one computer program is loaded and executed by the one or more processors 801 to implement the above-mentioned FPGA configuration method. Of course, the server 800 may also have components such as a wired or wireless network interface, a keyboard, and an input and output interface for input and output. The server 800 may also include other components for implementing device functions, which will not be described in detail here.

[0178] The embodiment of the present application also provides a computer-readable storage medium, the computer-readable storage medium includes a stored computer program, wherein when the computer program is running, the device where the computer-readable storage medium is located is controlled to execute the above-mentioned method for generating an image processing model. Optionally, the computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, etc.

[0179] A person skilled in the art will understand that all or part of the steps to implement the above embodiments may be accomplished by hardware, or by a program to instruct the relevant hardware, and the program may be stored in a computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0180] The above description is only an optional embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for configuring an FPGA, characterized in that: include: Acquire an initial configuration parameter set; the initial configuration parameter set includes a plurality of initial configuration parameters; The initial configuration parameters correspond one-to-one to the preset modules in the SoC; the initial configuration parameters describe the functions and timing of the preset modules; Configuring the i-th FPGA based on the i-th initial configuration parameter to obtain the i-th first intermediate FPGA; The i-th first intermediate FPGA is used to execute the function of the i-th preset module; i is an integer greater than or equal to 1; Run each of the first intermediate FPGAs to obtain a first original delay; the first original delay indicates a first critical path; the first critical path indicates the kth first intermediate FPGA and the fth first intermediate FPGA; the first original delay includes a first database delay and a second database delay; the first database delay indicates the delay of the kth first intermediate FPGA transmitting data; the second database delay indicates the delay of the fth first intermediate FPGA transmitting the data; k, f are integers greater than or equal to 1, and k is not equal to f; Adjusting the first database delay to obtain a first adjusted delay; and adjusting the second database delay to obtain a second adjusted delay; Based on the first adjustment delay, the second adjustment delay, and the i-th initial configuration parameter, the i-th first intermediate FPGA is configured to obtain the i-th first target FPGA.

2. The method according to claim 1, characterized in that The obtaining of the initial configuration parameter set includes: The code file of the SoC is divided to obtain the initial configuration parameter set; each of the initial configuration parameters includes a code block of the code file.

3. The method according to claim 1, characterized in that The first database delay indicates the delay of the data being transmitted between the first target database trigger and the first target input / output pin; the second database delay indicates the delay of the data being transmitted between the second target database trigger and the second input / output pin; The database trigger is generated based on the code; the first target input and output pins are set in the kth first intermediate FPGA; the second target input and output pins are set in the fth first intermediate FPGA.

4. The method according to claim 3, characterized in that The first original delay also includes a board-level delay; the board-level delay indicates the delay of transmitting the data between the first target input / output pin and the second target input / output pin.

5. The method according to claim 4, characterized in that adjusting the first database delay to obtain a first adjusted delay; and adjusting the second database delay to obtain a second adjusted delay, comprising: Taking the ratio between the first database delay and the second database delay as the target ratio; The difference between the preset delay and the board-level delay is used as the target difference; Based on the target ratio and the target difference, the first adjustment delay and the second adjustment delay are obtained; the ratio of the first adjustment delay and the second adjustment delay is the target ratio; and the sum of the first adjustment delay and the second adjustment delay is the target difference.

6. The method according to claim 1, characterized in that The method further comprises: Get trigger parameters; The i-th FPGA is configured based on the trigger parameters and the i-th initial configuration parameters to obtain the i-th second intermediate FPGA; the input-output unit in the second intermediate FPGA is provided with a plurality of physical triggers and a plurality of input-output pins; the input-output pins correspond one-to-one to the physical triggers; i is an integer greater than or equal to 1.

7. The method according to claim 6, characterized in that The method further comprises: Run each of the second intermediate FPGAs to obtain a second original delay; the second original delay indicates a second critical path; the second critical path indicates the mth second intermediate FPGA and the nth second intermediate FPGA; the second original delay includes a first physical delay and a second physical delay; The first physical delay indicates the delay of the data being transmitted between the first target physical trigger and the first target input / output pin; the second physical delay indicates the delay of the data being transmitted between the second target physical trigger and the fourth input / output pin; The first target physical trigger and the first target input-output pin are set in the mth second intermediate FPGA; the second target physical trigger and the fourth input-output pin are set in the nth second intermediate FPGA; m, n are integers greater than or equal to 1, and m is not equal to n.

8. The method according to claim 7, characterized in that The method further comprises: Adjusting the first physical delay to obtain a third adjusted delay; and adjusting the second physical delay to obtain a fourth adjusted delay; Based on the third adjustment delay, the fourth adjustment delay and the i-th initial configuration parameter, the i-th second intermediate FPGA is configured to obtain the i-th second target FPGA.

9. A device for configuring an FPGA, characterized in that: include: An acquisition module, used to acquire an initial configuration parameter set; the initial configuration parameter set includes a plurality of initial configuration parameters; The initial configuration parameters correspond one-to-one to the preset modules in the SoC; the initial configuration parameters describe the functions and timing of the preset modules; A first configuration module, configured to configure the i-th FPGA based on the i-th initial configuration parameter to obtain the i-th first intermediate FPGA; The i-th first intermediate FPGA is used to execute the function of the i-th preset module; i is an integer greater than or equal to 1; An operation module, configured to operate each of the first intermediate FPGAs to obtain a first original delay; the first original delay indicates a first critical path; The first critical path indicates the kth first intermediate FPGA and the fth first intermediate FPGA; the first original delay includes a first database delay and a second database delay; the first database delay indicates the delay of the kth first intermediate FPGA transmitting data; the second database delay indicates the delay of the fth first intermediate FPGA transmitting the data; k, f are integers greater than or equal to 1, and k is not equal to f; An adjustment module, configured to adjust the first database delay to obtain a first adjusted delay; and adjust the second database delay to obtain a second adjusted delay; The second configuration module is used to configure the i-th first intermediate FPGA based on the first adjustment delay, the second adjustment delay and the i-th initial configuration parameter to obtain the i-th first target FPGA.

10. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory is used to store at least one program, and the at least one program is loaded by the processor and executes the method for configuring the FPGA according to any one of claims 1 to 8.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores at least one program, and the at least one program is loaded and executed by a processor to implement the method for configuring an FPGA according to any one of claims 1 to 8.

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