Pixel circuit and display system thereof

Abstract

The invention discloses a pixel circuit of a display screen. The pixel circuit comprises a light-emitting component, a first transistor, a second transistor, a third transistor and a fourth transistor, the first transistor has a gate terminal, a drain terminal and a source terminal. The second transistor is coupled to the gate terminal of the first transistor. The third transistor is coupled to the source terminal of the first transistor. The fourth transistor is coupled to the drain terminal of the first transistor and the light emitting device, and comprises a gate terminal, a drain terminal and a source terminal. The gate terminal of the fourth transistor is coupled to a gate line on the display screen, the drain terminal of the fourth transistor is coupled to the gate line, and the source terminal of the fourth transistor is coupled to the drain terminal of the first transistor.

Description

Technical Field

[0001] The invention relates to a pixel circuit of a display screen, and in particular to a pixel circuit structure located on the display screen and used for eliminating critical voltage deviation. Background Art

[0002] Among various next-generation display technologies, the importance of micro-OLED (micro Organic Light Emitting Diode) panels has gradually increased in recent years. Unlike traditional LED or OLED panels, whose screens are built on glass substrates, the screens of micro-OLED panels are directly mounted on silicon wafers. This silicon-based implementation can achieve a large number of benefits, such as small size, light weight, low power consumption, high luminous efficiency, high contrast, high pixel density, etc. With the above advantages, micro-OLED panels are particularly suitable for augmented reality (AR) and virtual reality (VR) applications. Summary of the invention

[0003] Therefore, the main purpose of the present invention is to provide a novel pixel circuit that can be used in an organic light emitting diode (OLED) panel, especially a micro-OLED panel.

[0004] An embodiment of the present invention discloses a pixel circuit of a display screen, the pixel circuit comprising a light-emitting component, a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor has a gate terminal, a drain terminal and a source terminal. The second transistor is coupled to the gate terminal of the first transistor. The third transistor is coupled to the source terminal of the first transistor. The fourth transistor is coupled to the drain terminal of the first transistor and the light-emitting component, and comprises a gate terminal, a drain terminal and a source terminal. The gate terminal of the fourth transistor is coupled to a gate line on the display screen, the drain terminal of the fourth transistor is coupled to the gate line, and the source terminal of the fourth transistor is coupled to the drain terminal of the first transistor.

[0005] Another embodiment of the present invention discloses a display system, which includes a display screen, a source driving device and a gate driving device. The display screen includes a plurality of pixels. The source driving device has a plurality of channels, wherein each channel is coupled to a column of pixels among the plurality of pixels. The gate driving device is coupled to a plurality of gate lines on the display screen, and each of the plurality of gate lines is coupled to a row of pixels among the plurality of pixels. Each of the plurality of pixels has a pixel circuit, which includes a light-emitting component, a first transistor, a second transistor, a third transistor and a fourth transistor. The first transistor has a gate terminal, a drain terminal and a source terminal. The second transistor is coupled to the gate terminal of the first transistor. The third transistor is coupled to the source terminal of the first transistor. The fourth transistor is coupled to the drain terminal of the first transistor and the light-emitting component, and includes a gate terminal, a drain terminal and a source terminal. The gate terminal of the fourth transistor is coupled to a first gate line among the plurality of gate lines, the drain terminal of the fourth transistor is coupled to the first gate line, and the source terminal of the fourth transistor is coupled to the drain terminal of the first transistor. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 FIG. 1 is a schematic diagram of a display system according to an embodiment of the present invention.

[0007] Figure 2 FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

[0008] Figure 3 for Figure 2 Waveform diagram of relevant signals and voltages of the pixel circuit in FIG.

[0009] FIG. 4A to FIG. 4E The operation of the pixel circuit is shown in several stages.

[0010] Figure 5 FIG. 4 is a schematic diagram of another pixel circuit according to an embodiment of the present invention.

[0011] Figure 6 for Figure 5 Waveform diagram of relevant signals and voltages of the pixel circuit in FIG.

[0012] Figure 7 Schematic diagram of a circuit model of a row of pixel circuits in the initial stage.

[0013] Figures 8 to 11 FIG. 4 is a timing diagram of the operation of multiple rows of pixels during a frame period according to an embodiment of the present invention.

[0014] Fig.12 FIG. 4 is a schematic diagram of another pixel circuit according to an embodiment of the present invention.

[0015] Fig.13 for Fig.12Waveform diagram of relevant signals and voltages of the pixel circuit in FIG.

[0016] Fig.14 FIG. 1 is a schematic diagram of a pixel circuit according to an embodiment of the present invention.

[0017] The reference numerals are described as follows:

[0018] 10 Display System

[0019] 100 Display

[0020] 102 Source driver

[0021] 104 Gate drive device

[0022] 106 Timing Controller

[0023] 108 Gamma Control Circuit

[0024] 20, 50, 120, 140 pixel circuits

[0025] T1, T2, T3, T4, T5, T6 transistors

[0026] C1, C2 capacitors

[0027] L1 Light emitting component

[0028] ELVDD, ELVSS power supply voltage

[0029] ILED drive current

[0030] GL2, GL3, GL4, GL5, GL6 gate lines

[0031] DL1 Data Cable

[0032] NS, NG, ND, ND2 nodes

[0033] P1~P5 stage

[0034] VINI Initial voltage

[0035] VDATA Data voltage

[0036] Cs pix1 ~Cs pixM Storage capacitor

[0037] R Parasitic resistance

[0038] I Current

[0039] R_1~R_3N pixel rows DETAILED DESCRIPTION

[0040] Figure 1 FIG. 1 is a schematic diagram of a display system 10 according to an embodiment of the present invention. The display system 10 includes a display screen 100, a source driver 102, a gate driver 104, a timing controller 106, and a gamma control circuit 108. The display screen 100 includes a plurality of pixels arranged in an array. For example, Figure 1 As shown, the display screen 100 has Y rows and X columns of pixels, where X and Y can be any and suitable positive integers. In some embodiments, each pixel may include three sub-pixels, each sub-pixel can be used to display a specific color, and has a pixel circuit composed of a plurality of transistors, a capacitor and a light-emitting component, where the light-emitting component can be a light-emitting diode (LED) or an organic light-emitting diode (OLED), but is not limited thereto.

[0041] The source driver 102 includes a plurality of channels, each of which can be coupled to a column of pixels, or coupled to a plurality of columns of pixels through the control of a multiplexer. The source driver 102 can provide a data voltage and an initial voltage to control the pixel circuit. Each channel of the source driver 102 can include a shift register, a digital-to-analog converter (DAC) and an output buffer. The detailed structure of the source driver 102 should be well known to those skilled in the art, so it is not repeated here.

[0042] The gate driver 104 also includes a plurality of channels, each of which can be coupled to one or more gate lines on the display screen 100 to supply a gate control signal and / or a light emitting control signal to the pixel circuit through the gate line. Each gate line can be connected to a row of pixels on the display screen 100. In one embodiment, the gate driver 104 can be implemented as a gate-on-array (GOA) circuit. Each channel of the gate driver 104 can include a shift register and an output buffer. The detailed structure of the gate driver 104 should be well known to those skilled in the art, so it is not repeated here.

[0043] The timing controller 106 can be used to control the operation of the source driver 102 and the gate driver 104. More specifically, the timing controller 106 can be used as a video source to provide image data to the source driver 102, so that the source driver 102 can convert the image data into a data voltage through the gamma control circuit 108. The gamma control circuit 108 can generate a plurality of gamma voltages for the source driver 102 to select, so as to generate the data voltage according to the image data. Correspondingly, the timing controller 106 can control the operation timing of the gate driver 104, so that the gate driver 104 can output a gate / light-emitting control signal to scan a specific row of pixels, so that it receives the corresponding data voltage during a display line period, so that the light-emitting diodes / organic light-emitting diodes in this row of pixels emit light according to the data voltage.

[0044] Figure 2 Schematic diagram of a pixel circuit 20 according to an embodiment of the present invention. The pixel circuit 20 includes four transistors T1 to T4, two capacitors C1 and C2, and a light-emitting element L1. The pixel circuit 20 can receive a first power supply voltage ELVDD and a second power supply voltage ELVSS to operate, wherein the power supply voltage ELVDD can be a positive voltage, and the power supply voltage ELVSS can be a negative voltage or a ground voltage. The pixel circuit 20 can be implemented in Figure 1 Any pixel on the display screen 100.

[0045] like Figure 2 As shown, transistor T1 can be a driving transistor for outputting a driving current ILED to drive the light-emitting element L1 to emit light. Transistors T2-T4 can be used as control switches to control the operation of the driving transistor T1 and the light-emitting element L1 at different stages. Transistors T2-T4 can eliminate the driving current ILED offset caused by the threshold voltage variation of the driving transistor T1 by appropriate setting and control. In this example, transistors T2, T3 and T4 receive control signals from different gate lines GL2, GL3 and GL4 respectively to operate, wherein the gate lines GL2-GL4 are coupled to the gate driving device, and their corresponding control signals also come from the gate driving device.

[0046] The capacitor C1 is coupled between the gate terminal of the transistor T1 and the source terminal of the transistor T1, and the capacitor C2 is coupled between the source terminal of the transistor T1 and a first power supply terminal for supplying the power supply voltage ELVDD. When the pixel circuit 20 receives the data voltage or the initial voltage, the voltage information can be stored in the capacitor C1 and / or C2, and the capacitor C1 and / or C2 can also be used to store the threshold voltage information of the transistor T1.

[0047] The transistor T2 is coupled between the gate terminal of the transistor T1 and a data line DL1, and the data line DL1 is further coupled to the source driving device, so the transistor T2 can be used as a switch for receiving the data voltage and / or the initial voltage from the source driving device. In detail, a first end of the transistor T2 is coupled to the data line DL1 to receive the data voltage, a second end of the transistor T2 is coupled to the gate terminal of the transistor T1, and the gate terminal of the transistor T2 is coupled to the gate line GL2. The transistor T2 is responsible for controlling the pixel circuit 20 to receive the data voltage and the initial voltage.

[0048] The transistor T3 is coupled between the source terminal of the transistor T1 and the first power supply terminal for supplying the power supply voltage ELVDD, so as to serve as a switch for conducting the current flowing through the transistor T1. Specifically, a first terminal of the transistor T3 is coupled to the source terminal of the transistor T1, a second terminal of the transistor T3 is coupled to the first power supply terminal, and a gate terminal of the transistor T3 is coupled to the gate line GL3. The transistor T3 is responsible for controlling the current path for resetting and emitting light.

[0049] The transistor T4 is coupled to the drain terminal of the transistor T1 and the light emitting element L1 to serve as a switch for resetting the light emitting element L1. Specifically, the gate terminal and the drain terminal of the transistor T4 are coupled to the gate line GL4, and the source terminal of the transistor T4 is coupled to the drain terminal of the transistor T1. The transistor T4 is responsible for controlling the resetting of the light emitting element L1. In this example, the gate terminal of the transistor T4 is connected to the drain terminal of the transistor T4, and the two terminals are coupled to the gate line GL4 to be further coupled to the gate driving device.

[0050] In a general pixel circuit, the reset transistor for the light-emitting component is usually connected to a power supply terminal for discharge. Therefore, the voltage drop (IR-drop) on the power line may cause differences in the reset behavior between different pixels. Such differences are required to be eliminated in the back-end circuit or module, and a large amount of resources are needed to solve this problem. In contrast, in the present invention, the reset transistor (such as transistor T4) in the pixel circuit 20 can be discharged through the gate line GL4 instead of the power supply terminal, thereby avoiding the voltage drop problem and saving back-end resources. In addition, the drain terminal and the gate terminal of the transistor T4 are coupled to the same gate line GL4, so the power supply terminal does not need to be connected to the transistor T4, which can reduce the connection lines of the power supply terminal and simplify the layout structure of each pixel circuit.

[0051] The light emitting element L1 is coupled between the drain terminal of the transistor T1 and a second power supply terminal for supplying the power supply voltage ELVSS. The light emitting element L1 can receive the driving current ILED from the transistor T1 to emit light, and can be any device that emits light by receiving current, such as a light emitting diode or an organic light emitting diode.

[0052] The operation of the pixel circuit 20 includes several stages. Figure 3 2 is a waveform diagram of related signals and voltages of the pixel circuit 20, which shows the waveforms of the signal on the data line DL1, the signal on the gate lines GL2-GL4, and the voltages on the nodes NS, NG and ND. The nodes NS, NG and ND represent the source terminal, the gate terminal and the drain terminal of the transistor T1, respectively. It should be noted that in the pixel circuit 20, the transistors T2-T4 are all P-type metal oxide semiconductor transistors (PMOS transistors), so the signal at a low level can turn on the corresponding transistor and at a high level can turn off the corresponding transistor. Figure 3 The operation of the pixel circuit 20 has five phases P1 to P5, which are respectively Figures 4A to 4E Provide detailed explanation.

[0053] Please refer to Figure 4A Matching Figure 3 As shown, stage P1 can be regarded as an initial stage (or reset stage or pre-charging stage), in which transistor T2 is turned on first, then transistor T3 is turned on, and transistor T4 is continuously turned on during this stage. When transistor T2 is turned on, the pixel circuit 20 receives an initial voltage VINI from the data line DL1. The initial voltage VINI can be written to the gate terminal of transistor T1 to reset the charge at the gate terminal of transistor T1 and store the charge in capacitor C1. In addition, since transistor T4 is turned on, the charge of light-emitting component L1 can be discharged through transistor T4 to reset light-emitting component L1. Transistor T4 can pull down the anode voltage of light-emitting component L1 to avoid unnecessary light emission of light-emitting component L1 in the initial stage P1. As shown Figure 4A As shown, the drain terminal and the gate terminal of the transistor T4 are both coupled to the gate line GL4 , so the discharge current from the transistor T1 and / or the light emitting element L1 can flow to the gate line GL4 through the transistor T4 .

[0054] Please refer to Figure 4B Matching Figure 3 As shown, stage P2 can be regarded as a compensation stage, in which transistors T2 and T3 are turned off and transistor T4 continues to be turned on. In stage P2, transistor T1 performs self-discharge, so that the threshold voltage information is stored in capacitors C1 and C2 in the form of the gate-to-source voltage of transistor T1 (i.e., the voltage difference between nodes NG and NS). In addition, the source voltage dropping to different levels may cause different degrees of body effect, and the information of the body effect can also be stored in capacitors C1 and C2. It should be noted that the pixel circuit 20 can be included in a small-sized sub-pixel, so the base (body) of the P-type metal oxide semiconductor transistors T1~T4 needs to be coupled to the power supply terminal, causing the body effect to be unavoidable.

[0055] Please refer to Figure 4C Matching Figure 3 As shown, phase P3 can be regarded as a data writing phase (or scanning phase), wherein transistor T2 is turned on, transistor T4 is continuously turned on, and transistor T3 is continuously turned off. In this phase, the data voltage VDATA is input from the data line DL1 through the turned-on transistor T2 to the gate terminal NG of the transistor T1. It should be noted that the threshold voltage information is stored in the capacitors C1 and C2, so the influence of the threshold voltage can be eliminated when the data voltage VDATA is input.

[0056] In this example, the initial voltage VINI and the data voltage VDATA are both received from the data line DL1. Therefore, the transistor T2 can transmit the initial voltage VINI to the transistor T1 in the initial phase P1, and transmit the data voltage VDATA to the transistor T1 in the data writing phase P3.

[0057] Please refer to Figure 4D Matching Figure 3 As shown, phase P4 can be regarded as a light-emitting phase, in which transistors T2 and T4 are turned off and transistor T3 is turned on. The turned-on transistor T3 allows the driving current ILED to be transmitted to the light-emitting element L1 to drive the light-emitting element L1 to emit light. Since the data voltage VDATA (after eliminating the offset caused by the threshold voltage) is stored in the capacitors C1 and C2, the driving current ILED can be maintained at its target level during the light-emitting time.

[0058] Please refer to Figure 4E Matching Figure 3 As shown, stage P5 can be regarded as a shutdown stage, in which transistor T4 is turned on, transistor T3 is turned off, and transistor T2 is continuously turned off. Stage P5 can be performed after the light-emitting stage P4. In stage P5, transistor T1 does not output any driving current to light-emitting element L1.

[0059] In some applications such as augmented reality (AR) or virtual reality (VR), the display screen should preferably operate at a lower light-emitting duty cycle to reduce the problem of image sticking. In other words, during a display frame or cycle, the light-emitting phase P4 only occupies a small proportion, and no operation is performed during the additional time. A closed phase P5 without any light emission can be configured. The closed phase P5 can be maintained until the beginning of the next cycle. Figure 4E In the embodiment of FIG. 5 , the state of the pixel circuit 20 in phase P5 is the same as its state in phase P2 .

[0060] Figure 5Schematic diagram of another pixel circuit 50 according to an embodiment of the present invention. The structure of the pixel circuit 50 is similar to that of the pixel circuit 20, so signals or components with similar functions are represented by the same symbols. The difference between the pixel circuit 50 and the pixel circuit 20 is that the pixel circuit 50 also includes a transistor T5, which is coupled between the gate terminal and another input terminal of the transistor T1, and is used to receive the initial voltage VINI and transmit the initial voltage VINI to the transistor T1. The transistor T5 is coupled to another gate line GL5, and is used to receive a control signal. In the pixel circuit 50, the data voltage VDATA is received from the data line DL1 and transmitted through the transistor T2, and the initial voltage VINI is transmitted through the transistor T5.

[0061] The waveforms of the pixel circuit 50 are shown in FIG. Figure 6 Since the initial voltage VINI is provided by another input terminal, the data line DL1 can continuously send the data voltage VDATA in phases P1 to P5. Correspondingly, the control signal on the gate line GL2 turns on the transistor T2 only in the data writing phase P3. The control signal on the gate line GL5 can turn on the transistor T5 in the initial phase P1 to receive the initial voltage VINI. Other operations of the pixel circuit 50 are similar to Figure 3 and Figures 4A to 4E The pixel circuit 20 shown is similar and will not be described again here.

[0062] Based on the compensation scheme of the critical voltage, the voltages of the capacitors C1 and C2 stored in the pixel circuit 20 or 50 in the initial stage P1 are required to be accurate, and these stored voltages are affected by the initial voltage VINI and the power supply voltage ELVDD. However, in the initial stage P1, each pixel has a steady-state current flowing from the first power supply terminal to the gate line GL4, and this current causes a voltage drop in the power line and the gate line GL4, thereby causing the power supply voltage ELVDD actually received by the pixel circuit to be offset.

[0063] Figure 7 Schematic diagram of a circuit model of a row of pixel circuits in the initial stage, wherein there are M pixel circuits in this row of pixel circuits, and each pixel circuit has a storage capacitor Cs pix1 ~Cs pixM Each storage capacitor Cs pix1 ~Cs pixM It can be the capacitor C1 in the pixel circuit 20 or 50. Assume that the power line between each two adjacent pixel circuits and the gate line GL4 between each two adjacent pixel circuits have a parasitic resistance R, and each pixel circuit passes a steady-state current I in the initial stage. In this example, a power supply can supply a power supply voltage ELVDD through the first power supply terminal, and a gate driving device can output a control voltage V GL4The first (leftmost) pixel circuit is closest to the power supply terminal and the gate driving device, and the Mth (rightmost) pixel circuit is farthest from the power supply terminal and the gate driving device.

[0064] Due to the existence of parasitic resistance R, the power supply voltage actually received by the pixel circuit is slightly lower than ELVDD, and the voltage values ​​received by different pixel circuits are different. Figure 7 This is because the total current flowing from the power supply end to each pixel circuit is different, depending on the distance between the pixel circuit and the power supply end, resulting in different degrees of voltage drop in different pixel circuits, causing the storage capacitor Cs pix1 ~Cs pixM The amount of stored charge cannot accurately reflect the initial voltage VINI, resulting in inconsistent reset / initial behavior. In the case of a display screen including more pixels under high-resolution applications, the above problem will be more serious.

[0065] In addition, the control voltage actually received by the pixel circuit through the gate line GL4 is slightly higher than V GL4 , and the voltage values ​​received by different pixel circuits are different, such as Figure 7 For similar reasons, the pixel circuit farther from the gate driving device can receive a higher control voltage from the gate line GL4. This control voltage should not be too high, otherwise the light-emitting components in the pixel circuit may produce erroneous light emission in the initial stage. In the case of a display screen with more pixels under high-resolution applications, the above problem will be more likely to occur.

[0066] About the power supply voltage ELVDD and the control voltage V GL4 The inconsistency problem can be alleviated by reducing the current I flowing through each pixel circuit in the initial stage. Under the smaller current I, the pixel circuit requires a longer compensation time (such as a longer compensation stage P2) to discharge the source voltage and gate voltage of the driving transistor (such as transistor T1) to their target levels. In other words, the increase in compensation time can effectively reduce the voltage offset received by the pixel circuit and stored in the storage capacitor in the initial stage; or, under the same voltage offset allowable value, the resolution of the display screen can be improved.

[0067] Please refer back Figure 5 The implementation method of using different input transistors to receive the data voltage VDATA and the initial voltage VINI helps to increase the time length of the compensation phase P2.

[0068] More specifically, in Figure 2In the pixel circuit 20, since the initial voltage VINI and the data voltage VDATA are received by the same data line DL1, the initialization phase P1, the compensation phase P2 and the data writing phase P3 for a row of pixels must be completed within the allocated display line period. Figure 5 In the pixel circuit 50, the initial voltage VINI and the data voltage VDATA are received by different endpoints. Therefore, for each row of pixels, it is not necessary to wait for the data writing of the previous row of pixels to be completed before starting to perform pixel compensation and data writing.

[0069] Figure 8 This is a timing diagram of the operation of multiple rows of pixels in an embodiment of the present invention during a frame period, and this timing diagram is used to illustrate the operation of the pixel circuit 20. Assume that there are N rows of pixels R_1~R_N on the panel, and each row of pixels R_1~R_N is scanned in sequence to perform the operations in stages P1~P5. It should be noted that stage P1 is an initial stage for receiving the initial voltage VINI, and stage P3 is a data writing stage for receiving the data voltage VDATA. Stages P1~P3 for receiving the initial voltage VINI and the data voltage VDATA should be completed within a display line period (hereinafter referred to as "line period"). Stage P4 is a light-emitting stage, and stage P5 is a closing stage. Stages P4 and P5 can be configured in the remaining time within the frame period to achieve the desired brightness through a suitable light-emitting duty cycle.

[0070] In this example, the initial voltage VINI and the data voltage VDATA are received by the same data line, so the phases P1-P3 for each row of pixels R_1-R_N are performed in a separate line period. In each line period, the data line (such as DL1) can first transmit the initial voltage VINI and then transmit the data voltage VDATA to the target pixel on a specific row.

[0071] Fig. 9 The timing diagram of the operation of multiple rows of pixels during one frame period when the initial voltage VINI and the data voltage VDATA are received by different endpoints according to an embodiment of the present invention is used to illustrate the operation of the pixel circuit 50. In this example, when the pixels of the first row R_1 complete the stage P1, the pixels of the second row R_2 begin to execute the stage P1 to receive the initial voltage VINI. In other words, for the pixels of a specific row R_n (n is an integer between 2 and N), the stage P1 of these pixels and the stage P2 of the pixels of the previous row R_(n-1) can be executed at the same time. In addition, before the pixels of the previous row R_(n-1) execute the stage P3 to receive the data voltage VDATA, the pixels of the current row R_n can execute the stage P1 to receive the initial voltage VINI. Since the reception of the data voltage VDATA does not affect the reception of the initial voltage VINI, the timing of the stages P1 and P3 can be set more flexibly.

[0072] like Fig. 9 As shown, since the length of a line period can accommodate the phase P1 of three rows of pixels, the same frame period length can be used to scan three times the number of rows (i.e., 3N rows of pixels R_1 to R_3N) at the same scanning speed, or the length of the frame period can be shortened. In this case, the display can support three times the refresh rate or resolution.

[0073] As described above, the implementation method of using different input transistors (and input terminals) to receive the data voltage VDATA and the initial voltage VINI can increase the time length of the compensation phase P2 to reduce the voltage offset caused by the voltage drop on the power line. The relevant implementation method is shown in Fig.10 Different from Figure 8 In the embodiment of the present invention, stages P1 to P3 must be completed within a specific line period. Fig.10 In the embodiment of the present invention, the length of the compensation phase P2 can be extended arbitrarily without affecting the reception of the initial voltage VINI and the data voltage VDATA. The extended compensation phase P2 allows the reset operation to use only a smaller initial current, which can reduce the voltage offset received by the pixel, reduce the impact of time skew and improve the accuracy of compensation. In this example, the refresh rate or resolution can also be tripled.

[0074] It is worth noting that the implementation method of using different input transistors (and input terminals) to receive the data voltage VDATA and the initial voltage VINI can provide more flexibility, so that the data writing phase P3 can be extended to improve the accuracy of data reception, such as Fig.11 In this example, the length of the data writing phase P3 can be extended without affecting the reception of the initial voltage VINI, and the refresh rate or resolution can be maintained unchanged. The extended data writing phase P3 allows the data voltage VDATA actually received by each pixel to reach its target level more accurately.

[0075] Fig.12 Schematic diagram of another pixel circuit 120 according to an embodiment of the present invention. The structure of the pixel circuit 120 is similar to that of the pixel circuit 20, so signals or components with similar functions are represented by the same symbols. The difference between the pixel circuit 120 and the pixel circuit 20 is that the pixel circuit 120 further includes a transistor T6, which is coupled between the transistor T1 and the light-emitting component L1. More specifically, one end of the transistor T6 is coupled to the drain end of the transistor T1, and the other end of the transistor T6 is coupled to the anode of the light-emitting component L1 and the transistor T4. Therefore, the transistor T6 can be used as a switch for controlling the conduction path between the transistor T6 and the light-emitting component L1.

[0076] The waveforms of the pixel circuit 120 are shown in FIG. Fig.13The gate terminal of transistor T6 is coupled to another gate line GL6, and its corresponding control signal can turn off transistor T6 in the initial stage P1. As mentioned above, the steady-state current in the initial stage P1 may cause a voltage drop on the power line and the gate line GL4, resulting in a voltage offset. Transistor T6 can cut off the current path, thereby preventing the steady-state current from flowing from the first power supply terminal to the gate line GL4. The reduction in current can reduce the power consumption of the display screen.

[0077] In this example, the transistor T1 can still be reset by receiving the initial voltage VINI, and the light emitting element L1 can still be reset by lowering its anode voltage using the transistor T4. Fig.12 and Fig.13 As shown, the voltage of the node ND2 represents the anode voltage of the light emitting element L1. Even when the node ND is pulled high due to the conduction of the transistor T3, the voltage of the node ND2 is still maintained at a low level to prevent the light emitting element L1 from emitting light in the phase P1. Figure 3 and Figures 4A to 4E The pixel circuit 20 shown is similar and will not be described again here.

[0078] It is worth noting that the purpose of the present invention is to propose a new pixel circuit that can be used to eliminate the offset caused by the threshold voltage of the driving transistor. Those skilled in the art can make modifications or changes accordingly, but are not limited to this. For example, in the above-mentioned embodiments, the transistors in the pixel circuit are all P-type metal oxide semiconductor transistors; but in other embodiments, N-type metal oxide semiconductor transistors (NMOS transistors) or a combination of P-type and N-type metal oxide semiconductor transistors can also be used to achieve a similar structure, wherein the levels of the control signal and the initial voltage can be modified accordingly. In the embodiment proposed in this specification, the structure of the pixel circuit adopts two capacitors C1 and C2, but the present invention is not limited to this. In another embodiment, the capacitor C2 can also be omitted, and only the capacitor C1 is retained, thereby realizing a pixel circuit structure with a single capacitor. In addition, the above-mentioned embodiments can be applied to the Thin-Film Transistor (TFT) process to be implemented on the glass substrate of the display screen, and can also be applied to the Complementary Metal-Oxide Semiconductor (CMOS) process to be implemented in an integrated circuit. In addition, the pixel circuit of the present invention can be applied to various self-luminous panels, including organic light emitting diode panels, mini light emitting diode (mini-LED) panels, micro light emitting diode (micro-LED) panels, and micro organic light emitting diode (micro-OLED) panels, but not limited thereto.

[0079] In another embodiment, the transistor dedicated to transmitting the initial voltage and the transistor for cutting off the steady-state current in the initial stage can be integrated into the same pixel circuit, such as Fig.14 shown. Fig.14 The pixel circuit 140 includes six transistors T1-T6, two capacitors C1-C2, and one light emitting element L1. The implementation and operation of the pixel circuit 140 are similar to those of the above embodiment and will not be repeated here.

[0080] In summary, the present invention proposes a pixel circuit of a display screen, which can be used to eliminate the offset caused by the critical voltage of the driving transistor included in the pixel circuit. In the pixel circuit, the transistor used to reset the light-emitting component is controlled by a control signal from a gate line, and the gate line is coupled to the gate driving device. For the reset transistor, its gate terminal and drain terminal are commonly coupled to the gate line, so it can be discharged through the gate line instead of the ground terminal or the power supply terminal, that is, the initial current is discharged through the gate line. In this way, resources for arranging additional ground lines or power lines to couple to the reset transistor can be saved. In one embodiment, the pixel circuit includes an additional transistor for receiving the initial voltage, so that the initial voltage and the data voltage can be received through different input terminals, so that any operation stage can be extended to provide higher flexibility in the timing configuration of each stage, thereby improving the resolution, refresh rate and reliability of the display screen. In one embodiment, the pixel circuit includes another transistor for cutting off the current conduction path in the initial stage, thereby reducing the steady-state current and reducing the voltage drop generated on the power line and / or the gate line, so as to improve the accuracy of the charge stored in the storage capacitor in the initial operation.

[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A pixel circuit of a display screen, characterized in that: include: a light emitting component; A first transistor having a gate terminal, a drain terminal and a source terminal; a second transistor coupled to the gate terminal of the first transistor; a third transistor coupled to the source terminal of the first transistor; as well as a fourth transistor coupled to the drain terminal of the first transistor and the light emitting element, the fourth transistor comprising: A gate terminal coupled to a gate line on the display screen; a drain terminal coupled to the gate line; and A source terminal is coupled to the drain terminal of the first transistor.

2. The pixel circuit according to claim 1, wherein: Also includes: a first capacitor coupled between the gate terminal of the first transistor and the source terminal of the first transistor; as well as A second capacitor is coupled between the source terminal of the first transistor and a first power supply terminal.

3. The pixel circuit according to claim 1, wherein: The light emitting component is coupled between the drain terminal of the first transistor and a second power supply terminal.

4. The pixel circuit according to claim 1, wherein: The fourth transistor resets the light emitting element in an initial stage.

5. The pixel circuit according to claim 1, wherein: The gate terminal of the fourth transistor is connected to the drain terminal of the fourth transistor.

6. The pixel circuit according to claim 1, wherein: In an initial stage, a discharge current flows to the gate line through the fourth transistor.

7. The pixel circuit according to claim 1, wherein: The second transistor transmits an initial voltage to the first transistor in an initial phase, and transmits a data voltage to the first transistor in a data writing phase.

8. The pixel circuit according to claim 1, wherein: The second transistor transmits a data voltage to the first transistor, and the pixel circuit further includes: A fifth transistor is coupled to the gate terminal of the first transistor and is used for transmitting an initial voltage to the first transistor.

9. The pixel circuit according to claim 1, wherein: After a light-emitting phase, the pixel circuit operates in a turn-off phase, in which the first transistor does not output any driving current to the light-emitting element.

10. The pixel circuit according to claim 1, wherein: Also includes: a sixth transistor, coupled between the first transistor and the light-emitting element, the sixth transistor comprising: a first terminal coupled to the drain terminal of the first transistor; as well as A second end is coupled to the light emitting component.

11. The pixel circuit according to claim 10, characterized in that: The sixth transistor is turned off in the initial stage.

12. The pixel circuit according to claim 1, wherein: The display screen includes a plurality of rows of pixels, the plurality of rows of pixels receiving an initial voltage in an initial phase and then receiving a data voltage in a data writing phase for scanning, and within a frame period, a second row of pixels in the plurality of rows of pixels is scanned after a first row of pixels in the plurality of rows of pixels; Wherein, during the frame period, before the first row of pixels receive the data voltage, the second row of pixels first receive the initial voltage.

13. The pixel circuit according to claim 1, wherein: The gate line is used to connect a row of pixels on the display screen.

14. A display system, characterized in that: include: a display screen including a plurality of pixels; a source driving device having a plurality of channels, wherein each channel is coupled to a column of pixels among the plurality of pixels; as well as A gate driving device coupled to a plurality of gate lines on the display screen, each of the plurality of gate lines being coupled to a row of pixels among the plurality of pixels; Each of the plurality of pixels has a pixel circuit, which includes: a light emitting component; A first transistor having a gate terminal, a drain terminal and a source terminal; a second transistor coupled to the gate terminal of the first transistor; a third transistor coupled to the source terminal of the first transistor; and a fourth transistor coupled to the drain terminal of the first transistor and the light emitting element, the fourth transistor comprising: A gate terminal coupled to a first gate line among the plurality of gate lines; a drain terminal coupled to the first gate line; and A source terminal is coupled to the drain terminal of the first transistor.

15. The display system according to claim 14, characterized in that: The pixel circuit also includes: a first capacitor coupled between the gate terminal of the first transistor and the source terminal of the first transistor; and A second capacitor is coupled between the source terminal of the first transistor and a first power supply terminal.

16. The display system according to claim 14, characterized in that: The light emitting component is coupled between the drain terminal of the first transistor and a second power supply terminal.

17. The display system according to claim 14, characterized in that: The fourth transistor resets the light emitting element in an initial stage.

18. The display system according to claim 14, characterized in that: The gate terminal of the fourth transistor is connected to the drain terminal of the fourth transistor.

19. The display system according to claim 14, characterized in that: In an initial stage, a discharge current flows to the first gate line through the fourth transistor.

20. The display system according to claim 14, characterized in that: The second transistor transmits an initial voltage to the first transistor in an initial phase, and transmits a data voltage to the first transistor in a data writing phase.

21. The display system according to claim 14, characterized in that: The second transistor transmits a data voltage to the first transistor, and the pixel circuit further includes: A fifth transistor is coupled to the gate terminal of the first transistor and is used for transmitting an initial voltage to the first transistor.

22. The display system according to claim 14, characterized in that: After a light-emitting phase, the pixel circuit operates in a turn-off phase, in which the first transistor does not output any driving current to the light-emitting element.

23. The display system according to claim 14, characterized in that: The pixel circuit also includes: a sixth transistor, coupled between the first transistor and the light-emitting element, the sixth transistor comprising: a first terminal coupled to the drain terminal of the first transistor; and A second end is coupled to the light emitting component.

24. The display system according to claim 23, characterized in that: The sixth transistor is turned off in the initial stage.

25. The display system according to claim 14, characterized in that: The plurality of pixels include a plurality of rows of pixels, the plurality of rows of pixels receive an initial voltage in an initial phase and then receive a data voltage in a data writing phase for scanning, and within a frame period, a second row of pixels in the plurality of rows of pixels is scanned after a first row of pixels in the plurality of rows of pixels; Wherein, during the frame period, before the first row of pixels receive the data voltage, the second row of pixels first receive the initial voltage.

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