Data processing circuit and memory

Abstract

The embodiment of the invention provides a data processing circuit and a memory, and the data processing circuit comprises a clock generation circuit which is used for generating a plurality of clock signals; the clock signals comprise a plurality of first effective pulses with a first pulse width, the plurality of clock signals are delayed in sequence, and the delay duration between two adjacent clock signals is equal to the first pulse width; the compression signal generation circuit is connected with the clock generation circuit, and the compression signal generation circuit is used for generating a plurality of compression signals according to the plurality of clock signals; the data bus driving circuit is connected with the compression signal generating circuit, and the data bus driving circuit is used for receiving multi-bit data and compressing the multi-bit data according to the plurality of compression signals; wherein the transmission duration of each bit of data after compression is equal to the first pulse width.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a data processing circuit and a memory. Background Art

[0002] With the continuous development of science and technology, semiconductor devices are widely used in various electronic devices and electronic products. For example, dynamic random access memory (DRAM), static random access memory (SRAM) and NAND memory are all commonly used semiconductor memory devices in computers.

[0003] Each time the memory is read, each data bus transmits one bit of data. If 128 bits of data are read at a time, 128 data buses are required. These data buses occupy a large number of line resources, which is not conducive to the miniaturization of the memory and will increase the difficulty of other line layouts. Summary of the invention

[0004] In view of this, an embodiment of the present disclosure provides a data processing circuit and a memory.

[0005] In a first aspect, an embodiment of the present disclosure provides a data processing circuit, including:

[0006] A clock generation circuit, the clock generation circuit is used to generate a plurality of clock signals; the clock signals include a plurality of first valid pulses with a first pulse width, the plurality of clock signals are delayed in sequence, and the delay time between two adjacent clock signals is equal to the first pulse width;

[0007] A compression signal generating circuit connected to the clock generating circuit, the compression signal generating circuit being used to generate a plurality of compression signals according to the plurality of clock signals;

[0008] A data bus driving circuit is connected to the compression signal generating circuit, and the data bus driving circuit is used to receive multi-bit data and compress the multi-bit data according to the multiple compression signals; wherein the transmission duration of each bit of the compressed data is equal to the first pulse width.

[0009] In a second aspect, an embodiment of the present disclosure provides a memory, including:

[0010] A storage array, wherein the storage array is used to store data;

[0011] The peripheral circuit comprises a data processing circuit as described in any one of the first aspects of the present disclosure, wherein the data processing circuit is used to process the data read out from the storage array.

[0012] In the embodiment of the present disclosure, the first pulse width of the first effective pulse of the clock signal is set to be equal to the transmission time of each bit of data after compression, and the number of clock signals is multiple, so that multiple compressed signals can be generated through relatively simple logical operations, thereby reducing the complexity of the compressed signal generation circuit and saving layout space. Moreover, since the clock signal includes multiple first effective pulses, the compressed signal can also include multiple effective pulses, so that the compressed signal is at a low level during the time other than the effective pulse, thereby reducing the power consumption of the data processing circuit. On the other hand, the data processing circuit provided by the embodiment of the present disclosure can compress data, thereby saving the number of data buses, saving the area used for metal wires by the data bus, facilitating the miniaturization of the device, and reducing the difficulty of wiring the metal conductive layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of a memory provided by an embodiment of the present disclosure;

[0014] Figure 2 A schematic diagram of a data processing circuit provided in an embodiment of the present disclosure;

[0015] Figure 3 A schematic diagram of a compressed signal provided by an embodiment of the present disclosure;

[0016] Figure 4 A schematic diagram of another data processing circuit provided by an embodiment of the present disclosure;

[0017] Figure 5 A schematic diagram of a clock signal provided in an embodiment of the present disclosure;

[0018] Figure 6 A schematic diagram of another data circuit provided by an embodiment of the present disclosure;

[0019] Figure 7 A schematic diagram of a clock generation circuit and a first delay circuit provided in an embodiment of the present disclosure;

[0020] Figure 8 A schematic diagram of an enable signal generating circuit and a second delay circuit provided in an embodiment of the present disclosure;

[0021] Fig. 9 A timing diagram of related signals in a read enable signal generation process provided by an embodiment of the present disclosure;

[0022] Fig.10A schematic diagram of a differential reset signal generating circuit provided in an embodiment of the present disclosure;

[0023] Fig.11 A schematic diagram of a compressed signal provided by an embodiment of the present disclosure;

[0024] Fig.12 A schematic diagram of a compression signal generating circuit provided by an embodiment of the present disclosure;

[0025] Fig.13 A schematic diagram of a data bus driving circuit provided by an embodiment of the present disclosure;

[0026] Fig.14 for Fig.13 The schematic diagram of the data bus driving circuit shown compresses data;

[0027] Figures 15a to 15c A timing diagram of a compressed signal and data provided by an embodiment of the present disclosure;

[0028] Figures 16a to 16c A timing diagram of another compressed signal and data provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] The technical solution of the present disclosure is described in detail below in conjunction with the accompanying drawings and specific embodiments of the specification. Although the exemplary implementation method of the present disclosure is shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0030] The present disclosure is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer according to the following description and claims. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present disclosure. It should be noted that the technical solutions recorded in the embodiments of the present disclosure can be arbitrarily combined without conflict.

[0031] The technical solution provided by the embodiments of the present disclosure is applicable to, but not limited to, dynamic random access memory (DRAM), static random access memory (SRAM), NAND memory, etc. DRAM includes, but is not limited to, DDR4 SDRAM (Double Data Rate Fourth Synchronous Dynamic Random Access Memory, DDR4 for short), DDR5 SDRAM (DDR5 for short) and DDR6 SDRAM (DDR6 for short). The embodiments of the present disclosure take DDR5 as an example to describe the technical solution provided by the embodiments of the present disclosure in detail, but it should be understood that the technical solution is also applicable to other memories.

[0032] Figure 1 A schematic diagram of a memory provided by an embodiment of the present disclosure. Figure 1 As shown, the memory may include multiple bank groups (Bank Group, BG), such as Figure 1 The eight shown are BGA, BGB, BGC, BGD, BGE, BGF, BGG and BGH. Each BG may include multiple banks, for example, four, Bank0 to Bank3. A bank may include one or more memory arrays. Each bank may independently perform operations such as activation, precharging, and data reading.

[0033] In some embodiments, the burst length BL of the memory can be 8 bits, 16 bits, or 32 bits. A burst refers to a method in which adjacent memory cells in the same row continuously transmit data, and the number of memory cells involved in the continuous transmission is the burst length (Burst Lengths, BL for short). For a memory configured in X8 mode (8 data input and output ports) with a burst length of 16 bits, after a burst read command, 16×8=128 bits of data are read from the memory and transmitted to the memory controller.

[0034] When the memory reads data, the data is read out from the storage array, transferred to the buffer, and then transferred from the buffer to the memory controller. Figure 1 Figure 2 shows the process of data being transferred from the storage array to the buffer. Figure 1As shown, the data read out from the storage array (such as BGA) is first transmitted to the input / output sense amplifier IOSA, and the input / output sense amplifier IOSA then transmits the data to the data bus driver circuit DATABUS_DRV, and the data bus driver circuit DATABUS_DRV further transmits the data to the buffer group (LDQ0, LDQ1, LDQ2, LDQ3, LDQ4, LDQ5, LDQ6 and LDQ7) through the data bus RDBUS. During each reading process, each data bus transmits one bit of data. If 128 bits of data are read at a time as described above, 128 data buses are required. These 128 data buses occupy more line resources, which is not conducive to the miniaturization of the memory and will increase the difficulty of other line layouts. In addition, in some embodiments, the data bus is usually located in the M4 metal layer with the fastest transmission rate. The data bus occupies a large area of ​​the M4 metal layer, resulting in a reduction in the area of ​​the M4 metal layer that can be used by other lines that need to transmit data at high speed, resulting in an increase in the difficulty of the line layout of the entire memory, which is not conducive to improving the performance of the memory.

[0035] In some embodiments, in order to reduce the area occupied by the data bus on the M4 metal layer and save more lines, data compression can be used to compress the data transmission time to half of the original. Originally, each data bus can only transmit one bit of data within its bus transmission time, and the transmission time of the compressed data is half of the original, so each data bus can transmit two bits of data within its bus transmission time, so 128 bits of data only needs 64 data buses for transmission, which reduces the number of data buses by half, thereby reducing the area occupied by the data bus on the M4 metal layer.

[0036] It should be noted that the transmission time of one bit of data is the time required for the data to be transmitted. In some embodiments, the transmission time of the data read from the memory array may be 8T. T is the clock signal CKT used to transmit data between the memory and the memory controller (see Fig. 9 ) cycle. The rate of reading data from the memory array is much lower than the market requirement for the data transmission rate between the memory and the memory controller. Therefore, the memory adopts a prefetch mechanism. For example, DDR5 uses 16n prefetch. Considering that DDR5 uses both the rising and falling edges of the clock to transmit data, the data transmission rate between the memory and the memory controller is equal to 8 times the rate of reading data from the memory array. Then the transmission time of the data read from the memory array is 8 times the period of the clock signal used to transmit data between the memory and the memory controller, that is, 8T.

[0037] The bus transfer time is the time that the data bus allows to transfer data between two adjacent read commands. In some embodiments, the bus transfer time can be obtained based on tCCD_S. In tCCD_S, CCD stands for "Column to Column Delay" and S stands for "Short". 。 tCCD_S indicates the shorter delay time between consecutive read / write commands of different bank groups (BG). Of course, there is another parameter tCCD_L for memory, where L stands for "Long". tCCD_L indicates the longer delay time between consecutive read / write commands of the same bank group (BG). The bus transfer time of the data bus should take into account different read and write situations, so the bus transfer time is determined based on tCCD_S with a shorter delay time.

[0038] In some embodiments, the bus transmission time of the data bus may be 8T. Before data compression, each data bus can only transmit one bit of data within the bus transmission time (8T), and after the transmission time of each bit of data is reduced by half, the transmission time of each bit of data is 4T, so the data bus can serially transmit two bits of data within the bus transmission time of 8T, thereby reducing the number of data buses by half.

[0039] Figure 2 Schematic diagram of a data processing circuit provided by an embodiment of the present disclosure, the data processing circuit can be used to transmit 128 bits of data to a buffer via 64 data buses. Figure 2 As shown, the data processing circuit includes a command generator 100, a column selection signal generating circuit 210, a column decoder 220, an input / output sense amplifier 230, an error correction code circuit (ECC) 310, a clock generating circuit 320, a data center 330, a data bus driving circuit 340, a data bus 350, and a buffer 360.

[0040] The command generator 100 receives the command RD sent by the memory controller and generates a read command READ. The read command READ includes column address information. The command generator 100 transmits the read command READ to the column selection signal generation circuit 210 and the clock generation circuit 320.

[0041] The column selection signal generating circuit 210 receives a read command READ, obtains column address information in the read command READ, generates a column selection signal CSL, and transmits the column selection signal CSL to the column decoder 220 .

[0042] The column decoder 220 opens the corresponding column address in the memory array according to the column select signal CSL to latch the data in the column address in the input / output sense amplifier 230. For example, the memory array may be Figure 1 A memory bank in any memory bank group.

[0043] The clock generating circuit 320 generates a clock signal RDCKD after receiving the read command READ, and transmits the clock signal RDCKD to the data center 330 .

[0044] The data center 330 receives the clock signal RDCKD, generates an enable signal IOSAEN according to the clock signal RDCKD, and transmits the enable signal IOSAEN to the input / output sense amplifier 230. In addition, the data center 330 also transmits the clock signal RDCKD to the error correction code circuit 310. The error correction code circuit 310 delays the clock signal RDCKD to generate a delayed clock signal DTCK_ECC. The delayed clock signal DTCK_ECC is returned to the data center 310. The data center 310 receives the delayed clock signal DTCK_ECC to generate a compression signal MUX, and transmits the compression signal MUX to the data bus driver circuit 340.

[0045] When receiving the enable signal IOSAEN, the input / output read amplifier 230 transmits the latched data to the error correction code circuit 310 . The error correction code circuit 310 can detect the data and correct the detected erroneous data, and transmit the corrected data to the data bus driver circuit 340 .

[0046] The data bus driving circuit 340 receives multi-bit data and a compression signal MUX, and upon receiving the compression signal MUX, compresses the multi-bit data according to the compression signal MUX, and then transmits the compressed data to the buffer 360 through the data bus 350 .

[0047] Figure 3 A schematic diagram of a compression signal is provided for an embodiment of the present disclosure. In some embodiments, the clock signal RDCKD includes a valid pulse with a pulse width of 4T. The number of compression signals MUX is two, and the two compression signals MUX are respectively as follows: Figure 3 The first compression signal MUX1 and the second compression signal MUX2 are shown, the first compression signal MUX1 includes a valid pulse with a pulse width of 4T, the second compression signal MUX2 is an inverted signal of the first compression signal MUX1, and the first compression signal MUX1 and the second compression signal MUX2 are synchronized. In this embodiment, the data bus driving circuit 340 can compress the transmission time of each bit of data from the original 8T to 4T according to the first compression signal MUX1 and the second compression signal MUX2, and transmit the two bits of data serially to a data bus 350, so that 128 bits of data are transmitted to the buffer 360 through 64 data buses within the bus transmission time, saving lines.

[0048] However, if Figure 3As shown in FIG. 1 , the second compression signal MUX2 is at a high level during other times except for the effective pulse, that is, the second compression signal MUX2 is always at a high level, and the input / output sense amplifier 230 and the data bus driving circuit 340 are connected by a bidirectional conductive line. The bidirectional conductive line includes a write data line when performing a write operation and a read data line when performing a read operation. When performing a read operation, the read data line can transmit the data in the input / output sense amplifier 230 to the data bus driving circuit 340, and when performing a write operation, the write data line transmits the data in the data bus driving circuit 340 to the input / output sense amplifier 230. Since the second compression signal MUX2 is always at a high level, when performing a write operation, the data on the write data line may affect the read data line, resulting in data generated on the read data line, that is, there is a high and low level switching on the read data line, which leads to an increase in the power consumption of the data processing circuit, and then leads to an increase in the power consumption of the memory.

[0049] In view of this, the present disclosure provides another data processing circuit, such as Figure 4 As shown, the data processing circuit also includes:

[0050] A clock generating circuit 410, the clock generating circuit 410 is used to generate a plurality of clock signals; the clock signals include a plurality of first valid pulses having a first pulse width, the plurality of clock signals are delayed in sequence, and the delay time between two adjacent clock signals is equal to the first pulse width;

[0051] A compression signal generating circuit 500 is connected to the clock generating circuit 410, and is used to generate a plurality of compression signals according to a plurality of clock signals, wherein the compression signals include one or more valid pulses;

[0052] The data bus driving circuit 600 is connected to the compression signal generating circuit 500. The data bus driving circuit 600 is used to receive multi-bit data and compress the multi-bit data according to multiple compression signals; wherein the transmission time length of each bit of compressed data is equal to the first pulse width.

[0053] In the embodiment of the present disclosure, each clock signal includes a plurality of first valid pulses, each first valid pulse has a first pulse width, and the time interval between adjacent first valid pulses is equal to the first pulse width. The first valid pulse is a high level pulse, and the first pulse width refers to the duration of the high level, while the clock signal is a low level at other times. The number of first valid pulses of the clock signal is finite, and "finite" means that the clock signal is not always switching between high and low levels (that is, the clock signal is not always toggle), but includes a finite number of first valid pulses, such as 2, 3 or 4. The clock signal provided in the embodiment of the present disclosure can reduce the power consumption of the memory.

[0054] The clock generation circuit 410 is used to generate multiple clock signals, and the multiple clock signals are delayed in sequence, that is, any two clock signals are not synchronized. The delay time between two adjacent clock signals in the multiple clock signals delayed in sequence is equal to the first pulse width.

[0055] The compression signal generating circuit 500 receives a plurality of clock signals, and generates a plurality of compression signals after performing logic operations on the plurality of clock signals. The compression signal includes one or more valid pulses, and the valid pulse of the compression signal is a high level pulse, and the compression signal is a low level during the time other than the valid pulse. In other words, before the compression signal generating circuit 500 receives the clock signal, the output terminal level is a low level, and after the compression signal is output, the output terminal level is restored to a low level.

[0056] The compression signal can be used to indicate the transmission order of the compressed data. In other words, the design process of the compression signal is: according to the required transmission order of the compressed data, a plurality of clock signals are logically operated to generate a plurality of compression signals. The compression signal must ensure that the transmission duration of the compressed data is equal to the first pulse width, and that the compressed data has the required transmission order. It should be understood that when the required transmission order is different, the pulse width and number of the effective pulses of the compression signal, as well as the delay relationship between different compression signals may be different.

[0057] In the embodiment of the present disclosure, the first pulse width of the first valid pulse of the clock signal is set to be equal to the transmission time of each bit of data after compression, and the number of clock signals is multiple, so that multiple compressed signals can be generated through relatively simple logical operations, thereby reducing the complexity of the compressed signal generation circuit and saving layout space. Moreover, since the clock signal includes multiple first valid pulses, the compressed signal can also include multiple valid pulses, so that the compressed signal is at a low level during the time other than the valid pulse, thereby reducing the power consumption of the data processing circuit. On the other hand, the data processing circuit provided by the embodiment of the present disclosure can compress the data, thereby saving the number of data buses, saving the area used by the data bus on the M4 metal layer, facilitating the miniaturization of the device, and reducing the difficulty of M4 metal layer wiring.

[0058] In some embodiments, Figure 5 As shown, the multiple clock signals include: a first clock signal QRDCK and a second clock signal QRDCK_I;

[0059] The first clock signal QRDCK includes two first valid pulses. The second clock signal QRDCK_I is a delayed signal of the first clock signal QRDCK, and the delay time length is the first pulse width.

[0060] The clock signal provided in this embodiment includes only two first valid pulses, and the clock signal does not switch between high and low levels all the time, which can reduce the power consumption of the memory.

[0061] In some embodiments, the first pulse width is equal to one-fourth of the bus transmission time. For example, when the bus transmission time is 8T as described above, the first pulse width is 2T, and the time interval between adjacent first valid pulses is 2T. The transmission time of each bit of data after compression is equal to the first pulse width, so that the transmission time of each bit of data after compression is 2T. Then each data bus can transmit 4 bits of data to the buffer within the bus transmission time of 8T, thereby reducing the number of data buses to one-fourth of the original. Taking the transmission of 128Bits of data as an example, 128Bits of data requires 32 data buses for transmission, thereby reducing the number of data buses from the original 128 to 32, thereby greatly reducing the area of ​​the M4 metal layer occupied by the data bus.

[0062] Figure 6 A schematic diagram of another data processing circuit provided by an embodiment of the present disclosure. Figure 6 As shown, the data processing circuit further includes a command generator 100, which receives the instruction RD sent by the memory controller and generates a read command READ. A clock generation circuit 410 is connected to the command generator 100, which receives the read command READ and generates a first clock signal QRDCK and a second clock signal QRDCK_I according to the read command READ.

[0063] In some embodiments, Figure 7 As shown, the clock generation circuit 410 includes:

[0064] A shift register, comprising four flip-flops 411 (including 411-1 to 411-4) connected in series; a signal input end of a current flip-flop 411 is connected to an output end of a previous flip-flop 411, a signal input end of a first flip-flop 411-1 is used to receive a read command READ, and the read command READ comprises a second valid pulse with a first pulse width;

[0065] The first clock generating unit includes a first OR gate circuit 412; two input terminals of the first OR gate circuit 412 are respectively connected to the output terminal of the first flip-flop 411-1 and the output terminal of the third flip-flop 411-3, and the output terminal of the first OR gate circuit 412 outputs the first clock signal QRDCK;

[0066] The second clock generating unit includes a second OR gate circuit 413; two input terminals of the second OR gate circuit 413 are respectively connected to the output terminal of the second flip-flop 411-2 and the output terminal of the fourth flip-flop 411-4, and the output terminal of the second OR gate circuit 413 outputs the second clock signal QRDCK_I.

[0067] Figure 7 The clock generation circuit 410 shown is used to generate Figure 5 The first clock signal QRDCK and the second clock signal QRDCK_I are shown.

[0068] In this embodiment, the signal input end of the current trigger 411 is connected to the output end of the previous trigger 411, which means: the signal input end of the second trigger 411-2 is connected to the output end of the first trigger 411-1, the signal input end of the third trigger 411-3 is connected to the output end of the second trigger 411-2, and the signal input end of the fourth trigger 411-4 is connected to the output end of the third trigger 411-3.

[0069] The clock terminals of the four flip-flops 411 are used to receive the same internal clock signal PCLKB, and the differential clock terminals of the four flip-flops are used to receive the same differential internal clock signal PCLKD. The differential internal clock signal PCLKD is a differential signal of the internal clock signal PCLKB.

[0070] In some embodiments, the internal clock signal PCLKB switches between a high level and a low level, and the clock period of the internal clock signal PCLKB is 2T. The signal at the output of the first trigger 411-1 includes a valid pulse with a first pulse width, and the signal at the output of the second trigger 411-2 is a delayed signal of the signal at the output of the first trigger 411-1, and the delay time is equal to the first pulse width. Similarly, the signal at the output of the third trigger 411-3 is a delayed signal of the signal at the output of the second trigger 411-2, and the delay time is equal to the first pulse width; the signal at the output of the fourth trigger 411-4 is a delayed signal of the signal at the output of the third trigger 411-3, and the delay time is equal to the first pulse width.

[0071] In this embodiment, since the signals at the output ends of the four flip-flops 411 have the above-mentioned delay relationship, the first clock signal QRDCK can include two first valid pulses with a first pulse width, and the second clock signal QRDCK_I is a delayed signal of the first clock signal QRDCK.

[0072] In some embodiments, the first OR gate circuit 412 may include a fourth NOR gate and a seventh inverter connected in series, the two input terminals of the fourth NOR gate are the two input terminals of the first OR gate circuit 412, and the output terminal of the seventh inverter is the output terminal of the first OR gate circuit 412. Similarly, the second OR gate circuit 413 may include a fifth NOR gate and an eighth inverter connected in series, the two input terminals of the fifth NOR gate are the two input terminals of the second OR gate circuit 413, and the output terminal of the eighth inverter is the output terminal of the second OR gate circuit 413.

[0073] In some other embodiments, the first OR gate circuit 412 may also include a first OR gate, and the second OR gate circuit 413 may also include a second OR gate.

[0074] In some embodiments, Figure 7 As shown, the trigger 411 includes two cascaded half latches (Half Latch, H / L), the signal input end of the second half latch is connected to the output end of the first half latch, the clock end of the second half latch is connected to the differential clock end of the first half latch, and the differential clock end of the second half latch is connected to the clock end of the first half latch.

[0075] In some embodiments, the trigger 411 may be a rising edge trigger, that is, when the internal clock signal switches from a low level to a high level, the state of the output terminal is changed according to the state of the signal input terminal. The trigger 411 may also be a falling edge trigger, that is, when the internal clock signal switches from a high level to a low level, the state of the output terminal is changed according to the state of the signal input terminal.

[0076] In some embodiments, Figure 6 and Figure 7 As shown, the data processing circuit also includes a first delay circuit 420, which is used to perform a first delay on the first clock signal QRDCK and the second clock signal QRDCK_I to obtain a first delayed first clock signal QRDCKD and a first delayed second clock signal QRDCKD_I.

[0077] The delay relationship between the first clock signal QRDCKD after the first delay and the second clock signal QRDCKD_I after the first delay is the same as the delay relationship between the first clock signal and the second clock signal. Figure 7 As shown, the first clock signal QRDCKD after the first delay includes two first valid pulses, and the second clock signal QRDCKD_I after the first delay is a delayed signal of the first clock signal QRDCKD after the first delay, and the delay time length is the first pulse width.

[0078] The duration of the first delay is the first preset duration. In some embodiments, the first preset duration is based on Figure 6 The column selection signal generating circuit 210 shown generates the column selection signal CSL, and the column decoder 220 determines the time to transmit the multi-bit data to the input / output sense amplifier 230 based on the column selection signal CSL, so that the subsequently generated read enable signal RDEN can be later than or synchronized with the data transmission to the input / output sense amplifier 230.

[0079] In some embodiments, Figure 7 As shown, the first delay circuit includes: a first delay unit 421 and a second delay unit 422;

[0080] The first delay unit 421 is connected to the first clock generating unit, and the first delay unit 421 is used to perform a first delay on the first clock signal QRDCK to generate a first clock signal QRDCKD after the first delay;

[0081] The second delay unit 422 is connected to the second clock generating unit, and is used for performing a first delay on the second clock signal QRDCK_I to generate a first delayed second clock signal QRDCKD_I.

[0082] In some embodiments, the second delay unit 422 has the same circuit as the first delay unit 421. For example, the first delay unit 421 may include an even number of inverters connected in series, and the second delay unit 422 includes the same number of inverters connected in series as the first delay unit 421.

[0083] In some embodiments, see Figure 6 , the data processing circuit further includes: an enable signal generating circuit 710 and an input / output sense amplifier 230;

[0084] The enable signal generating circuit 710 is connected to the clock generating circuit 410, and the enable signal generating circuit 710 is used to receive the first clock signal QRDCK (or the first clock signal QRDCKD after the first delay), and output the first first valid pulse in the first clock signal QRDCK (or the first clock signal QRDCKD after the first delay) as the read enable signal RDEN;

[0085] The input / output sense amplifier 230 is connected to the enable signal generating circuit 710 and the data bus driving circuit 600 , and the input / output sense amplifier 230 is used to transmit multi-bit data to the data bus driving circuit 600 according to the read enable signal RDEN.

[0086] It should be noted that, in some embodiments, when the data processing circuit includes the first delay circuit 420, the enable signal generating circuit 710 is connected to the first delay circuit 420, and the enable signal generating circuit 710 is used to receive the first clock signal QRDCKD after the first delay, and output the first first valid pulse in the first clock signal QRDCKD after the first delay as the read enable signal RDEN. It should be understood that the pulse width of the valid pulse of the read enable signal RDEN obtained using the first clock signal QRDCK and the read enable signal RDEN obtained using the first clock signal QRDCKD after the first delay are the same, but there is a slight delay in time.

[0087] In this embodiment, the enable signal generating circuit 710 selects the first first valid pulse of the first clock signal QRDCK (or the first clock signal QRDCKD after the first delay) as the read enable signal RDEN, and can generate the read enable signal RDEN as quickly as possible, thereby outputting the data as quickly as possible. It should be understood that the second first valid pulse of the first clock signal QRDCK or any first valid pulse of the second clock signal QRDCK_I can also be used as the read enable signal RDEN, but this requires a longer time to generate the read enable signal RDEN, affecting the output read rate, thereby affecting the read speed of the memory.

[0088] In some embodiments, Figure 8 As shown, the enable signal generating circuit 710 includes: a fifth inverter 711, an odd number of sixth inverters 712 connected in series, a third trigger 713 and a third NOR gate 714;

[0089] The input end of the fifth inverter 711 is used to receive the first clock signal QRDCK (or the first clock signal QRDCKD after the first delay), and the output end of the fifth inverter 711 is connected to the signal input end of the third flip-flop 713, the input end of the first sixth inverter 712 among the odd number of sixth inverters 712, and the first input end of the third NOR gate 714;

[0090] An output terminal of the last sixth inverter 712 among the odd number of sixth inverters 712 is connected to a clock terminal of the third flip-flop 713;

[0091] The reset terminal of the third flip-flop 713 is used to receive the differential reset signal RESETB, the output terminal of the third flip-flop 713 is connected to the second input terminal of the third NOR gate 714, and the output terminal of the third NOR gate 714 is used to output the read enable signal RDEN.

[0092] In some embodiments, the differential reset signal RESETB is obtained based on the next read command READ.

[0093] In some embodiments, Figure 8 As shown, the third trigger 713 includes two cascaded half latches, the signal input end of the second half latch is connected to the output end of the first half latch, the clock end of the second half latch is connected to the differential clock end of the first half latch, and the differential clock end of the second half latch is connected to the clock end of the first half latch.

[0094] In some embodiments, the third trigger 713 may be a rising edge trigger or a falling edge trigger.

[0095] Fig. 9 The timing diagram of the related signals in the generation process of the read enable signal RDEN provided in the embodiment of the present disclosure. Figure 8 and Fig. 9 As shown, the fifth inverter 711 inverts the first clock signal QRDCKD after the first delay to generate the first clock signal inversion signal QRDCKD_IN. The odd number of sixth inverters 712 connected in series delay the first clock signal inversion signal QRDCKD_IN and invert it again to generate the first clock signal delay signal QRDCKD_T. The signal input end of the third flip-flop 713 receives the first clock signal inversion signal QRDCKD_IN, the clock end receives the first clock signal delay signal QRDCKD_T, and the differential clock end receives the inversion signal QRDCKD_B of the first clock signal delay signal.

[0096] In this embodiment, the third flip-flop 713 is falling edge triggered, so when the first clock signal inversion signal QRDCKD_IN corresponding to the first falling edge of the first clock signal delay signal QRDCKD_T is high, the output terminal signal QRD_GATING of the third flip-flop 713 is switched to high level and maintained at high level. At the second falling edge of the first clock signal delay signal QRDCKD_T, the first clock signal inversion signal QRDCKD_IN is still high level, so the output terminal signal QRD_GATING of the third flip-flop 713 continues to maintain high level. Until the next read command READ arrives, the differential reset signal RESETB is applied to the differential reset terminal of the third flip-flop 713, and the output terminal signal QRD_GATING of the third flip-flop 713 is reset to low level.

[0097] Continue to see Fig. 9 The third NOR gate 714 receives the first clock signal inversion signal QRDCKD_IN and the output terminal signal QRD_GATING of the third flip-flop 713, and outputs the read enable signal RDEN. Fig. 9As shown, according to the truth table of the NOR gate, when the output terminal signal QRD_GATING of the third flip-flop 713 is at a low level, the read enable signal RDEN is the inverted signal of the first clock signal inverted signal QRDCKD_IN, so the read enable signal RDEN is at a high level, which is equivalent to retaining the first first valid pulse of the first clock signal QRDCKD after the first delay. When the output terminal signal QRD_GATING of the third flip-flop 713 is switched to a high level, the read enable signal RDEN is always at a low level, so that the read enable signal RDEN has only one valid pulse between two read commands READ.

[0098] Continue to see Fig. 9 When the next read command READ arrives, the clock generation circuit 410 generates the next set of first clock signals QRDCK and second clock signals QRDCK_I, and then generates the next first delayed first clock signal QRDCKD, and generates the next read enable signal RDEN. Fig. 9 In the embodiment, there is a delay VDLY between the read command READ and the first clock signal QRDCKD after the first delay, and this delay VDLY is generated by the first delay circuit 420, which is used to delay the time of generating the read enable signal RDEN so that the read enable signal RDEN reaches the input / output read amplifier 230 no earlier than the data. Fig. 9 The RD shown in can be considered as Figure 6 The command generator 100 receives the instruction RD from the memory controller.

[0099] In some embodiments, Fig. 9 The timing diagram shown is a timing diagram of the same memory bank group (BG) executing continuous read commands. In this embodiment, the longer delay time tCCD_L when the same memory bank group executes continuous read commands is 10T. In other embodiments, the shorter delay time tCCD_S when different memory bank groups execute continuous read / write commands is 8T. The data transmission time and the bus transmission time of the data bus are both less than or equal to 8T.

[0100] In some embodiments, Fig.10 As shown, the data processing circuit further includes a differential reset signal generating circuit 730, and the differential reset signal generating circuit 730 includes: a first AND gate circuit 731, an odd number of ninth inverters 732 connected in series, a second AND gate circuit 733 and a sixth NOR gate 734;

[0101] Two input terminals of the first AND gate circuit 731 receive a read command READ and a memory bank group command BG respectively; an output terminal of the first AND gate circuit 731 is connected to a first input terminal of a second AND gate circuit 733;

[0102] The input end of the first ninth inverter 732 of the odd number of ninth inverters 732 connected in series is connected to the output end of the first AND gate circuit 731, and the output end of the last ninth inverter 732 of the odd number of ninth inverters 732 connected in series is connected to the second input end of the second AND gate circuit 733;

[0103] The output end of the second AND gate circuit 733 is connected to the first input end of the sixth NOR gate 734 . The second input end of the sixth NOR gate 734 is used to receive the reset signal RESET. The output end of the sixth NOR gate circuit 734 outputs the differential reset signal RESETB.

[0104] In some embodiments, Fig.10 As shown, the first AND gate circuit 731 includes a first NAND gate and a tenth inverter connected in series, and the fourth AND gate circuit 733 includes a second NAND gate and an eleventh inverter connected in series.

[0105] The signals received at the two input terminals of the second AND gate circuit 733 are inverted signals, so the level of the output terminal of the second AND gate circuit 733 is a low level. Further, when the reset signal RESET is a high level, the signal at the output terminal of the sixth NOR gate 734 is a low level. When the reset signal RESET is a low level, the signal at the output terminal of the sixth NOR gate 734 is a high level. Fig.10 The differential reset signal generating circuit 730 shown in FIG. 1 generates a differential reset signal RESETB upon receiving a read command READ, thereby Figure 8 The third flip-flop 713 is shown reset.

[0106] In some embodiments, see Figure 6 and Figure 8 The data processing circuit also includes: a second delay circuit 720, the second delay circuit 720 is connected to the first delay circuit 420, and the second delay circuit 720 is used to perform a second delay on the first clock signal QRDCKD after the first delay and the second clock signal QRDCKD_I after the first delay to obtain the first clock signal QRDCKDD after the second delay and the second clock signal QRDCKDD_I after the second delay.

[0107] The delay relationship between the second delayed first clock signal QRDCKDD and the second delayed second clock signal QRDCKDD_I is the same as the delay relationship between the first clock signal QRDCK and the second clock signal QRDCK_I. Figure 8 As shown, the second delayed first clock signal QRDCKDD includes two first valid pulses, the second delayed second clock signal QRDCKDD_I is a delayed signal of the second delayed first clock signal QRDCKDD, and the delay time is the first pulse width.

[0108] The duration of the second delay is the second preset duration. In some embodiments, the second preset duration is determined according to the time when the enable signal generating circuit 710 generates the read RDEN enable signal, so as to synchronize the first clock signal QRDCKDD after the second delay, the second clock signal QRDCKDD_I after the second delay, and the read enable signal RDEN.

[0109] In some embodiments, Figure 8 As shown, the second delay circuit 720 includes: a third delay unit 721 and a fourth delay unit 722;

[0110] The third delay unit 721 is connected to the first delay unit 421, and is used to perform a second delay on the first clock signal QRDCKD after the first delay to generate the first clock signal QRDCKDD after the second delay;

[0111] The fourth delay unit 722 is connected to the second delay unit 422 , and is used for performing a second delay on the second clock signal QRDCKD_I after the first delay, to generate the second clock signal QRDCKDD_I after the second delay.

[0112] In some embodiments, the circuit elements of the third delay unit 721 and the fourth delay unit 722 may be the same or different.

[0113] In some embodiments, Figure 8 As shown, the third delay unit 721 includes: a fifth inverter 711 and a third NAND gate 7211; the first input end of the third NAND gate 7211 is connected to the output end of the fifth inverter 711, the second input end of the third NAND gate 7211 is used to receive the power supply voltage VDD, and the output end of the third NAND gate 7211 outputs the first clock signal QRDCKDD after the second delay.

[0114] like Figure 8 As shown, in the third delay unit 721, the fifth inverter 711 inverts the first clock signal QRDCKD after the first delay to generate the first clock signal inversion signal QRDCKD_IN. The second input terminal of the third NAND gate 7211 receives the power supply voltage VDD. For example, the power supply voltage VDD is at a high level. Therefore, the output terminal of the third NAND gate 7211 is inverted with the signal of the first input terminal, that is, the third NAND gate 7211 inverts the first clock signal inversion signal QRDCKD_IN, so that the signal outputted from the output terminal of the third AND gate 7211 is the same as the first clock signal QRDCKD. Therefore, the third delay unit 721 delays the first clock signal QRDCKD after the first delay.

[0115] The fourth delay unit 722 includes: a twelfth inverter 7221 and a fourth NAND gate 7222; the input end of the twelfth inverter 7221 is used to receive the second clock signal QRDCKD_I after the first delay, and the output end of the twelfth inverter 7221 is connected to the first input end of the fourth NAND gate 7222; the second input end of the fourth NAND gate 7222 is used to receive the power supply voltage VDD, and the output end of the fourth NAND gate 7222 outputs the second clock signal QRDCKDD_I after the second delay.

[0116] In some other embodiments, the fourth delay unit may also be: the twelfth inverter 7221 is connected to the output end of the fourth NAND gate 7222, and the two input ends of the fourth NAND gate 7222 are respectively used to receive the second clock signal QRDCKD_I and the power supply voltage VDD after the first delay. In the fourth delay unit 722, the second input end of the fourth NAND gate 7222 receives the power supply voltage VDD. For example, the power supply voltage VDD is at a high level, so the output end of the fourth NAND gate 7222 is consistent with the signal of the first input end, so that the fourth delay unit 722 delays the second clock signal QRDCKD_I after the first delay.

[0117] In this embodiment, the circuit elements in the fourth delay unit 722 are the same as the circuit elements in the third delay unit 721 , and therefore, the second delayed first clock signal QRDCKDD and the second delayed second clock signal QRDCKDD_I are synchronized.

[0118] It should be understood that, in some embodiments, the third delay unit 721 and the fourth delay unit 722 may also include an even number of inverters connected in series to achieve the delay function.

[0119] In some embodiments, Figure 6 and Figure 8 As shown, the data processing circuit also includes: an error correction code circuit 800, which is used to receive the data output by the input / output read amplifier 230, detect the data and correct the detected erroneous data, and then transmit the corrected data to the data bus driving circuit 600.

[0120] In this embodiment, if Figure 6 and Figure 8 As shown, the error correction code circuit 800 is also connected to the second delay circuit 720. The error correction code circuit 800 receives the first clock signal QRDCKDD after the second delay and the second clock signal QRDCKDD_I after the second delay, and delays the two signals to generate the first error correction clock signal QRDECC and the second error correction clock signal QRDECC_I accordingly.

[0121] The delay relationship between the first error correction clock signal QRDECC and the second error correction clock signal QRDECC_I is the same as the delay relationship between the first clock signal QRDCK and the second clock signal QRDCK_I. That is, the first error correction clock signal QRDECC includes two first valid pulses, and the second error correction clock signal QRDECC_I is a delayed signal of the first error correction clock signal QRDECC, and the delay time is the first pulse width.

[0122] The error correction code circuit 800 delays the first clock signal QRDCKDD after the second delay and the first clock signal QRDCKDD_I after the second delay because the data latched in the input / output read amplifier 230 needs to be detected and corrected by the error correction code circuit 800 before being transmitted to the data bus driver circuit 600. In order to make the compressed signal and data arrive at the data bus driver circuit 600 synchronously, these two clock signals are also delayed by the error correction code circuit 800.

[0123] From the perspective of data flow and signal flow, the first delay circuit 420 delays the clock signal for the first time in order to make the delayed read enable signal RDEN arrive later than or synchronously with the data at the input / output sense amplifier 230. The second delay circuit 720 and the error correction code circuit 800 delay the clock signal in order to compensate the compressed signal for the time spent on generating the read enable signal RDEN and the time for the data to be processed by the error correction code circuit 800, thereby synchronizing the compressed signal with the data.

[0124] It should be understood that the delay method for the clock signal provided in the above embodiment of the present disclosure is only an example. In other embodiments, the setting method of the delay circuit may not be limited to this. For example, in order to synchronize the compressed signal and the data, the first delay circuit may also be located between the command generator 100 and the clock generation circuit 410; the second delay circuit may also be located between the error correction code circuit 800 and the compressed signal generation circuit 500, or between the compressed signal generation circuit 500 and the data bus driving circuit 600; or the circuit elements of the enable signal generation circuit 710 and the compressed signal generation circuit 500 or the length of the conductive line during layout may be adjusted so that the data processing circuit does not need to be equipped with a delay circuit.

[0125] Continue to participate Figure 6 and Figure 8 The compression signal generating circuit 500 generates multiple compression signals according to multiple clock signals, the data bus driving circuit 600 compresses the multi-bit data according to the multiple compression signals, and the transmission time length of each bit of compressed data is equal to the first pulse width.

[0126] In some embodiments, if the clock signal is also delayed by the first delay circuit 420, the second delay circuit 720 and the error correction code circuit 800, the compression signal generation circuit 500 generates multiple compression signals according to the error correction clock signal output by the error correction code circuit 800. It should be understood that the error correction clock signal output by the error correction code 800 is exactly the same as the clock signal generated by the clock generation circuit 410, except that there is a delay, so the compressed signal generated according to the error correction clock signal is the same as the compressed signal generated directly according to the clock signal. The subsequent generation of compressed signals according to the clock signal mentioned in this article can be replaced by generating compressed signals according to the error correction clock signal, and vice versa.

[0127] In some embodiments, the compression signal may include a multi-level compression signal, the width of an effective pulse of the multi-level compression signal decreases in sequence according to the number of levels, wherein the width of an effective pulse of the last level compression signal is equal to the first pulse width.

[0128] Corresponding to the multi-level compression signal, the data bus driving circuit includes a multi-level driving circuit, and the multi-level driving circuit corresponds to the multi-level compression signal one by one; each level of the driving circuit is used to compress the received data according to the first level of compression signal, and transmit the compressed data to the next level of driving circuit; wherein the transmission time length of each bit of data output by each level of the driving circuit is equal to the width of the effective pulse of the corresponding compression signal received by it; the transmission time length of each bit of data output by the last level of the driving circuit is equal to the first pulse width.

[0129] In this embodiment, multi-level compression is performed on data using a multi-level compression signal, when the transmission time of the data compressed by the current level driving circuit is less than the transmission time of the data compressed by the previous level driving circuit, until the transmission time of the data compressed by the last level driving circuit is equal to the first pulse width.

[0130] In some embodiments, the pulse widths of the effective pulses of two adjacent compression signals have an integer multiple relationship. Specifically, the pulse width of the effective pulse of the previous compression signal is an integer multiple of the pulse width of the effective pulse of the current compression signal, such as 2 times, 3 times or 4 times. Correspondingly, the transmission duration of the output data of the previous drive circuit is an integer multiple of the transmission duration of the output data of the current drive circuit. In other words, each drive circuit is used to compress the transmission duration of the received data to an integer fraction of the original, such as one-half, one-third or one-quarter.

[0131] In some embodiments, the number of compression signals at each level is multiple, the multiple compression signals at the same level are delayed in sequence, and the delay time between two adjacent compression signals at the same level is equal to the width of the effective pulse of the compression signal; each level of the driving circuit is used to output multi-bit data serially according to the order of the received multiple compression signals.

[0132] The pulse width, number and time interval between adjacent effective pulses of multiple compression signals of the same level are the same. The sequential delay between multiple compression signals of the same level means that any two compression signals of the same level are not synchronized, and the delay time between two adjacent compression signals is equal to the width of the effective pulse of the compression signal of the current level.

[0133] In this embodiment, each level of the driving circuit can receive multi-bit data in parallel and simultaneously and sequentially receive multiple compressed signals of the same level. According to the order of the multiple compressed signals, the parallel multi-bit data is compressed and converted into a serial transmission mode, and the multi-bit compressed data is output serially from the output end.

[0134] In some embodiments, the amount of data received by each stage of the driving circuit is the same as the amount of the compressed signal.

[0135] In some embodiments, Fig.11 As shown, the multiple compression signals include two first-level compression signals MUX_BL and two second-level compression signals DRV_BL;

[0136] The first-stage compression signal MUX_BL includes a third effective pulse with a second pulse width, and the second pulse width is equal to twice the first pulse width; the delay time between the two first-stage compression signals MUX_BL is equal to the second pulse width;

[0137] The second-stage compression signal DRV_BL includes two fourth effective pulses with a first pulse width, and the time interval between the two fourth effective pulses is equal to the first pulse width; the delay time between the two second-stage compression signals DRV_BL is equal to the first pulse width.

[0138] In this embodiment, the two first-level compression signals MUX_BL are respectively the first first-level compression signal MUX_BLC0 and the second first-level compression signal MUX_BLC2. For example, the second first-level compression signal MUX_BLC2 is delayed by a second pulse width relative to the first first-level line pressure signal MUX_BLC0. For example, when the first pulse width is 2T as described above, the second pulse width is 4T.

[0139] The two second-level compression signals DRV_BL are respectively a first second-level compression signal DRV_BL02 and a second second-level compression signal DRV_BL13. For example, the second second-level compression signal DRV_BL13 is delayed by a first pulse width relative to the first second-level compression signal DRV_BL02. For example, the first pulse width is 2T as described above.

[0140] In this embodiment, the third effective pulse of the first-level compression signal MUX_BL and the fourth effective pulse of the second-level compression signal DRV_BL are both high-level pulses, and the constant levels of the first-level compression signal MUX_BL and the second-level compression signal DRV_BL are both low-level, that is, the first-level compression signal MUX_BL is built into a low level at other times except the third effective pulse, and the second-level compression signal DRV_BL is built into a low level at other times except the fourth effective pulse. Such a compression signal can reduce the influence of the data on the write data line between the input / output sense amplifier and the data bus driving circuit on the read data line between the two during the write operation, and avoid the high-low level switching of the read data line during the write operation to increase the power consumption, that is, the compression signal has the effect of reducing the function of the memory.

[0141] In some embodiments, Fig.12 As shown, the compression signal generating circuit 500 includes: a first compression unit 510 , a second compression unit 520 , a third compression unit 530 and a fourth compression unit 540 .

[0142] The first compression unit 510 includes: a first delayer 511, a first inverter 512, a first trigger 513 and a second inverter 514; wherein, the output end of the first delayer 511 is connected to the signal input end of the first trigger 513, and the first delayer 511 is used to receive the second clock signal QRDCK_I (or the second error correction clock signal QRDECC_I); the output end of the first inverter 512 is connected to the clock end of the first trigger 513, and the first inverter 512 is used to receive the first clock signal QRDCK (or the first error correction clock signal QRDECC); the input end of the second inverter 514 is connected to the output end of the first trigger 513, and the second inverter 514 is used to output the first first-level compression signal MUX_BLC0.

[0143] The second compression unit 520 includes: a second delay 521 and a second trigger 522; the output end of the second delay 521 is connected to the clock end of the second trigger 522, and the second delay 521 is used to receive the second clock signal QRDCK_I (or the second error correction clock signal QRDECC_I); the first input end of the second trigger 522 is used to receive the first clock signal QRDCK (or the first error correction clock signal QRDECC); the output end of the second trigger 522 is used to output the second first-level compression signal MUX_BLC2.

[0144] The third compression unit 530 includes an even number of third inverters 531 connected in series. The third compression unit 530 is used to receive the first clock signal QRDCK (or the first error correction clock signal QRDECC) and output the first second-stage compression signal DRV_BL02.

[0145] The fourth compression unit 540 includes an even number of fourth inverters 541 connected in series, wherein the number of fourth inverters 541 is the same as the number of third inverters 531; the fourth compression unit 540 is used to receive the second clock signal QRDCK_I (or the second error correction clock signal QRDECC_I) and output a second second-level compression signal DRV_BL13.

[0146] In some embodiments, Fig.12 As shown, the first delayer 511 and the second delayer 521 may each include an even number of inverters connected in series. For example, the first delayer 511 may include two inverters connected in series, and the second delayer 521 may include two inverters connected in series.

[0147] In some embodiments, the first trigger 513 and the second trigger 522 each include two cascaded half latches, the signal input end of the second half latch is connected to the output end of the first half latch, the clock end of the second half latch is connected to the differential clock end of the first half latch, and the differential clock end of the second half latch is connected to the clock end of the first half latch.

[0148] In some embodiments, the first trigger 513 and the second trigger 522 may be rising edge triggers or falling edge triggers.

[0149] In some implementations, a set terminal of the first flip-flop 513 is used to receive a set signal SET, and a reset terminal of the second flip-flop 522 is used to receive a differential reset signal RSETB.

[0150] The first compression unit 510 and the second compression unit 520 provided in this embodiment use triggers 513 and 522 to double the pulse width of the first error correction clock signal QRDECC and the second error correction clock signal QRDECC_I, thereby obtaining a first-level compression signal MUX_BL. The third compression unit 513 and the fourth compression unit 514 delay the first error correction clock signal QRDECC and the second error correction clock signal QRDECC_I by the same time, thereby obtaining two second-level compression signals DRV_BL. In summary, in the compression signal generating circuit 500 provided in the embodiment of the present disclosure, the four compression units all generate compression signals through the first clock signal and the second clock signal (or the first error correction clock signal and the second error correction clock signal), which is easy to control the delay relationship between the compression signals; and the four delay units have a simple structure and occupy a small layout area.

[0151] In some embodiments, Fig.13 As shown, corresponding to two first-stage compression signals MUX_BL and two second-stage compression signals DRV_BL, the data bus driving circuit 600 includes:

[0152] The first-stage driving circuit 610 has two first input terminals that receive two first-stage compression signals MUX_BLC0 and MUX_BLC2 respectively, and two second input terminals that receive two bits of data respectively; the first-stage driving circuit 610 is used to compress the transmission time length of each bit of the two bits of data to a second pulse width according to the two first-stage compression signals MUX_BLC0 and MUX_BLC2, and output the two bits of compressed data in series;

[0153] The second-stage driving circuit 620 has two first input ends that respectively receive two second-stage compression signals DRV_BL02 and DRV_BL13, and two second input ends that are respectively connected to the output ends of the two first-stage driving circuits 610; the second-stage driving circuit 620 is used to compress the transmission duration of each bit of the four-bit data received from the two first-stage driving circuits 620 from the second pulse width to the first pulse width according to the two second-stage compression signals DRV_BL02 and DRV_BL13, and output the four-bit data serially.

[0154] like Fig.13 As shown, the number of the first-stage driving circuits 610 is multiple. In some embodiments, the number of the first-stage driving circuits 610 is equal to half of the number of data received by the data bus driving circuit 600, and the number of the second-stage driving circuits 620 is half of the number of the first-stage driving circuits 610. For example, Fig.13 It shows that when 16 bits of data are transmitted, the number of the first-stage driving circuits 610 is 8 and the number of the second-stage driving circuits 620 is 4.

[0155] Fig.14 yes Fig.13 The schematic diagram of the data bus driving circuit compressing data is shown in FIG. Fig.13 and 14 As shown, the first first-stage driving circuit 610 receives two first-stage compression signals MUX_BLC0, MUX_BLC2 and data BL0, BL2, and compresses the data BL0 and BL2 and outputs them serially to form new data BL02. The second pulse width of the first-stage compression signal can be 4T. The transmission time length of each bit of data in the data BL02 is 4T, which is equal to the second pulse width.

[0156] By analogy, the second first-stage driving circuit 610 receives two first-stage compression signals MUX_BLC0, MUX_BLC2 and data BL1, BL3, and compresses data BL1 and BL3 and outputs them serially to form new data BL13. The transmission time of each bit of data in data BL13 is 4T, which is equal to the second pulse width.

[0157] The second-stage driving circuit 620 receives two second-stage compression signals DRV_BL02, DRV_BL13 and data BL02, BL13, and compresses the data BL02 and BL13 and outputs them serially to form new data BL0123. Among them, the first pulse width of the second-stage compression signal can be 2T, and the transmission time length of each bit of data in the data BL0123 is 2T, which is equal to the first pulse width. The transmission time length of the data BL0123 is 8T, which is equal to the bus transmission time length of the data bus 910, so the data BL0123 can be transmitted to the buffer 920 within the bus transmission time length of the data bus 910.

[0158] like Fig.13 and Fig.14 As shown, if 16 bits of data are transmitted, after compression by the first-stage driving circuit 610, the number of data buses 910 can be reduced from 16 to 8. After compression by the second-stage driving circuit 620, the number of data buses 910 is further reduced to 4, which is reduced to one-fourth of the original number, thereby saving lines.

[0159] In some embodiments, the transmission time of each bit of data BL0, BL1, BL2, BL3 (i.e., each bit of data before compression) read from the storage array may be 8T, which is equal to the bus transmission time. However, it should be understood that the transmission time of each bit of data before compression may not be equal to the bus transmission time, but only needs to be greater than the second pulse width of the first-stage compression pulse.

[0160] In some embodiments, Fig.13 As shown, the first stage driving circuit 610 includes: a first AND gate 611, a second AND gate 612 and a first NOR gate 613;

[0161] Two input terminals of the first AND gate 611 are respectively used to receive one bit of data and the first first-stage compression signal MUX_BLC0;

[0162] Two input terminals of the second AND gate 612 are respectively used to receive another bit of data and the second first-stage compression signal MUX_BLC2;

[0163] Two input ends of the first NOR gate 613 are connected to the output ends of the first AND gate 611 and the second AND gate 612 respectively; the output end of the first NOR gate 613 outputs two bits of data in series, and the transmission duration of each bit of the two bits of data is the second pulse width.

[0164] In some embodiments, Fig.13 As shown, the second stage driving circuit 620 includes: a third AND gate 621, a fourth AND gate 622 and a second NOR gate 623;

[0165] One of the two input terminals of the third AND gate 621 is connected to an output terminal of a first-stage driving circuit, and the other is used to receive the first second-stage compression signal DRV_BL02;

[0166] One of the two input terminals of the fourth AND gate 622 is connected to the output terminal of another first-stage driving circuit, and the other is used to receive the second first-stage compression signal DRV_BL13;

[0167] The two input ends of the second NOR gate 623 are respectively connected to the output ends of the third AND gate 621 and the fourth AND gate 622; the output end of the second NOR gate 623 serially outputs four-bit data, and the transmission duration of each bit of the four-bit data is the first pulse width.

[0168] Here, the first AND gate 611 and the second AND gate 612 can be replaced by a NAND gate and a NOT gate connected in series. Similarly, the third AND gate 621 and the fourth AND gate 622 can also be replaced by a NAND gate and a NOT gate connected in series.

[0169] Figures 15a to 15c A timing diagram of compressed signals and data provided in an embodiment of the present disclosure, wherein the values ​​of data BL0, BL2, BL1 and BL3 can be any one of 0 and 1. Fig.15a In the embodiment 1 shown, BL0=1, BL2=1, BL1=0, BL3=1, Fig.15b In the embodiment 2 shown, BL0=1, BL2=0, BL1=0, BL3=0, Fig.15c In the illustrated embodiment 3, BL0=0, BL2=0, BL1=1, and BL3=1. Figures 15a to 15c is based on Fig.13 The logic gates shown in FIG. 1 are used to store data BL0 to BL3, and Fig.11 The compression signals MUX_BL and DRV_BL shown are subjected to logical operation to obtain data BL02, BL13, and BL0123.

[0170] By comparing Example 1 and Example 2, it can be seen that when the value of BL2 changes from 1 to 0, the second valid pulse in BL02 changes from a low level to a high level, indicating that the first-level driving circuit can output the data BL0 and BL2 in series in the order of BL02, and the transmission time of each bit of data in BL02 is 4T, which is equal to the second pulse width 4T of the first-level compression signal MUX_BLC0 and MUX_BLC2. Similarly, the transmission time of data BL1 and BL3 is compressed to 4T and serialized in the order of BL13.

[0171] By comparing the examples 1 to 3, it can be seen that the output end of the second driving circuit serially outputs the four bits of data in the order of data BL0, BL1, BL2 and BL3 to form data BL0123. The transmission time of each bit of data in data BL0123 is 2T, which is equal to the first pulse width 2T of the second-stage compression signal DRV_BL02, DRV_BL13.

[0172] Figures 16a to 16c A timing diagram of another compressed signal and data provided in an embodiment of the present disclosure. Figures 16a to 16c and Figures 15a to 15c The same is that the second first-stage compression signal MUX_BLC2 is delayed by a second pulse width relative to the first first-stage compression signal MUX_BLC0, but Figures 15a to 15c The difference is that the first second-stage compression signal DRV_BL02 is delayed by the first pulse width relative to the second second-stage compression signal DRV_BL13 .

[0173] contrast Fig.15a and Fig.16a As can be seen from the first embodiment of the present invention, the first data outputted from the output terminal of the second stage driving circuit 620 is BL1. Fig.15b and Fig.16b As can be seen from the second embodiment, the second data outputted from the output terminal of the second stage driving circuit 620 is BL0. Fig.15c and Fig.16c As can be seen from the third embodiment, the third data outputted from the output terminal of the second stage driving circuit 620 is BL3, and the last data is BL2. That is, the output terminal of the second driving circuit 620 serially outputs the four bits of data in the order of data BL1, BL0, BL3 and BL2 to form data BL1032.

[0174] By the above Figures 15a to 16c As can be seen from the embodiment shown, each stage of the driving circuit is used to serially output multi-bit data according to the order of the received multiple compressed signals. Changing the order of the multiple compressed signals at each stage will not affect the transmission time of the compressed data, but will affect the order of the compressed data when it is transmitted serially. Therefore, the embodiment of the present disclosure can adjust the order of the serial data output by each stage of the driving circuit by adjusting the order of the multiple compressed signals at each stage.

[0175] From another perspective, the above adjustment of the order of the two second-stage compressed signals can also be regarded as: keeping the order of the two second-stage compressed signals unchanged, but connecting the second second-stage compressed signal DRV_BL13 and the data BL02 to the third AND gate 621, and connecting the first second-stage compressed signal DRV_BL02 and the data BL13 to the fourth AND gate 622. Therefore, when the order of multiple compressed signals at each stage is fixed, the order of the serial data outputted from the output end can be adjusted by adjusting the combination of the data and the compressed signal received at the input end of the AND gate in each stage of the driving circuit.

[0176] Reference again Figure 6 and Figure 8 In summary, the data processing circuit includes: a command generator 100, a column selection signal generating circuit 210, a column decoder 220, an input / output sense amplifier 230, an error correction code circuit 800, a clock generating circuit 410, a first delay circuit 420, a data center 50, a data bus driving circuit 600, a data bus 910 and a buffer 920. Among them, the data center 50 includes an enable signal generating circuit 710, a second delay circuit 720 and a compression signal generating circuit 500.

[0177] The command generator 100 receives the command RD sent by the memory controller and generates a read command READ. The read command READ includes column address information. The command generator 100 transmits the read command READ to the column selection signal generation circuit 210 and the clock generation circuit 410.

[0178] The column selection signal generating circuit 210 receives a read command READ, obtains column address information in the read command READ, generates a column selection signal CSL, and transmits the column selection signal CSL to the column decoder 220 .

[0179] The column decoder 220 opens the corresponding column address in the memory array according to the column select signal CSL to latch the data in the column address into the input / output sense amplifier 230. For example, 128 bits of data are latched into the input / output sense amplifier 230.

[0180] The clock generating circuit 410 generates clock signals QRDCK and QRDCK_I by receiving a read command READ, and transmits the clock signals QRDCK and QRDCK_I to the first delay circuit 420 .

[0181] The first delay circuit 420 performs a first delay on the clock signals QRDCK and QRDCK_I to generate clock signals QRDCKD and QRDCKD_I after the first delay, and transmits them to the data center 50. The first delay here is to compensate for the time taken for data to be transmitted from the storage array to the input / output amplifier 230, resulting in the data being out of sync with the read enable signal RDEN.

[0182] In the data center 50, the enable signal generating circuit 710 receives the first clock signal QRDCKD after the first delay, generates a read enable signal RDEN, and transmits it to the input / output sense amplifier 230. The second delay circuit 720 performs a second delay on the clock signals QRDCKD and QRDCKD_I after the first delay, and generates clock signals QRDCKDD and QRDCKDD_I after the second delay. The clock signals QRDCKDD and QRDCKDD_I after the second delay are synchronized with the read enable signal RDEN.

[0183] The error correction code circuit 800 delays the clock signals QRDCKDD and QRDCKDD_I after the second delay, and generates error correction clock signals QRDECC and QRDECC_I accordingly. The error correction clock signals QRDECC and QRDECC_I are returned to the compression signal generation circuit 500 of the data center 50. The compression signal generation circuit 500 receives the error correction clock signals QRDECC and QRDECC_I to generate compression signals MUX_BLC0, MUX_BLC2, DRV_BL02, and MUX_BL13, and transmits the compression signals to the data bus driving circuit 600.

[0184] When receiving the read enable signal RDEN, the input / output read amplifier 230 transmits the latched 128 bits of data to the error correction code circuit 800 . The error correction code circuit 800 can detect the data and correct the detected erroneous data, and transmit the corrected 128 bits of data to the data bus driver circuit 600 .

[0185] The data bus driving circuit 600 receives 128-bit data and compression signals MUX_BLC0, MUX_BLC2, DRV_BL02, and MUX_BL13, and upon receiving the compression signal, compresses the 128-bit data according to the compression signal. After compression, the transmission time of each bit of data is reduced from the original 8T to 2T, so that the 128-bit data can be transmitted to the buffer 920 through the 32 data buses 910.

[0186] In some embodiments, Figure 6 As shown, the memory in X8 mode includes 8 buffers 920 , each buffer 920 is used to receive 16 bits of data, so each buffer 920 is connected to 4 data buses 910 . Figure 6 The numerical value on the line representing the data bus indicates that the line includes multiple data buses indicated by the numerical value. For example, 32 / indicates that the line includes 32 data buses 910, and 8 / and 4 / indicate that the line includes 8 and 4 data buses 910, respectively.

[0187] In some embodiments, multiple data buses can be arranged in a data tree manner so that the lengths of the multiple data lines are substantially equal, so that a data read once (e.g., 128-bit data) is substantially transmitted to multiple buffers 920 (e.g., 8 buffers 920) at the same time. Such arrangement of data buses can reduce the impact of PVT (process-voltage-temperature) on data transmission. Even if the data transmission time is reduced to 2T, the control signal of the first-in-first-out circuit (FIFO) after the buffer can be more easily adjusted to write the data sequentially into the first-in-first-out circuit.

[0188] like Figure 6 As shown, the eight buffers 920 can be divided into four buffers 920 on the left and four buffers 920 on the right, and the four buffers 920 on the left and the four buffers 920 on the right are symmetrical. The 32 data buses 910 include 32 horizontal main lines and 32 horizontal branch lines; wherein, the end points of the horizontal main lines close to the buffers are located at the symmetry axis of the four buffers on the left and the four buffers on the right, and the horizontal branch lines are located near the buffers 920. The 32 horizontal branch lines are divided into eight on the upper left, eight on the upper right, eight on the lower left, and eight on the lower right. These four groups of horizontal branch lines are symmetrical on the left and the right, and are symmetrical up and down with the horizontal main lines as the symmetry axis.

[0189] like Figure 6 As shown, 32 horizontal main lines occupy 32 horizontal lines, and two horizontal branch lines symmetrically occupy one line. Therefore, 32 horizontal branch lines occupy 16 lines, so 32 data buses occupy a total of 48 (32 + 16) horizontal lines. Figure 2 If the 64 data buses shown are arranged in a data tree, they will include 64 horizontal main lines and 64 horizontal branch lines, occupying a total of 96 (64+32) horizontal lines. Figure 6 The data processing circuit provided is compared Figure 2 The data processing circuit shown saves 48 horizontal lines, is more conducive to the layout of other lines, and is more conducive to the miniaturization of the device and the improvement of the performance of the device.

[0190] The data processing circuit provided by the embodiment of the present disclosure sets the first pulse width of the first effective pulse of the clock signal to be equal to the transmission time of each bit of data after compression, and the number of clock signals is multiple, so that multiple compressed signals can be generated through relatively simple logical operations, thereby reducing the complexity of the compressed signal generation circuit and saving layout space. Moreover, since the clock signal includes multiple first effective pulses, the compressed signal can also include multiple effective pulses, so that the compressed signal is at a low level during other times except the effective pulses, thereby reducing the power consumption of the data processing circuit. On the other hand, the data processing circuit provided by the embodiment of the present disclosure can compress the data, so that the transmission time of the data is reduced to one-fourth of the original, thereby reducing the number of data buses to one-fourth of the original, saving the number of data buses, saving the area used by the data bus on the M4 metal layer, facilitating the miniaturization of the device, and reducing the difficulty of M4 metal layer wiring.

[0191] It should be noted that the above-mentioned data processing circuit provided in the embodiment of the present disclosure is not only applicable to the X8 mode of the memory, but also applicable to the X4 mode and X16 mode.

[0192] The present disclosure provides a memory, including:

[0193] Storage array, the storage array is used to store data;

[0194] The peripheral circuit includes the data processing circuit as described in any of the above embodiments, and the data processing circuit is used to process the data read from the storage array.

[0195] The memory includes but is not limited to dynamic random access memory (DRAM), static random access memory (SRAM), NAND memory, etc. DRAM includes but is not limited to DDR4 SDRAM (Double Data Rate Fourth Synchronous Dynamic Random Access Memory, referred to as DDR4), DDR5 SDRAM (DDR5 for short) and DDR6 SDRAM (DDR6 for short).

[0196] The above embodiments are merely illustrative of the principles and effects of the present disclosure, and are not intended to limit the present disclosure. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present disclosure. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed in the present disclosure shall still be covered by the claims of the present disclosure.

Claims

1. A data processing circuit, characterized in that: include: A clock generation circuit, wherein the clock generation circuit is used to generate a plurality of clock signals; the clock signals include a plurality of first valid pulses with a first pulse width, the plurality of clock signals are delayed in sequence, and the delay time between two adjacent clock signals is equal to the first pulse width; A compression signal generating circuit connected to the clock generating circuit, the compression signal generating circuit being used to generate a plurality of compression signals according to the plurality of clock signals; A data bus driving circuit is connected to the compression signal generating circuit, and the data bus driving circuit is used to receive multi-bit data and compress the multi-bit data according to the multiple compression signals; wherein the transmission duration of each bit of the compressed data is equal to the first pulse width.

2. The data processing circuit according to claim 1, characterized in that: The multiple clock signals include: a first clock signal and a second clock signal; The first clock signal includes two first valid pulses, and the second clock signal is a delayed signal of the first clock signal, and the delay time length is the first pulse width.

3. The data processing circuit according to claim 2, characterized in that: The clock generation circuit comprises: A shift register, comprising four flip-flops connected in series; a signal input end of each flip-flop is connected to an output end of a previous flip-flop, and a signal input end of the first flip-flop is used to receive a read command; wherein the read command comprises a second valid pulse having a first pulse width; A first clock generating unit comprises a first OR gate circuit; two input ends of the first OR gate circuit are respectively connected to an output end of the first trigger and an output end of the third trigger, and an output end of the first OR gate circuit outputs the first clock signal; The second clock generating unit comprises a second OR gate circuit; two input ends of the second OR gate circuit are respectively connected to the output end of the second trigger and the output end of the fourth trigger, and the output end of the second OR gate circuit outputs the second clock signal.

4. The data processing circuit according to claim 2, characterized in that: The compression signal comprises a multi-level compression signal, the width of an effective pulse of the multi-level compression signal decreases in sequence according to the level, wherein the width of an effective pulse of the compression signal of the last level is equal to the first pulse width.

5. The data processing circuit according to claim 4, characterized in that: The data bus driving circuit includes a multi-level driving circuit, and the multi-level driving circuit corresponds to the multi-level compression signal one by one; Each level of the driving circuit is used to compress each bit of received data according to the compression signal of the first level, and transmit it to the driving circuit of the next level; wherein the transmission duration of each bit of data output by the driving circuit of each level is equal to the width of the corresponding effective pulse of the compression signal; and the transmission duration of each bit of data output by the driving circuit of the last level is equal to the first pulse width.

6. The data processing circuit according to claim 5, characterized in that: The number of the compression signals at each level is multiple, the multiple compression signals at the same level are delayed in sequence, and the delay time between two adjacent compression signals at the same level is equal to the width of the effective pulse of the compression signal; Each stage of the driving circuit is used to output multi-bit data in series according to the order of the received plurality of compressed signals.

7. The data processing circuit according to claim 6, characterized in that: The plurality of compressed signals include two first-stage compressed signals and two second-stage compressed signals; The first-level compression signal includes a third effective pulse with a second pulse width, and the second pulse width is equal to twice the first pulse width; the delay time between two first-level compression signals is equal to the second pulse width; The second-level compression signal includes two fourth effective pulses having the first pulse width, and the time interval between the two fourth effective pulses is equal to the first pulse width; and the delay time between the two second-level compression signals is equal to the first pulse width.

8. The data processing circuit according to claim 7, characterized in that: The data bus driving circuit comprises: The first-stage driving circuit comprises a first AND gate, a second AND gate and a first NOR gate; the two input ends of the first AND gate are respectively used to receive one bit of data and one of the first-stage compressed signals; the two input ends of the second AND gate are respectively used to receive another bit of data and another of the first-stage compressed signals; the two input ends of the first NOR gate are respectively connected to the output ends of the first AND gate and the second AND gate; the output end of the first NOR gate serially outputs two bits of data, and the transmission duration of each bit of the two bits of data is a second pulse width; The second-stage driving circuit includes a third AND gate, a fourth AND gate and a second NOR gate; one of the two input ends of the third AND gate is connected to an output end of the first-stage driving circuit, and the other is used to receive a second-stage compressed signal; one of the two input ends of the fourth AND gate is connected to another output end of the first-stage driving circuit, and the other is used to receive another second-stage compressed signal; the two input ends of the second NOR gate are respectively connected to the output ends of the third AND gate and the fourth AND gate; the output end of the second NOR gate serially outputs four-bit data, and the transmission duration of each bit of the four-bit data is a first pulse width.

9. The data processing circuit according to claim 7, characterized in that: The compression signal generating circuit comprises: The first compression unit comprises: a first delayer, a first inverter, a first trigger and a second inverter; wherein the output end of the first delayer is connected to the signal input end of the first trigger, and the first delayer is used to receive a second clock signal; the output end of the first inverter is connected to the clock end of the first trigger, and the first inverter is used to receive the first clock signal; the input end of the second inverter is connected to the output end of the first trigger, and the second inverter is used to output a first first-stage compression signal; The second compression unit includes: a second delay and a second trigger; the output end of the second delay is connected to the clock end of the second trigger, and the second delay is used to receive the second clock signal; the first input end of the second trigger is used to receive the first clock signal; the output end of the second trigger is used to output a second first-level compression signal.

10. The data processing circuit according to claim 7, characterized in that: The compression signal generating circuit further comprises: A third compression unit, comprising an even number of third inverters connected in series; the third compression unit is used to receive the first clock signal and output a first second-stage compression signal; A fourth compression unit comprises an even number of fourth inverters connected in series, wherein the number of the fourth inverters is the same as the number of the third inverters; the fourth compression unit is used to receive the second clock signal and output a second second-level compression signal.

11. The data processing circuit according to claim 2, characterized in that: The data processing circuit further includes: an enable signal generating circuit, connected to the clock generating circuit, the enable signal generating circuit being used to receive the first clock signal and output the first first valid pulse in the first clock signal as a read enable signal; An input / output readout amplifier is connected to the enable signal generating circuit and the data bus driving circuit, and the input / output readout amplifier is used to transmit multi-bit data to the data bus driving circuit according to the read enable signal.

12. The data processing circuit according to claim 11, characterized in that: The enable signal generating circuit comprises a fifth inverter, an odd number of sixth inverters connected in series, a third trigger and a third NOR gate; The input end of the fifth inverter is used to receive the first clock signal, and the output end of the fifth inverter is connected to the signal input end of the third trigger, the input ends of the odd number of sixth inverters and the first input end of the third NOR gate; The output ends of the odd number of sixth inverters are connected to the clock end of the third flip-flop; The output end of the third trigger is connected to the second input end of the third NOR gate, and the output end of the third NOR gate is used to output the read enable signal.

13. The data processing circuit according to claim 11, characterized in that: The data processing circuit further includes: A first delay circuit, connected to the clock generating circuit; the first delay circuit is used to perform a first delay on the first clock signal and the second clock signal; A second delay circuit, connected to the first delay circuit; the second delay circuit is used to perform a second delay on the first clock signal after the first delay and the second clock signal after the first delay; An error correction code circuit is connected to the second delay circuit; the error correction code circuit is used to generate a first error correction clock signal and a second error correction clock signal according to the received first clock signal after the second delay and the received second clock signal after the second delay.

14. The data processing circuit according to claim 13, characterized in that: The enable signal generating circuit is connected to the first delay circuit; the enable signal generating circuit is used to receive the first clock signal after the first delay; wherein the read enable signal is the first valid pulse of the first clock signal after the first delay; The compressed signal generating circuit is connected to the error correction code circuit; the compressed signal generating circuit is used to receive the first error correction clock signal and the second error correction clock signal, and output the compressed signal; wherein the first error correction clock signal and the second error correction clock signal are delayed signals of the first clock signal and the second clock signal after being delayed by the first delay circuit, the second delay circuit and the error correction code circuit.

15. A memory, characterized in that: include: A storage array, wherein the storage array is used to store data; A peripheral circuit, comprising a data processing circuit as claimed in any one of claims 1 to 14, wherein the data processing circuit is used to process the data read from the storage array.

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