EFuse programming unit and programming method thereof, eFuse programming unit array and chip
By adding programming transistors and fuse bodies to the traditional eFuse programming unit and conducting a reasonable layout, the problems of large area and low utilization rate of the traditional eFuse programming unit are solved, and higher integration and reliability are achieved.
Patent Information
- Application Number
- CN202411423716.2
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-12
- Publication Date
- 2025-01-24
AI Technical Summary
The structural design of traditional eFuse programming units leads to a large area, which limits the high integration and high reliability of eFuse, and the programming units cannot be repeated and the utilization rate is not high.
On the basis of the traditional EFUSE programming unit, two programming transistors and two felling bodies are added to achieve secondary programming of a single EFUSE programming unit, and the area of the transistor can be reduced by reasonable layout.
Improve the utilization rate of the eFuse programming unit within a limited area, reduce the area of the eFuse programming unit and array, and achieve higher integration and reliability.
Smart Images
Figure CN119360923A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to an eFuse programming unit and a programming method thereof, an eFuse programming unit array and a chip. Background Art
[0002] eFuse (electrically programmable fuse) is a one-time programmable memory. It is based on the principle of electromigration (EM). It uses a large programming current to melt (repture) the fuse body (eFuseLink, which can be made of conductive materials such as silicon, silicide or metal) in its programming unit or to achieve silicide electromigration of the fuse body to achieve the programming function. It is widely used inside chips.
[0003] The core module inside the eFuse is the programming unit array, which is composed of several eFuse programming units. The structure of the traditional eFuse programming unit is as follows: Figure 1 As shown, it includes a fuse body eFuse1 and a programming transistor PGM1, the gate of the programming transistor PGM1 is connected to the corresponding word line WL of the programming cell array, one end of the fuse body eFuse1 is connected to the source or drain of the programming transistor PGM1, and the other end is connected to the corresponding bit line BL of the programming cell array.
[0004] However, since the programming mechanism of eFuse requires a large programming current, the width-to-length ratio (Width / Length, abbreviated as "W / L") of the programming transistor PGM1 in the eFuse programming unit must be relatively large, for example, occupying more than 4 / 5 of the area of the entire eFuse programming unit, resulting in a larger area of the programming unit.
[0005] Controlling the area of the eFuse programming unit and the programming unit array is the key way to reduce the area of the entire efuse. Obviously, the structural design of the traditional eFuse programming unit is not conducive to reducing the area of the entire eFuse and achieving high integration of the eFuse.
[0006] In addition, in order to ensure the high reliability of eFuse during the entire life of the chip, it is often necessary to find the best programming conditions (under-programming and over-programming often occur), which requires multiple decompositions (splits) of each variable, including size, current, temperature, etc. This results in the traditional eFuse programming unit being non-repeatable and having low utilization.
[0007] Therefore, how to improve the utilization rate of the eFuse programming unit within a limited area has become one of the technical problems that technical personnel in this field need to solve urgently. Summary of the invention
[0008] The object of the present invention is to provide an eFuse programming unit and a programming method thereof, an eFuse programming unit array and a chip, which can improve the utilization rate of the eFuse programming unit within a limited area.
[0009] To achieve the above object, the present invention provides an eFuse programming unit, which includes:
[0010] a first programming transistor, wherein a gate of the first programming transistor is connected to a word line, and a source of the first programming transistor is connected to a first power line;
[0011] a first fuse body, a second end of the first fuse body connected to the drain of the first programming transistor to form an output node, and a first end of the first fuse body connected to a second bit line;
[0012] a second programming transistor, wherein a gate of the second programming transistor is connected to the output node, and a source of the second programming transistor is connected to a second power line;
[0013] a second fuse body, wherein a first end of the second fuse body is connected to a drain of the second programming transistor, and a second end of the second fuse body is connected to a first bit line;
[0014] a third programming transistor, wherein a gate of the third programming transistor is connected to the output node, and a source of the third programming transistor is connected to the first power line;
[0015] A third fuse body, wherein a first end of the third fuse body is connected to a third bit line, and a second end of the third fuse body is connected to a drain of the third programming transistor.
[0016] Optionally, the third programming transistor has a conductivity type opposite to that of the second programming transistor.
[0017] Optionally, the first programming transistor and the third programming transistor are both NMOS transistors, and the second programming transistor is a PMOS transistor.
[0018] Optionally, in the layout structure of the eFuse programming unit, the second programming transistor has a first conductivity type well, and the third programming transistor has a second conductivity type well, the first conductivity type well and the second conductivity type well are arranged head to head, and the gate head end of the second programming transistor is connected to the gate head end of the third programming transistor, so that the second programming transistor and the third programming transistor share a common gate.
[0019] Based on the same inventive concept, the present invention also provides a programming method of the eFuse programming unit as described in the present invention, which comprises the following steps:
[0020] Initially, the eFuse programming unit is in an initial state, the first programming transistor, the second programming transistor and the third programming transistor are all turned off, and the eFuse programming unit is in a low resistance state;
[0021] A first programming operation: applying a bias voltage to the gate of the first programming transistor through the word line to turn on the first programming transistor, and applying a first programming voltage to the first fuse body through the second bit line to program the first fuse body to a high impedance state;
[0022] The second programming operation is as follows: applying a second programming voltage through the first bit line and applying a third programming voltage through the third bit line to program the second fuse body or the third fuse body to a high resistance state.
[0023] Optionally, the second programming voltage and the third programming voltage are the same.
[0024] Optionally, the programming method further comprises: judging whether the programming of the first fuse body by the first programming operation is good or bad according to which one of the second fuse body and the third fuse body is programmed to a high impedance state in the second programming operation;
[0025] And / or, determining the optimal programming condition of the eFuse programming unit according to which one of the second fuse body and the third fuse body is programmed to the high impedance state in the second programming operation.
[0026] Optionally, if the second fuse body is programmed to a high-impedance state in the second programming operation, it can be concluded that the first programming operation has better programming on the first fuse body, which will turn on the second programming transistor; if the third fuse body is programmed to a high-impedance state in the second programming operation, it can be concluded that the first programming operation has poor programming on the first fuse body, which will turn on the third programming transistor.
[0027] Based on the same inventive concept, the present invention further provides an eFuse programming unit array, which includes a plurality of eFuse programming units as described in the present invention arranged in an array.
[0028] Optionally, the eFuse programming unit array is an m*n array, including m rows of eFuse programming units and n columns of eFuse programming units, wherein n≥2 and n is an integer, m≥2 and m is an integer, and:
[0029] The gates of the first programming transistors of the eFuse programming cells in the same row are connected to the same word line;
[0030] The first ends of the first fuse bodies of the eFuse programming units in the same column are connected to the same second bit line;
[0031] The second ends of the second fuse bodies of the eFuse programming units in the same column are connected to the same first bit line;
[0032] The first ends of the third fuse bodies of the eFuse programming units in the same column are connected to the same third bit line.
[0033] Based on the same inventive concept, the present invention also provides a chip, which includes: a word line control circuit, a first bit line control circuit, a second bit line control circuit, a third bit line control circuit, and an eFuse programming unit array as described in the present invention; wherein, the word line control circuit is coupled to each word line of the eFuse programming unit array, the first bit line control circuit is coupled to each first bit line of the eFuse programming unit array, the second bit line control circuit is coupled to each second bit line of the eFuse programming unit array, and the third bit line control circuit is coupled to each third bit line of the eFuse programming unit array.
[0034] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:
[0035] 1. On the basis of the structure of the traditional eFuse programming unit (i.e., the structure formed by the first programming transistor and the first fuse body in series), two programming transistors and two fuse bodies (i.e., the second programming transistor, the third programming transistor, the second fuse body and the third fuse body) are added to realize the secondary programming of a single eFuse programming unit, thereby improving the utilization rate of the eFuse programming unit within a limited area.
[0036] 2. The second fuse body and the third fuse body in the eFuse programming unit are equivalent to the two next-level branches of the first fuse body. Therefore, the effect of the first programming operation on the programming of the first fuse body can be inferred based on the result of the second programming operation, as well as the optimal programming conditions of the eFuse programming unit.
[0037] 3. Reasonable layout of the second programming transistor and the third programming transistor in the eFuse programming unit can be performed to reasonably utilize the area. For example, the second programming transistor and the third programming transistor are connected in parallel head to head and share a gate, which can effectively reduce the area of the second programming transistor and the third programming transistor. This can improve the utilization rate while further effectively reducing the area of the eFuse programming unit and the eFuse programming unit array. For example, the area of the eFuse programming unit can be reduced to 1 / 2 of the area of the traditional eFuse programming unit. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Those skilled in the art will appreciate that the accompanying drawings are provided for a better understanding of the present invention and do not constitute any limitation on the scope of the present invention.
[0039] Figure 1 It is a schematic diagram of the circuit structure of a traditional eFuse programming unit.
[0040] Figure 2 It is a schematic diagram of the circuit structure of the eFuse programming unit according to a specific embodiment of the present invention.
[0041] Figure 3 It is a schematic diagram of the layout structure of the second programming transistor and the third programming transistor in the eFuse programming unit according to a specific embodiment of the present invention.
[0042] Figure 4 4 is a schematic diagram of an exemplary circuit of an eFuse programming cell array according to a specific embodiment of the present invention (where n=4).
[0043] Figure 5 It is an example diagram of the architecture of a chip according to a specific embodiment of the present invention. DETAILED DESCRIPTION
[0044] In the following description, a large number of specific details are given in order to provide a more thorough understanding of the present invention. However, it is obvious to those skilled in the art that the present invention can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present invention, some technical features known in the art are not described. It should be understood that the present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed here. On the contrary, providing these embodiments will make the disclosure thorough and complete, and the scope of the present invention will be fully conveyed to those skilled in the art. The same reference numerals represent the same elements from beginning to end. It should be understood that when an element is referred to as "connected to", "coupled" other elements, it can be directly connected to other elements, or there can be intervening elements. On the contrary, when an element is referred to as "directly connected to" other elements, there is no intervening element. When used here, the singular forms of "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates another way. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.
[0045] The technical solution proposed by the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer according to the following description. It should be noted that the accompanying drawings are all in a very simplified form and are not in precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.
[0046] Please refer to Figure 2 An embodiment of the present invention provides an eFuse programming unit, which includes a first programming transistor PGM1, a first fuse body eFuse1, a second programming transistor PGM2, a second fuse body eFuse2, a third programming transistor PGM3 and a third fuse body eFuse3.
[0047] The gate of the first programming transistor PGM1 is connected to the word line WL, and the source is connected to the first power line VSS. The second end (e.g., cathode) of the first fuse body eFuse1 is connected to the drain of the first programming transistor PGM1 to form an output node A, and the first end (e.g., anode) of the first fuse body eFuse1 is connected to the second bit line BLb. That is, the first programming transistor PGM1 and the first fuse body eFuse1 are connected in series.
[0048] The gate of the second programming transistor PGM2 is connected to the output node A, and the source of the second programming transistor PGM2 is connected to the second power line VDD. The first end (e.g., anode) of the second fuse body eFuse2 is connected to the drain of the second programming transistor PGM2, and the second end (e.g., cathode) of the second fuse body eFuse2 is connected to the first bit line BL. That is, the second programming transistor PGM2 and the second fuse body eFuse2 are connected in series, and constitute a next-level branch (split) of the first fuse body eFuse1.
[0049] The gate of the third programming transistor PGM3 is connected to the output node A, and the source of the third programming transistor PGM3 is connected to the first power line VSS. The first end (e.g., anode) of the third fuse body eFuse3 is connected to the third bit line BLR, and the second end (e.g., cathode) of the third fuse body eFuse3 is connected to the drain of the third programming transistor PGM3.
[0050] The conductivity types of the second programming transistor PGM2 and the third programming transistor PGM3 are opposite, so they are not turned on at the same time.
[0051] The first fuse body eFuse1, the second fuse body eFuse2 and the third fuse body eFuse3 can be made of the same material or different materials, which is not specifically limited in the present invention. For example, the first fuse body eFuse1, the second fuse body eFuse2 and the third fuse body eFuse3 are made of the same metal material or the same silicide material.
[0052] In addition, when an effective bias voltage (high level or low level is effective) is applied to the gate of the first programming transistor PGM1, the first programming transistor PGM1 is turned on, generating a large programming current, thereby realizing the programming operation of the first fuse body eFuse1, that is, the first fuse body eFuse1 is fused or the silicide electromigration of the first fuse body eFuse1 is realized, and the first fuse body eFuse1 changes from a low resistance state to a high resistance state. Among them, when the first fuse body eFuse1 is completely fused or its silicide is completely consumed, it is considered that the programming of the first fuse body eFuse1 is better, and the first fuse body eFuse1 will permanently remain in the disconnected state, and when the first fuse body eFuse1 is not fused or its silicide is not completely consumed, it is considered that the programming of the first fuse body eFuse1 is poor, and the first fuse body eFuse1 is still in the on state.
[0053] When the output node A loads an effective level (low level or high level is effective) to the gate of the second programming transistor PGM2, the second programming transistor PGM2 is turned on (the third programming transistor PGM3 is not turned on at this time), generating a large programming current, thereby realizing the programming operation of the second fuse body eFuse2, that is, the second fuse body eFuse2 is blown or the silicide electromigration of the second fuse body eFuse2 is realized, and the second fuse body eFuse2 changes from a low resistance state to a high resistance state. Among them, when the second fuse body eFuse2 is completely blown or its silicide is completely consumed, the second fuse body eFuse2 will permanently remain in the disconnected state, and when the second fuse body eFuse2 is not blown or its silicide is not completely consumed, the second fuse body eFuse2 is still in the on state.
[0054] When the output node A loads an effective level (low level or high level is effective) to the gate of the third programming transistor PGM3, the third programming transistor PGM3 is turned on (the second programming transistor PGM2 is not turned on at this time), generating a large programming current, thereby realizing the programming operation of the third fuse body eFuse3, that is, the third fuse body eFuse3 is blown or the silicide electromigration of the third fuse body eFuse3 is realized, and the third fuse body eFuse3 changes from a low resistance state to a high resistance state. Among them, when the third fuse body eFuse3 is completely blown or its silicide is completely consumed, the third fuse body eFuse3 will permanently remain in the disconnected state, and when the third fuse body eFuse3 is not blown or its silicide is not completely consumed, the third fuse body eFuse3 is still in the on state.
[0055] In addition, each programming transistor PGM1, PGM2, PGM3 can adopt any suitable switch element, such as MOS tube, triode, BJT (bipolar transistor), etc., and the present invention does not make any specific limitation on this.
[0056] As an example, please refer to Figure 2 The first programming transistor PGM1 and the third programming transistor PGM3 are both NMOS, the second programming transistor PGM2 is PMOS, the first power line VSS is connected to a low-level voltage such as 0V, the second power line VDD is connected to a high-level voltage (for example, the operating voltage of the chip where the eFuse programming unit is located), and the first end of each fuse body (i.e., eFuse1, eFuse2, eFuse3) is an anode, and the second end is a cathode. The first programming transistor PGM1 is turned on when its gate is connected to a high level, and at this time, a sufficiently large programming current passes through the first fuse body efuse1. Further, when the first fuse body efuse1 is well-programmed, the first fuse body efuse1 is in a high resistance state and will produce a very high resistance, the output node A outputs a low level, and the second programming transistor PGM2 is turned on, thereby programming the second fuse body efuse2. When the first fuse body efuse1 is poorly programmed (weakly-programmed), the resistance state of the first fuse body efuse1 increases relative to the initial state, but is not high enough. At this time, the output node A outputs a high level, and the third programming transistor PGM3 is turned on, thereby programming the third fuse body efuse3. Therefore, the programming quality of the first fuse body efuse1 can be estimated according to the programming status of the second fuse body efuse2 and the third fuse body efuse3, and the optimal programming condition of the eFuse programming unit can be obtained.
[0057] Optionally, refer to Figure 3 In the layout structure of the eFuse programming unit, the second programming transistor PGM2 has a first conductive type well NW, and the third programming transistor PGM3 has a second conductive type well PW. The first conductive type well NW and the second conductive type well PW are arranged head to head, and the gate G2 head end of the second programming transistor PGM2 is connected to the gate G1 head end of the third programming transistor PGM3 to form a common gate G. Thus, the second programming transistor PGM2 and the third programming transistor PGM3 are connected in common gate, thereby effectively reducing the area of the programming transistors in the eFuse programming unit while improving the utilization rate. For example, the area of the eFuse programming unit can be reduced to 1 / 2 of the area of the traditional eFuse programming unit.
[0058] In other examples, when the first programming transistor PGM1 and the third programming transistor PGM3 are replaced by PMOS, the second programming transistor PGM2 is replaced by NMOS, the connection terminals (i.e., source and drain) corresponding to each other between PGM1, PGM2, PGM3 and eFuse1, eFuse2, eFuse3 can be adaptively swapped, and the voltage levels connected to the first power line VSS and the second power line VDD are also adaptively swapped, which will not be elaborated here.
[0059] Based on the same invention concept, please combine Figure 2 As shown, this embodiment also provides a programming method for the above-mentioned eFuse programming unit, which includes the following steps:
[0060] Initially, the eFuse programming unit is in an initial state, the first programming transistor PGM1, the second programming transistor PGM2 and the third programming transistor PGM3 of the eFuse programming unit are all turned off, the first fuse body eFuse1, the second fuse body eFuse2 and the third fuse body eFuse3 are all in an unprogrammed low resistance state, that is, the eFuse programming unit is in a low resistance state as a whole;
[0061] First programming operation: applying a suitable bias voltage to the gate of the first programming transistor PGM1 through the word line WL to turn on the first programming transistor PGM1, and applying a first programming voltage (not shown, the programming voltage is a constant voltage) to the first fuse body eFuse1 through the second bit line BLb to program the first fuse body eFuse1 to a high impedance state;
[0062] Second programming operation: a second programming voltage (not shown, the programming voltage is a constant voltage) is applied through the first bit line BL, and a third programming voltage (not shown, the programming voltage is a constant voltage) is applied through the third bit line BLR. If the first programming operation is well-programmed for the first fuse body eFuse1, the silicide of the first fuse body eFuse1 will be completely consumed or the first fuse body eFuse1 will be completely blown, and then a very high resistance will be obtained, so the output node A will output a low level. At this time, the second programming transistor PGM2 is turned on, and the second fuse body efuse2 is turned on by the second programming operation. Programming; If the first programming operation programs the first fuse body eFuse1 poorly (Weakly-programmed), the silicide of the first fuse body eFuse1 is not completely consumed or diffuses back into the first fuse body eFuse1 again, or the first fuse body eFuse1 is not completely blown, then the output node A outputs a high level, and the third programming transistor PGM3 is turned on, and the third fuse body efuse3 is programmed by the second programming operation. That is to say, the second programming operation will adaptively program the second fuse body eFuse2 or the third fuse body eFuse3 to a high-impedance state according to the quality of the first programming operation.
[0063] Based on this, the programming method may optionally further include: judging the quality of programming of the first fuse body eFuse1 in the first programming operation according to which of the second fuse body eFuse2 and the third fuse body eFuse3 is programmed to a high-impedance state in the second programming operation, wherein, if the second fuse body eFuse2 is programmed to a high-impedance state in the second programming operation, it can be concluded that the programming of the first fuse body eFuse1 in the first programming operation is better, which will turn on the second programming transistor PGM2; if the third fuse body eFuse3 is programmed to a high-impedance state in the second programming operation, it can be concluded that the programming of the first fuse body eFuse1 in the first programming operation is poor, which will turn on the third programming transistor PGM3.
[0064] Optionally, based on this, the programming method may further include: determining the optimal programming conditions of the eFuse programming unit according to which of the second fuse body eFuse2 and the third fuse body eFuse3 is programmed to a high-impedance state in the second programming operation, the optimal programming conditions including the bias voltage and the first programming voltage magnitude applied by the first programming operation, the time of the first programming operation, the magnitude of the second programming voltage applied by the second programming operation and the operation time, etc.
[0065] Optionally, the second programming voltage and the third programming voltage applied in the second programming operation are the same.
[0066] Based on the same invention concept, please refer to Figure 4 This embodiment also provides an eFuse programming unit array, which includes a plurality of eFuse programming units as described in the present invention arranged in an array.
[0067] Optionally, the eFuse programming unit array is an m*n array, including m rows of eFuse programming units and n columns of eFuse programming units, wherein n≥2 and n is an integer, m≥2 and m is an integer, m may be equal to n, and m may also be equal to n, and:
[0068] The gates of the first programming transistors of the eFuse programming cells in the same row are connected to the same word line WL;
[0069] The first ends of the first fuse bodies of the eFuse programming units in the same column are connected to the same second bit line BLb;
[0070] The second ends of the second fuse bodies of the eFuse programming units in the same column are connected to the same first bit line BL;
[0071] The first ends of the third fuse bodies of the eFuse programming units in the same column are connected to the same third bit line BLR.
[0072] Therefore, according to actual application needs, by applying voltages to the word line WL, the first bit line BL, the second bit line BLb, and the third bit line BLR, one or more of the eFuse programming cells in the eFuse programming cell array can be selected for programming.
[0073] When m=n, the eFuse programming unit array is an n*n array.
[0074] In an example, see Figure 4 , the eFuse programming unit array is a 4*4 array (ie, m=n=4), which includes 4 rows of eFuse programming units as described in the present invention and 4 columns of eFuse programming units as described in the present invention, and has:
[0075] The gates of the first programming transistors PGM1 of the first row of eFuse programming cells are all connected to the first word line WL1;
[0076] The gates of the first programming transistors PGM1 of the eFuse programming units in the second row are all connected to the second word line WL2;
[0077] The gates of the first programming transistors PGM1 of the eFuse programming units in the third row are all connected to the third word line WL3;
[0078] The gates of the first programming transistors PGM1 of the eFuse programming cells in the 4th row are all connected to the 4th word line WL4;
[0079] The first ends of the first fuse bodies eFuse1 of the first column of eFuse programming units are all connected to the first second bit line BLb1, and the second ends of the second fuse bodies eFuse2 of the first column of eFuse programming units are all connected to the first first bit line BL1; the first ends of the third fuse bodies eFuse3 of the first column of eFuse programming units are all connected to the first third bit line BLR1;
[0080] The first ends of the first fuse bodies eFuse1 of the second column of eFuse programming units are all connected to the second second bit line BLb2, and the second ends of the second fuse bodies eFuse2 of the second column of eFuse programming units are all connected to the second first bit line BL2; the first ends of the third fuse bodies eFuse3 of the second column of eFuse programming units are all connected to the second third bit line BLR2;
[0081] The first ends of the first fuse bodies eFuse1 of the third column of eFuse programming units are all connected to the third second bit line BLb3, and the second ends of the second fuse bodies eFuse2 of the third column of eFuse programming units are all connected to the third first bit line BL3; the first ends of the third fuse bodies eFuse3 of the third column of eFuse programming units are all connected to the third third bit line BLR3;
[0082] The first end of the first fuse body eFuse1 of the 4th column eFuse programming unit is connected to the 4th second bit line BLb4, the second end of the second fuse body eFuse2 of the 4th column eFuse programming unit is connected to the 4th first bit line BL4; the first end of the third fuse body eFuse3 of the 4th column eFuse programming unit is connected to the 4th third bit line BLR4.
[0083] Based on the same invention concept, please refer to Figure 5 This embodiment also provides a chip, which includes: a word line control circuit 2, a first bit line control circuit 3, a second bit line control circuit 4, a third bit line control circuit 5, and the eFuse programming unit array 1 as described in the present invention. The eFuse programming unit array 1 is an n*n array, having n word lines WL1-WLn, n first bit lines BL1-BLn, n second bit lines BLb1-BLbn, and n third bit lines BLR1-BLRn. The word line control circuit 2 is coupled to each word line WL1-WLn of the eFuse programming unit array 1, the first bit line control circuit 3 is coupled to each first bit line BL1-BLn of the eFuse programming unit array 1, the second bit line control circuit 4 is coupled to each second bit line BLb1-BLbn of the eFuse programming unit array 1, and the third bit line control circuit 5 is coupled to each third bit line BLR1-BLRn of the eFuse programming unit array 1.
[0084] The chip may be any suitable chip, and may also include any other required internal circuits or functional modules. For example, the chip is an MCU (microcontroller) chip, and the MCU chip also has a CPU (central processing unit) core (not shown), SRAM (static random access memory, not shown), eflash (embedded memory, not shown), etc. The word line control circuit 2, the first bit line control circuit 3, the second bit line control circuit 4 and the third bit line control circuit 5 may be integrated in the CPU core.
[0085] In summary, the eFuse programming unit and programming method thereof, the eFuse programming unit array and the chip provided by the present invention, based on the structure of the traditional eFuse programming unit (i.e., the structure formed by the first programming transistor and the first fuse body in series), add two programming transistors and two fuse bodies (i.e., the second programming transistor, the third programming transistor, the second fuse body and the third fuse body), which can realize the secondary programming of a single eFuse programming unit, thereby improving the utilization rate of the eFuse programming unit within a limited area. Furthermore, the second programming transistor and the third programming transistor in the eFuse programming unit are reasonably laid out, for example, the second programming transistor and the third programming transistor are connected in parallel head to head and share a gate, which can effectively reduce the area of the second programming transistor and the third programming transistor, thereby improving the utilization rate while further effectively reducing the area of the eFuse programming unit and the eFuse programming unit array.
[0086] The above description is only a description of the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the technical solution of the present invention.
Claims
1. An eFuse programming unit, characterized in that: include: a first programming transistor, wherein a gate of the first programming transistor is connected to a word line, and a source of the first programming transistor is connected to a first power line; a first fuse body, a second end of the first fuse body connected to the drain of the first programming transistor to form an output node, and a first end of the first fuse body connected to a second bit line; a second programming transistor, wherein a gate of the second programming transistor is connected to the output node, and a source of the second programming transistor is connected to a second power line; a second fuse body, wherein a first end of the second fuse body is connected to a drain of the second programming transistor, and a second end of the second fuse body is connected to a first bit line; a third programming transistor, wherein a gate of the third programming transistor is connected to the output node, and a source of the third programming transistor is connected to the first power line; A third fuse body, wherein a first end of the third fuse body is connected to a third bit line, and a second end of the third fuse body is connected to a drain of the third programming transistor.
2. The eFuse programming unit according to claim 1, wherein: The third programming transistor has a conductivity type opposite to that of the second programming transistor.
3. The eFuse programming unit according to claim 2, wherein: The first programming transistor and the third programming transistor are both NMOS transistors, and the second programming transistor is a PMOS transistor.
4. The eFuse programming unit according to claim 1, wherein: In the layout structure of the eFuse programming unit, the second programming transistor has a first conductive type well, and the third programming transistor has a second conductive type well. The first conductive type well and the second conductive type well are arranged head to head, and the gate head end of the second programming transistor is connected to the gate head end of the third programming transistor, so that the second programming transistor and the third programming transistor share a common gate.
5. A programming method for an eFuse programming unit as claimed in any one of claims 1 to 4, characterized in that: The following steps are involved: Initially, the eFuse programming unit is in an initial state, the first programming transistor, the second programming transistor and the third programming transistor are all turned off, and the eFuse programming unit is in a low resistance state; A first programming operation: applying a bias voltage to the gate of the first programming transistor through the word line to turn on the first programming transistor, and applying a first programming voltage to the first fuse body through the second bit line to program the first fuse body to a high impedance state; The second programming operation is as follows: applying a second programming voltage through the first bit line and applying a third programming voltage through the third bit line to program the second fuse body or the third fuse body to a high resistance state.
6. The programming method according to claim 5, characterized in that: The second programming voltage is the same as the third programming voltage.
7. The programming method according to claim 5, characterized in that: Also includes: According to which one of the second fuse body and the third fuse body is programmed to a high impedance state in the second programming operation, determining whether the programming of the first fuse body by the first programming operation is good or bad; And / or, determining the optimal programming condition of the eFuse programming unit according to which one of the second fuse body and the third fuse body is programmed to the high impedance state in the second programming operation.
8. The programming method according to claim 7, characterized in that: If the second fuse body is programmed to a high-impedance state in the second programming operation, it can be concluded that the first programming operation has a better programming effect on the first fuse body, which will cause the second programming transistor to turn on; if the third fuse body is programmed to a high-impedance state in the second programming operation, it can be concluded that the first programming operation has a poor programming effect on the first fuse body, which will cause the third programming transistor to turn on.
9. An eFuse programming unit array, characterized in that: The invention comprises a plurality of eFuse programming units as claimed in any one of claims 1 to 4 arranged in an array.
10. The eFuse programming cell array according to claim 9, wherein: The eFuse programming unit array is an m*n array, including m rows of eFuse programming units and n columns of eFuse programming units, wherein n≥2 and n is an integer, m≥2 and m is an integer, and: The gates of the first programming transistors of the eFuse programming cells in the same row are connected to the same word line; The first ends of the first fuse bodies of the eFuse programming units in the same column are connected to the same second bit line; The second ends of the second fuse bodies of the eFuse programming units in the same column are connected to the same first bit line; The first ends of the third fuse bodies of the eFuse programming units in the same column are connected to the same third bit line.
11. A chip, characterized in that: include: A word line control circuit, a first bit line control circuit, a second bit line control circuit, a third bit line control circuit, and, an eFuse programming cell array as described in claim 9 or 10; wherein the word line control circuit is coupled to each word line of the eFuse programming cell array, the first bit line control circuit is coupled to each first bit line of the eFuse programming cell array, the second bit line control circuit is coupled to each second bit line of the eFuse programming cell array, and the third bit line control circuit is coupled to each third bit line of the eFuse programming cell array.