Crystal grain and testing method thereof

Abstract

The invention provides a crystal grain and a testing method thereof, and belongs to the technical field of semiconductors. The crystal grain comprises an input circuit, a first output channel, a second output channel and a coding circuit. Wherein the input circuit is used for receiving a test signal from a measurement output channel of a test machine, the first output channel and the second output channel are coupled to form a same shared output channel, and the coding circuit is used for coding the first output channel as a main channel and coding the second output channel as a slave channel. And the shared output channel is used for serially outputting the first test data in the main channel and the second test data in the slave channel according to the test signal so as to input the first test data and the second test data which are serially output into the same measurement input channel of the test machine.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a crystal grain and a testing method thereof. Background Art

[0002] In order to increase the integration of semiconductor products and improve data output efficiency, multiple (two or more) output channels are included in the same die. In the related art, when the same die includes multiple output channels, since the number of measurement input channels of the test machine is usually fixed, the number of dies that can be tested by the test machine at the same time is reduced, which reduces the test efficiency; or, in order to be able to test the same number of dies at the same time, the number of test machines needs to be increased, thereby increasing the test cost. Summary of the invention

[0003] The embodiment of the present disclosure provides a die, comprising: an input circuit, a first output channel, a second output channel, and an encoding circuit. The input circuit is used to receive a test signal from a measurement output channel of a test machine, the first output channel and the second output channel are coupled to form a same shared output channel, the encoding circuit is used to encode the first output channel as a master channel, and encode the second output channel as a slave channel, and the shared output channel is used to serially output first test data in the master channel and second test data in the slave channel according to the test signal, so as to input the first test data and the second test data outputted in series into the same measurement input channel of the test machine.

[0004] The disclosed embodiment further provides a method for testing a die, wherein the die includes a first output channel, a second output channel, and an encoding circuit; the first output channel and the second output channel are coupled to form a shared output channel, and the encoding circuit is used to encode the first output channel as a master channel and the second output channel as a slave channel. The method includes: the die receives a test signal from a measurement output channel of a test machine, wherein the test signal includes a delay signal; according to the test signal, the first test data in the master channel is output to the measurement input channel of the test machine through the shared output channel; according to the delay signal, the second test data in the slave channel is delayed by a predetermined clock cycle and then output to the measurement input channel through the shared output channel.

[0005] The disclosed embodiment further provides a method for testing a die, wherein the die includes a first output channel, a second output channel, and an encoding circuit; the first output channel and the second output channel are coupled to form a same shared output channel, and the encoding circuit is used to encode the first output channel as a master channel, and encode the second output channel as a slave channel. The method includes: a measurement output channel of a test machine inputs a test signal to the die, wherein the test signal includes a delay signal; the same measurement input channel of the test machine receives first test data and second test data outputted in series from the shared output channel, wherein the first test data is outputted from the master channel based on the test signal, and the second test data is outputted from the slave channel based on the test signal and the delay signal therein. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] Figure 1 It is a schematic diagram of a grain in the related art.

[0007] Figure 2 It is a test schematic diagram of a grain in the related technology.

[0008] Figure 3 It is a schematic diagram of another type of die testing in the related art.

[0009] Figure 4 is a schematic diagram of a die according to an exemplary embodiment of the present disclosure.

[0010] Figure 5 is a schematic diagram of a die according to another exemplary embodiment of the present disclosure.

[0011] Figure 6 Schematic diagram of a coding circuit according to an exemplary embodiment of the present disclosure.

[0012] Figure 7 is a schematic diagram of a die test according to an exemplary embodiment of the present disclosure.

[0013] Figure 8 is a schematic diagram of a die according to yet another exemplary embodiment of the present disclosure.

[0014] Fig. 9 is a schematic diagram of testing a die according to yet another exemplary embodiment of the present disclosure.

[0015] Fig.10 is a schematic diagram of a die according to yet another exemplary embodiment of the present disclosure.

[0016] Fig.11 is a schematic diagram of a die according to yet another exemplary embodiment of the present disclosure.

[0017] Fig.12 is a schematic diagram of a die according to yet another exemplary embodiment of the present disclosure.

[0018] Fig.13 is a schematic diagram of a die according to yet another exemplary embodiment of the present disclosure.

[0019] Fig.14 The present invention is a flowchart of a method for testing a finished semiconductor package according to an exemplary embodiment of the present invention.

[0020] Fig.15 The flowchart of a method for testing a finished semiconductor package product according to another exemplary embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0021] The accompanying drawings are only schematic diagrams of the present disclosure. The same reference numerals in the drawings represent the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the accompanying drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities can be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices. The memory provided in the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings.

[0022] like Figure 1 As shown, a die in the related art may include multiple output channels. Figure 1 In the example, two output channels are included. The test machine inputs a test signal to the die. The two output channels of the die simultaneously output their own test data. For example, the test data output from the first output channel of the die is assumed to be 0, 1, 2, 3, and the test data output from the second output channel of the die is assumed to be a, b, c, d, that is, the two output channels of the die are output in parallel. Therefore, during the test process, the two measurement input channels of the test machine need to be used to respectively receive the two parallel test data output by the two output channels of the die.

[0023] like Figure 2 As shown above Figure 1 Assume that each die includes two independent output channels. Assume that the test machine has only four fixed measurement input channels. Then, the four measurement input channels are connected to the four output channels of the two die respectively. That is, only two die can be tested at the same time. Figure 2 The grains 1 and 2 are shown in FIG.

[0024] like Figure 3 As shown, when each die includes 4 output channels and these 4 output channels output in parallel, assuming that the test machine still has only 4 fixed measurement input channels, the 4 measurement input channels are respectively connected to the 4 output channels of 1 die, that is, only 1 die can be tested.

[0025] According to the above Figures 1 to 3 It can be seen that since the same die includes multiple independent output channels, the multiple output channels output test data in parallel. In order to complete the test of the newly added output channels in the die, it is necessary to increase the test of the newly added output channels in the die. When the test machine does not increase the number of measurement input channels, the related art provides a corresponding multiple (for example Figure 2 In the middle, it is 2 times, Figure 3 The test of the die can be completed by using the measurement input channels (4 times in the example) but the number of dies tested at the same time will be reduced, which will increase the test cost and reduce the test efficiency.

[0026] Figure 4 Schematic diagram of a die according to an exemplary embodiment of the present disclosure. Figure 4 As shown, the die 400 provided in the embodiment of the present disclosure includes an input circuit (not shown in the figure), a first output channel 410, a second output channel 420 and an encoding circuit (not shown in the figure). It can be understood that the die in the embodiment of the present disclosure can include two or more output channels at the same time. Figure 4 The embodiment is described by taking two output channels as an example, but the present disclosure is not limited thereto.

[0027] The input end of the input circuit of the die 400 is used to receive a test signal from the measurement output channel 510 of the test machine 500. The first output channel 410 and the second output channel 420 are coupled to form a shared output channel 600. The encoding circuit in the die 400 is used to encode the first output channel 410 of the die 400 as a master channel and the second output channel 420 as a slave channel. The shared output channel 600 of the die 400 is used to serially output first test data of the master channel and second test data of the slave channel according to the received test signal, so as to input the serially output first test data and second test data into the same measurement input channel of the test machine.

[0028] In the disclosed embodiment, when there are multiple output channels in the same die, two or more output channels in the die are coupled into the same shared output channel, and the shared output channel is used to serially output test data of the two or more output channels. The output channel that outputs its test data preferentially is the master channel, and the output channel that outputs its test data through the shared output channel after the test data of the master channel is output is the slave channel.

[0029] For example, Figure 4As shown, assuming that according to the test signal, the first test signal output by the first output channel 410 of the grain 400 is 0, 1, 2, 3, and the second test data output by the second output channel 420 is a, b, c, d. When the first output channel 410 is encoded as a master channel and the second output channel 420 is encoded as a slave channel, the first test signal 0, 1, 2, 3 is output first, and then the second test data a, b, c, d is output, that is, the second test data is delayed by 4 clock cycles before being output.

[0030] In an exemplary embodiment, the test signal sent by the test machine 500 to the die 400 may include a test mode indication signal, and the test mode indication signal is used to indicate that the die 400 is currently in a test mode (test mode). When the die 400 is in the test mode, the first output channel 410 and the second output channel 420 of the die 400 are coupled to the same shared output channel 600. When the die 400 is not in the test mode, the first output channel 410 and the second output channel 420 of the die 400 are independent of each other, that is, they still maintain parallel output.

[0031] During the test, the test machine 500 can judge whether the die 400 can perform the correct data storage function by reading the first test data and the second test data from the die 400. For example, it is judged whether the read first test data and the second test data are respectively consistent with the first write data and the second write data previously written into the die 400. If the first test data is consistent with the first write data, and the second test data is consistent with the second write data, it is judged that the die 400 can perform the correct data storage function. If the first test data is inconsistent with the first write data, and the second test data is inconsistent with the second write data, it is judged that the die 400 cannot perform the correct data storage function.

[0032] The crystal grain provided by the embodiments of the present disclosure, on the one hand, can increase the integration degree of the crystal grain and improve the data reading speed by allowing the crystal grain to include multiple output channels at the same time; on the other hand, by coupling the multiple output channels of the crystal grain into the same shared output channel, during testing, the multiple output channels of the crystal grain are respectively encoded by the encoding circuit inside the crystal grain, for example, the first output channel is encoded as the main channel, and the second output channel is encoded as the slave channel, and the shared output channel is used to first output the first test data of the main channel and then output the second test data of the slave channel, so that the parallel output of the test data of the multiple output channels can be modified into a serial output. When the number of measurement input channels of the test machine is fixed, the number of crystal grains that complete the test at the same time can be increased without purchasing additional test machines, thereby reducing the test cost and improving the test efficiency.

[0033] In an exemplary embodiment, the first output terminal of the encoding circuit is used to output a first switch control signal of a first level to indicate that the first output channel is a main channel. The test signal includes a delay signal. The die also includes: a first delay output control circuit and a first switch element. The first switch element is used to not transmit the delay signal to the first delay output control circuit according to the first switch control signal of the first level, so that the shared output channel outputs the first test data to the test machine first.

[0034] In an exemplary embodiment, the second output terminal of the encoding circuit is used to output a second switch control signal of a second level to indicate that the second output channel is a slave channel. The test signal includes a delay signal. The die also includes: a second delay output control circuit and a second switch element. The second switch element is used to transmit the delay signal to the second delay output control circuit according to the second switch control signal of the second level, so that the shared output channel delays the second test data according to the delay signal for a predetermined clock period and then outputs it to the test machine.

[0035] Combine the following Figure 5 The crystal grains provided in the embodiments of the present disclosure are illustrated by way of example.

[0036] like Figure 5 As shown, the die 400 includes an encoding circuit 460, a first delayed output control circuit 411, an input circuit ( Figure 5In the embodiment, it is assumed that the input circuit includes a frequency receiver 430 and an instruction receiver 440), a database 450, a first output circuit 413, a first switch element 412, a second delayed output control circuit 421, a second output circuit 423, a second switch element 422, a first output channel 410 and a second output channel 420. The test signal sent by the test machine includes a delay signal SO. In the embodiment of the present disclosure, the delay signal is used to indicate that the corresponding test data is delayed for a predetermined clock cycle before being output to the test machine. Among them, the predetermined clock cycle is greater than or equal to the number of clock cycles of the test data previously output to the test machine through the shared output channel. The first output end of the encoding circuit 460 is used to output a first switch control signal Fzout1 of a first level to indicate that the first output channel 410 is the main channel. For example, the first level can be a low level, but the present disclosure is not limited thereto, as long as the first switch control signal of the first level can prevent the delay signal SO from being transmitted to the first delayed output control circuit 411. The first delayed output control circuit 411 includes a first input terminal, a second input terminal, a third input terminal, a first output terminal, and a second output terminal. The first switch element 412 includes an input terminal, a control terminal, and an output terminal. The frequency receiver 430 includes a first input terminal, a second input terminal, and an output terminal. The instruction receiver 440 includes multiple input terminals and a first output terminal and a second output terminal. The control terminal of the first switch element 412 is coupled to the first output terminal of the encoding circuit 460 to receive the first switch control signal Fzout1 of the first level, and the input terminal of the first switch element 412 is coupled to the first output terminal of the instruction receiver 440 to receive the delay signal SO (abbreviation of Slave Option) in the test signal sent by the test machine from the instruction receiver 440. The first input terminal of the first delayed output control circuit 411 is coupled to the output terminal of the first switch element 412. The frequency receiver 430 receives the differential clock signals CK_t and CK_c through its first input terminal and the second input terminal respectively. The differential clock signals CK_t and CK_c may be included in the test signal sent by the test machine, or may be provided by other clock generators, which is not limited in the present disclosure. The frequency receiver 430 may generate clock pulses according to the received differential clock signals CK_t and CK_c. The multiple input terminals of the instruction receiver 440 may be used to receive multiple test instructions (Commands, abbreviated as Cm), such as a read command (Read Command) or a write command (Write Command), an address signal, etc. The address signal may specifically include a bank group (storage body group) address signal, a bank (storage body) address signal, a row address signal, a column address signal, a delay signal, etc. The test signal includes the multiple test instructions. Here, the read command and the address signal and delay signal corresponding to the read command are used as an example for illustration, but the present disclosure is not limited thereto.The output end of the frequency receiver 430 is coupled to the second input end of the first delay output control circuit 411 to input the generated clock pulse to the first delay output control circuit 411. The second output end of the instruction receiver 440 is coupled to the input end of the database 450 to read the first test data and the second test data from the corresponding address of the database 450 according to the received test instruction such as the read command and the corresponding address signal. The output end of the database 450 is coupled to the third input end of the first delay output control circuit 411 and the third input end of the second delay output control circuit 421 respectively to input the first test data to the first delay output control circuit 411 and the second test data to the second delay output control circuit 421. The first switch element 412 is controlled by the first switch control signal Fzout1 of the first level, and the first switch element 412 is turned off (disconnected), so that the delay signal SO sent by the test machine will not be transmitted to the first delay output control circuit 411. Therefore, the first delayed output control circuit 411 outputs the first test data without delay through the first output terminal of the first delayed output control circuit 411 to the input terminal of the first output circuit 413 according to the received clock pulse and the first test data. The output terminal of the first output circuit 413 is coupled to the first output channel 410 of the die 400 to output the first test data.

[0037] Continue to refer Figure 5, the second output end of the encoding circuit 460 is used to output the second switch control signal Fzout2 of the second level to indicate that the second output channel 420 is a slave channel. For example, the second level can be a high level, but the present disclosure is not limited thereto, as long as the second switch control signal of the second level can transmit the delay signal to the second delay output control circuit 421. The second delay output control circuit 421 includes a first input end, a second input end, a third input end and an output end. The second switch element 422 includes an input end, a control end and an output end. The control end of the second switch element 422 is coupled to the second output end of the encoding circuit 460 to receive the second switch control signal Fzout2 of the second level, and the input end of the second switch element 422 is coupled to the first output end of the instruction receiver 440 to receive the delay signal SO sent by the test machine. The first input end of the second delay output control circuit 421 is coupled to the output end of the second switch element 422. The second output end of the first delay output control circuit 411 is coupled to the second input end of the second delay output control circuit 421 to input the clock pulse to the second delay output control circuit 421. Under the control of the second switch control signal Fzout2 of the second level, the second switch element 422 opens (closes) the second switch element 422, so that the delay signal SO sent by the test machine is transmitted to the second delay output control circuit 421. Therefore, the second delay output control circuit 421 delays the second test data by a predetermined clock cycle according to the received clock pulse, the delay signal and the second test data, and then outputs the second test data to the input end of the second output circuit 423 through the output end of the second delay output control circuit 421. The output end of the second output circuit 423 is coupled to the second output channel 420 of the die 400, and the second output channel 420 is coupled to the first output channel 410 to form a shared output channel, and the second test data after the delay of the predetermined clock cycle is output through the shared output channel. For example, if the first test data needs to occupy 4 clock cycles (4T) of the clock pulse to be output through the shared output channel, the predetermined clock cycle is greater than or equal to 4T.

[0038] In the embodiments of the present disclosure, the crystal grain may be a semiconductor memory chip, such as a DRAM (Dynamic Random Access Memory) chip. DRAM is used as an example below, but the present disclosure is not limited thereto. The instruction receiver may be a command receiving circuit (Control logic) in a DRAM chip, which may include a Command decode, an ODT (On-Die Termination) control, and a Mode register, but the present disclosure is not limited thereto. The database may be a data storage module in a DRAM chip, which may include multiple banks (e.g., bank 0 to bank 15). Figure 5 Not shown in the figure, it may also include row address latches and decoders of each bank, column address counters / latches, column decoders, sense amplifiers, self-refresh counters, etc. The first delayed output control circuit and the second delayed output control circuit may be read logic in a DRAM chip. The first output circuit and the second output circuit may be drivers in a DRAM chip.

[0039] The die provided by the embodiments of the present disclosure, on the one hand, couples multiple output channels packaged in the die (for example, the first output channel and the second output channel in the die) into the same shared output channel, and serially outputs the test data of the at least two output channels (for example, the first test data of the first output channel and the second test data of the second output channel) to the same measurement input channel of the test machine through the shared output channel, thereby increasing the number of die tested simultaneously without increasing the cost of the test machine, reducing the test cost and improving the test efficiency; on the other hand, a coding circuit is preset in the die, and the at least two output channels can be pre-encoded as a master channel and a slave channel respectively through the coding circuit preset inside the die, thereby knowing to which output channel the delay signal received simultaneously from the test machine is to be transmitted to the delay output control circuit corresponding to which output channel, so as to accurately determine which output channel's test data is to be output first and which output channel's test data is to be output later during serial transmission, thereby ensuring the accuracy of serial transmission and improving test reliability. At the same time, the encoding circuit is pre-set inside the die, and before the test, it has been encoded which output channel is the main channel and which output channel is the slave channel. In this way, after packaging, the at least two output channels can share the same external pins and receive the same test signals sent by the test machine. That is, from the external pins of the die after packaging, there is no difference between the at least two output channels, but the main channel and the slave channel are automatically identified inside the die, thereby reducing the complexity of the test, eliminating the need to add additional external pins and additional test signals after packaging, and simplifying the test process.

[0040] In an exemplary embodiment, the encoding circuit includes a first one-time programming memory cell in a die.

[0041] In an exemplary embodiment, the first one-time programming memory cell in the die is not programmed, so that the first output terminal of the encoding circuit outputs a first switch control signal of a first level.

[0042] In an exemplary embodiment, the encoding circuit includes a second one-time programming memory cell in the die.

[0043] In an exemplary embodiment, the second one-time programming memory cell in the die has been programmed so that the second output terminal of the encoding circuit outputs a second switch control signal of a second level.

[0044] In other embodiments, the first one-time programming storage unit in the die may be programmed to indicate that the first output channel is the master channel, and the second one-time programming storage unit in the unprogrammed die may be programmed to indicate that the second output channel is the slave channel, which is not limited in the present disclosure.

[0045] In the disclosed embodiment, at least two output channels in the same die are coupled to form the same shared output channel. For the at least two output channels, a coding circuit is pre-set inside the die to identify the master channel and the slave channel. The coding circuit set inside the die can reuse the existing one-time programming memory (efuse) inside the die, thereby simplifying the internal structure of the die and reducing the design complexity and cost. Specifically, each die includes an efuse array, and the efuse array includes a plurality of efuse cells (one-time programming storage units) arranged in an array. Before testing, at least one efuse cell can be selected from the plurality of efuse cells in advance to be used as the coding circuit inside the die. The selected efuse cell used to indicate the master channel is called the first one-time programming storage unit, and the one used to indicate the slave channel is called the second one-time programming storage unit.

[0046] Combine the following Figure 6 Examples are given for illustration, but the present disclosure is not limited thereto. Figure 6 As shown, the encoding circuit 600 in the embodiment of the present disclosure can be used as Figure 5The first one-time programming storage unit and / or the second one-time programming storage unit in the encoding circuit 460 in the embodiment. The encoding circuit 600 may include a control circuit 610, an efuse transistor M1 and a switch transistor M2. The control end of the efuse transistor M1 is coupled to the output end of the control circuit 610, and the first end of the efuse transistor M1 is coupled to the second end of the efuse transistor M1. The second end of the efuse transistor M1 is coupled to the first end of the switch transistor M2. The control end of the switch transistor M2 is used to receive the address selection signal Xadd. The second end of the switch transistor M2 serves as the output end of the encoding circuit 600. The switch transistor M2 can be turned on or off according to the high or low level of the received address selection signal Xadd. When the switch transistor M2 is turned on according to the received address selection signal Xadd, it is determined that the efuse transistor M1 is selected as the first one-time programming storage unit or the second one-time programming storage unit of the die. The control circuit 610 can be used to generate a first control signal Con1, and input the first control signal Con1 to the control end of the efuse transistor M1 through the output end of the control circuit 610 to control the conduction or cutoff of the efuse transistor M1. For example, when the first control signal Con1 is at a high level to turn on the efuse transistor M1, it is determined that the one-time programming storage unit is burned, and the switch control signal Fzout output at this time is the second switch control signal Fzout2 of the second level, that is, the one-time programming storage unit is the second one-time programming storage unit. When the first control signal Con1 is at a low level so that the efuse transistor M1 is turned off, it is determined that the one-time programming storage unit is not burned, and the switch control signal Fzout output at this time is the first switch control signal Fzout1 of the first level, that is, the one-time programming storage unit is the first one-time programming storage unit.

[0047] Figure 6 The efuse transistor M1 and the switch transistor M2 in the embodiment can be PMOS (P-channel Metal Oxide Semiconductor, P-type channel metal oxide semiconductor) transistors, or NMOS (N-channel Metal Oxide Semiconductor, N-type channel metal oxide semiconductor) transistors. At this time, the control end of the efuse transistor M1 and the switch transistor M2 is the gate of PMOS or NMOS, the first end is the source or drain of PMOS or NMOS, and the second end is the drain or source of PMOS or NMOS. If the efuse transistor M1 and the switch transistor M2 are NMOS transistors, the high level is turned on and the low level is cut off; if they are PMOS transistors, the low level is turned on and the high level is cut off.

[0048] In the disclosed embodiment, the existing efuse in the die is used as the coding circuit of the die for burning or not burning to identify the master channel and the slave channel, which can reduce the design complexity of the die and reduce the manufacturing cost of the die.

[0049] In an exemplary embodiment, the second one-time programming memory cell in the die is burned before or after the die is packaged into a finished semiconductor package.

[0050] In the embodiment of the present disclosure, if the second output channel is indicated as a slave channel by burning the second one-time programming storage unit in the die, the second one-time programming storage unit in the die can be burned before the die is packaged into the finished semiconductor package. Alternatively, the second one-time programming storage unit in the die can be burned after the die is packaged into the finished semiconductor package and before testing. Before the test, a corresponding control instruction is then sent to the die to burn the second one-time programming storage unit in the die separately. In an exemplary embodiment, before and after the test, the first output channel and the second output channel of the die are not coupled together, that is, they are independent of each other.

[0051] like Figure 7 As shown, in the same case where each die includes 2 output channels and the test machine has 4 measurement input channels, the method provided by the embodiment of the present disclosure can simultaneously test 4 dies, namely, die 1 to die 4. Figure 2 The number of die tested simultaneously has doubled.

[0052] like Figure 8 As shown, it is assumed that the same die 800 includes four output channels, namely output channel 810, output channel 820, output channel 830 and output channel 840. The four output channels can be coupled together to form a shared output channel 900, so as to serially output the first test data (e.g., 1, 2, 3, 4) of the output channel 810, the second test data (e.g., ①, ②, ③, ④) of the output channel 820, the third test data (e.g., A, B, C, D) of the output channel 830 and the fourth test data (e.g., a, b, c, d) of the output channel 840 to a measurement input channel of the test machine, for example, the second test data delay is 4T, the third test data delay is 8T, and the fourth test data delay is 12T.

[0053] like Fig. 9 As shown, each die includes 4 output channels, and these 4 output channels are coupled as a shared output channel. In the same case where the test machine has 4 measurement input channels, the method provided by the embodiment of the present disclosure can be used to test 4 dies at the same time, namely, die 1 to die 4. Figure 3The number of dies tested simultaneously has increased fourfold.

[0054] correspond Figure 8 The die 800 shown can be used Fig.10 The structure shown in the figure is used to implement this. Fig.10As shown, the delay signal includes a first delay signal SO1, a second delay signal SO2 and a third delay signal. The first delay signal SO1 is used to indicate that the second test data is delayed by a first predetermined clock cycle (for example, 4T, depending on the clock cycle occupied by the first test data) before being output to the test machine. The second delay signal SO2 is used to indicate that the third test data is delayed by a second predetermined clock cycle (for example, 8T, depending on the clock cycle occupied by the first test data and the second test data) before being output to the test machine. The third delay signal SO3 is used to indicate that the fourth test data is delayed by a third predetermined clock cycle (for example, 12T, depending on the clock cycle occupied by the first test data, the second test data and the third test data) before being output to the test machine. The first switch control signal of the first level includes a first-level switch control signal Fzout141, a first-level switch control signal Fzout142, and a first-level switch control signal Fzout143. The first output terminal of the encoding circuit 6 includes a first-level output terminal, a first-level output terminal, and a first-level output terminal, so as to respectively output the first-level switch control signal Fzout141, the first-level switch control signal Fzout142, and the first-level switch control signal Fzout143, so as to indicate that the first output channel 810 is the main channel. The first switch element includes a first-level switch element 121, a first-level switch element 122, and a first-level switch element 123. The first input terminal of the first delay output control circuit 11 includes a first-level input terminal, a first-level input terminal, and a first-level input terminal, so as to respectively couple the output terminal of the first-level switch element 121, the output terminal of the first-level switch element 122, and the output terminal of the first-level switch element 123. The first output terminal of the encoding circuit 6 includes a first-level output terminal, a first-level output terminal, and a first-level output terminal. The first output end of the instruction receiver 4 includes a first output end, a first second output end, and a first third output end. The control end of the first first switch element 121 is coupled to the first first output end of the encoding circuit 6 to receive the first first switch control signal Fzout141 of the first level, and the input end of the first first switch element 121 is coupled to the first first output end of the instruction receiver 4 to receive the first delay signal SO1 in the test signal sent by the test machine. The control end of the first second switch element 122 is coupled to the first second output end of the encoding circuit 6 to receive the first second switch control signal Fzout142 of the first level, and the input end of the first second switch element 122 is coupled to the first second output end of the instruction receiver 4 to receive the second delay signal SO2 in the test signal sent by the test machine. The control end of the first third switch element 123 is coupled to the first third output end of the encoding circuit 6 to receive the first third switch control signal Fzout143 of the first level, and the input end of the first second switch element 123 is coupled to the first third output end of the instruction receiver 4 to receive the third delay signal SO3 in the test signal sent by the test machine.The first input terminal, the first second input terminal and the first third input terminal of the first delay output control circuit 11 are respectively coupled to the output terminals of the first first switch element 121, the first second switch element 122 and the first third switch element 123. The first input terminal and the second input terminal of the frequency receiver 3 respectively receive the differential clock signals CK_t and CK_c to generate clock pulses, and the output terminal of the frequency receiver 3 is coupled to the second input terminal of the first delay output control circuit 11 to input the clock pulse to the first delay output control circuit 11. The multiple input terminals of the instruction receiver 4 can be used to receive the test instruction Cm respectively. The second output terminal of the instruction receiver 4 is coupled to the input terminal of the database 5 to read the first test data, the second test data, the third test data and the fourth test data from the corresponding address of the database 5 according to the received test instruction. The output end of the database 5 is respectively coupled to the third input end of the first delayed output control circuit 11, the second delayed output control circuit 21, the third delayed output control circuit 31, and the fourth delayed output control circuit 41, so as to respectively input the first test data, the second test data, the third test data, and the fourth test data into the first delayed output control circuit 11, the second delayed output control circuit 21, the third delayed output control circuit 31, and the fourth delayed output control circuit 41. The first first switch element 121, the first second switch element 122, and the first third switch element 123 are respectively controlled by the first first switch control signal Fzout141, the first second switch control signal Fzout142, and the first third switch control signal Fzout142 of the first level to close (disconnect) the first first switch element 121, the first second switch element 122, and the first third switch element 123, so that the first delay signal SO1, the second delay signal SO2, and the third delay signal SO3 are not transmitted to the first delayed output control circuit 11. Therefore, the first delayed output control circuit 11 outputs the first test data without delay through the output end of the first delayed output control circuit 11 to the input end of the first output circuit 13 according to the received clock pulse and the first test data. The output end of the first output circuit 13 is coupled to the first output channel 810 of the die 800 to output the first test data.

[0055] Continue to refer Fig.10, the second switch control signal includes a second-level second-switch control signal Fzout241, a first-level second-switch control signal Fzout242, and a first-level second-switch control signal Fzout243. The second output terminal of the encoding circuit 6 includes a second-level output terminal, a second-level output terminal, and a second-level output terminal, so as to respectively output the second-level second-switch control signal Fzout241, a first-level second-switch control signal Fzout242, and a first-level second-switch control signal Fzout243, so as to indicate that the second output channel 820 of the die 800 is the first slave channel. The second switch element includes a second-level switch element 221, a second-level switch element 222, and a second-level switch element 223. The first input terminal of the second delay output control circuit 21 includes a second-level input terminal, a second-level input terminal, and a second-level input terminal, so as to respectively couple the output terminal of the second-level switch element 221, the output terminal of the second-level switch element 222, and the output terminal of the second-level switch element 223. The control end of the second-first switch element 221 is coupled to the second-first output end of the encoding circuit 6 to receive the second-first switch control signal Fzout241 of the second level, and the input end of the second-first switch element 221 is coupled to the first-first output end of the instruction receiver 4 to receive the first delay signal SO1. The control end of the second-second switch element 222 is coupled to the second-second output end of the encoding circuit 6 to receive the second-second switch control signal Fzout242 of the first level, and the input end of the second-second switch element 222 is coupled to the first-second output end of the instruction receiver 4 to receive the second delay signal SO2. The control end of the second-third switch element 223 is coupled to the second-third output end of the encoding circuit 6 to receive the second-third switch control signal Fzout243 of the first level, and the input end of the second-third switch element 223 is coupled to the first-third output end of the instruction receiver 4 to receive the third delay signal SO3. The second-first input end, the second-second input end, and the second-third input end of the second delayed output control circuit 21 are respectively coupled to the output ends of the second-first switch element 221, the second-second switch element 222, and the second-third switch element 223. The second output terminal of the first delayed output control circuit 11 is coupled to the second input terminal of the second delayed output control circuit 21 to input the clock pulse to the second delayed output control circuit 21. Under the control of the second-first switch control signal Fzout241 of the second level, the second-first switch element 221 is turned on (closed), so that the first delayed signal SO1 is transmitted to the second delayed output control circuit 21. The second-second switch element 222 and the second-third switch element 223 are respectively turned off (disconnected) under the control of the second-second switch control signal Fzout242 and the second-third switch control signal Fzout243 of the first level, so that the second delayed signal SO2 and the third delayed signal SO3 are not transmitted to the second delayed output control circuit 21.Therefore, the second delay output control circuit 21 delays the second test data by the first predetermined clock cycle according to the received clock pulse, the second test data and the first delay signal SO1, and outputs the second test data to the input end of the second output circuit 23 through the output end of the second delay output control circuit 21. The output end of the second output circuit 23 is coupled to the second output channel 820 of the die 800 to output the second test data.

[0056] Continue to refer Fig.10, the encoding circuit 6 also outputs a third switch control signal, the third switch control signal includes a third-first switch control signal Fzout341 of a first level, a third-second switch control signal Fzout342 of a second level, and a third-third switch control signal Fzout343 of a first level, and the encoding circuit 6 also includes a third output terminal, the third output terminal includes a third-first output terminal, a third-second output terminal, and a third-third output terminal, to respectively output the third-first switch control signal Fzout341 of a first level, the third-second switch control signal Fzout342 of a second level, and the third-third switch control signal Fzout343 of a first level, to indicate that the third output channel 830 of the die 800 is a second slave channel. The third switch element includes a third-first switch element 321, a third-second switch element 322, and a third-third switch element 323. The first input terminal of the third delayed output control circuit 31 includes a third-first input terminal, a third-second input terminal, and a third-third input terminal, to respectively couple the output terminal of the third-first switch element 321, the output terminal of the third-second switch element 322, and the output terminal of the third-third switch element 323. The control end of the third-first switch element 321 is coupled to the third-first output end of the encoding circuit 6 to receive the third-first switch control signal Fzout341 of the first level, and the input end of the third-first switch element 321 is coupled to the first-first output end of the instruction receiver 4 to receive the first delay signal SO1. The control end of the third-second switch element 322 is coupled to the third-second output end of the encoding circuit 6 to receive the third-second switch control signal Fzout342 of the second level, and the input end of the third-second switch element 322 is coupled to the first-second output end of the instruction receiver 4 to receive the second delay signal SO2. The control end of the third-third switch element 323 is coupled to the third-third output end of the encoding circuit 6 to receive the third-third switch control signal Fzout343 of the first level, and the input end of the third-third switch element 323 is coupled to the first-third output end of the instruction receiver 4 to receive the third delay signal SO3. The third-first input end, the third-second input end and the third-third input end of the third delayed output control circuit 31 are respectively coupled to the output ends of the third-first switch element 321, the third-second switch element 322 and the third-third switch element 323. The second output terminal of the second delayed output control circuit 21 is coupled to the second input terminal of the third delayed output control circuit 31 to input the clock pulse to the third delayed output control circuit 31. The third-first switch element 321 and the third-third switch element 323 are respectively controlled by the third-first switch control signal Fzout341 and the third-third switch control signal Fzout343 of the first level to turn off (disconnect) the third-first switch element 321 and the third-third switch element 323, so that the first delayed signal SO1 and the third delayed signal SO3 are not transmitted to the third delayed output control circuit 31.The third second switch element 322 is controlled by the third second switch control signal Fzout242 of the second level, and the third second switch element 322 is turned on (closed), so that the second delay signal SO2 is transmitted to the third delay output control circuit 31. Therefore, the third delay output control circuit 31 delays the third test data by the second predetermined clock cycle according to the received clock pulse, the third test data and the second delay signal SO2, and outputs the third test data to the input end of the third output circuit 33 through the output end of the third delay output control circuit 31. The output end of the third output circuit 33 is coupled to the third output channel 830 of the die 800 to output the third test data.

[0057] Continue to refer Fig.10, the encoding circuit 6 also outputs a fourth switch control signal, the fourth switch control signal includes a fourth-first switch control signal Fzout441 of a first level, a fourth-second switch control signal Fzout442 of a first level, and a fourth-third switch control signal Fzout443 of a second level, and the encoding circuit 6 also includes a fourth output terminal, the fourth output terminal includes a fourth-first output terminal, a fourth-second output terminal, and a fourth-third output terminal, to respectively output the fourth-first switch control signal Fzout441 of a first level, the fourth-second switch control signal Fzout442 of a first level, and the fourth-third switch control signal Fzout443 of a second level, to indicate that the fourth output channel 830 of the die 800 is the third slave channel. The fourth switch element includes a fourth-first switch element 421, a fourth-second switch element 422, and a fourth-third switch element 423. The first input terminal of the fourth delayed output control circuit 41 includes a fourth-first input terminal, a fourth-second input terminal, and a fourth-third input terminal, to respectively couple the output terminal of the fourth-first switch element 421, the output terminal of the fourth-second switch element 422, and the output terminal of the fourth-third switch element 423. The control end of the fourth-first switch element 421 is coupled to the fourth-first output end of the encoding circuit 6 to receive the fourth-first switch control signal Fzout441 of the first level, and the input end of the fourth-first switch element 421 is coupled to the first-first output end of the instruction receiver 4 to receive the first delay signal SO1. The control end of the fourth-second switch element 422 is coupled to the fourth-second output end of the encoding circuit 6 to receive the fourth-second switch control signal Fzout442 of the first level, and the input end of the fourth-second switch element 422 is coupled to the first-second output end of the instruction receiver 4 to receive the second delay signal SO2. The control end of the fourth-third switch element 423 is coupled to the fourth-third output end of the encoding circuit 6 to receive the fourth-third switch control signal Fzout443 of the second level, and the input end of the fourth-third switch element 423 is coupled to the first-third output end of the instruction receiver 4 to receive the third delay signal SO3. The fourth first input terminal, the fourth second input terminal and the fourth third input terminal of the fourth delayed output control circuit 41 are respectively coupled to the output terminals of the fourth first switch element 421, the fourth second switch element 422 and the fourth third switch element 423. The second output terminal of the third delayed output control circuit 31 is coupled to the second input terminal of the fourth delayed output control circuit 41 to input the clock pulse to the fourth delayed output control circuit 41. The fourth first switch element 421 and the fourth second switch element 422 are respectively controlled by the fourth first switch control signal Fzout441 and the fourth second switch control signal Fzout442 of the first level to close (disconnect) the fourth first switch element 421 and the fourth second switch element 422, so that the first delayed signal SO1 and the second delayed signal SO2 will not be transmitted to the fourth delayed output control circuit 41.Under the control of the fourth third switch control signal Fzout443 of the second level, the fourth third switch element 423 is turned on (closed), so that the third delay signal SO3 is transmitted to the fourth delay output control circuit 41. Therefore, the fourth delay output control circuit 41 delays the fourth test data by the third predetermined clock cycle according to the received clock pulse, the fourth test data and the third delay signal SO3, and outputs the fourth test data to the input end of the fourth output circuit 43 through the output end of the fourth delay output control circuit 41. The output end of the fourth output circuit 43 is coupled to the fourth output channel 840 of the die 800 to output the fourth test data.

[0058] like Fig.11 As shown, it is assumed that four output channels are simultaneously packaged in the same die 1100. Three of the output channels can be coupled together to share the output channel, and the remaining output channel maintains its original independent output channel. For example, output channels 1 to 3 are coupled to a shared output channel to serially output the first test data of output channel 1, the second test data of output channel 2, and the third test data of output channel 3 to a measurement input channel of the test machine, and the fourth test data of output channel 4 is output to another measurement input channel of the test machine.

[0059] correspond Fig.11 The die 1100 shown can be used Fig.12 The structure shown in the figure is used to implement this. Fig.12As shown, the first input end of the first delayed output control circuit 11' includes a first input end and a first second input end, which are respectively coupled to the output end of the first switch element 121 and the output end of the first second switch element 122. The control end of the first switch element 121 is coupled to the first output end of the encoding circuit 6 to receive the first switch control signal Fzout141 of the first level, and the input end of the first switch element 121 is coupled to the first output end of the instruction receiver 4 to receive the first delay signal SO1 in the test signal sent by the test machine. The control end of the first second switch element 122 is coupled to the first second output end of the encoding circuit 6 to receive the first second switch control signal Fzout142 of the first level, and the input end of the first second switch element 122 is coupled to the first second output end of the instruction receiver 4' to receive the second delay signal SO2 in the test signal sent by the test machine. The first input end and the first second input end of the first delayed output control circuit 11' are respectively coupled to the output ends of the first switch element 121 and the first second switch element 122. The output end of the frequency receiver 3 is coupled to the second input end of the first delayed output control circuit 11' to input the clock pulse to the first delayed output control circuit 11'. The second output end of the instruction receiver 4' is coupled to the input end of the database 5 to read the first test data, the second test data, the third test data and the fourth test data from the corresponding address of the database 5 according to the received test instruction. The output end of the database 5 is respectively coupled to the third input ends of the first delayed output control circuit 11', the second delayed output control circuit 21', the third delayed output control circuit 31' and the output control circuit 41' to input the first test data, the second test data, the third test data and the fourth test data to the first delayed output control circuit 11', the second delayed output control circuit 21', the third delayed output control circuit 31' and the output control circuit 41'. The first-one switch element 121 and the first-two switch element 122 are respectively controlled by the first-one switch control signal Fzout141 and the first-two switch control signal Fzout142 of the first level, and close (disconnect) the first-one switch element 121 and the first-two switch element 122, so that the first delay signal SO1 and the second delay signal SO2 are not transmitted to the first delay output control circuit 11'. Therefore, the first delay output control circuit 11' outputs the first test data to the input end of the first output circuit 13 through the output end of the first delay output control circuit 11' without delay according to the received clock pulse and the first test data. The output end of the first output circuit 13 is coupled to the first output channel 10 of the die 1100 to output the first test data.

[0060] The first input end of the second delayed output control circuit 21' includes a second-first input end and a second-second input end, which are respectively coupled to the output end of the second-first switch element 221 and the output end of the second-second switch element 222. The control end of the second-first switch element 221 is coupled to the second-first output end of the encoding circuit 6 to receive the second-first switch control signal Fzout241 of the second level, and the input end of the second-first switch element 221 is coupled to the first-first output end of the instruction receiver 4 to receive the first delay signal SO1. The control end of the second-second switch element 222 is coupled to the second-second output end of the encoding circuit 6 to receive the second-second switch control signal Fzout242 of the first level, and the input end of the second-second switch element 222 is coupled to the first-second output end of the instruction receiver 4 to receive the second delay signal SO2. The second-first input end and the second-second input end of the second delayed output control circuit 21' are respectively coupled to the output ends of the second-first switch element 221 and the second-second switch element 222. The second output end of the first delayed output control circuit 11' is coupled to the second input end of the second delayed output control circuit 21' to input the clock pulse to the second delayed output control circuit 21'. Under the control of the second first switch control signal Fzout241 of the second level, the second first switch element 221 is turned on (closed) so that the first delayed signal SO1 is transmitted to the second delayed output control circuit 21'. Under the control of the second second switch control signal Fzout242 of the first level, the second second switch element 222 is turned off (disconnected) so that the second delayed signal SO2 is not transmitted to the second delayed output control circuit 21'. Therefore, the second delayed output control circuit 21' delays the second test data by the first predetermined clock cycle according to the received clock pulse, the second test data and the first delayed signal SO1, and outputs it to the input end of the second output circuit 23 through the output end of the second delayed output control circuit 21'. The output end of the second output circuit 23 is coupled to the second output channel 20 of the die 1100 to output the second test data.

[0061] The first input end of the third delayed output control circuit 31' includes a third-first input end and a third-second input end, which are respectively coupled to the output end of the third-first switch element 321 and the output end of the third-second switch element 322. The control end of the third-first switch element 321 is coupled to the third-first output end of the encoding circuit 6 to receive the third-first switch control signal Fzout341 of the first level, and the input end of the third-first switch element 321 is coupled to the first-first output end of the instruction receiver 4 to receive the first delay signal SO1. The control end of the third-second switch element 322 is coupled to the third-second output end of the encoding circuit 6 to receive the third-second switch control signal Fzout342 of the second level, and the input end of the third-second switch element 322 is coupled to the first-second output end of the instruction receiver 4 to receive the second delay signal SO2. The third-first input end and the third-second input end of the third delayed output control circuit 31 are respectively coupled to the output ends of the third-first switch element 321 and the third-second switch element 322. The second output end of the second delayed output control circuit 21' is coupled to the second input end of the third delayed output control circuit 31' to input the clock pulse to the third delayed output control circuit 31'. The third-first switch element 321 is controlled by the third-first switch control signal Fzout341 of the first level, and the third-first switch element 321 is turned off (disconnected), so that the first delayed signal SO1 is not transmitted to the third delayed output control circuit 31'. The third-second switch element 322 is controlled by the third-second switch control signal Fzout242 of the second level, and the third-second switch element 322 is turned on (closed), so that the second delayed signal SO2 is transmitted to the third delayed output control circuit 31'. Therefore, the third delayed output control circuit 31' delays the third test data by the second predetermined clock cycle according to the received clock pulse, the third test data and the second delayed signal SO2, and outputs it to the input end of the third output circuit 33 through the output end of the third delayed output control circuit 31'. The output end of the third output circuit 33 is coupled to the third output channel 30 of the die 1100 to output the third test data.

[0062] Continue to refer Fig.12 The second output terminal of the third delayed output control circuit 31' is coupled to the second input terminal of the output control circuit 41' to input the clock pulse to the output control circuit 41'. The output control circuit 41' outputs the fourth test data to the input terminal of the fourth output circuit 43 through the output terminal of the output control circuit 41' according to the received clock pulse and the fourth test data. The output terminal of the fourth output circuit 43 is coupled to the fourth output channel 40 of the die 1100 to output the fourth test data.

[0063] like Fig.13As shown, it is assumed that there are 4 output channels in the same die 1000. Every 2 output channels of the 4 output channels can be coupled together to share the output channel, so as to serially output the first test data and the second test data to a measurement input channel of the test machine, and serially output the third test data and the fourth test data to another measurement input channel of the test machine.

[0064] Fig.14 FIG. 1 is a flow chart of a method for testing a die according to an exemplary embodiment of the present disclosure. Fig.14 In an embodiment, the die includes a first output channel, a second output channel, and an encoding circuit. The first output channel and the second output channel are coupled to form a shared output channel. The encoding circuit is used to encode the first output channel as a master channel and encode the second output channel as a slave channel. Fig.14 As shown, the method provided by the embodiment of the present disclosure may include the following steps.

[0065] In S1410 , the die receives a test signal from a measurement output channel of a test machine, where the test signal includes a delay signal.

[0066] In S1420 , first test data in the main channel is output to a measurement input channel of the test machine through a shared output channel according to the test signal.

[0067] In S1430, the second test data in the channel is delayed by a predetermined clock cycle according to the delay signal and then output to the measurement input channel through the shared output channel.

[0068] Fig.15 FIG. 1 is a flow chart of a method for testing a die according to another exemplary embodiment of the present disclosure. Fig.15 In an embodiment, the die includes a first output channel, a second output channel, and an encoding circuit. The first output channel and the second output channel are coupled to form a shared output channel, and the encoding circuit is used to encode the first output channel as a master channel and encode the second output channel as a slave channel. Fig.15 As shown, the method provided by the embodiment of the present disclosure may include the following steps.

[0069] In S1510 , a measurement output channel of a test machine inputs a test signal to the die, where the test signal includes a delay signal.

[0070] In S1520, the same measurement input channel of the test machine receives first test data and second test data output in series from a shared output channel, wherein the first test data is output from a main channel based on a test signal, and the second test data is output from a slave channel based on the test signal and a delayed signal therein.

[0071] The present disclosure is intended to cover any variation, use or adaptation of the present disclosure, which follows the general principles of the present disclosure and includes common knowledge or customary technical means in the technical field not disclosed in the present disclosure. The description and examples are to be regarded as exemplary only, and the true scope and concept of the present disclosure are indicated by the claims.

Claims

1. A crystal grain, characterized in that: include: An input circuit, a first output channel, a second output channel and an encoding circuit; Wherein, the input circuit is used to receive a test signal from a measurement output channel of a test machine, the first output channel and the second output channel are coupled as the same shared output channel, the encoding circuit is used to encode the first output channel as a master channel, and encode the second output channel as a slave channel, and the shared output channel is used to serially output the first test data in the master channel and the second test data in the slave channel according to the test signal, so as to input the serially output first test data and the second test data into the same measurement input channel of the test machine.

2. The crystal grain according to claim 1, characterized in that The first output terminal of the encoding circuit is used to output a first switch control signal of a first level to indicate that the first output channel is a main channel; the test signal includes a delay signal; The die also includes: a first delayed output control circuit and a first switch element; The first switch element is used for not transmitting the delay signal to the first delay output control circuit according to the first switch control signal of the first level, so that the shared output channel outputs the first test data to the test machine first.

3. The crystal grain according to claim 2, characterized in that The encoding circuit includes a first one-time programming memory cell in the die.

4. The crystal grain according to claim 3, characterized in that The first one-time programming memory cell is not programmed, so that the first output terminal of the encoding circuit outputs the first switch control signal of the first level.

5. The crystal grain according to claim 1, characterized in that The second output terminal of the encoding circuit is used to output a second switch control signal of a second level to indicate that the second output channel is a slave channel; the test signal includes a delay signal; The die further comprises: a second delayed output control circuit and a second switch element; The second switch element is used to transmit the delay signal to the second delay output control circuit according to the second switch control signal of the second level, so that the shared output channel delays the second test data by a predetermined clock cycle according to the delay signal and outputs it to the test machine.

6. The crystal grain according to claim 5, characterized in that The encoding circuit includes a second one-time programming memory cell in the die.

7. The crystal grain according to claim 6, characterized in that The second one-time programming memory cell has been programmed so that the second output terminal of the encoding circuit outputs the second switch control signal of the second level.

8. The crystal grain according to claim 7, characterized in that Before or after packaging the die into a finished semiconductor package, a second one-time programming memory cell in the die is burned.

9. A method for testing grains, characterized in that: The die comprises a first output channel, a second output channel and an encoding circuit; the first output channel and the second output channel are coupled as a same shared output channel, the encoding circuit is used to encode the first output channel as a master channel and encode the second output channel as a slave channel; wherein the method comprises: The die receives a test signal from a measurement output channel of a test machine, wherein the test signal includes a delay signal; Outputting the first test data in the main channel to the measurement input channel of the test machine through the shared output channel according to the test signal; After the second test data in the slave channel is delayed for a predetermined clock cycle according to the delay signal, the second test data is output to the measurement input channel through the shared output channel.

10. A method for testing a grain, characterized in that: The die comprises a first output channel, a second output channel and an encoding circuit; the first output channel and the second output channel are coupled as a same shared output channel, the encoding circuit is used to encode the first output channel as a master channel and encode the second output channel as a slave channel; wherein the method comprises: The measurement output channel of the test machine inputs a test signal to the die, wherein the test signal includes a delay signal; The same measurement input channel of the test machine receives first test data and second test data output serially from the shared output channel, wherein the first test data is output from the main channel based on the test signal, and the second test data is output from the slave channel based on the test signal and a delayed signal therein.

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