SOI substrate comprising intermediate isolation layer and preparation method thereof

Abstract

The invention provides an SOI substrate containing an intermediate isolation layer and a preparation method thereof, and the method comprises the steps: carrying out the patterning of a high-resistance material layer, and forming a high-resistance side wall which extends from a first main surface of the high-resistance material layer to a second main surface of the high-resistance material layer, so as to define a plurality of through holes; the through holes are filled, a plurality of columnar supporting structures which are separated from one another are formed, and each columnar supporting structure comprises a center cylinder made of the rich defect state material. After the high-resistance material layer is formed, the through holes penetrating through the high-resistance material layer are formed through the etching process, good filling in the through holes can be obtained in a short time through the thin film deposition mode, the columnar supporting structure is formed, the process time can be obviously shortened, and the manufacturing cost can be reduced; the columnar supporting structure is surrounded by the high-resistance side wall, so that the grain size of recrystallized polycrystalline semiconductor materials contained in the columnar supporting structure and even the central cylinder is limited, and the influence of grain growth on the defect state density in the high-temperature treatment process is inhibited.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to an SOI substrate and a preparation method thereof. Background Art

[0002] Radio Frequency (RF) devices need to maintain high signal transmission efficiency and low signal loss, and the substrate material around the RF devices needs to have good insulation performance. Therefore, a large number of RF devices and systems are made on silicon-on-insulator (SOI) substrates.

[0003] In SOI substrates for RF applications, the substrate layer near the device area needs to be kept in a high-resistance state to avoid large energy loss in the substrate caused by RF signals. However, since the insulating layer of the SOI substrate usually contains a certain amount of positive charge, when the insulating layer contacts the substrate layer, it can attract electrons in the substrate layer and make the attracted electrons enriched at the interface where the substrate layer and the insulating layer contact, forming a better conductive path, resulting in large RF signal loss. In some cases, the electromagnetic field of the high-frequency signal may even penetrate the substrate and cause electrical performance problems such as crosstalk and parasitic capacitance. Figure 1a and Figure 1b Structural schematic diagrams of two typical high-resistivity SOI substrates are provided.

[0004] like Figure 1a As shown, the high resistivity SOI substrate includes a trap rich polysilicon layer (Trap rich layer) 110a inserted between the substrate layer and the insulating layer. The SOI substrate is TR-SOI. The polysilicon layer contains more grain boundary defects. Since the grain boundary defects can block the flow of carriers, the positive charge in the insulating layer will not introduce too much RF signal loss in the polysilicon layer. In addition, the substrate layer is separated from the insulating layer by the polysilicon layer and is not affected by the positive charge in the insulating layer.

[0005] like Figure 1b As shown, the high resistivity SOI substrate includes a porous silicon layer 110b interposed between a substrate layer and an insulating layer. Since the porous silicon layer has a large resistivity, it can also be protected from the influence of positive charges in the insulating layer.

[0006] Nevertheless, the above-mentioned high resistivity SOI substrate has the following disadvantages:

[0007] 1) Low thermal conductivity: such as Figure 1b In the SOI substrate shown, the thermal conductivity of the porous silicon layer is even lower and may even act as an insulator, which is not conducive to the heat dissipation of the device located in the top functional layer.

[0008] 2) Poor high temperature performance: such as Figure 1a For the SOI substrate shown in the figure, when the device operating temperature is high, for example, at 200°C, the high temperature will increase the number of carriers generated by phonon excitation in the trap-rich polysilicon layer. At the same time, with the assistance of phonons, it becomes easier for carriers to cross the grain boundary barrier, ultimately reducing the resistivity of the layer and increasing the loss of the RF signal.

[0009] 3) Intolerant to high temperature processes: e.g. Figure 1a The trap-rich poly layer of the SOI substrate shown in FIG. 1 , when the substrate process temperature is too high, for example, exceeding 1000° C., it will significantly cause the recrystallization of polysilicon, increase the grain size, reduce the grain boundary density, and reduce the resistivity of the trap-rich poly layer, so the upper limit of the process temperature of this SOI substrate is relatively low; Figure 1b The porous silicon layer of the SOI substrate shown has poor high-temperature stability. When the process temperature is high, for example, exceeding 950°C, the porous silicon layer is more likely to agglomerate and combine to form a polycrystalline silicon layer, which reduces the resistivity of the original porous silicon layer and deteriorates the mechanical stability, seriously affecting the performance of the RF device.

[0010] 4) Poor mechanical stability: such as Figure 1b The SOI substrate shown has a porous silicon layer with a porosity generally above 50%, and its mechanical strength is greatly reduced compared to single crystal silicon and polycrystalline silicon. As a result, when the SOI substrate is subjected to certain process stresses and mechanical force impacts, the porous silicon layer is prone to deformation and fracture, which seriously affects the process stability.

[0011] Therefore, there is an urgent need to find a new type of SOI substrate. Summary of the invention

[0012] In view of the shortcomings of the prior art mentioned above, the object of the present invention is to provide an SOI substrate comprising an intermediate isolation layer and a preparation method thereof, so as to solve the problems that the existing SOI substrate has poor mechanical properties, the high temperature resistance process cannot meet the requirements, RF loss and crosstalk in the application of RF devices, and high manufacturing costs.

[0013] To achieve the above object and other related objects, the present invention provides a method for preparing an SOI substrate including an intermediate isolation layer, comprising the following steps:

[0014] Providing a substrate, the substrate comprising a substrate layer and a high-resistance material layer located on the substrate layer, the high-resistance material layer comprising a first main surface and a second main surface opposite to each other;

[0015] Patterning the high-resistance material layer to form high-resistance sidewalls extending from the first main surface to the second main surface of the high-resistance material layer to define a plurality of through holes;

[0016] Filling the through holes to form a plurality of columnar support structures separated from each other, thereby obtaining an intermediate isolation layer including a plurality of the columnar support structures, wherein the columnar support structure includes a central column composed of defect-rich material;

[0017] At least one insulating layer and at least one top functional layer are alternately formed on the columnar support structure.

[0018] Optionally, the step of defining the through hole comprises:

[0019] Forming a hard mask layer on the high-resistance material layer, and patterning the hard mask layer by one or more methods including photolithography, nanoimprinting, electrochemical etching, and self-assembly lithography, wherein the high-resistance material layer comprises one or more of an insulating dielectric material, a wide bandgap semiconductor material, and a passivated porous semiconductor material;

[0020] The high-resistance material layer is anisotropically etched based on the patterned hard mask layer.

[0021] Optionally, the step of forming the columnar support structure comprises:

[0022] forming a shell layer on the inner surface of the through hole;

[0023] filling the through-hole with the defect-rich material and covering the through-hole;

[0024] The defect-rich material comprises one or more polycrystalline semiconductor materials with a grain size not greater than 2 μm, or a mixture of the polycrystalline semiconductor material and the amorphous semiconductor material.

[0025] Optionally, the step of forming the central column comprises:

[0026] Filling the through hole to form a central column, and covering the through hole and the high-resistance sidewall to form a trap-rich material;

[0027] The step of separating the ends of the central column from each other by executing the following steps includes: performing a thinning process from the first main surface of the high-resistance material layer to remove the trap-rich material covering the high-resistance sidewalls and retaining only the trap-rich material located in the through hole; wherein the thinning process includes one or more of wet etching, chemical mechanical polishing, dry etching, and thermal oxidation.

[0028] Optionally, after the step of defining the through hole, the step further includes: using an isotropic etching process to laterally expand the through hole, so as to thin the high-resistance sidewall to define the expanded through hole.

[0029] Optionally, the step of forming the central column comprises:

[0030] Filling and covering the through hole with an amorphous semiconductor material; then,

[0031] The amorphous semiconductor material covering the intermediate isolation layer is removed by a planarization process to expose the top surface of the central column;

[0032] After forming the insulating layer and the top functional layer on the intermediate isolation layer, the amorphous semiconductor material is annealed to transform the amorphous semiconductor material into a defect-rich polycrystalline semiconductor material.

[0033] The present invention also provides a method for preparing an SOI substrate including an intermediate isolation layer, comprising the following steps:

[0034] Providing an initial substrate, the initial substrate comprising a first surface and a second surface disposed opposite to each other;

[0035] Patterning the initial substrate to form spacer sidewalls extending from the first surface of the initial substrate to the interior to define a plurality of through holes;

[0036] Filling the through holes to form a plurality of columnar support structures separated from each other, thereby obtaining an intermediate isolation layer including a plurality of the columnar support structures, wherein the columnar support structure includes a central column composed of defect-rich material;

[0037] Selectively etching the initial substrate to transform the semiconductor material extending from the first surface to the second main surface of the initial substrate into a porous structure, so that the spacer sidewalls are transformed into high-resistance sidewalls, thereby obtaining an intermediate isolation layer including a plurality of the columnar support structures and the high-resistance sidewalls;

[0038] At least one insulating layer and at least one top functional layer are alternately formed on the columnar support structure.

[0039] Optionally, the step of selectively etching the initial substrate comprises:

[0040] Selectively etching the initial substrate by one of an electrochemical etching process and a photoelectrochemical etching process, so that at least the single crystal or polycrystalline semiconductor material between the first surface and the second surface of the initial substrate is transformed into a porous structure to form a porous semiconductor layer;

[0041] The porous semiconductor layer is passivated, wherein the passivation treatment includes oxidation, electrochemical oxidation, nitridation, annealing under hydrogen-containing gas to repair defects, high-pressure water vapor to repair defects, and deposition of a passivation film, and the porous semiconductor layer after passivation treatment has an equivalent resistivity of not less than 1000Ω·cm.

[0042] The present invention also provides an SOI substrate including an intermediate isolation layer, comprising: a substrate layer, an insulating layer and a top functional layer stacked from bottom to top, an intermediate isolation layer is arranged between the substrate layer and the insulating layer, the intermediate isolation layer comprises a first main surface and a second main surface far away from the substrate layer relative to the first main surface, the intermediate isolation layer comprises a high-resistance side wall and a plurality of columnar support structures separated by the high-resistance side wall, at least one insulating layer and at least one top functional layer are arranged on the intermediate isolation layer; wherein each columnar support structure is arranged along the thickness direction of the intermediate isolation layer from the first main surface to the second main surface, and the columnar support structure comprises a central column composed of defect-rich material, which is used to shield positive charges from the insulating layer.

[0043] Optionally, multiple insulating layers and multiple top functional layers are stacked on the intermediate isolation layer.

[0044] Optionally, the defect-rich material includes one or more polycrystalline semiconductor materials with a grain size not greater than 2 μm, or a mixture of the above-mentioned polycrystalline semiconductor materials and amorphous semiconductor materials, and the material of the high-resistance sidewall includes one or more of an insulating dielectric material, a wide bandgap semiconductor material, and a passivated porous semiconductor material.

[0045] Optionally, each columnar support structure has a cross-section of a non-closed shape parallel to the surface of the substrate layer, and the cross-sectional shape of the columnar support structure includes a shape formed by strips crossing at an angle.

[0046] Optionally, a plurality of columnar support structures are discretely arranged on the substrate layer, some of the plurality of columnar support structures each having a radial cross-section parallel to the surface of the substrate layer, the radial cross-section of the columnar support structure comprising at least one slender portion, and the slender portion is arranged to extend toward an adjacent columnar support structure.

[0047] Optionally, the columnar support structure comprises a single shell layer arranged around the central column, and the shell layer is configured as a high-resistance shell layer with a resistivity of not less than 500Ω·cm; or,

[0048] The columnar support structure includes a nested shell layer, wherein the nested shell layer includes a high-resistance shell layer and a semiconductor shell layer, wherein the high-resistance shell layer and the semiconductor shell layer surround the central column and are alternately arranged in a radial direction to have a nested ring-shaped cross section, so as to improve the interface resistance of the nested shell layer;

[0049] The high-resistance shell layer comprises one of an insulating dielectric material and a wide-bandgap semiconductor material, and the semiconductor shell layer comprises the same defect-rich material as the central body.

[0050] The present invention also provides an SOI device, which is prepared based on the above-mentioned SOI substrate including the intermediate isolation layer.

[0051] As described above, the SOI substrate including the intermediate isolation layer and the preparation method thereof provided by the present invention have the following beneficial effects:

[0052] The preparation method of the SOI substrate including the intermediate isolation layer provided by the present invention, after forming the high-resistance material layer, forms a plurality of through holes penetrating the high-resistance material layer by an etching process, and fills the through hole array in the high-resistance material layer by thin film deposition, so that good filling in the through holes can be obtained in a short time to form a columnar support structure, which can significantly shorten the process time, and the preparation method of the present invention can be highly compatible with the existing substrate process and CMOS process, and has the advantages of low manufacturing cost, short manufacturing cycle, high process consistency, etc., and can realize mass production to meet the production needs of the production line; in addition, compared with the method of wrapping the columnar support structure to form a high-resistance filler, the material and resistivity of the obtained high-resistance side wall are better controlled based on the etching of the high-resistance material layer to form the through hole, so that the overall performance of the intermediate isolation layer is more uniform.

[0053] The SOI substrate including an intermediate isolation layer provided by the present invention is obtained by inserting the intermediate isolation layer between the substrate layer and the insulating layer, wherein the intermediate isolation layer includes a plurality of columnar support structures and high-resistance side walls surrounding the columnar support structures, wherein the columnar support structure includes a central column composed of a defect-rich material, and the central columns are separated by the high-resistance side walls, and the positive charges from the insulating layer and the signal interference to the substrate are shielded by the central columns arranged at intervals. At the same time, the columnar support structure includes a central column composed of a trap-rich material, and the columnar support structure is surrounded by the high-resistance side walls, so that the recrystallized grain size of the polycrystalline semiconductor material contained in the columnar support structure and even the central column is limited, and the grain boundary area between the grains in the defect-rich polycrystalline semiconductor material will not be significantly reduced, thereby suppressing the influence of grain growth on the defect state density during high-temperature treatment; by constructing the columnar support structure, the mechanical strength and thermal conductivity of the intermediate isolation layer are significantly improved, and the application requirements of radio frequency devices are better met. BRIEF DESCRIPTION OF THE DRAWINGS

[0054] Figure 1a and Figure 1b Shown are schematic diagrams of the structures of two typical high-resistivity SOI substrates.

[0055] Figure 2 It is a flow chart of a method for preparing an SOI substrate including an intermediate isolation layer according to a first embodiment of the present invention.

[0056] Figure 3a to Figure 3h Schematic diagram of the structure obtained at each stage of the method for preparing an SOI substrate including an intermediate isolation layer according to Embodiment 1 of the present invention.

[0057] Figure 4It is another exemplary structural schematic diagram of the structure obtained after the step of forming a columnar support structure in the preparation process of the SOI substrate including the intermediate isolation layer according to the first embodiment of the present invention.

[0058] Figure 5a and Figure 5b It is a partial structural diagram of the intermediate isolation layer obtained by the method for preparing an SOI substrate including the intermediate isolation layer according to the first embodiment of the present invention; wherein, Figure 5a A top view of the structure shown, Figure 5b is a cross-sectional view of the structure shown.

[0059] Figure 6a and Figure 6b This is a partial structural diagram of an intermediate isolation layer obtained by another example of the method for preparing an SOI substrate including an intermediate isolation layer according to the first embodiment of the present invention; wherein, Figure 6a A top view of the structure shown, Figure 6b is a cross-sectional view of the structure shown.

[0060] Figures 7a to 7d It is a schematic diagram of the structure obtained at each stage of the method for preparing an SOI substrate including an intermediate isolation layer in the second embodiment of the present invention.

[0061] Figure 8 It shows a cross-sectional view of a SOI substrate including an intermediate isolation layer according to a third embodiment of the present invention, including a columnar support structure having a non-closed cross-section.

[0062] Fig. 9 and Fig.10 It is a schematic diagram showing another example of a columnar support structure having a non-closed cross-section in which the SOI substrate including the intermediate isolation layer in the third embodiment of the present invention comprises a columnar support structure.

[0063] Fig.11 and Fig.12 It is a schematic diagram showing the structure obtained after forming the insulating layer and the top functional layer in the method for preparing the SOI substrate structure according to the third embodiment of the present invention.

[0064] Component number description

[0065] 10. Substrate layer

[0066] 130a Trap-rich polysilicon layer

[0067] 130b Porous silicon

[0068] 140 Insulation layer

[0069] 150 Top functional layer

[0070] 20 substrate layer

[0071] 30 Intermediate isolation layer

[0072] 300 High resistance material layer

[0073] 302 Through Hole

[0074] 302e Extended Through Hole

[0075] 310 Column support structure

[0076] 312 Passivation layer

[0077] 304 High resistance side wall

[0078] 3110 Trap-rich materials

[0079] 200 Initial substrate

[0080] 202 Through Hole

[0081] 204 Partition side wall

[0082] 40 Insulation layer

[0083] 50 Top functional layer

[0084] 410 Cavity DETAILED DESCRIPTION

[0085] The following is a description of the implementation of the present invention by means of specific embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0086] Please refer to Figures 1 to Fig.12 . It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings in this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention, so they have no substantial technical significance. Any modification of the structure, change in the proportional relationship, or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the effects and purposes that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle" and "one" quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0087] Embodiment 1

[0088] In order to optimize the RF loss performance, enhance the ability to suppress substrate noise, and improve the mechanical properties and thermal conductivity, the present invention provides a method for preparing an SOI substrate including an intermediate isolation layer, see Figure 2 , including the following steps:

[0089] First, step S100 is performed to provide a substrate, wherein the substrate includes a substrate layer and a high-resistance material layer located on the substrate layer, wherein the high-resistance material layer includes a first main surface and a second main surface opposite to each other.

[0090] Specifically, the substrate layer 20 may be a single crystal semiconductor substrate or a polycrystalline semiconductor substrate, and its material includes silicon, silicon carbide, silicon germanium or other suitable semiconductor materials; the material of the high resistance material layer 300 includes one or more of an insulating dielectric material, a wide bandgap semiconductor material, and a passivated porous semiconductor material. In this embodiment, the substrate layer 20 is selected to be a single crystal silicon substrate.

[0091] Figure 3a and Figure 3h The schematic diagram of the structure obtained at each stage of the preparation method of the SOI substrate including the intermediate isolation layer is shown. Figure 3b As shown, in some embodiments, the method of forming the high-resistance material layer 300 includes but is not limited to: growing a passivation layer by a thermal oxidation process, growing a wide bandgap semiconductor material by an epitaxial process, and growing a combination of grain materials and insulating materials, such as a combination of silicon grains and silicon oxide.

[0092] The high-resistance material layer 300 can be formed based on the semiconductor material layer on the substrate layer. In some embodiments, the method of forming a porous semiconductor material includes, but is not limited to: converting a semiconductor material layer into a porous semiconductor layer by electrochemical corrosion, photoelectrochemical corrosion, or the like, wherein the semiconductor material layer comprises a single crystal or polycrystalline semiconductor material, such as single crystal silicon or polycrystalline silicon. Further, the porous semiconductor layer is passivated by one or more of oxidation, electrochemical oxidation, nitridation, hydrogen-containing gas annealing to repair defects, high-pressure water vapor to repair defects, and deposition of a surface passivation film, wherein the passivated porous semiconductor material has an equivalent resistivity of ≥1000Ω·cm.

[0093] Next, step S200 is performed to pattern the high-resistance material layer to form high-resistance sidewalls extending from the first main surface to the second main surface of the high-resistance material layer to define a plurality of through holes.

[0094] Specifically, the step of defining the through hole 302 includes: forming a hard mask layer on the first main surface of the high-resistance material layer 300, defining a transfer pattern layer on the hard mask layer by one or more methods including photolithography, nanoimprinting, electrochemical etching, and self-assembly lithography; then, etching the hard mask layer based on the transfer pattern layer to form a patterned area corresponding to the transfer pattern layer in the hard mask layer; etching the high-resistance material layer 300 by an anisotropic etching process based on the patterned hard mask layer until the surface of the substrate layer is exposed. After performing the step of forming the through hole, the patterned hard mask layer covering the high-resistance material layer can be removed. Figure 3c The high-resistance sidewall 304 defines a through hole 302, and the through hole 302 has a diameter denoted by d; preferably, the high-resistance material layer is etched using a reactive ion etching process. The geometric shape, size and height of the through hole can be appropriately adjusted as needed and are not particularly limited here.

[0095] Optionally, at step S200, after the step of defining the through hole 302, an isotropic etching process is used to expand the through hole laterally, and the high-resistance sidewall is thinned to define the expanded through hole. Figure 3d As shown, after thinning, the high-resistance sidewall defines an extended through hole 302e, and the extended through hole 302e has a d e The diameter represented by the extended through hole 302e is used to form a columnar support structure. By introducing an isotropic etching process after the step of forming the through hole, the process window of the through hole is widened, allowing the side wall thickness around the through hole to be reduced from several microns to tens of nanometers, for example, from 1μm to less than 50nm, increasing the area ratio of the columnar support structure on the cross section, and providing the ability to adjust the filling of the central column, so that the resistivity of the intermediate isolation layer can be better adjusted.

[0096] At step S200, after forming the plurality of through holes 302 or the extended through holes 302e, the surface of the through holes is passivated; Figure 3e As shown, the high-resistance sidewall 304 is coated to form a passivation layer 312, wherein the passivation treatment includes oxidation, electrochemical oxidation, nitridation, annealing under hydrogen-containing gas to repair defects, high-pressure water vapor to repair defects, and deposition of a passivation layer. The surface roughness after etching is improved by the passivation treatment, especially the porous surface exposed after etching is filled, which effectively reduces the risk of introducing perforation defects in subsequent processes.

[0097] Next, step S300 is performed to fill the through hole to form a plurality of columnar support structures separated from each other, thereby obtaining an intermediate isolation layer including a plurality of the columnar support structures, wherein the columnar support structure includes a central column composed of defect-rich material.

[0098] Specifically, step S300 includes: filling and covering the through hole 302 with the defect-rich material; then, removing the trap-rich material covering the high-resistance sidewall to form a columnar support structure surrounded by the high-resistance sidewall and separated from each other; wherein the columnar support structure includes a central column 3102. Figure 5a to Figure 5b FIG. 1 is a partial structural diagram of an intermediate isolation layer obtained according to a method for preparing an SOI substrate including an intermediate isolation layer. Figure 5b As shown, in one implementation, the through hole is only filled with a central column 3102 composed of trap-rich material.

[0099] Different from the method of forming the central column by etching, by filling the through hole array in the high-resistance material layer, for example, a group of through holes with a radial size of 1 μm and a depth of 10 μm (regular or irregular shape), only ≤500nm of defect-rich material needs to be deposited to make it grow evenly on the hole wall to completely fill the hole. Figure 3c The through hole array shown in the figure, pre-grows a trap-rich material layer, for example, a 10μm thick trap-rich material layer, and then performs an etching process on the trap-rich material layer to form a central column, which greatly increases the time and cost required. In addition, compared with the method of wrapping the columnar support structure to form a high-resistance filler, the high-resistance sidewall is formed by etching the high-resistance material layer, and the material and resistivity of the obtained high-resistance sidewall are better controlled, so that the overall performance of the intermediate isolation layer is more uniform.

[0100] At step S300, the step of forming the central column includes: filling and covering the through hole 302 with the defect-rich material, wherein the defect-rich material includes one or more polycrystalline semiconductor materials with a grain size of no more than 2 μm, or a mixture of the above-mentioned polycrystalline semiconductor materials and amorphous semiconductor materials. In some examples, the polycrystalline semiconductor material is deposited by a low-pressure chemical vapor deposition (LPCVD) process, and the deposited polycrystalline semiconductor material conformally fills the through hole, and the polycrystalline semiconductor material can be, for example, polycrystalline silicon.

[0101] In another implementation, before the step of forming the central column 3102, a shell layer is deposited on the inner surface of the through hole, and the shell layer can be a single shell layer or a nested shell layer. When a single shell layer is formed on the inner surface of the through hole, the shell layer is preferably a high-resistance shell layer; when the columnar support structure includes a nested shell layer, the shell layer is deposited layer by layer on the inner surface of the through hole by thin film deposition. Different from a columnar support structure having only a central column, by setting a single shell layer or multiple nested shell layers, the size of the layer or central column composed of defect-rich materials, especially the growth thickness, is limited, the grain size of the polycrystalline semiconductor material recrystallized during the high-temperature process will be limited, the grain boundary area between the grains will not be significantly reduced, and the defect state density of the intermediate isolation layer will not be significantly reduced. Therefore, after the high-temperature process, its shielding ability is still relatively ideal.

[0102] Further, Figure 6a to Figure 6b This is a partial structural diagram of another example of an intermediate isolation layer obtained according to a method for preparing an SOI substrate including an intermediate isolation layer, wherein the step of forming the nested shell layer includes alternately forming a high-resistance shell layer 3104 and a semiconductor shell layer 3106 on the inner surface of the through hole; wherein the high-resistance shell layer 3104 comprises an insulating dielectric material, and the semiconductor shell layer 3106 comprises a polycrystalline semiconductor material, and the semiconductor shell layer and the high-resistance shell layer are alternately formed by a chemical vapor deposition (CVD) process, a molecular beam epitaxy (MBE) process, or a similar thin film deposition process with good step coverage. Preferably, when the semiconductor shell layer 3106 is made of a polycrystalline semiconductor material having a resistivity lower than that of the high-resistance shell layer, the layered high-resistance material and the polycrystalline semiconductor material are alternately deposited by thin film deposition, which can give the multi-layer nested columnar support structure a very small characteristic size in the cross section, such as a thickness as low as 10 nm, which exceeds the capabilities of conventional photolithography processes. In addition, the high-resistance shell layer is used to separate the trap-rich polycrystalline semiconductor material and introduce a high-resistance interface, thereby avoiding the central column composed of trap-rich material having a large diameter and introducing an additional conductive path.

[0103] Furthermore, if Figure 3f As shown, the through hole is filled to form a central column, and the through hole and the high-resistance sidewall are covered with a trap-rich material 3110. After the step of forming the central column, the ends of the central column are separated from each other by performing the following steps: performing a thinning process on the first main surface of the high-resistance material layer to remove the trap-rich material covering the high-resistance sidewall, and only retaining the trap-rich material located in the through hole, such as Figure 3g As shown, the columnar support structure 310 and the high-resistance spacer 304 surrounding the columnar support structure are exposed; wherein the thinning process includes one or more of wet etching, chemical mechanical polishing, dry etching, and thermal oxidation. If there is a shell layer covering the high-resistance spacer, the shell layer is also removed during the thinning process.

[0104] In a specific embodiment, the trap-rich polycrystalline semiconductor material covering the first main surface of the intermediate isolation layer is converted into an insulating dielectric material by a thermal oxidation process, while the polycrystalline semiconductor material is retained in the through hole, so as to separate the columnar support structures from each other. The insulating dielectric material obtained after thermal oxidation can constitute the insulating layer of the SOI substrate, or the insulating dielectric material obtained can be removed by an etching process.

[0105] In some cases, the step of forming the central column 3102 includes: filling and covering the through hole 302 with an amorphous semiconductor material; then, removing the amorphous semiconductor material covering the intermediate isolation layer through a planarization process to expose the top surface of the central column; after forming the insulating layer and the top functional layer on the intermediate isolation layer in step S400, annealing the amorphous semiconductor material to transform the amorphous semiconductor material into a polycrystalline semiconductor material rich in defects. Due to the advantages of the amorphous material itself being easy to thin and easy to bond with other functional layers, it is conducive to the subsequent planarization process. After bonding, the planarized amorphous material is properly annealed to be transformed into a polycrystalline material rich in defects.

[0106] Next, step S400 is performed to alternately form at least one insulating layer and at least one top functional layer on the middle isolation layer.

[0107] Specifically, after covering the top surface of the intermediate isolation layer with an insulating layer, a top functional layer is formed on the insulating layer, and the material of the insulating layer is selected from one or more combinations of insulating dielectric materials, porous semiconductor materials, nanocrystalline materials, porous insulating dielectric materials, and wide bandgap semiconductor materials with a larger bandgap width; the top functional layer is selected from one or more combinations of semiconductor materials, piezoelectric materials, and conductive materials.

[0108] As an example, the insulating layer 40 is formed by thin film deposition, thin film bonding, thin film transfer, oxidation, or the like.

[0109] As an example, the top functional layer 50 is formed by thin film deposition, thin film bonding, thin film transfer, epitaxial growth or the like.

[0110] Fig. 5 is a schematic diagram of a structure obtained after step S400 of the method for preparing a SOI substrate including an intermediate isolation layer. As shown in Fig. 5, two or more periods of insulating layers 40 and top functional layers 50 are alternately formed on the intermediate isolation layer, and the SOI substrate structure further includes an embedded cavity 410, which can be formed in one of the insulating layer and the top functional layer, or at the interface between the two.

[0111] The substrate, intermediate isolation layer, insulating layer and / or top functional layer obtained in the above steps are subjected to surface treatment according to application requirements. The surface treatment may be performed by one or more of a polishing process, a deposition process, and an annealing process under a specific atmosphere to repair the surface roughness and mechanical strength of the obtained material layer. The above surface treatment step may be performed before the operation of patterning the high-resistance material layer in step S200, after the operation of forming the columnar support structure in step S300, and / or after the operation of forming the insulating layer / top functional layer in step S400.

[0112] In a specific example, the repair process includes annealing the obtained material layer in a hydrogen atmosphere, and the annealing temperature is between 800° C. and 1300° C., for example, 1000° C.

[0113] Embodiment 2

[0114] This embodiment provides a method for preparing an SOI substrate including an intermediate isolation layer, comprising the following steps:

[0115] S100': providing an initial substrate, wherein the initial substrate comprises a first surface and a second surface arranged opposite to each other;

[0116] S200': patterning the initial substrate to form spacer sidewalls extending from the first surface of the initial substrate to the interior to define a plurality of through holes;

[0117] S300': filling the through hole to form a plurality of columnar support structures separated from each other, thereby obtaining an intermediate isolation layer including a plurality of the columnar support structures, wherein the columnar support structure includes a central column composed of a defect-rich material;

[0118] S400': alternately forming at least one insulating layer and at least one top functional layer on the columnar support structure;

[0119] S500': selectively corroding the initial substrate to transform the semiconductor material extending inwardly from the first surface of the initial substrate to the second surface into a porous structure, causing the spacer sidewalls to transform into high-resistance sidewalls, thereby obtaining an intermediate isolation layer including a plurality of the columnar support structures and the high-resistance sidewalls.

[0120] It should be noted that the above sequence does not strictly represent the execution sequence of the SOI substrate including the intermediate isolation layer protected by the present invention, and those skilled in the art may change the sequence of steps according to the actual process.

[0121] See also Figures 7a to 7d , which is a schematic diagram of the structure obtained at different stages of the preparation method of the SOI substrate including the intermediate isolation layer.

[0122] First, in step S100 ′, an initial substrate is provided. The initial substrate includes a first surface and a second surface that are opposite to each other.

[0123] Specifically, the initial substrate 200 may be a semiconductor substrate commonly used in the art, such as a single crystal semiconductor substrate or a polycrystalline semiconductor substrate, and its material includes but is not limited to silicon, silicon carbide, silicon germanium or other suitable semiconductor materials.

[0124] Next, step S200 ′ is performed to pattern the initial substrate to form spacer sidewalls extending from the first surface of the initial substrate to the inside to define a plurality of through holes.

[0125] The step of defining a plurality of through holes in step S200′ of this embodiment can be performed in a manner substantially similar to step S200 in the previous embodiment, which includes: forming a patterned hard mask layer on the first surface of the initial substrate; etching the initial substrate 200 by an anisotropic etching process based on the patterned hard mask layer until the second surface of the initial substrate is exposed to form a spacer sidewall 204, thereby defining a plurality of through holes 202, such as Figure 7b The structure shown.

[0126] Next, step S300 ′ is performed to fill the through hole to form a plurality of columnar support structures separated from each other, thereby obtaining an intermediate isolation layer including a plurality of the columnar support structures, wherein the columnar support structure includes a central column composed of defect-rich material.

[0127] The step of forming the columnar support structure in step S300' of this embodiment can be performed in substantially the same manner as step S300 in the previous embodiment, which includes: filling and covering the through hole with a trap-rich material to form a central column. In some examples, the central column 3102 can be formed through the initial substrate 200.

[0128] In some cases, before the step of forming the central column, a shell layer is formed on the inner surface of the through hole, and the shell layer can be a single shell layer or a nested shell layer. Figure 7b As shown, the step of forming the nested shell layer includes alternately forming a high-resistance shell layer 3104 and a semiconductor shell layer 3106 on the inner surface of the through hole; that is, in addition to the sidewall of the through hole, the high-resistance shell layer 3104 or the semiconductor shell layer 3106 also covers the substrate surface exposed at the bottom of the through hole.

[0129] Furthermore, if Figure 7cAs shown, the through hole is filled to form a central column, and at the same time, the through hole and the high-resistance sidewall are covered with a trap-rich material 3110. After the step of forming the central column, the first surface of the initial substrate can be thinned by one or more methods including but not limited to the following items to remove the trap-rich material covering the high-resistance sidewall, and only retain the trap-rich material located in the through hole, so that the ends of the central column are separated from each other: wet etching, chemical mechanical polishing, dry etching, and thermal oxidation. If there is a shell layer covering the spacer sidewall, the shell layer is also removed during the thinning process to reveal the top surface of the spacer sidewall.

[0130] Next, step S400' is performed to selectively etch the initial substrate to transform the semiconductor material extending inwardly from the first surface of the initial substrate to the second main surface into a porous structure, so that the spacing sidewalls are transformed into high-resistance sidewalls, thereby obtaining an intermediate isolation layer including a plurality of the columnar support structures and the high-resistance sidewalls.

[0131] The step of transforming the semiconductor material between the first surface and the second surface of the initial substrate into a porous structure in step S400 ′ may be performed before the step of forming a plurality of through holes, or after the step of forming the central column.

[0132] In a specific embodiment, the initial substrate is selected as a doped single crystal semiconductor substrate, and the initial substrate is selectively etched by electrochemical etching, photoelectrochemical etching or the like, so that the portion of the initial substrate between the first surface and the second surface is formed into a porous semiconductor layer. Figure 7d As shown, after the step of forming the central column, the initial substrate is selectively etched, and the spacer sidewall 204 is transformed into a high-resistance spacer 304. Since the initial substrate is selected as a doped single crystal semiconductor substrate, and the central column is selected as a low-doped or undoped high-resistance material, the single crystal semiconductor substrate with a high doping degree will be preferentially corroded in the electrochemical and photoelectrochemical etching process, so the spacer sidewall used to separate the central column is selectively etched to form a high-resistance spacer. By adjusting the doping concentration and doping impurity type of the single crystal semiconductor substrate, its corrosion rate in the electrochemical and photoelectrochemical etching process can be adjusted accordingly.

[0133] Further, the porous semiconductor layer is passivated by one or more of oxidation, electrochemical oxidation, nitridation, hydrogen-containing gas annealing to repair defects, high-pressure water vapor to repair defects, and deposition of a surface passivation film, wherein the passivated porous semiconductor layer has an equivalent resistivity of ≥1000Ω·cm.

[0134] Next, step S500 ′ is performed to alternately form at least one insulating layer and at least one top functional layer on the middle isolation layer.

[0135] Step S500 ′ in this embodiment may be performed in substantially the same manner as step S400 in the previous embodiment, and will not be described in detail herein.

[0136] Embodiment 3

[0137] The present application provides an SOI substrate including an intermediate isolation layer. The SOI substrate is preferably prepared by using the method for preparing the SOI substrate including an intermediate isolation layer in the previously described embodiment.

[0138] The SOI substrate structure provided in the present application includes: a substrate layer 20, an insulating layer 40 and a top functional layer 50 stacked from bottom to top, an intermediate isolation layer 30 is arranged between the substrate layer 20 and the insulating layer 40, the intermediate isolation layer 30 includes a high-resistance side wall and a plurality of columnar support structures separated by the high-resistance side wall, and at least one insulating layer and at least one top functional layer are arranged on the intermediate isolation layer; wherein the columnar support structure 310 is filled in the through hole defined by the high-resistance side wall and is arranged in the thickness direction of the intermediate isolation layer from the first main surface to the second main surface, and the columnar support structure 310 includes a central column 3102 composed of defect-rich material, and the defect-rich material can generate relatively rich defect interface charges, thereby shielding the additional electric field generated by the positive charges in the insulating layer.

[0139] An intermediate isolation layer is provided between the substrate layer and the insulating layer, the intermediate isolation layer includes a columnar support structure and a high-resistance side wall surrounding the columnar support structure, the columnar support structure includes a central column composed of defect-rich material, and the high-resistance side wall limits the size of the columnar support structure, so that the grain size of the polycrystalline semiconductor material contained in the columnar support structure that is recrystallized is also limited, that is, the grain boundary area between the grains will not be significantly reduced, and the defect state density of the intermediate isolation layer will not be significantly reduced. Therefore, after a high-temperature process, its shielding ability for the additional electric field generated by the positive charges in the insulating layer is still relatively ideal, and the mechanical properties and thermal conductivity of the intermediate isolation layer can also be improved.

[0140] Specifically, the substrate layer 20 may be a single crystal silicon substrate, and its material includes, for example, silicon, silicon carbide, silicon germanium or other suitable semiconductor materials; the material of the high resistance sidewall 304 includes one or more of an insulating dielectric material, a wide bandgap semiconductor material, and a passivated porous semiconductor material, and the passivated porous semiconductor material is rich in nano-semiconductor grains, insulating dielectric films and pores, and cannot form an effective conductive path. For example, when the high resistance sidewall 304 is selected as a porous semiconductor material, its own mechanical strength is weak and its thermal conductivity is poor. By adding a columnar support structure, the mechanical strength and thermal conductivity of the intermediate isolation layer can be significantly improved, so that it has better process stability.

[0141] The central column is made of a trap-rich material, which includes one or more polycrystalline semiconductor materials with a grain size of no more than 2 μm, or a mixture of the above polycrystalline semiconductor materials and amorphous semiconductor materials, wherein the polycrystalline semiconductor material includes: a single substance, alloy or compound of the IV main group, such as silicon, germanium, Si x Ge 1-x alloy, SiC; or, a semiconductor compound of the III-V main group, such as a binary compound of the III-V main group, a ternary compound of the III-V main group, or a quaternary compound of the III-V main group.

[0142] Preferably, the substrate layer 20 is a high-resistance substrate layer to suppress eddy current loss and capacitance and inductance loss caused by the electromagnetic field of the radio frequency signal penetrating the intermediate isolation layer. In some embodiments, the substrate layer 20 may include a multi-layer functional layer structure. According to the different functional modules desired to be implemented, the substrate layer 20 includes an integrated circuit, a micro-electromechanical system, or a similar integrated system fabricated thereon.

[0143] In one implementation, Figure 5a and Figure 5b As shown, the columnar support structure consists only of a central column 3102 .

[0144] In another implementation, the columnar support structure 310 includes a shell layer between the central column and the high-resistance sidewall, and the interface between the shell layer and the central column has a large interface resistance, wherein the shell layer includes a high-resistance shell layer, a semiconductor shell layer, or a combination thereof. The high-resistance shell layer may have a resistivity of not less than 500Ω·cm, and its material includes one of an insulating dielectric material, a polycrystalline semiconductor material, a single crystal semiconductor material, or a mixture thereof, and the material of the semiconductor shell layer includes one of a polycrystalline semiconductor material and an amorphous semiconductor material. In some embodiments, the shell layer encapsulating the central column is a single shell layer.

[0145] In another embodiment, the columnar support structure includes a nested shell layer surrounding the central column 3102; preferably, the nested shell layer includes a high-resistance shell layer and a semiconductor shell layer, the high-resistance shell layer and the semiconductor shell layer surround the central column and are alternately arranged radially to have a nested ring-shaped cross-section to increase the interface resistance of the nested shell layer, wherein the high-resistance shell layer comprises an insulating dielectric material, and the semiconductor shell layer comprises a polycrystalline semiconductor material, or a mixture of a polycrystalline semiconductor material and an amorphous semiconductor material. Figure 6bAs shown, high-resistance shell layers 3104 and semiconductor shell layers 3106 are alternately arranged radially around the central pillar 3102. By inserting the high-resistance shell layer between the central pillar and the polycrystalline semiconductor shell layer, the size of the layer or central pillar composed of defect-rich material, especially the growth thickness, is limited. The grain size of the polycrystalline semiconductor material that recrystallizes during the high-temperature process will be limited, the grain boundary area between the grains will not be significantly reduced, and the defect state density of the intermediate isolation layer will not be significantly reduced. Therefore, the negative impact of the high-temperature process can be reduced, and the central pillar composed of trap-rich material can be prevented from having a large diameter and introducing additional conductive paths.

[0146] The columnar support structure can be arranged throughout the thickness direction of the intermediate isolation layer, and has a base portion joined to the substrate layer and an end portion extending away from the substrate layer. Fig.11 and Fig.12 As shown, the columnar support structure 310 is disposed on the substrate layer 20 and has a base bonded to the substrate layer.

[0147] The columnar support structure 310 can penetrate the intermediate isolation layer 30 and extend into the substrate layer 20. In a specific embodiment, the high-resistance sidewall 304 is processed based on the first surface of the initial substrate, and the portion below the second surface of the initial substrate constitutes the substrate layer, so that the body of the high-resistance sidewall and the substrate layer have the same or similar material; for example, the high-resistance sidewall 304 can be formed based on electrochemical corrosion or photoelectrochemical corrosion of a portion of the initial substrate, and its material is a porous semiconductor layer with passivation treatment, and the passivated porous semiconductor layer can have an equivalent resistivity of not less than 1000Ω·cm. Of course, the high-resistance sidewall 304 can also be made of a material different from that of the substrate layer.

[0148] The columnar support structures 310 may be vertically disposed on the substrate layer, and adjacent columnar support structures may be disposed separately. Figure 7d The schematic diagram of the SOI substrate including a columnar support structure having a closed cross-section is shown. Figure 7d As shown, the columnar support structure has a closed cross-section parallel to the surface of the substrate layer, such as a circular or annular cross-section. The "closed shape" mentioned herein may mean that the outer periphery of the cross-section of the columnar support structure or the central column may be circular, elliptical, oblong, annular or any closed polygon, closed shape or nearly closed shape.

[0149] In another embodiment, Figure 8Shown is a schematic diagram of a SOI substrate including a columnar support structure with a non-closed cross-sectional shape. The columnar support structure may have a non-closed cross-section parallel to the surface of the substrate layer. Eddy currents in the form of circular rings are not easily generated inside such structures, thereby further suppressing the loss of radio frequency signals. Preferably, a plurality of columnar support structures are separately disposed on the substrate layer. The columnar support structure and its central column each have a radial cross-section parallel to the surface of the substrate layer. As Figure 8 shown, the columnar support structure 310 has a radial cross-section. Correspondingly, the central column 3102 includes an elongated portion extending towards an adjacent central column. The resulting geometric shape of the columnar support structure may have a relatively high surface-to-volume ratio. Herein, the "surface-to-volume ratio" refers to the ratio of the perimeter of the outer contour of the columnar support structure to its area. Such columnar support structures have strong anti-deformation capabilities and good process stability, which helps to improve the mechanical stability of the columnar structure.

[0150] In another embodiment, the columnar support structure includes a plurality of bar-shaped sections intersecting at an angle, for example, an angle between 60° and 90°. The columnar support structures are nested with each other by their bar-shaped sections. For example, the columnar support structure includes a plurality of bar-shaped sections intersecting perpendicularly, forming structures such as "十", "工", "王", "丰" or other extendable structures that allow adjacent central columns to nest with each other, thereby enhancing the anti-deformation ability of the columnar structure. Fig. 9 and Fig.10 Shown is a schematic diagram of another example of a SOI substrate including a columnar support structure with a non-closed cross-sectional shape. As Fig. 9 and Fig.10 shown, a plurality of columnar support structures 310 are disposed on the substrate layer 20. Each columnar support structure 310 has a "王" - shaped cross-section parallel to the surface of the substrate layer. The cross-sectional shape of the columnar support structure 310 includes an elongated portion, and the elongated portion is embedded between the elongated portions of the surrounding central columns. In some cases, there are two or more types of columnar support structures 310a and 310b with different cross-sectional shapes on the substrate layer 20. As Fig. 9 shown, some of the columnar support structures 310b on the substrate layer 20 have a "王" - shaped cross-sectional shape and its deformed combinations.

[0151] The material of the insulating layer 40 is selected from one or more combinations of insulating dielectric materials, porous semiconductor materials, nanocrystal materials, porous insulating dielectric materials, and wide bandgap semiconductor materials with a relatively large bandgap; the top functional layer 50 is selected from one or more combinations of semiconductor materials, piezoelectric materials, and conductive materials.

[0152] At least one insulating layer and at least one top functional layer are disposed on the second major surface of the intermediate isolation layer. Return to Fig.11A plurality of insulating layers and a plurality of top functional layers are stacked on the second main surface of the middle isolation layer. The number of insulating layers and top functional layers can be configured according to the monolithic integration of different functional modules to be realized, and some of the plurality of insulating layers / top functional layers can be adjacent to each other, without being limited to the insulating layers and top functional layers shown in the figure being alternately stacked on each other.

[0153] Return to see Fig.12 The SOI substrate structure further includes a cavity 410, which is located at the interface of one or both of the insulating layer 40 and the top functional layer 50, and the cavity 410 can be configured as a vacuum cavity or a cavity filled with air.

[0154] The present invention also provides an SOI device, which is prepared based on the aforementioned SOI substrate structure. For example, the SOI substrate structure can be configured to manufacture an integrated structure of a fully depleted silicon-on-insulator device (FDSOI) and a radio frequency SOI (RFSOI) device. The above SOI substrate structure can be used to improve the isolation of the substrate layer and reduce the loss and crosstalk of the radio frequency signal.

[0155] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing an SOI substrate comprising an intermediate isolation layer, characterized in that: The following steps are involved: Providing a substrate, the substrate comprising a substrate layer and a high-resistance material layer located on the substrate layer, the high-resistance material layer comprising a first main surface and a second main surface opposite to each other; Patterning the high-resistance material layer to form high-resistance sidewalls extending from the first main surface to the second main surface of the high-resistance material layer to define a plurality of through holes; Filling the through holes to form a plurality of columnar support structures separated from each other, thereby obtaining an intermediate isolation layer including a plurality of the columnar support structures, wherein the columnar support structure includes a central column composed of defect-rich material; At least one insulating layer and at least one top functional layer are alternately formed on the columnar support structure.

2. The preparation method according to claim 1, characterized in that: The step of defining the through hole comprises: Forming a hard mask layer on the high-resistance material layer, and patterning the hard mask layer by one or more methods selected from photolithography, nanoimprinting, electrochemical etching, and self-assembly lithography, wherein the high-resistance material layer comprises one or more selected from insulating dielectric materials, wide bandgap semiconductor materials, and passivated porous semiconductor materials; The high-resistance material layer is anisotropically etched based on the patterned hard mask layer.

3. The preparation method according to claim 1, characterized in that: The steps of forming the columnar support structure include: Depositing a shell layer on the inner surface of the through hole; Filling and covering the through hole with the defect-rich material to form a central column; The defect-rich material comprises one or more polycrystalline semiconductor materials with a grain size not greater than 2 μm, or a mixture of the polycrystalline semiconductor material and the amorphous semiconductor material.

4. The preparation method according to claim 3, characterized in that: The steps of forming the central column include: Filling the through hole to form a central column, and covering the through hole and the high-resistance sidewall to form a trap-rich material; The step of separating the ends of the central column from each other by executing the following steps includes: performing a thinning process from the first main surface of the high-resistance material layer to remove the trap-rich material covering the high-resistance sidewalls and retaining only the trap-rich material located in the through hole; wherein the thinning process includes one or more of wet etching, chemical mechanical polishing, dry etching, and thermal oxidation.

5. The preparation method according to claim 1 or 3, characterized in that: After the step of defining the through hole, the method includes: using an isotropic etching process to laterally expand the through hole, so as to thin the high-resistance sidewall to define the expanded through hole.

6. The preparation method according to claim 1, characterized in that: The steps of forming the central column include: Filling and covering the through hole with an amorphous semiconductor material; then, The amorphous semiconductor material covering the intermediate isolation layer is removed by a planarization process to expose the top surface of the central column; The amorphous semiconductor material is annealed to transform the amorphous semiconductor material into a defect-rich polycrystalline semiconductor material.

7. A method for preparing a SOI substrate comprising an intermediate isolation layer, characterized in that: The following steps are involved: Providing an initial substrate, the initial substrate comprising a first surface and a second surface disposed opposite to each other; Patterning the initial substrate to form spacer sidewalls extending from the first surface of the initial substrate to the interior to define a plurality of through holes; Filling the through holes to form a plurality of columnar support structures separated from each other, thereby obtaining an intermediate isolation layer including a plurality of the columnar support structures, wherein the columnar support structure includes a central column composed of defect-rich material; Selectively etching the initial substrate to transform the semiconductor material extending from the first surface to the second main surface of the initial substrate into a porous structure, so that the spacer sidewalls are transformed into high-resistance sidewalls, thereby obtaining an intermediate isolation layer including a plurality of the columnar support structures and the high-resistance sidewalls; At least one insulating layer and at least one top functional layer are alternately formed on the columnar support structure.

8. The preparation method according to claim 7, characterized in that: The step of selectively etching the initial substrate comprises: Selectively etching the initial substrate by one of an electrochemical etching process and a photoelectrochemical etching process, so that at least the single crystal or polycrystalline semiconductor material between the first surface and the second surface of the initial substrate is transformed into a porous structure to form a porous semiconductor layer; The porous semiconductor layer is passivated, wherein the passivation treatment includes oxidation, electrochemical oxidation, nitridation, annealing under hydrogen-containing gas to repair defects, high-pressure water vapor to repair defects, and deposition of a passivation film, and the porous semiconductor layer after passivation treatment has an equivalent resistivity of not less than 1000Ω·cm.

9. An SOI substrate comprising an intermediate isolation layer, characterized in that: It includes a substrate layer, an insulating layer and a top functional layer stacked from bottom to top, an intermediate isolation layer is arranged between the substrate layer and the insulating layer, the intermediate isolation layer includes a first main surface and a second main surface far away from the substrate layer relative to the first main surface, the intermediate isolation layer includes a plurality of columnar support structures and high-resistance side walls surrounding the columnar support structures, at least one insulating layer and at least one top functional layer are arranged on the intermediate isolation layer; wherein the columnar support structure is arranged along the first main surface to the second main surface of the intermediate isolation layer through the thickness direction, and includes a central column composed of defect-rich material.

10. The SOI substrate according to claim 9, characterized in that: Multiple insulating layers and multiple top functional layers are stacked on the middle isolation layer.

11. The SOI substrate according to claim 9, characterized in that: The defect-rich material includes one or more polycrystalline semiconductor materials with a grain size not greater than 2 μm, or a mixture of the above-mentioned polycrystalline semiconductor materials and amorphous semiconductor materials. The material of the high-resistance sidewall includes one or more of an insulating dielectric material, a wide bandgap semiconductor material, and a passivated porous semiconductor material.

12. The SOI substrate according to claim 9, characterized in that: Each columnar support structure has a cross section of a non-closed shape parallel to the surface of the substrate layer, and the cross-sectional shape of the columnar support structure includes a shape formed by strips crossing at an angle.

13. The SOI substrate according to claim 9, characterized in that: A plurality of columnar support structures are discretely arranged on the substrate layer, some of the plurality of columnar support structures each have a radial cross-section parallel to the surface of the substrate layer, and the radial cross-section of the columnar support structure includes at least one slender portion, and the slender portion is arranged to extend toward an adjacent columnar support structure.

14. The SOI substrate according to claim 9, characterized in that: The columnar support structure comprises a single shell layer arranged around the central column, wherein the shell layer is arranged as a high-resistance shell layer with a resistivity of not less than 500Ω·cm; or The columnar support structure includes a nested shell layer, wherein the nested shell layer includes a high-resistance shell layer and a semiconductor shell layer, wherein the high-resistance shell layer and the semiconductor shell layer surround the central column and are alternately arranged in a radial direction to have a nested ring-shaped cross section, so as to improve the interface resistance of the nested shell layer; The high-resistance shell layer comprises one of an insulating dielectric material and a wide-bandgap semiconductor material, and the semiconductor shell layer comprises the same defect-rich material as the central body.

15. An SOI device, characterized in that: The SOI device is prepared based on the SOI substrate comprising an intermediate isolation layer as claimed in any one of claims 9 to 14.

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