Packaging structure with chips pasted on two sides and inductors pasted on back and corresponding packaging method

Abstract

The invention discloses a packaging structure with chips pasted on two sides and inductors pasted on the back, which uses a double-layer substrate to package the chips and the inductors, is low in packaging cost and is reliably applied to packaging of power supply chips. The display panel includes: a first substrate; a second substrate; an upper layer chipset; a lower layer chip group; and an inductor; the first substrate is a double-face packaging substrate, a first packaging face of the first substrate is welded to the upper surface of the second substrate through a supporting solder ball on the lower portion, a first space is formed by the space between the lower surface of the first substrate and the upper surface of the second substrate, the space of the upper surface of the first substrate is a second space, and the second space is a third space. At least one chip and corresponding components are positioned and welded on the upper surface of the second substrate; the invention also provides a corresponding packaging method of the packaging structure.

Description

Technical Field

[0001] The present invention relates to the technical field of chip packaging, in particular to a packaging structure with a double-sided chip and a back-mounted inductor. The present invention also provides a packaging method for the packaging structure. Background Art

[0002] Chip packaging structures are becoming more and more complex, and the number of chips in a single package structure is also increasing. Figure 1 It is a normal FCBGA packaging structure, and the chip is a WLCSP integrated packaging structure. The chip is integrated on the same chip using packaging processes such as RDL. However, the current processing cost of this chip integration process is high, and a heat sink is required to dissipate heat for the chip. This packaging structure is applicable to computing chips such as GPU / CPU, but cannot be used in power processing packaging structures, because the structure cannot optimize the spatial position of the inductor. For this reason, it is urgently necessary to develop a packaging structure that can be used for power processing packaging with an inductor. Summary of the invention

[0003] In view of the above problems, the present invention provides a packaging structure with a double-sided chip and a back-mounted inductor, which uses a double-layer substrate to package the chip and the inductor, has a low packaging cost, and can be reliably applied to the packaging of power chips.

[0004] A packaging structure of a double-sided chip and an inductor back-mounted package, characterized in that it comprises:

[0005] a first substrate;

[0006] a second substrate;

[0007] Upper chipset;

[0008] The underlying chipset;

[0009] and inductance;

[0010] The first substrate is a double-sided packaging substrate, the first packaging surface of the first substrate is welded to the upper surface of the second substrate through the supporting solder balls at the bottom, the space between the bottom surface of the first substrate and the top surface of the second substrate forms a first space, the top surface space of the first substrate is a second space, at least one chip and corresponding components are positioned and welded on the top surface of the second substrate, the first space is filled with high thermal conductivity plastic packaging material, a flip-chip upper chip group is arranged on the top surface of the first substrate, the upper chip group includes at least one upper chip, the upper chip group is laid flat, the inductor is arranged at the upper portion corresponding to the upper chip group, the outer edge pins of the inductor are welded to the corresponding solder joints of the upper layer of the first substrate, the inductor covers the entire surface area of ​​the upper chip group, and the contact area between the lower surface of the inductor and the upper chip group is filled with thermal conductive silver glue.

[0011] It is further characterized by:

[0012] The upper chip group includes only one upper chip, the periphery of the upper surface of the upper chip is coated with thermosetting glue, the central area of ​​the upper surface of the upper chip is coated with the heat conductive silver glue, and the lower surface of the inductor is attached with the thermosetting glue and the heat dissipation silver glue, which ensures that the position of the inductor is stable and reliable, and ensures that the upper chip can reliably dissipate heat through the inductor;

[0013] The lower chip group includes a first lower chip group and a second lower chip group, the first lower chip group is flip-chip soldered on the upper surface of the second substrate, the second lower chip group is flip-chip soldered on the lower surface of the first substrate, the number of the first lower chip group is not less than 1, and the number of the second lower chip group is not less than 1;

[0014] The lower surface of the second substrate is also provided with a lower convex solder ball, which is used to connect the entire packaging structure with an external mechanism;

[0015] After flip-chip welding, the chips in the first lower chip group, the chips in the second lower chip group, and the chips in the upper chip group are all filled with glue between the chips and the corresponding substrates to ensure stable and reliable welding;

[0016] The height of the first space formed by the first substrate and the second substrate is greater than the stacking height of the chips in the single first lower chip group and the chips in the single second lower chip group, ensuring reliable packaging.

[0017] A packaging method for a double-sided chip and inductor back-mounted packaging structure, characterized in that it comprises the following steps:

[0018] S1, performing flip-chip mounting, SMT, and bottom filling on the first lower chip on the second substrate;

[0019] S2, flip-chip die placement, SMT, bottom filling and ball planting are performed on the first substrate, and then cut into single products;

[0020] S3, the single product obtained in step S2 is flip-chip soldered to the upper surface of the second substrate;

[0021] S4, injecting plastic sealing glue into the first space in the height direction of the first substrate and the second substrate;

[0022] S5, performing SMT packaging on the first substrate, flipping the upper chip, and soldering the chip to the bottom;

[0023] S6. Apply heat-conductive silver glue and thermosetting glue on the upper surface of the upper chip, attach the inductor, and weld the pins of the inductor to the corresponding contacts on the upper exposed surface of the first substrate.

[0024] It is further characterized by:

[0025] In step S6, after the inductor is connected, it is heated in an oven once and then baked at 200°C for 30-60 minutes to completely cure the thermally conductive silver glue;

[0026] The method further comprises step S7, after step S6, planting solder balls on the back side of the second substrate to connect the entire packaging structure with an external mechanism.

[0027] After adopting the above technical scheme, a highly integrated packaging structure is realized. The height direction of the structural chip is divided into three layers and embedded in the packaging process. The two substrates are stacked with high thermal conductivity plastic packaging material and solder balls. The first substrate continues to secondary package the external components (including the upper chip) on the back of the substrate. After that, the inductor is stacked on the upper chip. It does not need to use advanced WLCSP packaging, but can be achieved in the conventional packaging process. The first space of the first substrate and the second substrate assembly is used to encapsulate the chip and components with high thermal conductivity plastic packaging material. The space design is highly utilized to meet the packaging needs of power supply devices to optimize the spatial structure of the inductor for packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 It is a FCBGA packaging structure of the prior art;

[0029] Figure 2 A schematic diagram of a packaging structure of a specific embodiment of the present invention;

[0030] Figure 3 is a flow chart of a packaging method according to a specific embodiment of the present invention;

[0031] The names corresponding to the serial numbers in the figure are as follows:

[0032] A first substrate 10, supporting solder balls 11, a second substrate 20, solder balls 21, an inductor 30, a pin 31, an upper chip 40, thermosetting glue 41, thermally conductive silver glue 42, a first lower chip 50, a second lower chip 60, a first component 70, a high thermal conductivity plastic packaging material 80, a filling glue 90, and a second component 100. DETAILED DESCRIPTION

[0033] A packaging structure with double-sided chip and inductor back-mounted, see Figure 2 , which includes a first substrate 10, a second substrate 20, an upper chip set, a lower chip set, and an inductor 30;

[0034] In a specific embodiment, the upper chip set includes only one upper chip 40 , and the lower chip set includes a first lower chip 50 and a second lower chip 60 .

[0035] In a specific implementation, the first substrate 10 is a double-sided packaging substrate, the first packaging surface of the first substrate 10 is welded to the upper surface of the second substrate 20 through the supporting solder ball 11 at the bottom, the space between the lower surface of the first substrate 10 and the upper surface of the second substrate 20 forms a first space, the upper surface space of the first substrate 10 is the second space, the upper surface of the second substrate 20 is positioned and welded with the first lower chip 50 and the corresponding first component 70, the first space is filled with a high thermal conductivity plastic sealing material 80, the first packaging surface of the first substrate is welded with the second lower chip 60, the upper surface of the first substrate 10 A flip-chip upper chip 40 is arranged on the surface, and an inductor 30 is arranged on the upper part corresponding to the upper chip 40. The outer edge pins 31 of the inductor 30 are welded to the corresponding solder joints on the upper layer of the first substrate 10. The inductor 30 covers the entire surface area of ​​the upper chip 40. The outer periphery of the upper surface of the upper chip 40 is coated with thermosetting glue 41, and the central area of ​​the upper surface of the upper chip 40 is coated with thermal conductive silver glue 42. The lower surface of the inductor 30 is adhered to the thermosetting glue 41 and the heat dissipation silver glue 42, which ensures that the position of the inductor 30 is stable and reliable, and ensures that the upper chip 40 can reliably dissipate heat through the inductor 30.

[0036] In a specific implementation, the lower surface of the second substrate 20 is further provided with a lower convex solder ball 21, which is used to connect the entire packaging structure with an external mechanism;

[0037] After flip-chip welding, the first lower chip 50, the second lower chip 60, and the upper chip 40 are all provided with filling glue 90 between the corresponding substrates to ensure stable and reliable welding;

[0038] The height of the first space formed by the first substrate 10 and the second substrate 20 is greater than the stacking height of the first lower chip 50 and the second lower chip 60, ensuring reliable packaging.

[0039] A second component 100 is arranged on the outer periphery of the second packaging surface of the first substrate 10 corresponding to the inductor 30 . The second component 100 is a component arranged corresponding to an actual function.

[0040] For the packaging method of the packaging structure corresponding to the specific embodiment, see Figure 2-Figure 3 , which comprises the following steps:

[0041] S1, performing flip-chip mounting, SMT, and bottom filling on the second substrate 20, so that the first lower chip 50 is welded and connected to the second substrate 20, and glue 90 is filled, and at the same time, the first component 70 is welded to the second substrate 20;

[0042] S2, performing flip-chip chip mounting, SMT, bottom filling and ball planting on the first packaging surface of the first substrate 10, and then cutting into single products, so that the second lower layer chip 60 is welded and connected to the first packaging surface of the first substrate 10, and filled with filling glue 90;

[0043] S3, the single product obtained in step S2 is flip-chip soldered to the upper surface of the second substrate 20;

[0044] S4, injecting a high thermal conductivity plastic sealing material 80 into a first space in a height direction of the first substrate 10 and the second substrate 20;

[0045] S5, performing SMT, flip-chip mounting, and bottom filling on the upper surface of the first substrate 10, so that the upper chip 40 is welded and connected to the second packaging surface of the first substrate 10, and is filled with filling glue 90, and at the same time, the second component 100 is welded to the first substrate 10, and a gap is left between the second component 100 and the upper chip 40;

[0046] S6. Apply heat-conducting silver glue 42 and thermosetting glue 41 on the upper surface of the upper chip 40, and attach the inductor 30. Meanwhile, solder the pins 31 of the inductor 30 to the corresponding contacts on the upper exposed surface of the first substrate 10. After the inductor 30 is connected, it is heated in an oven once, and then baked at 200° C. for 30 min-60 min to completely cure the heat-conducting silver glue 42.

[0047] S7, implanting solder balls 21 on the back side of the second substrate 20, so as to connect the entire packaging structure with an external mechanism.

[0048] Step S4, encapsulation uses an open mold encapsulation structure to obtain the corresponding shape of the high thermal conductivity plastic encapsulation material 80 in the first space. It should be noted that the release film used for the high thermal conductivity plastic encapsulation material 80 is a base film and an adhesive. The adhesive is an important factor in compatibility with the overall flatness. In specific implementation, the supporting solder ball 11 is 0.76μm, and the solder ball itself will collapse during welding. Therefore, the thickness of all adhesives must be greater than 75um to accommodate the problem of inconsistent substrate height coplanarity.

[0049] Its working principle is as follows: it realizes a highly integrated packaging structure, and the structural chip is embedded in three layers in the height direction of the packaging process. The two substrates are stacked with high thermal conductivity plastic packaging materials and solder balls. The first substrate continues to encapsulate external components (including upper chips) on the back of the substrate for a second time, and then the inductor is stacked on the upper chip. It does not require the use of advanced WLCSP packaging, but can be achieved in the conventional packaging process. The first space of the first substrate and the second substrate assembly is used to encapsulate the chip and components with high thermal conductivity plastic packaging materials. The highly utilized space design meets the packaging needs of power supply devices to optimize the spatial structure of the inductor for packaging.

[0050] It will be apparent to those skilled in the art that the invention is not limited to the details of the exemplary embodiments described above and that the invention can be implemented in other specific forms without departing from the spirit or essential features of the invention. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the invention is defined by the appended claims rather than the foregoing description, and it is intended that all variations falling within the meaning and scope of the equivalent elements of the claims be included in the invention. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

[0051] In addition, it should be understood that although the present specification is described according to implementation modes, not every implementation mode contains only one independent technical solution. This description of the specification is only for the sake of clarity. Those skilled in the art should regard the specification as a whole. The technical solutions in each embodiment may also be appropriately combined to form other implementation modes that can be understood by those skilled in the art.

Claims

1. A packaging structure with a double-sided chip and an inductor back-mounted, characterized in that: It includes: a first substrate; a second substrate; Upper chipset; The underlying chipset; and inductance; The first substrate is a double-sided packaging substrate, the first packaging surface of the first substrate is welded to the upper surface of the second substrate through the supporting solder balls at the bottom, the space between the bottom surface of the first substrate and the top surface of the second substrate forms a first space, the top surface space of the first substrate is a second space, at least one chip and corresponding components are positioned and welded on the top surface of the second substrate, the first space is filled with high thermal conductivity plastic packaging material, a flip-chip upper chip group is arranged on the top surface of the first substrate, the upper chip group includes at least one upper chip, the upper chip group is laid flat, the inductor is arranged at the upper portion corresponding to the upper chip group, the outer edge pins of the inductor are welded to the corresponding solder joints of the upper layer of the first substrate, the inductor covers the entire surface area of ​​the upper chip group, and the contact area between the lower surface of the inductor and the upper chip group is filled with thermal conductive silver glue.

2. The packaging structure of a double-sided chip and an inductor back-mounted package according to claim 1, characterized in that: The upper chip group includes only one upper chip, the periphery of the upper surface of the upper chip is coated with thermosetting glue, the central area of ​​the upper surface of the upper chip is coated with the thermal conductive silver glue, and the lower surface of the inductor is attached to the thermosetting glue and the heat dissipation silver glue.

3. The packaging structure of a double-sided chip and an inductor back-mounted package according to claim 1, characterized in that: The lower chip group includes a first lower chip group and a second lower chip group. The first lower chip group is flip-chip soldered on the upper surface of the second substrate, and the second lower chip group is flip-chip soldered on the lower surface of the first substrate. The number of the first lower chips group is not less than 1, and the number of the second lower chips group is not less than 1.

4. The packaging structure of a double-sided chip and an inductor back-mounted package according to claim 1, characterized in that: The lower surface of the second substrate is also provided with lower convex solder balls.

5. The packaging structure of a double-sided chip and an inductor back-mounted package according to claim 3, characterized in that: After flip-chip welding, the chips in the first lower chip group, the chips in the second lower chip group, and the chips in the upper chip group are all provided with filling glue between the chips and the corresponding substrates.

6. The packaging structure of a double-sided chip and an inductor back-mounted package according to claim 3, characterized in that: The height of the first space formed by the first substrate and the second substrate is greater than the stacking height of the chips in the single first lower chip group and the chips in the single second lower chip group.

7. A packaging method for a double-sided chip and inductor back-mounted packaging structure as claimed in any one of claims 1 to 6, characterized in that: It includes the following steps: S1, performing flip-chip mounting, SMT, and bottom filling on the first lower chip on the second substrate; S2, flip-chip die placement, SMT, bottom filling and ball planting are performed on the first substrate, and then cut into single products; S3, the single product obtained in step S2 is flip-chip soldered to the upper surface of the second substrate; S4, injecting plastic sealing glue into the first space in the height direction of the first substrate and the second substrate; S5, performing SMT packaging on the first substrate, flipping the upper chip, and soldering the chip to the bottom; S6. Apply heat-conductive silver glue and thermosetting glue on the upper surface of the upper chip, attach the inductor, and weld the pins of the inductor to the corresponding contacts on the upper exposed surface of the first substrate.

8. The packaging method of a double-sided chip and inductor back-mounted packaging structure according to claim 7, characterized in that: In step S6, after the inductor is connected and heated once, it is necessary to bake at 200° C. for 30 min-60 min to completely cure the thermally conductive silver glue.

9. The packaging method of a double-sided chip and inductor back-mounted packaging structure according to claim 7, characterized in that: The method further comprises step S7, after step S6, planting solder balls on the back side of the second substrate to connect the entire packaging structure with an external mechanism.

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