Incremental Sigma-Delta analog-to-digital converter

Abstract

The invention provides an incremental Sigma-Delta analog-to-digital converter, which comprises N groups of accumulative weight modules, each group of accumulative weight module comprises a comparator, the positive input end of the comparator is connected with a serial number of an element to be subjected to analog-to-digital conversion, the output end of the comparator is connected with a DAC (Digital-to-Analog Converter) module, the output end of the comparator outputs an enable signal, and the enable signal is used for opening or closing the element; the enable end of the register is connected with the output end of the comparator; one input end of the summator receives the code word weight, the other input end of the summator is connected with the output end of the register, the output end of the summator is connected with the input end of the register, the registers output accumulated weights, and the N registers output N accumulated weights; and the sequencing module is used for sequencing the N accumulated weights output by the output ends of the N registers and inputting the sequenced code word weights into the negative input end of the comparator.

Description

Technical Field

[0001] The invention relates to the technical field of analog integrated circuit design, and in particular to an incremental Sigma-Delta analog-to-digital converter. Background Art

[0002] Incremental Sigma-Delta analog-to-digital converters (ADCs) can achieve high-precision conversion through noise shaping and oversampling techniques. In theory, multi-bit quantized incremental Sigma-Delta ADCs have more advantages in high-precision conversion, but in actual production, multi-bit quantizers will have component values ​​that do not match the set values ​​under the influence of analog layout, process and other conditions. The existence of component mismatch errors deteriorates the noise performance and harmonic performance of multi-bit quantized incremental Sigma-Delta ADCs, limiting the improvement of ADC accuracy. There are two methods to solve the component mismatch problem: analog correction method and digital correction method. Analog correction method usually transforms the original analog circuit, making the ADC complicated, while digital correction method does not affect the design of analog circuit and is easy to transplant to ADCs of various structures. Digital correction method can be further divided into foreground correction method and background correction method. Foreground correction method refers to the use of digital circuits to compensate for component mismatch errors a priori before the ADC is normally converted; background correction method refers to the use of digital circuits to reduce or even eliminate the impact of component mismatch errors when the ADC is normally converted. The foreground correction method cannot achieve real-time correction, which brings difficulties to the long-term use of the ADC chip, and the a priori compensation for component mismatch errors usually requires a lot of time and labor costs.

[0003] In the prior art, digital background correction methods usually use dynamic element matching (DEM) circuits to reduce or even eliminate the impact of element mismatch errors. Among various DEM circuits, data weighted averaging (DWA) circuits are widely used in Sigma-Delta ADCs of various structures due to their simple structure, low power consumption and obvious effect.

[0004] However, the prior art has the following problems: the output codeword sequences of high-order (second order and above) incremental Sigma-Delta analog-to-digital converters have different weights. For example, the first sampling output codeword weight of the second-order incremental Sigma-Delta analog-to-digital converter is the highest, and as the number of samplings increases, the weight of the output codeword decreases linearly, and the weight of the output codeword of the last sampling is the lowest. The data weight averaging circuit is designed based on the fact that the output codeword will not change with the increase in the number of samplings, and is weak in suppressing the mismatch noise of the high-order incremental Sigma-Delta modulator, which limits the accuracy of the incremental Sigma-Delta analog-to-digital converter. Summary of the invention

[0005] The object of the present invention is to provide an incremental Sigma-Delta analog-to-digital converter, which can change the weight of the output codeword as the number of sampling times increases, improve the ability to suppress mismatch noise, and improve the accuracy of the incremental Sigma-Delta analog-to-digital converter.

[0006] In order to achieve the above object, the present invention provides an incremental Sigma-Delta analog-to-digital converter for performing analog-to-digital conversion on N elements included in a DAC module, comprising:

[0007] N groups of cumulative weight modules, each group of the cumulative weight modules includes: a comparator, the positive input end of the comparator receives the serial number of the element to be converted into analog to digital, the output end of the comparator is connected to the DAC module, the output end of the comparator outputs an enable signal, and the enable signal is used to turn on or off the element; a register, the enable end of the register is connected to the output end of the comparator; an adder, one input end of the adder receives the codeword weight, the other input end is connected to the output end of the register, the output end of the adder is connected to the input end of the register, the register outputs the cumulative weight, and N registers output N cumulative weights;

[0008] A sorting module, used for sorting the N accumulated weights outputted from the output ends of the N registers, and inputting the sorted codeword weights into the negative input end of the comparator; wherein the sorting module comprises X Y-port input sorters, X Y-port input adders and an X-port input sorter, the N accumulated weights are sequentially connected to the input ends of the X Y-port input sorters and the input ends of the Y-port input adders, the output ends of the X Y-port input sorters respectively output a first group of sorted accumulated weights Order_M[1] to Order_M[N], the output ends of the X Y-port input adders are sequentially connected to the input end of the X-port input sorter, and the output end of the X-port input sorter outputs a second group of sorted accumulated weights Order_L[1] to Order_L[X];

[0009] The sorted cumulative weights output by the sorting module are as follows:

[0010] Wherein, N, X and Y are all integers greater than or equal to 1, and X×Y=N, and n is any integer between 1 and N.

[0011] Optionally, in the incremental Sigma-Delta analog-to-digital converter, the value of the codeword weight starts from 250 and gradually decreases by 1 in steps of 1 until it reaches 1.

[0012] Optionally, in the incremental Sigma-Delta analog-to-digital converter, the enable signal is 1 or 0, and when it is 0, the element corresponding to the element number is turned off, and when it is 1, the element corresponding to the element number is turned on.

[0013] Optionally, in the incremental Sigma-Delta analog-to-digital converter, the N registers output N accumulated weights including: RegQ1~RegQ 32 , RegQ1 is input to the first port of the first Y input sequencer and the first port of the first Y input adder, RegQ 32 Input to the Yth port of the Xth Y-input sequencer and the Yth port of the Xth Y-input adder.

[0014] Optionally, in the incremental Sigma-Delta analog-to-digital converter, the X-port input sequencer includes X input terminals, each of which is connected to an output terminal of a Y-port input adder.

[0015] Optionally, in the incremental Sigma-Delta analog-to-digital converter, the X-port input sequencer includes X output terminals, and the X output terminals sequentially output the second group of arranged cumulative weights Order_L[1] to Order_L[X].

[0016] Optionally, in the incremental Sigma-Delta analog-to-digital converter, when the number of elements is 32, the sorting module includes 8 4-port input sorters, 8 4-port input adders and one 8-port input sorter.

[0017] Optionally, in the incremental Sigma-Delta analog-to-digital converter, the first group of arranged cumulative weights Order_M[1]~Order_M

[32] is a 2-bit codeword.

[0018] Optionally, in the incremental Sigma-Delta analog-to-digital converter, the second group of arranged cumulative weights Order_L[1]~Order_L

[32] is a 3-bit codeword.

[0019] Optionally, in the incremental Sigma-Delta analog-to-digital converter, the sorted cumulative weights Order1 to Order 32 It is a 5-bit code word.

[0020] In the incremental Sigma-Delta analog-to-digital converter provided by the present invention, the weight of the output codeword is changed as the number of sampling times increases, thereby improving the ability to suppress mismatch noise and improving the accuracy of the incremental Sigma-Delta analog-to-digital converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 Schematic diagram of an incremental Sigma-Delta analog-to-digital converter according to an embodiment of the present invention;

[0022] Figure 2 is a schematic diagram of a sorting module according to an embodiment of the present invention;

[0023] Figure 3 is a schematic diagram of a sorting module when N is 32 in an embodiment of the present invention; Figure 4 is a schematic diagram of a specific embodiment of the sorting module of the present invention; Figure 5 and 6 is the post-simulation output spectrum of the prior art; Figure 7 4 is a post-simulation output spectrum of the incremental Sigma-Delta ADC according to an embodiment of the present invention. DETAILED DESCRIPTION

[0024] The specific implementation of the present invention will be described in more detail below in conjunction with the schematic diagram. The advantages and features of the present invention will become clearer based on the following description. It should be noted that the drawings are all in a very simplified form and are not in exact proportions, and are only used to facilitate and clearly assist in explaining the purpose of the embodiments of the present invention.

[0025] Hereinafter, the terms "first", "second", etc. are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological sequence. It is to be understood that these terms used in this manner are interchangeable where appropriate. Similarly, if the method described herein includes a series of steps, the order of these steps presented herein is not necessarily the only order in which these steps can be performed, and some of the steps described may be omitted and / or some other steps not described herein may be added to the method.

[0026] Furthermore, it should be understood that when a layer (or film), region, pattern or structure is referred to as being "on" a substrate, layer (or film), region and / or pattern, it can be directly on another layer or substrate, and / or there can be intervening layers. In addition, it should be understood that when a layer is referred to as being "under" another layer, it can be directly under another layer, and / or there can be one or more intervening layers. In addition, references to being "on" and "under" each layer can be made based on the accompanying drawings.

[0027] Please refer to Figure 1 The present invention provides an incremental Sigma-Delta analog-to-digital converter for performing analog-to-digital conversion on N elements included in a DAC module, comprising:

[0028] N groups of cumulative weight modules, each group of cumulative weight modules includes: a comparator 11, the positive input end of the comparator 11 receives the component serial number for analog-to-digital conversion, the output end of the comparator 11 is connected to the DAC module 31, the output end of the comparator 11 outputs an enable signal work_en, and the enable signal work_en is used to turn on or off the component corresponding to the component serial number contained in the DAC module 31; a register 12, the enable end of the register 12 is connected to the output end of the comparator 11; an adder 13, one input end of the adder 13 receives the codeword weight, and the other input end is connected to the output end of the register 12, the output end of the adder 13 is connected to the input end of the register 12, the register 12 outputs the cumulative weight, and the N registers 12 output N cumulative weights;

[0029] A sorting module 21 is used to sort the N accumulated weights outputted from the output ends of the N registers 12, and input the sorted codeword weights into the negative input end of the comparator 11; wherein the sorting module 21 comprises X Y-port input sorters, X Y-port input adders and an X-port input sorter, the N accumulated weights are sequentially connected to the input ends of the X Y-port input sorters and the input ends of the Y-port input adders, the output ends of the X Y-port input sorters respectively output the first group of sorted accumulated weights Order_M[1] to Order_M[N], the output ends of the X Y-port input adders are sequentially connected to the input end of the X-port input sorter, and the output end of the X-port input sorter outputs the second group of sorted accumulated weights Order_L[1] to Order_L[X];

[0030] The sorted cumulative weights output by the sorting module are as follows:

[0031] Wherein, N, X and Y are all integers greater than or equal to 1, and X×Y=N, and n is any integer between 1 and N.

[0032] Please refer to Figure 2 , N registers output N cumulative weights including: RegQ1~RegQ 32 , RegQ1 is input to the first port of the first Y input sequencer and the first port of the first Y input adder, RegQ 32 Input to the Yth port of the Xth Y input sequencer and the Yth port of the Xth Y input adder. The X-port input sequencer includes X input terminals, each of which is connected to an output terminal of a Y-port input adder. The X-port input sequencer includes X output terminals, which sequentially output the second group of arranged cumulative weights Order_L[1] to Order_L[X].

[0033] Please refer to Figure 3, when the number of elements is 32, the sorting module includes 8 4-port input sorters, 8 4-port input adders and one 8-port input sorter. The cumulative weights of the first group after arrangement Order_M[1]~Order_M

[32] are 2-bit codewords. The cumulative weights of the second group after arrangement Order_L[1]~Order_L

[32] are 3-bit codewords. The sorted cumulative weights Order1 to Order32 output by the sorting module are 5-bit codewords. Specifically, when the number of elements N is 32, the number of groups X of the coarse sorting module is 8, and the number of inputs Y contained in each group is 4. It contains 8 4-port input sorters, 8 4-port input adders and one 8-input sorter. RegQ1 to RegQ 32 32 Q outputs with enable registers, RegQ1 to RegQ 32 On the one hand, it is input to the 4-port input sorter of the corresponding group, generating 2-bit codeword output Order_M[1]~Order_M

[32] . On the other hand, it is input to the 4-port input adder of the corresponding group. The outputs of the 8 4-input adders are input to the 8-input sorter, generating 3-bit codeword output Order_L[1]~Order_L

[32] . The Order_M corresponding to each input is combined with the Order_L corresponding to the group to which it belongs to obtain the 5-bit codeword output Order1 port Order32 of the sorting module. Order1 port Order32 satisfies the following expression:

[0034] Order n =(Order_M[n]-1)×2 3 +Order_L[m]-1, Where n is any integer between 1 and 32.

[0035] Please refer to Figure 4 , the 4 inputs I1, I2, I3 and I4 are respectively input into a comparator together with the other 3 inputs, consuming 6 comparators in total, and obtaining 6 outputs C12, C13, C14, C23, C24 and C34, and 6 inverted outputs C21, C31, C41, C32, C42 and C43. Output O1 is obtained by C12, C13 and C14 through a 3-input adder, output O2 is obtained by C21, C23 and C24 through a 3-input adder, output O3 is obtained by C31, C32 and C34 through a 3-input adder, and output O4 is obtained by C41, C42 and C43 through a 3-input adder.

[0036] The value of the codeword weight in the embodiment of the present invention starts from 250 and gradually decreases by 1 in steps of 1 until it reaches 1. The enable signal is 1 or 0. When it is 0, the element corresponding to the element number is turned off, and when it is 1, the element corresponding to the element number is turned on.

[0037] Please refer to Figure 5 The simulation results of the incremental Sigma-Delta ADC of the embodiment of the present invention show that the signal-to-noise-distortion ratio (SNDR) is 80.3dB.

[0038] Please refer to Figure 5 , the post-simulation output spectrum of the incremental Sigma-Delta ADC of the embodiment of the present invention. The post-simulation result of the incremental Sigma-Delta ADC shows that the SNDR is 108.8dB.

[0039] Please refer to Figure 5 , the post-simulation output spectrum of the incremental Sigma-Delta ADC of the embodiment of the present invention. The post-simulation result of the incremental Sigma-Delta ADC shows that the SNDR is 113.4dB. Figure 5 The DEM circuit of the present invention significantly improves the noise performance and harmonic performance of the ADC. Figure 6 In the case where the DWA circuit is applied, the DEM circuit of the present invention further improves the noise performance of the ADC, so that the ADC can achieve higher accuracy.

[0040] When applied to a second-order incremental Sigma-Delta ADC with an oversampling rate of 250 and a number of elements of 32, a comparison of resource consumption between a coarse sorting module circuit and a precise sorting circuit according to an embodiment of the present invention is shown in Table 1. The DEM circuit of the present invention significantly reduces the resource consumption of the DEM circuit without affecting the performance, reduces the area of ​​the DEM circuit, and reduces the power consumption of the DEM circuit.

[0041] Table 1 Comparison of resource consumption of a coarse sorting module circuit and a precise sorting circuit in one embodiment of the present invention

[0042]

[0043] In summary, in the incremental Sigma-Delta analog-to-digital converter provided in the embodiment of the present invention, the weight of the output codeword is changed as the number of sampling times increases, thereby improving the ability to suppress mismatch noise and improving the accuracy of the incremental Sigma-Delta analog-to-digital converter.

[0044] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. An incremental Sigma-Delta analog-to-digital converter for performing analog-to-digital conversion on N elements included in a DAC module, characterized in that: include: N groups of cumulative weight modules, each group of the cumulative weight modules includes: a comparator, the positive input end of the comparator receives the serial number of the element to be converted into analog to digital, the output end of the comparator is connected to the DAC module, the output end of the comparator outputs an enable signal, and the enable signal is used to turn on or off the element; a register, the enable end of the register is connected to the output end of the comparator; an adder, one input end of the adder receives the codeword weight, the other input end is connected to the output end of the register, the output end of the adder is connected to the input end of the register, the register outputs the cumulative weight, and N registers output N cumulative weights; A sorting module, used for sorting the N accumulated weights outputted from the output ends of the N registers, and inputting the sorted codeword weights into the negative input end of the comparator; wherein the sorting module comprises X Y-port input sorters, X Y-port input adders and an X-port input sorter, the N accumulated weights are sequentially connected to the input ends of the X Y-port input sorters and the input ends of the Y-port input adders, the output ends of the X Y-port input sorters respectively output a first group of sorted accumulated weights Order_M[1] to Order_M[N], the output ends of the X Y-port input adders are sequentially connected to the input end of the X-port input sorter, and the output end of the X-port input sorter outputs a second group of sorted accumulated weights Order_L[1] to Order_L[X]; The sorted cumulative weights output by the sorting module are as follows: Wherein, N, X and Y are all integers greater than or equal to 1, and X×Y=N, and n is any integer between 1 and N.

2. The incremental Sigma-Delta analog-to-digital converter according to claim 1, wherein: The value of the codeword weight starts from 250 and gradually decreases by 1 in steps of 1 until it reaches 1.

3. The incremental Sigma-Delta analog-to-digital converter according to claim 1, wherein: The enable signal is 1 or 0. When it is 0, the component corresponding to the component number is turned off, and when it is 1, the component corresponding to the component number is turned on.

4. The incremental Sigma-Delta analog-to-digital converter according to claim 1, wherein: The N registers output N accumulated weights including: RegQ1~RegQ 32 , RegQ1 is input to the first port of the first Y input sequencer and the first port of the first Y input adder, RegQ 32 Input to the Yth port of the Xth Y-input sequencer and the Yth port of the Xth Y-input adder.

5. The incremental Sigma-Delta analog-to-digital converter according to claim 1, wherein: The X-port input sequencer includes X input terminals, each of which is connected to an output terminal of a Y-port input adder.

6. The incremental Sigma-Delta analog-to-digital converter according to claim 1, wherein: The X-port input sequencer includes X output terminals, and the X output terminals sequentially output the second group of arranged cumulative weights Order_L[1] to Order_L[X].

7. The incremental Sigma-Delta analog-to-digital converter according to claim 1, wherein: When the number of elements is 32, the sorting module includes 8 4-port input sorters, 8 4-port input adders and one 8-port input sorter.

8. The incremental Sigma-Delta analog-to-digital converter according to claim 7, characterized in that: The first group of accumulated weights after arrangement Order_M[1] to Order_M[32] are 2-bit code words.

9. The incremental Sigma-Delta analog-to-digital converter according to claim 7, wherein: The second group of accumulated weights after arrangement Order_L[1] to Order_L[32] are 3-bit code words.

10. The incremental Sigma-Delta analog-to-digital converter according to claim 7, characterized in that: The sorting module outputs the sorted cumulative weights Order1 to Order 32 It is a 5-bit code word.

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