Vertical RGB three-primary-color Micro LED chip and preparation method thereof

Abstract

The invention discloses a vertical RGB three-primary-color Micro LED chip and a preparation method thereof, and the method comprises the steps: providing a target wafer which comprises a substrate, and a first epitaxial layer, a second epitaxial layer and a third epitaxial layer which are disposed on the substrate at intervals, and then carrying out the chip manufacturing based on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer, a positive electrode connected with a P-type semiconductor layer, a first negative electrode independently connected with an N-type semiconductor layer, and a second negative electrode connected with a plurality of first negative electrodes in a common-cathode manner are manufactured, and finally, laser giant conversion equipment is adopted for transferring, so that the laser giant conversion equipment is aligned with a preset circuit substrate, bonding fixation is realized, and the vertical RGB three-primary-color Micro LED chip is obtained. The chip is manufactured by adopting the process, so that the mass transfer process of the chip can be simplified, the dependence on high-quality and high-quality equipment is avoided, and the overall manufacturing cost of the chip is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a vertical RGB three-primary color Micro LED chip and a preparation method thereof. Background Art

[0002] Micro LED micro-display technology has the characteristics of self-luminescence. Each pixel can be driven to emit light independently. Its advantages include high brightness, low power consumption, small size, ultra-high resolution and color saturation. Compared with OLED technology, which is also a self-luminous display, Micro LED is not only more efficient and has a longer lifespan, but also has relatively stable materials that are not easily affected by the environment, and can also avoid the phenomenon of afterimage.

[0003] Traditional Micro displays require substrate peeling and laser mass transfer of the wafers of each of the three primary colors to form a three-primary color display chip, which places high demands on equipment precision and greatly increases costs. Summary of the invention

[0004] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a vertical RGB three-primary color Micro LED chip and a preparation method thereof, aiming to solve the problem in the prior art of substrate peeling and laser mass transfer of three-primary color wafers, which has high requirements on equipment and leads to high overall chip cost.

[0005] A first aspect of the present invention is to provide a method for preparing a vertical RGB three-primary color Micro LED chip, the preparation method comprising: Providing a target wafer, the target wafer comprising a substrate and a first epitaxial layer, a second epitaxial layer and a third epitaxial layer spaced apart from each other on the substrate; Fabricating a passivation layer on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer of the target wafer, so that the passivation layer covers the first epitaxial layer, the second epitaxial layer and the third epitaxial layer; Performing photolithography on the passivation layer to expose the first epitaxial layer, the second epitaxial layer and the third epitaxial layer respectively, obtaining a positive electrode connection hole, and making a positive electrode connected to the first epitaxial layer, the second epitaxial layer and the third epitaxial layer in the positive electrode connection hole; On the surface of the positive electrode, a temporary substrate is fixed to the electrode surface via a bonding medium, and the substrate is removed; Coating a reflective layer on the surface of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer on a side away from the temporary substrate; By photolithography and dry etching, the reflective layer, the first epitaxial layer and the buffer layer at the bottom of the second epitaxial layer are penetrated, and at least a portion of the epitaxial layer is removed, so that the reflective layer is penetrated and at least a portion of the epitaxial layer in the third epitaxial layer is removed, and reflective layer through holes corresponding to each epitaxial layer are obtained; Performing photolithography and dry etching in the through hole of the reflective layer to expose the N-type semiconductor layer in the first epitaxial layer and the second epitaxial layer, and to expose the N-type semiconductor layer in the third epitaxial layer, and to obtain negative electrode connection holes corresponding to each epitaxial layer; Making a first negative electrode in contact with the N-type semiconductor layer in the negative electrode connection hole; By photolithography and coating, a common cathode second negative electrode connected to each first negative electrode is manufactured; The second negative electrode is bonded to the common cathode area of ​​the circuit substrate to achieve electrical connection of the negative electrode. The positive electrode side is irradiated by a laser giant conversion device to detach the temporary substrate and obtain an RGB three-primary color Micro LED chip.

[0006] According to one aspect of the above technical solution, the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are a blue epitaxial layer, a green epitaxial layer and a red epitaxial layer respectively.

[0007] According to one aspect of the above technical solution, the structure and material of the positive electrode in the first epitaxial layer and the second epitaxial layer are the same, and the structure and material of the positive electrode in the third epitaxial layer are different, but the thickness is equal; Among them, the positive electrodes in the first epitaxial layer and the second epitaxial layer are, from bottom to top, an ohmic contact layer, an electrode reflection layer, a wrapping layer and a connecting layer, and the positive electrodes in the third epitaxial layer are, from bottom to top, an adhesion layer, an ohmic layer, a coating layer and a connecting layer.

[0008] According to one aspect of the above technical solution, the thickness of the positive electrodes in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all 30nm-1000nm.

[0009] According to one aspect of the above technical solution, on the surface of the positive electrode, a temporary substrate is fixed to the electrode surface through a bonding medium, and the step of removing the substrate includes: On the positive electrode surfaces in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer, a preset temporary substrate is fixed on the positive electrode surfaces via a bonding medium; The substrate is removed by wet etching, the etching solution is a 1:9 NH4OH:H2O2 mixed solution, and the etching time is 20min-60min; Wherein, the temporary substrate is made of transparent material, and the bonding medium is made of UV photosensitive material.

[0010] According to one aspect of the above technical solution, in the step of coating a reflective layer on the surface of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer away from the temporary substrate, the reflective layer is a DBR structure of alternating SiO2 / Ti2O5 materials, and the reflectivity in the wavelength range of 440nm-470nm, the wavelength range of 520nm-550nm and the wavelength range of 610nm-630nm is greater than 97%.

[0011] According to one aspect of the above technical solution, the steps of penetrating the reflective layer, the first epitaxial layer and the buffer layer at the bottom of the second epitaxial layer, removing at least part of the epitaxial layer, penetrating the reflective layer and removing at least part of the epitaxial layer in the third epitaxial layer by photolithography and dry etching to obtain reflective layer through holes corresponding to each epitaxial layer include: By performing photolithography and dry etching for the first time, the reflective layer and the buffer layer at positions corresponding to the first epitaxial layer and the second epitaxial layer, as well as at least a portion of the first epitaxial layer and the second epitaxial layer are removed to obtain reflective layer through holes corresponding to the first epitaxial layer and the second epitaxial layer respectively; By performing photolithography and dry etching again, the reflective layer at a corresponding position of the third epitaxial layer and at least a portion of the third epitaxial layer are removed to obtain a reflective layer through hole corresponding to the third epitaxial layer; The steps also include: During the first or second photolithography and dry etching process, the reflective layer and the passivation layer between adjacent RGB units on the target wafer are removed, so that the reflective layer and the passivation layer are disconnected between adjacent RGB units.

[0012] According to one aspect of the above technical solution, the step of performing photolithography and dry etching in the through hole of the reflective layer to expose the N-type semiconductor layer in the first epitaxial layer and the second epitaxial layer, and to expose the N-type semiconductor layer in the third epitaxial layer, and obtaining the negative electrode connection hole corresponding to each epitaxial layer includes: By performing photolithography and dry etching for the first time, at least a portion of the N-type semiconductor layer is removed in the through holes of the reflective layer at positions corresponding to the first epitaxial layer and the second epitaxial layer to expose the negative electrode connection holes corresponding to the first epitaxial layer and the second epitaxial layer; By performing photolithography and dry etching again, at least a portion of the N-type semiconductor layer is removed in the through hole of the reflective layer at a corresponding position of the third epitaxial layer to expose the negative electrode connection hole corresponding to the third epitaxial layer.

[0013] According to one aspect of the above technical solution, the first negative electrode contacts the N-type semiconductor layer of each epitaxial layer in the negative electrode connecting hole, the second negative electrode is commonly cathode-connected to all the first negative electrodes in each RGB unit, and the surface on one side away from the first negative electrode remains flush.

[0014] The second aspect of the present invention is to provide a vertical RGB three-primary color Micro LED chip, which is prepared by the preparation method described in the above technical solution.

[0015] Compared with the prior art, the vertical RGB three-primary color Micro LED chip and the preparation method thereof shown in the present invention have the following beneficial effects: A target wafer is provided, the target wafer includes a substrate and a first epitaxial layer, a second epitaxial layer and a third epitaxial layer spaced apart on the substrate, and then chips are manufactured based on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer respectively, a positive electrode connected to the P-type semiconductor layer is manufactured on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer, a first negative electrode separately connected to the N-type semiconductor layer in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer, and a second negative electrode connected to a plurality of first negative electrodes in a cathode-like manner is manufactured, and finally a laser giant transfer device is used for transfer, so that it is aligned with a preset circuit substrate to achieve bonding and fixation, and a vertical RGB three-primary color Micro LED chip is obtained. The present invention uses the above process to manufacture vertical RGB three-primary color Micro LED chips, which can simplify the mass transfer process of the chip, avoid relying on high-precision equipment, and reduce the overall chip manufacturing cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 A schematic diagram of the structure of a target wafer in one embodiment of the present invention; Figure 2 A schematic diagram of manufacturing a passivation layer and opening holes in one embodiment of the present invention; Figure 3 A schematic diagram of manufacturing a positive electrode in one embodiment of the present invention; Figure 4 A schematic diagram of manufacturing a temporary substrate on the surface of a positive electrode in one embodiment of the present invention; Figure 5 A schematic diagram of manufacturing a reflective layer on the surface of an epitaxial layer in one embodiment of the present invention; Figure 6 It is a schematic diagram of making a reflective layer through hole on a reflective layer in one embodiment of the present invention; Figure 7 A schematic diagram of making a negative electrode connection hole in a through hole of a reflective layer in one embodiment of the present invention; Figure 8 A schematic diagram of manufacturing a first negative electrode in a negative electrode connection hole according to an embodiment of the present invention; Fig. 9 It is a schematic diagram of manufacturing a common cathode second negative electrode in one embodiment of the present invention; Component symbol description: Substrate 10, buffer layer 11, first epitaxial layer 21, second epitaxial layer 22, third epitaxial layer 23, passivation layer 30, positive electrode connection hole 31, positive electrode 40, temporary substrate 50, bonding medium 51, reflective layer 60, reflective layer through hole 61, negative electrode connection hole 70, first negative electrode 81, second negative electrode 82. DETAILED DESCRIPTION

[0017] In order to make the purpose, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are described in detail below in conjunction with the accompanying drawings. Several embodiments of the present invention are shown in the accompanying drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0018] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0019] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0020] First embodiment See also Figures 1 to 9 The first embodiment of the present invention provides a method for preparing a vertical RGB three-primary color Micro LED chip, which is used to manufacture a vertical structured RGB three-primary color Micro LED chip to simultaneously meet the three indicators of verticality, RGB three-color display and Micro.

[0021] The preparation method shown in this embodiment includes steps S10 to S100: In step S10 , a target wafer is provided. The target wafer includes a substrate and a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer spaced apart from each other on the substrate.

[0022] like Figure 1As shown, in this embodiment, the target wafer is a semiconductor wafer to be processed, including a substrate 10 and a first epitaxial layer 21, a second epitaxial layer 22 and a third epitaxial layer 23 spaced apart on the substrate 10, wherein the substrate 10 is a GaAs substrate, that is, a gallium arsenide substrate, and the first epitaxial layer 21, the second epitaxial layer 22 and the third epitaxial layer 23 spaced apart on the substrate 10 are specifically a blue epitaxial layer, a green epitaxial layer and a red epitaxial layer, respectively, and the blue epitaxial layer, the green epitaxial layer and the red epitaxial layer are used to construct an RGB unit.

[0023] There is one substrate 10 in the target wafer, and the number of RGB units can be single or multiple. Moreover, on the substrate 10, the surfaces of the first epitaxial layer 21, the second epitaxial layer 22 and the third epitaxial layer 23 away from the substrate 10 are in the same horizontal plane and remain flush.

[0024] More specifically, the size of each epitaxial layer for display corresponds to the size of the Micro chip, the chip size is ≤15µm, and the chip is square.

[0025] Step S20 , forming a passivation layer on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer of the target wafer, so that the passivation layer covers the first epitaxial layer, the second epitaxial layer and the third epitaxial layer.

[0026] like Figure 2 As shown, in this embodiment, on the above structure, a passivation layer 30 is produced on the first epitaxial layer 21, the second epitaxial layer 22 and the third epitaxial layer 23 in the target wafer through the ALD process. The material can be SiO2, Al2O3, preferably SiO2, with a thickness of 30nm-500nm.

[0027] Step S30, photolithography the passivation layer to expose the first epitaxial layer, the second epitaxial layer and the third epitaxial layer respectively to obtain a positive electrode connection hole, and fabricate a positive electrode in the positive electrode connection hole to connect to the first epitaxial layer, the second epitaxial layer and the third epitaxial layer.

[0028] In this embodiment, after the passivation layer 30 is deposited on the first epitaxial layer 21, the second epitaxial layer 22 and the third epitaxial layer 23 by ALD, at least a portion of the passivation layer 30 is etched by wet etching to expose the P-type semiconductor layer of the first epitaxial layer 21, the second epitaxial layer 22 and the third epitaxial layer 23, thereby obtaining the positive electrode connection hole 31.

[0029] The shape of the positive electrode connection hole 31 is required to be circular, with a diameter of 2µm-5µm. Of course, other holes with relatively smooth hole walls, such as elliptical holes, are also acceptable.

[0030] like Figure 3As shown, in this embodiment, after the positive electrode connection hole 31 is produced, photolithography and metal plating equipment will be used to produce a positive electrode 40, that is, a P-type electrode, in the positive electrode connection hole 31 and connected to the P-type semiconductor layer in the first epitaxial layer 21, the second epitaxial layer 22 and the third epitaxial layer 23.

[0031] Among them, the structure and material of the positive electrode 40 of the first epitaxial layer 21 and the second epitaxial layer 22 are exactly the same, while the structure and material of the third epitaxial layer 23 are slightly different, but the thickness of the positive electrode 40 in the first epitaxial layer 21, the second epitaxial layer 22 and the third epitaxial layer 23 is the same, and the thickness H of the positive electrode 40 ranges from 30nm to 1000nm, and the shape of the positive electrode 40 is also circular, with a diameter slightly larger than the diameter of the connecting port of the positive electrode 40, which is 4µm-10µm.

[0032] Specifically, the positive electrode 40 on the P-type semiconductor layer in the first epitaxial layer 21 and the second epitaxial layer 22 has an ohmic contact layer, an electrode reflective layer, a coating layer and a connection layer from bottom to top. More specifically, the ohmic contact layer material is one of Cr, Ti or Ni, with a thickness of 10Å-100Å, the electrode reflective layer material is Al, with a thickness of 500Å-3000Å, the coating layer material is a stacked structure formed by Ti or Ni and Pt, and the connection layer material is a metal material such as Au, Sn, Ni, Cu, AuSn alloy, etc., the purpose of which is to be eutectic connected to the power substrate for conductivity, with a thickness of 0.5µm-3µm.

[0033] In addition, the positive electrode 40 on the P-type semiconductor layer in the third epitaxial layer 23 has a structure of an adhesion layer, an ohmic layer, a coating layer and a connection layer from bottom to top. More specifically, the adhesion layer material is Au with a thickness of 50Å-500Å, the ohmic layer material is AuGeNi alloy with a thickness of 500Å-3000Å, the coating layer material is a stacked structure formed by Ti or Ni and Pt, and the connection layer material is a metal material such as Au, Sn, Ni, Cu, AuSn alloy, etc., the purpose of which is to be eutectic connected to the power substrate for conductivity, and the thickness is 0.5µm-3µm.

[0034] As described above, the positive electrodes 40 are respectively fabricated on the P-type semiconductor layers in the first epitaxial layer 21 , the second epitaxial layer 22 , and the third epitaxial layer 23 .

[0035] Step S40: on the surface of the positive electrode, fix a temporary substrate on the electrode surface via a bonding medium, and remove the substrate.

[0036] In this embodiment, on the surface of the positive electrode, a temporary substrate is fixed to the electrode surface through a bonding medium, and the step of removing the substrate includes: On the positive electrode surfaces in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer, a preset temporary substrate is fixed on the positive electrode surfaces via a bonding medium; The substrate is removed by wet etching, the etching solution is a 1:9 NH4OH:H2O2 mixed solution, and the etching time is 20min-60min.

[0037] Specifically, if Figure 4 As shown, on the electrode surface of the above structure, a bonding medium 51 is used to bond the temporary substrate 50 to the above wafer. After completion, the GaAs substrate on the side away from the positive electrode 40 is removed by wet etching. The etching solution is a mixture of NH4OH:H2O2 with a ratio of 1:9. Depending on the thickness of the substrate 10, the etching time is 20min-60min.

[0038] The temporary substrate 50 is a transparent material, such as glass or sapphire. In addition, the bonding medium 51 is a temporary bonding glue, which is made of UV photosensitive material.

[0039] In step S50, a reflective layer is coated on the surfaces of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer on a side away from the temporary substrate.

[0040] like Figure 5 As shown, in this embodiment, after the temporary substrate 50 is fixed and the substrate 10 is removed, a metal coating device is used to coat a reflective layer 60 on the surface of the first epitaxial layer 21, the second epitaxial layer 22 and the third epitaxial layer 23 on the side away from the temporary substrate 50, that is, the reflective layer 60 is coated on the surface where the original substrate 10 is located.

[0041] Among them, the reflective layer 60 is a DBR structure of alternately stacked SiO2 / Ti2O5 materials, and its reflectivity in the wavelength range of 440nm-470nm is greater than 97%, in the wavelength range of 520nm-550nm is greater than 97%, and in the wavelength range of 610nm-630nm is also greater than 97%.

[0042] Step S60, through photolithography and dry etching, the reflective layer, the first epitaxial layer and the buffer layer at the bottom of the second epitaxial layer are penetrated, and at least part of the epitaxial layer is removed, so that the reflective layer is penetrated and at least part of the epitaxial layer in the third epitaxial layer is removed, to obtain reflective layer through holes corresponding to each epitaxial layer.

[0043] In this embodiment, the steps of penetrating the reflective layer, the first epitaxial layer, and the buffer layer at the bottom of the second epitaxial layer, removing at least part of the epitaxial layer, penetrating the reflective layer, and removing at least part of the epitaxial layer in the third epitaxial layer by photolithography and dry etching to obtain reflective layer through holes corresponding to each epitaxial layer include: By performing photolithography and dry etching for the first time, the reflective layer and the buffer layer at positions corresponding to the first epitaxial layer and the second epitaxial layer, as well as at least a portion of the first epitaxial layer and the second epitaxial layer are removed to obtain reflective layer through holes corresponding to the first epitaxial layer and the second epitaxial layer respectively; By performing photolithography and dry etching again, the reflective layer at a corresponding position of the third epitaxial layer and at least a portion of the third epitaxial layer are removed to obtain a reflective layer through hole corresponding to the third epitaxial layer; The steps also include: During the first or second photolithography and dry etching process, the reflective layer and the passivation layer between adjacent RGB units on the target wafer are removed, so that the reflective layer and the passivation layer are disconnected between adjacent RGB units.

[0044] Specifically, if Figure 6 As shown, on the above structure, a reflective layer through hole 61 is prepared by photolithography and dry etching. It is required that the reflective layer 60 and the buffer layer 11 at the corresponding positions of the first epitaxial layer 21 and the second epitaxial layer 22 are etched through, and a portion of the N-type semiconductor layer is also etched away. Since there is no buffer layer 11 at the bottom of the third epitaxial layer 23, only the reflective layer 60 at the corresponding position is etched through, and at least part of the epitaxial layer of the N-type semiconductor layer is also etched away. At the same time, the reflective layer 60 and the passivation layer 30 pre-deposited between different RGB units are also etched and disconnected, so that multiple independent RGB units can be obtained, and each RGB unit can work independently after the chip structure is manufactured later.

[0045] Step S70, performing photolithography and dry etching in the through hole of the reflective layer to expose the N-type semiconductor layer in the first epitaxial layer and the second epitaxial layer, and to expose the N-type semiconductor layer in the third epitaxial layer, and obtain negative electrode connection holes corresponding to each epitaxial layer.

[0046] In this embodiment, the steps of performing photolithography and dry etching in the through hole of the reflective layer to expose the N-type semiconductor layer in the first epitaxial layer and the second epitaxial layer, and to expose the N-type semiconductor layer in the third epitaxial layer, and obtaining the negative electrode connection hole corresponding to each epitaxial layer include: By performing photolithography and dry etching for the first time, at least a portion of the N-type semiconductor layer is removed in the through holes of the reflective layer at positions corresponding to the first epitaxial layer and the second epitaxial layer to expose the negative electrode connection holes corresponding to the first epitaxial layer and the second epitaxial layer; By performing photolithography and dry etching again, at least a portion of the N-type semiconductor layer is removed in the through hole of the reflective layer at a corresponding position of the third epitaxial layer to expose the negative electrode connection hole corresponding to the third epitaxial layer.

[0047] Specifically, if Figure 7As shown, at the location of the reflective layer through hole 61 of the above structure, a negative electrode connection hole 70 is prepared by two photolithography and dry etching. Among them, the first photolithography and dry etching respectively prepare the negative electrode connection holes 70 corresponding to the first epitaxial layer 21 and the second epitaxial layer 22, exposing the N-type semiconductor layer doped with a certain Si concentration in the first epitaxial layer 21 and the second epitaxial layer 22, so that the negative electrode can be in good electrode contact with the N-type semiconductor layer in the first epitaxial layer 21 and the second epitaxial layer 22; the second photolithography and dry etching prepare the negative electrode connection hole 70 corresponding to the third epitaxial layer 23, and by etching the epitaxial layer to a certain depth, the N-type semiconductor layer doped with a certain Si concentration is exposed, so that the negative electrode can be in good electrode contact with the N-type semiconductor layer in the third epitaxial layer 23.

[0048] Step S80 , forming a first negative electrode in contact with the N-type semiconductor layer in the negative electrode connection hole.

[0049] like Figure 8 As shown, in the present embodiment, a first negative electrode 81 in contact with the N-type semiconductor layer in the first epitaxial layer 21, the second epitaxial layer 22 and the third epitaxial layer 23 is manufactured in the negative electrode connection hole 70 by photolithography and metal plating, and the surface of the first negative electrode 81 at the bottom of the first epitaxial layer 21, the second epitaxial layer 22 and the third epitaxial layer 23 away from the N-type semiconductor layer is on the same horizontal plane and remains flush.

[0050] Step S90 , manufacturing a common cathode second negative electrode connected to each first negative electrode by photolithography and coating.

[0051] like Fig. 9 As shown, in this embodiment, a common cathode second negative electrode 82 connecting each first negative electrode 81 in a single RGB unit is further manufactured through photolithography and coating, that is, three first negative electrodes 81 are connected to one second negative electrode 82.

[0052] Among them, the first negative electrode 81 contacts the N-type semiconductor layer of each epitaxial layer in the negative electrode connecting hole 70, the second negative electrode 82 is commonly cathode-connected to all the first negative electrodes 81 in each RGB unit, and the surface of the second negative electrode 82 away from the first negative electrode 81 remains flush.

[0053] Specifically, the purpose of using a common cathode second negative electrode 82 to connect three independent first negative electrodes 81 and keep the surface flush is to make the negative electrode of the RGB Micro chip achieve a common cathode, and to facilitate metal bonding with the circuit substrate and achieve electrical connection with the negative electrode of the power supply.

[0054] In step S100, the second negative electrode is aligned and bonded to the common cathode region of the circuit substrate to achieve electrical connection of the negative electrode, and the positive electrode side is irradiated by a laser giant conversion device to separate the temporary substrate to obtain an RGB three-primary color Micro LED chip.

[0055] Specifically, the semi-finished chip is aligned with the circuit substrate so that the common cathode second negative electrode 82 is aligned with the common cathode area on the circuit substrate. As needed, the positive electrode 40 side of the RGB three-primary color Micro LED chip is irradiated by laser mass transfer equipment. The temporary substrate 50 is debonded and removed due to the UV sensitivity of the temporary bonding glue. The metal bonding technology is used to achieve bonding and fixing with the circuit substrate to achieve negative electrode electrical connection. Finally, a vertical structured common anode and cathode separately driven RGB three-primary color Micro LED chip is prepared to meet the four conditional indicators of vertical, RGB three-color display, Micro, and common cathode and anode separately driven.

[0056] Compared with the prior art, the method for preparing the vertical RGB three-primary color Micro LED chip shown in this embodiment has the following beneficial effects: A target wafer is provided, the target wafer includes a substrate and a first epitaxial layer, a second epitaxial layer and a third epitaxial layer spaced apart on the substrate, and then chips are manufactured based on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer respectively, a positive electrode connected to the P-type semiconductor layer is manufactured on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer, a first negative electrode separately connected to the N-type semiconductor layer in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer, and a second negative electrode connected to a plurality of first negative electrodes in a cathode-like manner is manufactured, and finally a laser giant transfer device is used for transfer, so that it is aligned with a preset circuit substrate to achieve bonding and fixation, and a vertical RGB three-primary color Micro LED chip is obtained. The present invention uses the above process to manufacture vertical RGB three-primary color Micro LED chips, which can simplify the mass transfer process of the chip, avoid relying on high-precision equipment, and reduce the overall chip manufacturing cost.

[0057] Second embodiment The second embodiment of the present invention provides a vertical RGB three-primary color Micro LED chip, which is prepared by the preparation method described in the first embodiment.

[0058] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0059] The above-mentioned embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for those of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A method for preparing a vertical RGB three-primary color Micro LED chip, characterized in that: The preparation method comprises: Providing a target wafer, the target wafer comprising a substrate and a first epitaxial layer, a second epitaxial layer and a third epitaxial layer spaced apart from each other on the substrate; Fabricating a passivation layer on the first epitaxial layer, the second epitaxial layer and the third epitaxial layer of the target wafer, so that the passivation layer covers the first epitaxial layer, the second epitaxial layer and the third epitaxial layer; Performing photolithography on the passivation layer to expose the first epitaxial layer, the second epitaxial layer and the third epitaxial layer respectively, obtaining a positive electrode connection hole, and making a positive electrode connected to the first epitaxial layer, the second epitaxial layer and the third epitaxial layer in the positive electrode connection hole; On the surface of the positive electrode, a temporary substrate is fixed to the electrode surface via a bonding medium, and the substrate is removed; Coating a reflective layer on the surface of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer on a side away from the temporary substrate; By photolithography and dry etching, the reflective layer, the first epitaxial layer and the buffer layer at the bottom of the second epitaxial layer are penetrated, and at least a portion of the epitaxial layer is removed, so that the reflective layer is penetrated and at least a portion of the epitaxial layer in the third epitaxial layer is removed, and reflective layer through holes corresponding to each epitaxial layer are obtained; Performing photolithography and dry etching in the through hole of the reflective layer to expose the N-type semiconductor layer in the first epitaxial layer and the second epitaxial layer, and to expose the N-type semiconductor layer in the third epitaxial layer, and to obtain negative electrode connection holes corresponding to each epitaxial layer; Making a first negative electrode in contact with the N-type semiconductor layer in the negative electrode connection hole; By photolithography and coating, a common cathode second negative electrode connected to each first negative electrode is manufactured; The second negative electrode is bonded to the common cathode area of ​​the circuit substrate to achieve electrical connection of the negative electrode. The positive electrode side is irradiated by a laser giant conversion device to detach the temporary substrate and obtain an RGB three-primary color Micro LED chip.

2. The method for preparing a vertical RGB three-primary color Micro LED chip according to claim 1, characterized in that: The first epitaxial layer, the second epitaxial layer and the third epitaxial layer are respectively a blue epitaxial layer, a green epitaxial layer and a red epitaxial layer.

3. The method for preparing a vertical RGB three-primary color Micro LED chip according to claim 2, characterized in that: The structures and materials of the positive electrodes in the first epitaxial layer and the second epitaxial layer are the same, and the structures and materials of the positive electrodes in the third epitaxial layer are different, but the thicknesses are the same; Among them, the positive electrodes in the first epitaxial layer and the second epitaxial layer are, from bottom to top, an ohmic contact layer, an electrode reflection layer, a wrapping layer and a connecting layer, and the positive electrodes in the third epitaxial layer are, from bottom to top, an adhesion layer, an ohmic layer, a coating layer and a connecting layer.

4. The method for preparing a vertical RGB three-primary color Micro LED chip according to claim 3, characterized in that: The thickness of the positive electrodes in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer are all 30nm-1000nm.

5. The method for preparing a vertical RGB three-primary color Micro LED chip according to claim 1, characterized in that: On the surface of the positive electrode, a temporary substrate is fixed to the electrode surface through a bonding medium, and the step of removing the substrate comprises: On the positive electrode surfaces in the first epitaxial layer, the second epitaxial layer and the third epitaxial layer, a preset temporary substrate is fixed on the positive electrode surfaces via a bonding medium; The substrate is removed by wet etching, the etching solution is a 1:9 NH4OH:H2O2 mixed solution, and the etching time is 20min-60min; Wherein, the temporary substrate is made of transparent material, and the bonding medium is made of UV photosensitive material.

6. The method for preparing a vertical RGB tri-color Micro LED chip according to claim 1, characterized in that: In the step of coating a reflective layer on the surface of the first epitaxial layer, the second epitaxial layer and the third epitaxial layer away from the temporary substrate, the reflective layer is a DBR structure of alternating SiO2 / Ti2O5 materials, and the reflectivity in the wavelength range of 440nm-470nm, the wavelength range of 520nm-550nm and the wavelength range of 610nm-630nm is greater than 97%.

7. The method for preparing a vertical RGB three-primary color Micro LED chip according to claim 1, characterized in that: The steps of penetrating the reflective layer, the first epitaxial layer and the buffer layer at the bottom of the second epitaxial layer by photolithography and dry etching, removing at least part of the epitaxial layer, penetrating the reflective layer and removing at least part of the epitaxial layer in the third epitaxial layer to obtain reflective layer through holes corresponding to each epitaxial layer include: By performing photolithography and dry etching for the first time, the reflective layer and the buffer layer at positions corresponding to the first epitaxial layer and the second epitaxial layer, as well as at least a portion of the first epitaxial layer and the second epitaxial layer are removed to obtain reflective layer through holes corresponding to the first epitaxial layer and the second epitaxial layer respectively; By performing photolithography and dry etching again, the reflective layer at a corresponding position of the third epitaxial layer and at least a portion of the third epitaxial layer are removed to obtain a reflective layer through hole corresponding to the third epitaxial layer; The steps also include: During the first or second photolithography and dry etching process, the reflective layer and the passivation layer between adjacent RGB units on the target wafer are removed, so that the reflective layer and the passivation layer are disconnected between adjacent RGB units.

8. The method for preparing a vertical RGB three-primary color Micro LED chip according to claim 7, characterized in that: The step of performing photolithography and dry etching in the through hole of the reflective layer to expose the N-type semiconductor layer in the first epitaxial layer and the second epitaxial layer, and to expose the N-type semiconductor layer in the third epitaxial layer, and to obtain the negative electrode connection hole corresponding to each epitaxial layer includes: By performing photolithography and dry etching for the first time, at least a portion of the N-type semiconductor layer is removed in the through holes of the reflective layer at positions corresponding to the first epitaxial layer and the second epitaxial layer to expose the negative electrode connection holes corresponding to the first epitaxial layer and the second epitaxial layer; By performing photolithography and dry etching again, at least a portion of the N-type semiconductor layer is removed in the through hole of the reflective layer at a corresponding position of the third epitaxial layer to expose the negative electrode connection hole corresponding to the third epitaxial layer.

9. The method for preparing a vertical RGB three-primary color Micro LED chip according to claim 8, characterized in that: The first negative electrode contacts the N-type semiconductor layer of each epitaxial layer in the negative electrode connection hole, the second negative electrode is cathode-combined to all the first negative electrodes in each RGB unit, and the surface on one side away from the first negative electrode remains flush.

10. A vertical RGB three-primary color Micro LED chip, characterized in that: The invention is prepared by the preparation method according to any one of claims 1 to 9.

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