Multilayer ceramic capacitor

Abstract

Provided is a laminated ceramic capacitor capable of suppressing the occurrence of peeling between internal electrode layers at an end portion of a laminated body even if a dielectric layer or the like is thinned. The laminated ceramic capacitor according to the present invention comprises: a laminated body having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, the first main surface and the second main surface are opposite to each other in the stacking direction, the first end surface and the second end surface are opposite to each other in the length direction orthogonal to the stacking direction, and the first side surface and the second side surface are opposite to each other in the width direction orthogonal to the stacking direction and the length direction. A first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, in which the plurality of internal electrode layers include a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately disposed on different dielectric layers. The plurality of first internal electrode layers have a plurality of first opposing electrode sections that face the second internal electrode layers, and a plurality of first lead-out sections that extend from the plurality of first opposing electrode sections and are led out to the first end surface. The second internal electrode layer has a plurality of second opposing electrode sections that face the first internal electrode layer, and a plurality of second lead-out sections that extend from each of the plurality of second opposing electrode sections and are led out to the first side surface. The first lead-out portions have a first connection portion between the first lead-out portions on the different dielectric layers located on at least the first main surface side or at least the second main surface side, the first connection portion being connected so as to span at least two or more of the first lead-out portions in the stacking direction. The second lead-out section has a second connection section between the second lead-out sections located on different dielectric layers on at least the first main surface side or at least the second main surface side, the second connection section being connected so as to span at least two or more second lead-out sections in the stacking direction.

Description

Technical Field

[0001] The present invention relates to a laminated ceramic capacitor. Background Art

[0002] Conventionally, a laminated ceramic capacitor is known as a laminated ceramic electronic component. Generally, a laminated ceramic capacitor includes a laminated body in which a plurality of dielectric layers and internal electrode layers are alternately laminated, and external electrodes provided on both end surfaces of the laminated body. For example, Patent Document 1 discloses a laminated ceramic capacitor having the above-mentioned structure and in which the external electrodes include a base electrode layer formed by sintering (see Patent Document 1).

[0003] In recent years, as for the laminated ceramic capacitors such as those described in Patent Document 1, the impedance of electronic circuit lines has been accelerating, mainly in mobile devices, and there is a need for increasing the capacitance of laminated ceramic capacitors for decoupling purposes.

[0004] As a method for increasing the capacity of a multilayer ceramic capacitor, there is generally a method of increasing the number of laminated internal electrode layers by reducing the thickness of dielectric layers and internal electrode layers.

[0005] Prior Art Literature

[0006] Patent Literature

[0007] Patent Document 1: Japanese Patent Application Publication No. 2003-243249 Summary of the invention

[0008] Problem that the invention aims to solve

[0009] However, when the number of laminated internal electrode layers is increased by thinning the dielectric layers and the internal electrode layers, a spherical phenomenon occurs in which the internal electrode layers are agglomerated in the length and width directions and expand in the height direction (stacking direction) to increase the thickness due to the heat during firing of the laminated body in the internal layer portion formed by stacking a plurality of internal electrode layers and the outer layer portion formed by stacking only a plurality of dielectric layers. In this case, tensile stress in the height direction increases in the end face portion that is a structural singularity of the inner layer portion and the outer layer portion, and peeling between the internal electrode layers may become more likely to occur.

[0010] The present invention has been made in view of the above problems, and an object of the present invention is to provide a multilayer ceramic capacitor capable of suppressing the occurrence of separation between internal electrode layers at the end of a multilayer body even when dielectric layers and the like are thinned.

[0011] Technical solutions to solve problems

[0012] The multilayer ceramic capacitor of the present invention comprises: a multilayer body having a plurality of stacked dielectric layers and a plurality of internal electrode layers stacked on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a stacking direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the stacking direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the stacking direction and the length direction; a first external electrode arranged on the first end surface; and a second external electrode arranged on the second end surface, wherein the plurality of internal electrode layers comprises a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately arranged on different dielectric layers, and the plurality of first internal electrode layers comprises a plurality of first opposing electrodes opposite to the second internal electrode layers. The first lead portion includes a first connecting portion connected to the first lead portion on different dielectric layers located at least on the first main surface side or at least on the second main surface side, and a second connecting portion connected to the second lead portion on different dielectric layers located at least on the first main surface side or at least on the second main surface side, and a second connecting portion connected to the second lead portion on different dielectric layers located at least on the first main surface side or at least on the second main surface side.

[0013] According to the multilayer ceramic capacitor of the present invention, the first lead portion of the first internal electrode layer has a first connection portion configured to connect to at least two or more first lead portions in the stacking direction between the first lead portions arranged on different dielectric layers located on at least one of the first main surface side and the second main surface 12b side, and the second lead portion of the second internal electrode layer has a second connection portion configured to connect to at least two or more second lead portions in the stacking direction between the second lead portions arranged on different dielectric layers located on at least one of the first main surface side and the second main surface side. Therefore, in the first lead portion of the first internal electrode layer and the second lead portion of the second internal electrode layer located on both main surface sides of the multilayer ceramic capacitor where peeling easily occurs, the adhesion strength between the first lead portions located on different dielectric layers and between the second lead portions located on different dielectric layers can be improved. As a result, even if a spherical phenomenon occurs in which the internal electrode layers condense in the lateral direction and expand in the height direction and increase in thickness due to the heat during firing of the stack, the internal electrode layers can be firmly connected to each other in the parts of the two end surfaces of the stack and the internal electrode layers on the two main surface sides where peeling is likely to occur, thereby suppressing the occurrence of peeling between the internal electrode layers.

[0014] Effects of the Invention

[0015] According to the present invention, it is possible to provide a multilayer ceramic capacitor which can suppress the occurrence of separation between internal electrode layers at the end of a multilayer body even when the dielectric layer and the like are thinned.

[0016] The above objects, other objects, features and advantages of the present invention will become more apparent from the following description of specific embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is an external perspective view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention.

[0018] Figure 2 It is a front view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention.

[0019] Figure 3 yes Figure 1 Cross-sectional view at line III-III.

[0020] Figure 4 yes Figure 1 Cross-sectional view at line IV-IV.

[0021] Figure 5 yes Figure 3 Cross-sectional view at line VV of .

[0022] Figure 6 It is shown Figure 3 FIG. 1 is an enlarged view of the structure of the connection portion of the two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention in region R1.

[0023] Figure 7 It is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention.

[0024] Figure 8 It is a plan view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention.

[0025] Fig. 9 It is a front view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention.

[0026] Fig.10 yes Figure 7 Cross-sectional view at line XX.

[0027] Fig.11 yes Figure 7 A cross-sectional view taken along line XI-XI.

[0028] Fig.12 yes Fig.11 A cross-sectional view taken along line XI-XI.

[0029] Fig.13 yes Fig.11 A sectional view taken along line XII-XII. DETAILED DESCRIPTION

[0030] A. First embodiment

[0031] 1. Two-terminal multilayer ceramic capacitors

[0032] As a laminated ceramic capacitor according to a first embodiment of the present invention, referring to Figures 1 to 5 The two-terminal multilayer ceramic capacitor 10 will be described.

[0033] Figure 1 It is an external perspective view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 2 It is a front view showing an example of a two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention. Figure 3 yes Figure 1 Cross-sectional view at line III-III. Figure 4 yes Figure 1 Cross-sectional view at line IV-IV. Figure 5 yes Figure 3 Cross-sectional view at line VV of . Figure 6 It is shown Figure 3 FIG. 1 is an enlarged view of the structure of the connection portion of the two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention in region R1.

[0034] like Figures 1 to 4 As shown, the two-terminal multilayer ceramic capacitor 10 includes a multilayer body 12 and an external electrode 30 disposed on the surface of the multilayer body 12 .

[0035] like Figures 1 to 4 As shown, the two-terminal multilayer ceramic capacitor 10 includes a rectangular parallelepiped multilayer body 12 and external electrodes 30 disposed at both ends of the multilayer body 12 .

[0036] The laminate 12 has a plurality of laminated dielectric layers 14 and a plurality of internal electrode layers 16 laminated on the dielectric layers 14. Furthermore, the laminate 12 has a first main surface 12a and a second main surface 12b opposite to each other in a lamination direction x, a first side surface 12c and a second side surface 12d opposite to each other in a width direction y orthogonal to the lamination direction x, and a first end surface 12e and a second end surface 12f opposite to each other in a length direction z orthogonal to the lamination direction x and the width direction y. In the laminate 12, the corners and the ridges are rounded. In addition, the so-called corners are the portions where three adjacent faces of the laminate intersect, and the so-called ridges are the portions where two adjacent faces of the laminate intersect. In addition, the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f may be partially or entirely formed with concave and convex portions. The dielectric layer 14 and the internal electrode layer 16 are stacked in the height direction.

[0037] The laminate 12 has an inner layer portion 18 composed of a single or multiple dielectric layers 14 and multiple internal electrode layers 16 arranged thereon. The internal electrode layer 16 has a first internal electrode layer 16a extending to a first end face 12e and a second internal electrode layer 16b extending to a second end face 12f. In the inner layer portion 18, multiple first internal electrode layers 16a and second internal electrode layers 16b are opposed to each other with the dielectric layer 14 interposed therebetween.

[0038] The stacked body 12 has a first main surface side outer layer portion 20a, which is located on the first main surface 12a side and is formed by a plurality of dielectric layers 14 located between the first main surface 12a and the outermost surface of the inner layer portion 18 on the first main surface 12a side and a straight line on the outermost surface.

[0039] Similarly, the stack 12 has a second main surface side outer layer portion 20b, which is located on the second main surface 12b side and is formed by a plurality of dielectric layers 14 located between the second main surface 12b and the outermost surface of the inner layer portion 18 on the second main surface 12b side and a straight line on the outermost surface.

[0040] The laminate 12 has a first side surface side outer layer portion 22a located on the first side surface 12c side and formed of a plurality of dielectric layers 14 located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side.

[0041] Similarly, the laminate 12 has a second side outer layer portion 22b located on the second side 12d side and formed of a plurality of dielectric layers 14 located between the second side 12d and the outermost surface of the inner layer portion 18 on the second side 12d side.

[0042] In addition, the first side surface outer layer portion 22a and the second side surface outer layer portion 22b are also referred to as W gaps or side gaps.

[0043] The laminate 12 has a first end surface side outer layer portion 24a located on the first end surface 12e side and formed of a plurality of dielectric layers 14 located between the first end surface 12e and the outermost surface of the inner layer portion 18 on the first end surface 12e side.

[0044] Similarly, the laminate 12 has a second end surface side outer layer portion 24b located on the second end surface 12f side and formed of a plurality of dielectric layers 14 located between the second end surface 12f and the outermost surface of the inner layer portion 18 on the second end surface 12f side.

[0045] The first end surface side outer layer portion 24 a and the second end surface side outer layer portion 24 b are also referred to as L gaps or end gaps.

[0046] The first main surface side outer layer portion 20a is located on the first main surface 12a side of the stacked body 12, and is an aggregate of a plurality of dielectric layers 14 located between the first main surface 12a and the internal electrode layer 16 closest to the first main surface 12a. The dielectric layer 14 used in the first main surface side outer layer portion 20a may be the same as the dielectric layer 14 used in the internal layer portion 18.

[0047] The second principal surface side outer layer portion 20 b is located on the second principal surface 12 b side of the laminate 12 and is an assembly of a plurality of dielectric layers 14 located between the second principal surface 12 b and the internal electrode layer 16 closest to the second principal surface 12 b .

[0048] For example, the dielectric layer 14 can be formed of a dielectric material as a ceramic material. As such a dielectric material, for example, BaTiO 3 、CaTiO 3 、SrTiO 3 or CaZrO 3 In the case of containing the above dielectric material as a main component, depending on the desired properties of the laminate 12, for example, a material to which a secondary component such as a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound is added in an amount less than the main component may be used.

[0049] The size of the laminate 12 is not particularly limited.

[0050] For example, the dielectric layer 14 can be formed of a dielectric material as a ceramic material. As such a dielectric material, for example, BaTiO 3 、CaTiO 3 、SrTiO 3 or CaZrO3 In the case of containing the above dielectric material as a main component, depending on the desired properties of the laminate 12, for example, a material to which a secondary component such as a Mn compound, a Fe compound, a Cr compound, a Co compound, or a Ni compound is added in an amount less than the main component may be used.

[0051] The thickness of dielectric layer 14 in laminated body 12 after firing is preferably about 0.5 μm or more and 10.0 μm or less.

[0052] The number of laminated dielectric layers 14 is preferably 15 or more and 700 or less. However, the number of dielectric layers 14 is the sum of the number of dielectric layers 14 constituting the inner layer portion 18 and the number of dielectric layers constituting the first main surface side outer layer portion 20a and the second main surface side outer layer portion 20b.

[0053] The stacked body 12 includes a plurality of first internal electrode layers 16a and a plurality of second internal electrode layers 16b as the plurality of internal electrode layers 16. The plurality of first internal electrode layers 16a and the plurality of second internal electrode layers 16b are buried substantially parallel to the first main surface 12a and the second main surface 12b, and are alternately arranged with the dielectric layer 14 interposed therebetween along the stacking direction x of the stacked body 12.

[0054] The first internal electrode layer 16a is arranged on the plurality of dielectric layers 14 and is located inside the stacked body 12. The first internal electrode layer 16a includes a first opposing electrode portion 26a opposed to the second internal electrode layer 16b, and a first lead portion 28a located on one end side of the first internal electrode layer 16a and extending from the first opposing electrode portion 26a to the first end surface 12e of the stacked body 12. Therefore, the ends of the plurality of first lead portions 28a are led out to the surface of the first end surface 12e and exposed from the stacked body 12.

[0055] The shape of the first counter electrode portion 26a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in a plan view. However, the corners may be rounded in a plan view, or the corners may be inclined (conical) in a plan view. In addition, the shape may be a cone in a plan view that is inclined in any direction.

[0056] The shape of the first lead portion 28a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in a plan view. However, the corners may be rounded in a plan view, or may be inclined (tapered) in a plan view. In addition, the shape may be tapered in a plan view with an inclination in any direction.

[0057] The width of the first counter electrode portion 26a of the first internal electrode layer 16a and the width of the first lead portion 28a of the first internal electrode layer 16a may be formed to be the same width, or one of the widths may be formed to be smaller.

[0058] The second internal electrode layer 16b is arranged on the plurality of dielectric layers 14 and is located inside the stacked body 12. The second internal electrode layer 16b includes a second opposing electrode portion 26b opposed to the first internal electrode layer 16a, and a second lead portion 28b located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 26b to the second end face 12f of the stacked body 12. Therefore, the ends of the plurality of second lead portions 28b are led out to the surface of the second end face 12f and exposed from the stacked body 12.

[0059] The shape of the second counter electrode portion 26b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in a plan view. However, the corners may be rounded in a plan view, or the corners may be inclined (conical) in a plan view. In addition, the shape may be tapered in a plan view with an inclination in any direction.

[0060] The shape of the second lead portion 28b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in a plan view. However, the corners may be rounded in a plan view, or the corners may be inclined (tapered) in a plan view. In addition, the shape may be tapered in a plan view with an inclination in any direction.

[0061] The width of the second counter electrode portion 26b of the second internal electrode layer 16b and the width of the second lead portion 28b of the second internal electrode layer 16b may be formed to be the same width, or one of the widths may be formed to be smaller.

[0062] Here, in Figure 6 In Figure 3 The structure of the connection portion of the two-terminal multilayer ceramic capacitor according to the first embodiment of the present invention in the region R1.

[0063] The first lead portion 28a includes a first connecting portion 29a that connects the first lead portions 28a disposed on different dielectric layers 14 located on at least one of the first main surface 12a side and the second main surface 12b side and is disposed across at least two first lead portions 28a in the stacking direction.

[0064] The second lead portion 28b includes a second connecting portion 29b that connects the second lead portions 28b arranged on different dielectric layers 14 located on at least one of the first main surface 12a side and the second main surface 12b side so as to span at least two or more second lead portions 28b in the stacking direction.

[0065] The first connection portion 29a is preferably located closer to the first end surface 12e than 1 / 2 of the dimension of the first end surface side outer layer portion 24a in the longitudinal direction z.

[0066] The second connection portion 29b is preferably located closer to the second end surface 12f than 1 / 2 of the dimension of the second end surface side outer layer portion 24b in the longitudinal direction z.

[0067] This can further improve the adhesion strength between the internal electrode layers 16 directly at the location where stress concentration caused by the spheroidization phenomenon in which the internal electrode layers 16 aggregate in the lateral direction and expand in the height direction due to the heat during firing of the stack 12 is most likely to occur.

[0068] It is preferable that a plurality of first connection portions 29a exist.

[0069] It is preferable that a plurality of second connection portions 29b exist.

[0070] This can further improve the adhesion strength between the internal electrode layers 16 directly at the location where stress concentration caused by the spheroidization phenomenon in which the internal electrode layers 16 aggregate in the lateral direction and expand in the height direction due to the heat during firing of the stack 12 is most likely to occur.

[0071] The first connecting portion 29a is preferably located on the first main surface 12a side of the inner layer portion 18 excluding the central portion in the stacking direction and on the second main surface 12b side of the inner layer portion 18 excluding the central portion in the stacking direction.

[0072] The second connecting portion 29b is preferably located on the first main surface 12a side except the center portion of the inner layer portion 18 in the stacking direction x and on the second main surface 12b side except the center portion of the inner layer portion 18 in the stacking direction.

[0073] Thus, it is possible to suppress the occurrence of peeling between the internal electrode layers 16 while maintaining the ceramic strength of the laminated body 12 at the portion where the lead portion of the internal electrode layer 16 is located in the central portion in the stacking direction of the inner layer portion 18. Therefore, while suppressing the occurrence of peeling between the internal electrode layers 16, it is also possible to suppress the occurrence of breakage, chipping, cracking, etc. in the laminated body 12 of the two-terminal type laminated ceramic capacitor 10 when an external impact is applied to the two-terminal type laminated ceramic capacitor 10.

[0074] At this time, the dimension t in the stacking direction of the center portion of the inner layer portion 18 in the stacking direction x, which is the region where the first connecting portion 29a is not arranged, is 2 The dimension t of the inner layer portion 18 in the lamination direction is preferably 1 more than 25% and less than 75% of the total.

[0075] In addition, the dimension t in the stacking direction of the center portion of the inner layer portion 18 in the stacking direction, which is the region where the second connecting portion 29b is not arranged, is 2 The dimension t of the inner layer portion 18 in the lamination direction is preferably 1 more than 25% and less than 75% of the total.

[0076] Here, the dimension t in the stacking direction of the center portion in the stacking direction of the inner layer portion 18 in the region where the first connecting portion 29a and the second connecting portion 29b are not arranged is 2 becomes smaller than the dimension t of the inner layer portion 18 in the stacking direction 1 When the external impact is applied to the two-terminal multilayer ceramic capacitor 10, the laminated body 12 of the two-terminal multilayer ceramic capacitor 10 may be damaged, chipped, cracked, etc. In addition, the dimension t in the stacking direction of the center portion of the inner layer portion 18 in the stacking direction in the region where the first connecting portion 29a and the second connecting portion 29b are not arranged is 2 becomes larger than the dimension t of the inner layer portion 18 in the stacking direction 1 In the case of 75% of the cases, in the lead-out portions of the internal electrode layer 16 of the inner layer portion 18 located on the main surface side outer layer portion 20a, 20b side of the two-terminal multilayer ceramic capacitor 10 which is prone to peeling, the adhesion strength of the internal electrode layers 16 between the first lead-out portions 28a located on different dielectric layers 14 and between the second lead-out portions 28b located on different dielectric layers 14 cannot sometimes be sufficiently ensured.

[0077] The dimension of the first connecting portion 29a in the length direction z connecting the first end face 12e and the second end face 12f is preferably 3% to 97% of the thickness of the first lead portion 28a of the first internal electrode layer 16a.

[0078] The dimension of the second connecting portion 29b in the length direction z connecting the first end face 12e and the second end face 12f is preferably 3% to 97% of the thickness of the second lead portion 28b of the second internal electrode layer 16b.

[0079] As a result, the resistance becomes higher than that of the internal electrode layer 16 and current is less likely to flow, so that it is possible to prevent the change in electrical characteristics due to the first connecting portion 29 a and the second connecting portion 29 b and suppress separation between the internal electrode layers 16 .

[0080] The first connecting portion 29a and the second connecting portion 29b may be formed in the width direction y in the region where the first internal electrode layer 16a and the second internal electrode layer 16b of the two-terminal multilayer ceramic capacitor 10 are arranged. Figure 5 The arrangement may be continuous or discontinuous, although this is not shown.

[0081] The first connecting portion 29 a and the second connecting portion 29 b are preferably concentrated in the center of the two-terminal multilayer ceramic capacitor 10 in the width direction y.

[0082] Thus, the adhesion strength between the internal electrode layers 16 can be more reliably ensured in the central portion of the two-terminal multilayer ceramic capacitor 10 in the width direction y.

[0083] The first connection portion 29a and the second connection portion 29b are confirmed by the method described below.

[0084] That is, the two-terminal multilayer ceramic capacitor 10 is ground to a position 1 / 2W of the dimension in the width direction y of the two-terminal multilayer ceramic capacitor 10 so as to be parallel to the first side surface 12c or the second side surface 12d, and the LT cross section is exposed. Then, the exposed LT cross section is observed, and the first connecting portion 29a and the second connecting portion 29b are confirmed using an electron microscope.

[0085] The measurement method of the dimension of the first connection portion 29a and the second connection portion 29b in the length direction z connecting the first end surface 12e and the second end surface 12f is performed by the method described below.

[0086] That is, to measure the length z dimension of the first connecting portion 29a and the second connecting portion 29b, first, the two-terminal multilayer ceramic capacitor 10 is ground to a position 1 / 2W of the width y dimension of the two-terminal multilayer ceramic capacitor 10 so as to be parallel to the first side surface 12c or the second side surface 12d, and the LT cross section is exposed. Thereafter, the exposed LT cross section is observed, and the first connecting portion 29a and the second connecting portion 29b are observed using an electron microscope to measure the length z dimension of the first connecting portion 29a and the second connecting portion 29b.

[0087] Specifically, in the internal electrode layer 16 located on the side of the first principal surface 12a, the dimension of the length direction z of the first connecting portion 29a and the second connecting portion 29b connecting the first end face 12e and the second end face 12f from the first principal surface 12a toward the second principal surface 12b to the 10th layer is measured, or, in the internal electrode layer 16 located on the side of the second principal surface 12b, the dimension of the length direction z of the first connecting portion 19a and the second connecting portion 29b connecting the first end face 12e and the second end face 12f is measured, and the averaged value is set as the dimension of the length direction z of the first connecting portion 29a and the second connecting portion 29b.

[0088] The first internal electrode layer 16 a and the second internal electrode layer 16 b can be formed of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals such as an Ag—Pd alloy.

[0089] The thickness of each of the first internal electrode layer 16 a and the second internal electrode layer 16 b is not particularly limited, but is preferably about 0.4 μm or more and 0.8 μm or less, for example.

[0090] The number of each of the first internal electrode layer 16 a and the second internal electrode layer 16 b is not particularly limited, but the total number is preferably 2 or more and 1000 or less.

[0091] The first internal electrode layer 16 a and the second internal electrode layer 16 b can be formed of an appropriate conductive material such as a metal such as Ni, Cu, Ag, Pd, Au, or an alloy containing at least one of these metals such as an Ag—Pd alloy.

[0092] Then, if Figures 1 to 4 As shown, the external electrodes 30 are provided on the first side surface 12 c and the second side surface 12 d and the first end surface 12 e and the second end surface 12 f of the laminate 12 .

[0093] The external electrode 30 includes a first external electrode 30 a and a second external electrode 30 b .

[0094] The first external electrode 30a is connected to the first internal electrode layer 16a and is disposed at least on the surface of the first end surface 12e. In addition, the first external electrode 30a extends from the first end surface 12e of the stacked body 12 and is also disposed on a portion of the first main surface 12a and a portion of the second main surface 12b, and a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first lead portion 28a of the first internal electrode layer 16a.

[0095] The second external electrode 30b is connected to the second internal electrode layer 16b and is disposed at least on the surface of the second end surface 12f. In addition, the second external electrode 30b extends from the second end surface 12f and is also disposed on a portion of the first main surface 12a and a portion of the second main surface 12b, and a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second lead portion 28b of the second internal electrode layer 16b.

[0096] In the laminate 12, an electrostatic capacitor is formed by the first opposing electrode portion 26a of the first internal electrode layer 16a and the second opposing electrode portion 26b of the second internal electrode layer 16b being opposed to each other via the dielectric layer 14. Therefore, an electrostatic capacitor can be obtained between the first external electrode 30a connected to the first internal electrode layer 16a and the second external electrode 30b connected to the second internal electrode layer 16b, thereby exhibiting the characteristics of a capacitor.

[0097] The external electrode 30 includes a base electrode layer 32 including a metal component and a glass component, and a plating layer 34 formed on the surface of the base electrode layer 32 .

[0098] The first external electrode 30a preferably includes a first foundation electrode layer 32a disposed on the surface of the first end surface 12e, and includes a first plating layer 34a disposed on the surface of the first foundation electrode layer 32a.

[0099] The second external electrode 30b preferably includes a second foundation electrode layer 32b disposed on the surface of the second end surface 12f, and includes a second plating layer 34b disposed on the surface of the second foundation electrode layer 32b.

[0100] The foundation electrode layer 32 includes a first foundation electrode layer 32 a and a second foundation electrode layer 32 b .

[0101] The first foundation electrode layer 32a is disposed on the surface of the first end surface 12e of the laminate 12, and is formed to extend from the first end surface 12e to cover a portion of each of the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d.

[0102] The second foundation electrode layer 32b is disposed on the surface of the second end surface 12f of the laminate 12, and is formed so as to extend from the second end surface 12f to cover a portion of each of the first main surface 12a, the second main surface 12b, the first side surface 12c, and the second side surface 12d.

[0103] Alternatively, the first foundation electrode layer 32 a may be disposed only on the surface of the first end face 12 e of the stacked body 12 , and the second foundation electrode layer 32 b may be disposed only on the surface of the second end face 12 f of the stacked body 12 .

[0104] The base electrode layer 32 includes at least one selected from a sintered layer, a conductive resin layer, a thin film layer, and the like.

[0105] Hereinafter, each structure in the case where the base electrode layer 32 is set as the above-mentioned sintered layer, conductive resin layer, and thin film layer will be described.

[0106] The sintered layer contains a glass component and a metal component. The glass component of the sintered layer contains at least one selected from B, Si, Ba, Mg, Al, Li, etc. As the metal component of the sintered layer, for example, it contains at least one selected from Cu, Ni, Ag, Pd, Ag-Pd alloy, Au, etc. The sintered layer is obtained by applying a conductive paste containing a glass component and a metal component to the stacked body 12 and sintering it. The sintered layer can be obtained by simultaneously firing a stacked chip having an internal electrode layer 16 and a dielectric layer 14 and a conductive paste applied to the stacked chip, or it can be obtained by firing a stacked chip having an internal electrode layer 16 and a dielectric layer 14 to obtain a stacked body and then sintering the conductive paste to the stacked body.

[0107] When the laminated small pieces having the internal electrode layer 16 and the dielectric layer 14 are fired simultaneously with the conductive paste applied to the laminated small pieces, the fired layer is preferably formed by firing a material to which a dielectric material is added instead of a glass component.

[0108] The sintered layer can also be multi-layered.

[0109] When the first foundation electrode layer 32a is formed of a sintered layer, the thickness of the first foundation electrode layer 32a at the center of the first end surface 12e in the stacking direction x is preferably about 3 μm or more and 100 μm or less, for example.

[0110] When the second foundation electrode layer 32b is formed by a sintered layer, the thickness of the second foundation electrode layer 32b at the center of the second end surface 12f in the stacking direction x is preferably about 3 μm or more and 100 μm or less, for example.

[0111] In addition, in the case where the base electrode layer 32 is provided on the first main surface 12a and the second main surface 12b by sintering the layer, the thickness of the first base electrode layer 32a located on the first main surface 12a and the second main surface 12b at the central portion of the longitudinal direction z in the direction connecting the first main surface 12a and the second main surface 12b is, for example, preferably greater than 3 μm and less than 70 μm, and the thickness of the second base electrode layer 32b located on the first main surface 12a and the second main surface 12b at the central portion of the longitudinal direction z in the direction connecting the first main surface 12a and the second main surface 12b is, for example, preferably greater than 3 μm and less than 70 μm.

[0112] Furthermore, in the case where the base electrode layer 32 is provided on the first side surface 12c and the second side surface 12d by sintering the layer, the thickness of the first base electrode layer 32a located on the first side surface 12c and the second side surface 12d at the central portion in the longitudinal direction z in the direction connecting the first side surface 12c and the second side surface 12d is, for example, preferably greater than 10 μm and less than 100 μm, and the thickness of the second base electrode layer 32b located on the first side surface 12c and the second side surface 12d at the central portion in the longitudinal direction z in the direction connecting the first side surface 12c and the second side surface 12d is, for example, preferably greater than 10 μm and less than 100 μm.

[0113] When a conductive resin layer is provided as the base electrode layer 32, the conductive resin layer may be arranged on the sintered layer so as to cover the sintered layer, or directly arranged on the laminate 12. However, the conductive resin layer may be arranged only on the base electrode layer 32 located on both end surfaces 12e and 12f.

[0114] The conductive resin layer contains metal and thermosetting resin.

[0115] The conductive resin layer may completely cover the base electrode layer or may cover a portion of the base electrode layer.

[0116] Since the conductive resin layer contains a thermosetting resin, it is more flexible than a conductive layer containing, for example, a plated film or a fired product of a conductive paste. Therefore, even when a physical impact or an impact caused by a thermal cycle is applied to the two-terminal multilayer ceramic capacitor 10, the conductive resin layer functions as a buffer layer and can prevent cracks from being generated in the two-terminal multilayer ceramic capacitor 10.

[0117] As the metal contained in the conductive resin layer, Ag, Cu, Ni, Sn, Bi, or an alloy containing these can be used.

[0118] In addition, metal powder coated with Ag on the surface of the metal powder can also be used. When using metal powder coated with Ag on the surface of the metal powder, it is preferred to use Cu, Ni, Sn, Bi or their alloy powder as the metal powder. In addition, materials subjected to oxidation resistance treatment on Cu and Ni can also be used. The reason for using Ag conductive metal powder as the conductive metal is that the metal of the base material can be made of a cheap metal while maintaining the above-mentioned characteristics of Ag.

[0119] The metal contained in the conductive resin layer preferably accounts for 35 vol % or more and 75 vol % or less relative to the volume of the entire conductive resin.

[0120] The average particle size of the metal contained in the conductive resin layer is not particularly limited. For example, the average particle size of the conductive filler may be about 0.3 μm or more and 10 μm or less.

[0121] The metal contained in the conductive resin layer is mainly responsible for the conductivity of the conductive resin layer. Specifically, the conductive fillers are in contact with each other, thereby forming a conductive path inside the conductive resin layer.

[0122] The metal contained in the conductive resin layer may be a spherical metal, a flat metal, or the like, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0123] As the resin of the conductive resin layer, various known thermosetting resins such as epoxy resin, phenolic resin, polyurethane resin, silicone resin, polyimide resin, etc. can be used. Among them, epoxy resin is one of the most suitable resins because of its excellent heat resistance, moisture resistance, adhesion, etc.

[0124] In addition, the conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol, amine, anhydride, imidazole, active ester, and amide-imide can be used as the curing agent for the epoxy resin.

[0125] The conductive resin layer may be a multi-layered layer.

[0126] The thickness of the conductive resin layer located at the first end surface 12 e and the second end surface 12 f and located at the center of the stacking direction x of the stacked body 12 is preferably about 10 μm or more and 150 μm or less, for example.

[0127] The thin film layer is formed by a thin film forming method such as sputtering or vapor deposition, and is a layer of 1 μm or less in which metal particles are deposited.

[0128] The plating layer 34 includes a first plating layer 34 a and a second plating layer 34 b .

[0129] The first plating layer 34a is arranged to cover the surface of the first foundation electrode layer 32a.

[0130] The second plating layer 34b is arranged to cover the surface of the second foundation electrode layer 32b.

[0131] The plating layer 34 may include at least one metal selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0132] The plating layer 34 may be formed of a single layer or a plurality of layers. In the case of forming a plurality of layers, for example, a two-layer structure of Ni plating and Sn plating is preferred. By setting the layer directly in contact with the base electrode layer as a plating layer including Ni plating, especially when the base electrode layer is a conductive resin layer, when mounting the laminated ceramic capacitor, the base electrode layer can be prevented from being corroded by the solder used for mounting.

[0133] Furthermore, by providing a plated layer composed of Sn plating as an upper layer of a plated layer composed of Ni plating, when mounting the two-terminal multilayer ceramic capacitor 10 on a mounting substrate, wettability of solder used for mounting can be improved, thereby facilitating mounting.

[0134] The thickness of each of the plating layers 34 is preferably 1.0 μm or more and 15.0 μm or less.

[0135] Alternatively, the external electrode 30 may be formed only of a plating layer without providing the base electrode layer 32 .

[0136] Although not shown in the drawings, a structure in which the base electrode layer 32 is not provided but the plating layer is provided will be described below.

[0137] The first external electrode 30a and the second external electrode 30b may be formed with a plated layer directly on the surface of the laminate 12 without providing a base electrode layer. That is, the two-terminal laminated ceramic capacitor 10 may also have a structure including a plated layer electrically connected to the first internal electrode layer 16a or the second internal electrode layer 16b. In such a case, the plated layer may be formed after a catalyst is provided on the surface of the laminate 12 as a pretreatment.

[0138] In addition, when a plating layer is formed directly on the stack without providing a base electrode layer, the height can be reduced, i.e., the thickness can be thinned, according to the amount by which the thickness of the base electrode layer is reduced, or the amount by which the thickness of the base electrode layer is reduced can be converted into the thickness of the stack, i.e., the thickness of the effective layer portion, thereby increasing the design freedom of the thickness of the stack 12.

[0139] The plating layer preferably includes a lower plating electrode formed on the surface of the laminate 12 and an upper plating electrode formed on the surface of the lower plating electrode. The lower plating electrode and the upper plating electrode each preferably include at least one metal selected from, for example, Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, or Zn, or an alloy containing the metal.

[0140] Furthermore, the lower-layer plated electrode is preferably formed using Ni having a solder barrier property, and the upper-layer plated electrode is preferably formed using Sn or Au having good solder wettability.

[0141] In addition, for example, when Ni is used to form the first internal electrode layer 16a and the second internal electrode layer 16b, the lower plated electrode is preferably formed using Cu having good bonding properties with Ni. In addition, the upper plated electrode can be formed as needed, and the first external electrode 30a and the second external electrode 30b can also be composed of only the lower plated electrode. The plated layer can be the upper plated electrode as the outermost layer, or other plated electrodes can be formed on the surface of the upper plated electrode.

[0142] Here, when the external electrode 30 is formed only of a plating layer without providing the base electrode layer 32 , the thickness of each plating layer arranged without providing the base electrode layer 32 is preferably 1.0 μm to 15.0 μm.

[0143] Furthermore, the plating layer preferably does not contain glass. The metal ratio per unit volume of the plating layer is preferably 99 volume % or more.

[0144] The dimension of the two-terminal multilayer ceramic capacitor 10 in the length direction z including the stack 12, the first external electrode 30a and the second external electrode 30b is set to L dimension, the dimension of the two-terminal multilayer ceramic capacitor 10 in the stacking direction x including the stack 12, the first external electrode 30a and the second external electrode 30b is set to T dimension, and the dimension of the two-terminal multilayer ceramic capacitor 10 in the width direction y including the stack 12, the first external electrode 30a and the second external electrode 30b is set to W dimension.

[0145] The dimensions of the two-terminal multilayer ceramic capacitor 10 are L dimension in the length direction z of 0.2 mm to 11.0 mm, W dimension in the width direction y of 0.1 mm to 11.0 mm, and T dimension in the stacking direction x of 0.1 mm to 11.0 mm. The dimensions of the two-terminal multilayer ceramic capacitor 10 can be measured using a microscope.

[0146] exist Figure 1In the two-terminal multilayer ceramic capacitor 10 shown, the first lead portion 28a of the first internal electrode layer 16a has a first connecting portion 29a configured to connect to at least two or more first lead portions 28a in the stacking direction, and the second lead portion 28b of the second internal electrode layer 16b has a second connecting portion 29b configured to connect to at least two or more second lead portions 28b in the stacking direction, and the second lead portion 28b of the second internal electrode layer 16b has a second connecting portion 29b configured to connect to at least two or more second lead portions 28b in the stacking direction. Therefore, in the first lead portion 28a of the first internal electrode layer 16a and the second lead portion 28b of the second internal electrode layer 16b located on the main surface side outer layer portion 20a, 20b side where peeling is likely to occur of the two-terminal type multilayer ceramic capacitor 10, the adhesion strength between the first lead portions 28a located on different dielectric layers 14 and between the second lead portions 28b located on different dielectric layers 14 can be improved. As a result, even if a spherical phenomenon occurs in which the internal electrode layers 16 are aggregated in the lateral direction and expand in the stacking direction x to increase the thickness due to the heat during the firing of the laminated body 12, the internal electrode layers 16 can be firmly connected to each other in the portions of the two end surfaces 12e, 12f of the laminated body 12 and the main surface side outer layer portions 20a, 20b side where peeling is likely to occur, so that the occurrence of peeling between the internal electrode layers 16 can be suppressed.

[0147] 2. Method for manufacturing two-terminal multilayer ceramic capacitor

[0148] Next, a method for manufacturing a two-terminal multilayer ceramic capacitor will be described.

[0149] First, a dielectric sheet for a dielectric layer and a conductive paste for an internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0150] Then, when forming the dielectric sheet, a paste containing a dielectric is printed by inkjet printing to form the dielectric sheet. At this time, the dielectric sheet on which the pattern of the internal electrode layer is not printed is printed continuously. On the other hand, the dielectric sheet on which the pattern for the first internal electrode layer and the pattern for the second internal electrode layer are printed is printed discontinuously at the place where the first connecting part and the second connecting part are to be formed, and when the conductive paste for the internal electrode is printed by inkjet printing or screen printing, the conductive paste for the internal electrode is made to enter the discontinuous part, thereby forming the first connecting part and the second connecting part. At this time, by controlling the width of the discontinuous part in inkjet printing, the length direction dimension of the first connecting part and the second connecting part connecting the first end face and the second end face can be controlled.

[0151] In addition, regarding the dielectric sheet, a dielectric sheet for an outer layer on which the pattern of the internal electrode layer is not printed is also prepared.

[0152] Next, a predetermined number of dielectric sheets for outer layers without the pattern of the internal electrode layer printed thereon are stacked to form a portion of the second main surface side outer layer portion. Then, a dielectric sheet with the pattern of the first internal electrode layer printed thereon and a dielectric sheet with the pattern of the second internal electrode layer printed thereon are sequentially stacked on the portion of the second main surface side outer layer portion to form the structure of the present invention, thereby forming a portion of the inner layer portion. Thereafter, a predetermined number of dielectric sheets for outer layers without the pattern of the internal electrode layer printed thereon are further stacked on the portion of the inner layer portion to form a portion of the first main surface side outer layer portion. Thus, a laminated sheet is produced.

[0153] Next, the laminated sheets are pressed in the lamination direction by isostatic pressing or the like, thereby producing a laminated block.

[0154] Then, the stacked block is cut into a given size to cut out stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0155] Next, the stacked small pieces are fired to produce the stacked body 12. The firing temperature depends on the materials of the dielectric layer and the internal electrode layer, but is preferably 900°C or higher and 1400°C or lower.

[0156] (Formation of external electrodes)

[0157] (a) Sintered layer

[0158] In the following description, it is assumed that the base electrode layer is formed of a sintered layer. When forming the sintered layer, a conductive paste containing a glass component and a metal is prepared and applied, and then sintered to form the base electrode layer.

[0159] The first foundation electrode layer 32a of the first external electrode 30a and the second foundation electrode layer 32b of the second external electrode 30b are formed on the first end surface 12e and the second end surface 12f of the laminated body 12 obtained by firing.

[0160] When forming a sintered layer as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied by a dipping method, and then sintered to form a sintered layer as the base electrode layer 32. The temperature of the sintering treatment at this time is preferably 700° C. or higher and 900° C. or lower.

[0161] When the base electrode layer 32 is formed of a sintered layer, the sintered layer may contain a ceramic component. In this case, the ceramic component may be contained instead of the glass component, or both.

[0162] For example, the ceramic component is preferably a ceramic material of the same type as the laminate 12. In addition, when the sintered layer contains a ceramic component, it is preferred that a conductive paste is applied to the pre-sintered laminated small pieces, and the pre-sintered laminated small pieces and the conductive paste applied to the pre-sintered laminated small pieces are simultaneously sintered (fired) to form the laminate 12 having the sintered layer formed thereon. The temperature of the sintering treatment (firing temperature) at this time is preferably 900° C. or more and 1400° C. or less.

[0163] (b) Conductive resin layer

[0164] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of the calcined layer, or the conductive resin layer may be formed directly on the laminate 12 without forming a calcined layer.

[0165] A conductive resin paste containing a thermosetting resin and a metal component is applied to the sintered layer or the laminate 12, and heat-treated at a temperature of 250°C or more and 550°C or more to heat-cure the resin, thereby forming a conductive resin layer. The atmosphere during the heat treatment is preferably N 2 In order to prevent the resin from scattering and the oxidation of various metal components, the oxygen concentration is preferably suppressed to 100 ppm or less.

[0166] As a method for applying the conductive resin paste, similar to the method of forming the base electrode layer 32 from a sintered layer, for example, a method of applying the conductive resin paste by extruding it from a slit or a roll transfer method can be used.

[0167] (c) Thin film layer

[0168] In addition, when the base electrode layer 32 is formed by a thin film layer, the base electrode layer can be formed by covering the portion other than the desired portion where the external electrode 30 is to be formed by masking or the like, and performing a thin film forming method such as sputtering or evaporation on the exposed desired portion. The base electrode layer formed by a thin film layer is set to a layer of 1 μm or less in which metal particles are deposited.

[0169] (Plating electrode)

[0170] Furthermore, the external electrodes may be formed by using only the plated layers as the plated electrodes without providing the base electrode layer 32. In this case, the external electrodes may be formed by the following method.

[0171] Either or both of the first external electrode 30a and the second external electrode 30b may form a plating layer directly on the surface of the laminate 12 without providing the base electrode layer 32. That is, the two-terminal laminated ceramic capacitor 10 may also be a structure including a plating layer directly electrically connected to the first internal electrode layer 16a and the second internal electrode layer 16b. When performing the plating process, either electrolytic plating or electroless plating may be used, but electroless plating requires pretreatment with a catalyst or the like in order to increase the plating deposition rate, which has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferably used. As a plating method, drum plating is preferably used. In addition, the upper plating electrode formed on the surface of the lower plating electrode may also be formed in the same manner as required.

[0172] (Production of coating layer)

[0173] Next, a plating layer is formed on the surface of the base electrode layer 32 , the surface of the conductive resin layer, or the surface of the lower plating electrode or the surface of the upper plating electrode as necessary.

[0174] More specifically, in the present embodiment, Ni-plated layers and Sn-plated layers are formed as the plating layers 34 on the base electrode layer 32 as the sintered layer. The Ni-plated layers and the Sn-plated layers are formed successively by, for example, a drum plating method. When the plating process is carried out, any one of electrolytic plating and electroless plating can also be adopted. However, electroless plating needs to use the pre-treatment of a catalyst etc. in order to improve the plating precipitation speed, and there is a shortcoming that the process is complicated. Therefore, it is usually preferred to adopt electrolytic plating.

[0175] As described above, the two-terminal multilayer ceramic capacitor 10 according to the first embodiment is manufactured.

[0176] B. Second Embodiment

[0177] 1. Three-terminal multilayer ceramic capacitor

[0178] As a laminated ceramic capacitor according to a second embodiment of the present invention, referring to Figures 7 to 12 The three-terminal multilayer ceramic capacitor 110 will be described.

[0179] Figure 7 It is an external perspective view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Figure 8 It is a plan view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Fig. 9 It is a front view showing an example of a three-terminal multilayer ceramic capacitor according to a second embodiment of the present invention. Fig.10 yes Figure 7 Cross-sectional view at line XX. Fig.11 yes Figure 7 A cross-sectional view taken along line XI-XI. Fig.12 yes Fig.11 A cross-sectional view taken along line XI-XI. Fig.13 yes Fig.11 A sectional view taken along line XII-XII.

[0180] The laminate 12 includes a plurality of laminated dielectric layers 14 and a plurality of internal electrode layers 116 laminated on the dielectric layers 14. The dielectric layers 14 and the internal electrode layers 116 are laminated in the lamination direction x.

[0181] The stacked body 12 has the first main surface 12a and the second main surface 12b opposite on the stacking direction x, the first side surface 12c and the second side surface 12d opposite on the width direction y orthogonal to the stacking direction x, and the first end surface 12e and the second end surface 12f opposite on the length direction z orthogonal to the stacking direction x and the width direction y. In this stacked body 12, there are rounded corners at the corners and ridges. In addition, the so-called corner refers to the part where three adjacent faces of the stacked body intersect, and the so-called ridges refer to the part where two adjacent faces of the stacked body intersect. In addition, it is also possible to form concave-convex etc. on part or all of the first main surface 12a and the second main surface 12b, the first side surface 12c and the second side surface 12d, and the first end surface 12e and the second end surface 12f.

[0182] The laminate 12 has an inner layer portion 18 composed of a single or multiple dielectric layers 14 and multiple internal electrode layers 116 arranged thereon. The internal electrode layer 116 has a first internal electrode layer 116a extending to the first end face 12e and the second end face 12f and a second internal electrode layer 116b extending to the first side face 12c and the second side face 12d. In the inner layer portion 18, multiple first internal electrode layers 116a and second internal electrode layers 116b are opposed to each other with the dielectric layer 14 interposed therebetween.

[0183] The stacked body 12 has a first main surface side outer layer portion 20a, which is located on the first main surface 12a side and is formed by a plurality of dielectric layers 14 located between the first main surface 12a and the outermost surface of the inner layer portion 18 on the first main surface 12a side and a straight line on the outermost surface.

[0184] Similarly, the stack 12 has a second main surface side outer layer portion 20b, which is located on the second main surface 12b side and is formed by a plurality of dielectric layers 14 located between the second main surface 12b and the outermost surface of the inner layer portion 18 on the second main surface 12b side and a straight line on the outermost surface.

[0185] Furthermore, the laminate 12 has a first side surface side outer layer portion 22a located on the first side surface 12c side and formed of a plurality of dielectric layers 14 located between the first side surface 12c and the outermost surface of the inner layer portion 18 on the first side surface 12c side.

[0186] Similarly, the laminate 12 has a second side outer layer portion 22b located on the second side 12d side and formed of a plurality of dielectric layers 14 located between the second side 12d and the outermost surface of the inner layer portion 18 on the second side 12d side.

[0187] Furthermore, the laminate 12 has a first end surface side outer layer portion 24a located on the first end surface 12e side and formed of a plurality of dielectric layers 14 located between the first end surface 12e and the outermost surface of the inner layer portion 18 on the first end surface 12e side.

[0188] Similarly, the laminate 12 has a second end surface side outer layer portion 24b located on the second end surface 12f side and formed of a plurality of dielectric layers 14 located between the second end surface 12f and the outermost surface of the inner layer portion 18 on the second end surface 12f side.

[0189] The first principal surface side outer layer portion 20a is located on the first principal surface 12a side. The first principal surface side outer layer portion 20a is an aggregate of a plurality of dielectric layers 14 located between the first principal surface 12a and the internal electrode layer 116 closest to the first principal surface 12a.

[0190] The second principal surface side outer layer portion 20b is located on the second principal surface 12b side. The second principal surface side outer layer portion 20b is an aggregate of a plurality of dielectric layers 14 located between the second principal surface 12b and the internal electrode layer 116 closest to the second principal surface 12b.

[0191] The size of the laminate 12 is not particularly limited.

[0192] The material of the dielectric layer 14 is the same as that of the two-terminal multilayer ceramic capacitor 10 , and therefore the description thereof will be omitted.

[0193] The average thickness of the dielectric layer 14 in the stacking direction x after firing is also the same as that of the two-terminal multilayer ceramic capacitor 10 , and therefore the description thereof will be omitted.

[0194] The laminate 12 includes a plurality of first internal electrode layers 116a and a plurality of second internal electrode layers 116b as the plurality of internal electrode layers 116. The plurality of first internal electrode layers 116a and the plurality of second internal electrode layers 116b are buried so as to be alternately arranged at equal intervals along the lamination direction x of the laminate 12.

[0195] As shown in FIG16 , the first internal electrode layer 116a includes a first opposing electrode portion 126a opposed to the second internal electrode layer 116b, a first lead portion 128a led out from the first opposing electrode portion 126a to the surface of the first end face 12e of the laminate 12, and a second lead portion 128b led out from the first opposing electrode portion 126a to the surface of the second end face 12f of the laminate 12. Therefore, the ends of the plurality of first lead portions 128a are led out to the surface of the first end face 12e and exposed from the laminate 12, and the ends of the plurality of second lead portions 128b are led out to the surface of the second end face 12f and exposed from the laminate 12. Therefore, the first internal electrode layer 116a is not exposed on the surfaces of the first side face 12c and the second side face 12d of the laminate 12.

[0196] As shown in FIG. 17 , the second internal electrode layer 116b has a substantially cross shape and includes a second opposing electrode portion 126b opposing the first internal electrode layer 116a, a third lead portion 128c led from the second opposing electrode portion 126b to the surface of the first side surface 12c of the laminate 12, and a fourth lead portion 128d led from the second opposing electrode portion 126b to the surface of the second side surface 12d of the laminate 12. Therefore, the end of the third lead portion 128c is led to the surface of the first side surface 12c and exposed from the laminate 12, and the end of the fourth lead portion 128d is led to the surface of the second side surface 12d and exposed from the laminate 12. Therefore, the second internal electrode layer 116b is not exposed on the surface of the first end surface 12e and the surface of the second end surface 12f of the laminate 12.

[0197] In addition, the four corners of the second opposing electrode portion 126b in the second internal electrode layer 116b are not chamfered, but may be chamfered. This can prevent the corners of the first opposing electrode portion 126a of the first internal electrode layer 116a from overlapping, and can prevent electric field concentration. As a result, insulation breakdown of the ceramic capacitor that may occur due to electric field concentration can be prevented.

[0198] The first lead portion 128a includes a first connecting portion 129a that connects the first lead portions 128a arranged on different dielectric layers 14 located on at least one of the first main surface 12a side and the second main surface 12b side and is arranged to span at least two or more first lead portions 128a in the stacking direction.

[0199] The second lead portion 128b includes a second connecting portion 129b that connects the second lead portions 128b arranged on different dielectric layers 14 located on at least one of the first main surface 12a side and the second main surface 12b side and is arranged to span at least two or more second lead portions 128b in the stacking direction.

[0200] The third lead portion 128c includes a third connecting portion 129c connected between the third lead portions 128c arranged on different dielectric layers 14 located on at least one of the first main surface 12a side and the second main surface 12b side, and is arranged to span at least two or more third lead portions 128c in the stacking direction.

[0201] The fourth lead portion 128d includes a fourth connecting portion 129d connected between the fourth lead portions 128d arranged on different dielectric layers 14 located on at least one of the first main surface 12a side and the second main surface 12b side, and is connected to span at least two or more fourth lead portions 128d in the stacking direction.

[0202] The first connection portion 129a is preferably located closer to the first end surface 12e than 1 / 2 of the dimension of the first end surface side outer layer portion 24a in the longitudinal direction z.

[0203] The second connection portion 129b is preferably located closer to the second end surface 12f than 1 / 2 of the dimension of the second end surface side outer layer portion 24b in the longitudinal direction z.

[0204] The third connection portion 129c is preferably located closer to the first end surface 12e than 1 / 2 of the dimension of the first side surface outer layer portion 22a in the longitudinal direction z.

[0205] The fourth connection portion 129d is preferably located closer to the second end surface 12f than 1 / 2 of the dimension of the second side surface outer layer portion 22b in the longitudinal direction z.

[0206] As a result, the adhesion strength between the internal electrode layers 116 can be directly further improved at the location where stress concentration caused by the spherical phenomenon that causes the internal electrode layers 116 to aggregate in the lateral direction and expand in the stacking direction x to increase thickness due to the heat during firing of the stack 12 is most likely to occur.

[0207] It is preferable that there are a plurality of first connection portions 129a.

[0208] It is preferable that a plurality of second connection portions 129b exist.

[0209] It is preferable that a plurality of third connection parts 129c exist.

[0210] It is preferable that a plurality of fourth connection portions 129d exist.

[0211] As a result, the adhesion strength between the internal electrode layers 116 can be directly further improved at the location where stress concentration caused by the spherical phenomenon that causes the internal electrode layers 116 to aggregate in the lateral direction and expand in the stacking direction x to increase thickness due to the heat during firing of the stack 12 is most likely to occur.

[0212] The first connection portion 129a is preferably located on the first main surface 12a side of the inner layer portion 18 excluding the central portion in the stacking direction and on the second main surface 12b side of the inner layer portion 18 excluding the central portion in the stacking direction.

[0213] The second connection portion 129b is preferably located on the first main surface 12a side except the central portion in the stacking direction of the inner layer portion 18 and on the second main surface 12b side except the central portion in the stacking direction of the inner layer portion 18.

[0214] The third connection portion 129c is preferably located on the first main surface 12a side except the central portion in the stacking direction of the inner layer portion 18 and on the second main surface 12b side except the central portion in the stacking direction of the inner layer portion 18.

[0215] The fourth connecting portion 129d is preferably located on the first main surface 12a side except the central portion in the stacking direction of the inner layer portion 18 and on the second main surface 12b side except the central portion in the stacking direction of the inner layer portion 18.

[0216] Thus, it is possible to suppress the occurrence of peeling between the internal electrode layers 116 while maintaining the ceramic strength of the laminated body 12 at the portion where the lead portion of the internal electrode layer 116 is located in the central portion in the stacking direction of the inner layer portion 18. Therefore, while suppressing the occurrence of peeling between the internal electrode layers 116, it is also possible to suppress the occurrence of damage, chipping, cracking, etc. in the laminated body 12 of the three-terminal laminated ceramic capacitor 110 when an external impact is applied to the three-terminal laminated ceramic capacitor 110.

[0217] At this time, the dimension t in the stacking direction of the center portion of the inner layer portion 18 in the stacking direction, which is the region where the first connecting portion 129a is not arranged, is 2 The dimension t of the inner layer portion 18 in the lamination direction is preferably 1 more than 25% and less than 75% of the total.

[0218] The dimension t in the stacking direction of the center portion of the inner layer portion 18 in the stacking direction in the region where the second connecting portion 129b is not arranged is2 The dimension t of the inner layer portion 18 in the lamination direction is preferably 1 more than 25% and less than 75% of the total.

[0219] The dimension t in the stacking direction of the center portion of the inner layer portion 18 in the stacking direction of the region where the third connecting portion 129c is not arranged is 3 The dimension t of the inner layer portion 18 in the lamination direction is preferably 1 more than 25% and less than 75% of the total.

[0220] The dimension t in the stacking direction of the center portion of the inner layer portion 18 in the stacking direction in the region where the fourth connecting portion 129d is not arranged is 3 The dimension t of the inner layer portion 18 in the lamination direction is preferably 1 more than 25% and less than 75% of the total.

[0221] Here, the dimension t in the stacking direction of the center portion of the inner layer portion 18 in the stacking direction in the region where the first connecting portion 129a and the second connecting portion 129b are not arranged is 2 becomes smaller than the dimension t of the inner layer portion 18 in the stacking direction 1 When the external impact is applied to the three-terminal multilayer ceramic capacitor 110, the laminate 12 of the three-terminal multilayer ceramic capacitor 110 may be damaged, chipped, cracked, etc. In addition, the dimension t in the stacking direction of the center portion of the inner layer portion 18 in the stacking direction in the region where the first connecting portion 129a and the second connecting portion 129b are not arranged is 2 becomes larger than the dimension t of the inner layer portion 18 in the stacking direction 1 In 75% of the cases, in the lead-out portions of the internal electrode layer 116 of the inner layer portion 18 located on the main surface side outer layer portion 20a, 20b side of the three-terminal multilayer ceramic capacitor 110 which is prone to peeling, the adhesion strength between the first lead-out portions 128a located on different dielectric layers 14 and between the second lead-out portions 128b located on different dielectric layers 14 cannot sometimes be fully ensured.

[0222] In addition, the dimension t in the stacking direction of the center portion of the inner layer portion 18 in the stacking direction in the region where the third connecting portion 129c and the fourth connecting portion 129d are not arranged is 3 becomes smaller than the dimension t of the inner layer portion 18 in the stacking direction 1 When the external impact is applied to the three-terminal multilayer ceramic capacitor 110, the laminated body 12 of the three-terminal multilayer ceramic capacitor 110 may be damaged, chipped, cracked, etc. In addition, the dimension t in the stacking direction of the central portion of the inner layer portion 18 in the stacking direction in the region where the third connecting portion 129c and the fourth connecting portion 129d are not arranged is3 becomes larger than the dimension t of the inner layer portion 18 in the stacking direction 1 In 75% of the cases, in the lead-out portions of the internal electrode layer 116 of the inner layer portion 18 located on the side outer layer portions 22a, 22b of the three-terminal multilayer ceramic capacitor 110 where peeling is prone to occur, the adhesion strength between the first lead-out portions 128a located on different dielectric layers 14 and between the second lead-out portions 128b located on different dielectric layers 14 is sometimes not sufficiently ensured.

[0223] The dimension of the first connecting portion 129a in the length direction z connecting the first end face 12e and the second end face 12f is preferably 3% to 97% of the thickness of the first lead portion 128a of the first internal electrode layer 116a.

[0224] The dimension of the second connecting portion 129b in the length direction z connecting the first end face 12e and the second end face 12f is preferably 3% to 97% of the thickness of the second lead portion 128b of the first internal electrode layer 116a.

[0225] The dimension of the third connecting portion 129c in the length direction z connecting the first side surface 12c and the second side surface 12d is preferably 3% to 97% of the thickness of the third lead portion 128c of the second internal electrode layer 116b.

[0226] The dimension of the fourth connecting portion 129d in the length direction z connecting the first side surface 12c and the second side surface 12d is preferably 3% to 97% of the thickness of the fourth lead portion 128d of the second internal electrode layer 116b.

[0227] As a result, the resistance becomes higher than that of the internal electrode layer 16 and current becomes less likely to flow, so that it is possible to prevent the change in electrical characteristics caused by the first to fourth connecting portions 129 a , 129 d and suppress separation between the internal electrode layers 116 .

[0228] The first connecting portion 129 a and the second connecting portion 129 b are preferably concentrated in the center of the three-terminal multilayer ceramic capacitor 110 in the width direction y.

[0229] Furthermore, the third connecting portion 129 c and the fourth connecting portion 129 d are preferably concentrated in the center of the three-terminal multilayer ceramic capacitor 110 in the width direction y.

[0230] As a result, the adhesion strength between the internal electrode layers 16 can be more reliably ensured in the central portion of the three-terminal multilayer ceramic capacitor 110 in the width direction y.

[0231] The material composition of the first internal electrode layer 116a and the second internal electrode layer 116b and the composition within the layer in the stacking direction x are similar to those of the first internal electrode layer 16a and the second internal electrode layer 16b of the two-terminal multilayer ceramic capacitor 10 of the first embodiment.

[0232] The external electrode 30 includes a first external electrode 30 a , a second external electrode 30 b , a third external electrode 30 c , and a fourth external electrode 30 d .

[0233] The first external electrode 30a is connected to the first internal electrode layer 116a and is arranged on the surface of the first end surface 12e. In addition, the first external electrode 30a extends from the first end surface 12e of the stacked body 12 and is also arranged on a portion of the first main surface 12a and a portion of the second main surface 12b, and a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the first external electrode 30a is electrically connected to the first lead portion 128a of the first internal electrode layer 116a.

[0234] The second external electrode 30b is connected to the first internal electrode layer 116a and is arranged on the surface of the second end surface 12f. In addition, the second external electrode 30b extends from the second end surface 12f of the stacked body 12 and is also arranged on a portion of the first main surface 12a and a portion of the second main surface 12b, and a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the second external electrode 30b is electrically connected to the second lead portion 128b of the first internal electrode layer 116a.

[0235] The third external electrode 30c is connected to the second internal electrode layer 116b and is arranged on the surface of the first side surface 12c. In addition, the third external electrode 30c extends from the first side surface 12c of the stacked body 12 and is also arranged on a part of the first main surface 12a and a part of the second main surface 12b. In this case, the third external electrode 30c is electrically connected to the third lead portion 128c of the second internal electrode layer 116b.

[0236] The fourth external electrode 30d is connected to the second internal electrode layer 116b and is disposed on the surface of the second side surface 12d. In addition, the fourth external electrode 30d extends from the second side surface 12d of the stacked body 12 and is also disposed on a portion of the first main surface 12a and a portion of the second main surface 12b. In this case, the fourth external electrode 30d is electrically connected to the fourth lead portion 128d of the second internal electrode layer 116b.

[0237] In the laminate 12, an electrostatic capacitor is formed by the first opposing electrode portion 126a of the first internal electrode layer 116a and the second opposing electrode portion 126b of the second internal electrode layer 116b being opposed to each other via the dielectric layer 14. Therefore, an electrostatic capacitor can be obtained between the first external electrode 30a and the second external electrode 30b connected to the first internal electrode layer 116a and the third external electrode 30c and the fourth external electrode 30d connected to the second internal electrode layer 116b, thereby exhibiting the characteristics of a capacitor.

[0238] The foundation electrode layer 32 includes a first foundation electrode layer 32 a , a second foundation electrode layer 32 b , a third foundation electrode layer 32 c , and a fourth foundation electrode layer 32 d .

[0239] The first foundation electrode layer 32a is connected to the first internal electrode layer 116a and is arranged on the surface of the first end surface 12e. In addition, the first foundation electrode layer 32a extends from the first end surface 12e and is also arranged on a portion of the first main surface 12a and a portion of the second main surface 12b, and a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the first foundation electrode layer 32a is electrically connected to the first lead portion 128a of the first internal electrode layer 116a.

[0240] The second foundation electrode layer 32b is connected to the first internal electrode layer 116a and is arranged on the surface of the second end surface 12f. In addition, the second foundation electrode layer 32b extends from the second end surface 12f and is also arranged on a portion of the first main surface 12a and a portion of the second main surface 12b, and a portion of the first side surface 12c and a portion of the second side surface 12d. In this case, the second foundation electrode layer 32b is electrically connected to the second lead portion 128b of the first internal electrode layer 116a.

[0241] The third foundation electrode layer 32c is connected to the second internal electrode layer 116b and is arranged on the surface of the first side surface 12c. In addition, the third foundation electrode layer 32c extends from the first side surface 12c and is also arranged on a part of the first main surface 12a and a part of the second main surface 12b. In this case, the third foundation electrode layer 32c is electrically connected to the third lead portion 128c of the second internal electrode layer 116b.

[0242] The fourth foundation electrode layer 32d is connected to the second internal electrode layer 116b and is arranged on the surface of the second side surface 12d. In addition, the fourth foundation electrode layer 32d extends from the second side surface 12d and is also arranged on a part of the first main surface 12a and a part of the second main surface 12b. In this case, the fourth foundation electrode layer 32d is electrically connected to the fourth lead portion 128d of the second internal electrode layer 116b.

[0243] The plating layer 34 includes a first plating layer 34 a , a second plating layer 34 b , a third plating layer 34 c , and a fourth plating layer 34 d .

[0244] The first plating layer 34 a is arranged to cover the surface of the first foundation electrode layer 32 a .

[0245] The second plating layer 34b is arranged to cover the surface of the second foundation electrode layer 32b.

[0246] The third plating layer 34c is arranged to cover the surface of the third foundation electrode layer 32c.

[0247] The fourth plating layer 34d is arranged to cover the surface of the fourth foundation electrode layer 32d.

[0248] The material composition of the first external electrode 30a, the second external electrode 30b, the third external electrode 30c and the fourth external electrode 30d of the three-terminal multilayer ceramic capacitor 110 and the structure within the layer are the same as the first external electrode 30a and the second external electrode 30b of the two-terminal multilayer ceramic capacitor 10 of the first embodiment.

[0249] The dimension of the length direction z of the three-terminal multilayer ceramic capacitor 110 including the stacked body 12 and the first external electrodes 30a to the fourth external electrodes 30d is set to L dimension, the dimension of the stacking direction x of the three-terminal multilayer ceramic capacitor 110 including the stacked body 12 and the first external electrodes 30a to the fourth external electrodes 30d is set to T dimension, and the dimension of the width direction y of the three-terminal multilayer ceramic capacitor 110 including the stacked body 12 and the first external electrodes 30a to the fourth external electrodes 30d is set to W dimension.

[0250] The dimensions of the three-terminal multilayer ceramic capacitor 110 are not particularly limited, but the L dimension in the length direction z is 0.2 mm or more and 11.0 mm or less, the W dimension in the width direction y is 0.1 mm or more and 11.0 mm or less, and the T dimension in the stacking direction x is 0.1 mm or more and 11.0 mm or less. In addition, the dimensions of the three-terminal multilayer ceramic capacitor 110 can be measured using a microscope.

[0251] thus, Figure 6 The three-terminal multilayer ceramic capacitor 110 shown can be used with Figure 1 The two-terminal multilayer ceramic capacitor 10 shown can adopt various structures similar to the structure, and achieve various effects corresponding to the various structures.

[0252] 2. Method for manufacturing three-terminal multilayer ceramic capacitor

[0253] Next, a method for manufacturing a three-terminal multilayer ceramic capacitor will be described.

[0254] First, a dielectric sheet for a dielectric layer and a conductive paste for an internal electrode layer are prepared. The dielectric sheet and the conductive paste for the internal electrode layer contain a binder and a solvent. The binder and the solvent may be known binders and solvents.

[0255] Then, when forming the dielectric sheet, a paste containing a dielectric is printed by inkjet printing to form the dielectric sheet. At this time, the dielectric sheet on which the pattern of the internal electrode layer is not printed is printed continuously. On the other hand, the dielectric sheet on which the pattern for the first internal electrode layer and the pattern for the second internal electrode layer are printed is printed discontinuously at the place where the first connecting part and the second connecting part are to be formed, and when the conductive paste for the internal electrode is printed by inkjet printing or screen printing, the conductive paste for the internal electrode is made to enter the discontinuous part, thereby forming the first connecting part and the second connecting part. At this time, by controlling the width of the discontinuous part in inkjet printing, the length direction dimension of the first connecting part and the second connecting part connecting the first end face and the second end face can be controlled.

[0256] In addition, regarding the dielectric sheet, a dielectric sheet for an outer layer on which the pattern of the internal electrode layer is not printed is also prepared.

[0257] Next, a predetermined number of dielectric sheets for outer layers without the pattern of the internal electrode layer printed thereon are stacked to form a portion of the second main surface side outer layer portion. Then, a dielectric sheet with the pattern of the first internal electrode layer printed thereon and a dielectric sheet with the pattern of the second internal electrode layer printed thereon are sequentially stacked on the portion of the second main surface side outer layer portion to form the structure of the present invention, thereby forming a portion of the inner layer portion. Thereafter, a predetermined number of dielectric sheets for outer layers without the pattern of the internal electrode layer printed thereon are further stacked on the portion of the inner layer portion to form a portion of the first main surface side outer layer portion. Thus, a laminated sheet is produced.

[0258] Next, the laminated sheets are pressed in the lamination direction by isostatic pressing or the like, thereby producing a laminated block.

[0259] Then, the stacked block is cut into a given size to cut out stacked small pieces. At this time, the corners and ridges of the stacked small pieces may be rounded by barrel grinding or the like.

[0260] Next, the stacked small pieces are fired to produce the stacked body 12. The firing temperature depends on the materials of the dielectric layer and the internal electrode layer, but is preferably 900°C or higher and 1400°C or lower.

[0261] (Formation of external electrodes)

[0262] (a) Sintered layer

[0263] In the following description, it is assumed that the base electrode layer is formed of a sintered layer. When forming the sintered layer, a conductive paste containing a glass component and a metal is prepared and applied, and then sintered to form the base electrode layer.

[0264] The third foundation electrode layer 32c of the third external electrode 30c is formed on the first side surface 12c of the laminated body 12 obtained by firing, and the fourth foundation electrode layer 32d of the fourth external electrode 30d is formed on the second side surface 12d of the laminated body 12.

[0265] When forming a sintered layer as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied and then sintered to form a sintered layer as the base electrode layer 32. The sintering temperature is preferably 700°C or more and 900°C or less.

[0266] Here, various methods can be used as a method for forming the sintered layer. For example, a method of applying the conductive paste by extruding it from a slit can be used. In the case of this method, by increasing the amount of conductive paste extruded, the base electrode layer 32 can be formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b.

[0267] In addition, the base electrode layer 32 can also be formed using a roller transfer method. In the case of the roller transfer method, when the base electrode layer 32 is formed not only on the first side surface 12c and the second side surface 12d, but also on a part of the first main surface 12a and a part of the second main surface 12b, the base electrode layer 32 can be formed on a part of the first main surface 12a and a part of the second main surface 12b by increasing the pressing pressure during the roller transfer.

[0268] Next, the first foundation electrode layer 32a of the first external electrode 30a is formed on the first end surface 12e of the fired laminate 12, and the second foundation electrode layer 32b of the second external electrode 30b is formed on the second end surface 12f of the laminate 12.

[0269] In the case of forming a sintered layer as the base electrode layer 32, similarly to the formation of each base electrode layer 32 of the third external electrode 30c and the fourth external electrode 30d, a conductive paste containing a glass component and a metal component is applied, and then a sintering process is performed to form a sintered layer as the base electrode layer 32. The temperature of the sintering process at this time is preferably 700° C. or higher and 900° C. or lower.

[0270] In addition, as a method of forming a sintered layer to serve as a base electrode layer 32 for the first external electrode 30a and the second external electrode 30b, a conductive paste for the base electrode layer is formed by an immersion method so as to extend not only to the first end face 12e and the second end face 12f but also to a portion of the first main surface 12a, a portion of the second main surface 12b, a portion of the first side surface 12c, and a portion of the second side surface 12d.

[0271] In addition, regarding the sintering process, the third base electrode layer 32c of the third external electrode 30c, the fourth base electrode layer 32d of the fourth external electrode 30d, the first base electrode layer 32a of the first external electrode 30a, and the second base electrode layer 32b of the second external electrode 30b can be sintered simultaneously, or the third base electrode layer 32c of the third external electrode 30c and the fourth base electrode layer 32d of the fourth external electrode 30d and the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b can be sintered separately.

[0272] (b) Conductive resin layer

[0273] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method: The conductive resin layer may be formed on the surface of the calcined layer, or the conductive resin layer may be formed directly on the laminate 12 without forming a calcined layer.

[0274] The conductive resin paste containing a thermosetting resin and a metal component is applied on the sintered layer or the laminate 12, and heat-treated at a temperature of 250°C to 550°C to heat-cure the resin, thereby forming a conductive resin layer. The atmosphere during the heat treatment is preferably N 2 In order to prevent the resin from scattering and the oxidation of various metal components, the oxygen concentration is preferably suppressed to 100 ppm or less.

[0275] As a method for applying the conductive resin paste, similar to the method of forming the base electrode layer 32 from a sintered layer, for example, a method of applying the conductive resin paste by extruding it from a slit or a roll transfer method can be used.

[0276] (c) Thin film layer

[0277] In addition, when the base electrode layer 32 is formed by a thin film layer, the base electrode layer can be formed by covering the portion other than the desired portion where the external electrode 30 is to be formed by masking or the like, and performing a thin film forming method such as sputtering or evaporation on the exposed desired portion. The base electrode layer formed by a thin film layer is set to a layer of 1 μm or less in which metal particles are deposited.

[0278] (Plating electrode)

[0279] Furthermore, the external electrodes may be formed by using only the plated layers as the plated electrodes without providing the base electrode layer 32. In this case, the external electrodes may be formed by the following method.

[0280] Any one of the first external electrode 30a to the fourth external electrode 30d or each of them may also form a plating layer directly on the surface of the laminate 12 without providing the base electrode layer 32. That is, the three-terminal laminated ceramic capacitor 110 may also be a structure including a plating layer directly electrically connected to the first internal electrode layer 116a and the second internal electrode layer 116b. When performing the plating process, any one of electrolytic plating and electroless plating may also be used, but electroless plating requires pretreatment with a catalyst or the like in order to increase the plating deposition speed, and has the disadvantage of complicating the process. Therefore, electrolytic plating is usually preferably used. As a plating method, drum plating is preferably used. In addition, the upper plating electrode formed on the surface of the lower plating electrode may also be formed in the same manner as required.

[0281] (Production of coating layer)

[0282] Next, a plating layer is formed on the surface of the base electrode layer 32 , the surface of the conductive resin layer, or the surface of the lower plating electrode or the surface of the upper plating electrode as necessary.

[0283] More specifically, in the present embodiment, Ni-plated layers and Sn-plated layers are formed as the plating layers 34 on the base electrode layer 32 as the sintered layer. The Ni-plated layers and the Sn-plated layers are formed successively by, for example, a drum plating method. When the plating process is carried out, any one of electrolytic plating and electroless plating can also be adopted. However, electroless plating needs to use the pre-treatment of a catalyst etc. in order to improve the plating precipitation speed, and there is a shortcoming that the process is complicated. Therefore, it is usually preferred to adopt electrolytic plating.

[0284] As described above, the three-terminal multilayer ceramic capacitor 110 according to the second embodiment is manufactured.

[0285] Including the contents described above, the present invention can make various changes to the above-described embodiments in terms of structure, shape, material, quantity, position or configuration without departing from the scope of the technical idea and purpose of the present invention, which are also included in the present invention.

[0286] <1>

[0287] A stacked ceramic capacitor having:

[0288] A laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a lamination direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction and the length direction;

[0289] a first external electrode disposed on the first end surface; and

[0290] a second external electrode disposed on the second end surface,

[0291] in,

[0292] The plurality of internal electrode layers include a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately arranged on different dielectric layers.

[0293] The plurality of first internal electrode layers include a plurality of first opposing electrode portions opposed to the second internal electrode layers, and a plurality of first lead portions extending from the plurality of first opposing electrode portions and led to the first end surface, respectively.

[0294] The second internal electrode layer includes a plurality of second opposing electrode portions opposed to the first internal electrode layer, and a plurality of second lead portions extending from the plurality of second opposing electrode portions and led to the first side surface.

[0295] The first lead portion has a first connection portion connected between the first lead portions located on the different dielectric layers at least on the first main surface side or at least on the second main surface side so as to span at least two or more of the first lead portions in the stacking direction.

[0296] The second lead portion includes a second connection portion connecting the second lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side so as to span over at least two or more of the second lead portions in the stacking direction.

[0297] <2>

[0298] according to <1> The multilayer ceramic capacitor described herein, wherein

[0299] The laminated body has:

[0300] An inner layer portion where the plurality of internal electrode layers are opposed;

[0301] a first end surface side outer layer portion located on the first end surface side and formed of the plurality of dielectric layers located between the first end surface and the outermost surface of the inner layer portion on the first end surface side; and

[0302] a second end surface side outer layer portion located on the second end surface side and formed by the plurality of dielectric layers located between the second end surface and the outermost surface of the inner layer portion on the second end surface side,

[0303] The first connection portion is located closer to the first end surface than 1 / 2 of the lengthwise dimension of the first end surface side outer layer portion.

[0304] The second connection portion is located closer to the second end surface than 1 / 2 of the dimension of the second end surface side outer layer portion in the longitudinal direction.

[0305] <3>

[0306] according to <1> or <2> The multilayer ceramic capacitor described herein, wherein

[0307] There are a plurality of the first connection portion and a plurality of the second connection portion.

[0308] <4>

[0309] according to <1> to <3> The multilayer ceramic capacitor according to any one of the preceding claims, wherein:

[0310] The first connection portion and the second connection portion are located on at least one of the first main surface side of the inner layer portion excluding the central portion in the stacking direction and the second main surface side of the inner layer portion excluding the central portion in the stacking direction.

[0311] <5>

[0312] A stacked ceramic capacitor having:

[0313] A laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a lamination direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction and the length direction;

[0314] a plurality of first internal electrode layers, arranged on the plurality of dielectric layers and led out to the first end surface and the second end surface;

[0315] a plurality of second internal electrode layers, arranged on the plurality of dielectric layers and extending to the first side surface and the second side surface;

[0316] a first external electrode disposed on the first end surface and connected to the first internal electrode layer;

[0317] a second external electrode, disposed on the second end surface and connected to the first internal electrode layer;

[0318] a third external electrode disposed on the first side surface and connected to the second internal electrode layer; and

[0319] a fourth external electrode, disposed on the second side surface and connected to the second internal electrode layer;

[0320] in,

[0321] The plurality of first internal electrode layers include:

[0322] a plurality of first opposing electrode portions, facing the second internal electrode layer via the dielectric layer;

[0323] a plurality of first lead portions extending from the plurality of first opposing electrode portions respectively and led out to the first end surface; and

[0324] a plurality of second lead portions extending from the plurality of first opposing electrode portions respectively and led out to the second end surface;

[0325] The plurality of second internal electrode layers include:

[0326] a plurality of second opposing electrode portions, facing the first internal electrode layer via the dielectric layer;

[0327] a plurality of third lead portions extending from the plurality of second opposing electrode portions respectively and led out to the first side surface; and

[0328] a plurality of fourth lead portions extending from the plurality of second opposing electrode portions respectively and led out to the second side surface;

[0329] The first lead portion includes a first connection portion connected to at least two of the first lead portions in the stacking direction between the first lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side.

[0330] The second lead portion includes a second connection portion connected to the second lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side so as to span at least two or more of the second lead portions in the stacking direction.

[0331] The third lead portion has a third connection portion connected between the third lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side so as to span at least two of the third lead portions in the stacking direction.

[0332] The fourth lead portion includes a fourth connection portion that connects the fourth lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side so as to span over at least two of the fourth lead portions in the stacking direction.

[0333] <6>

[0334] according to <5> The multilayer ceramic capacitor described herein, wherein

[0335] The laminated body has:

[0336] An inner layer portion where the plurality of internal electrode layers are opposed;

[0337] a first side surface side outer layer portion, located on the first side surface and formed by the plurality of dielectric layers located between the first side surface and the outermost surface of the inner layer portion on the first side surface;

[0338] a second side surface side outer layer portion, located on the second side surface and formed by the plurality of dielectric layers located between the second side surface and the outermost surface of the inner layer portion on the second side surface;

[0339] a first end surface side outer layer portion located on the first end surface side and formed of the plurality of dielectric layers located between the first end surface and the outermost surface of the inner layer portion on the first end surface side; and

[0340] a second end surface side outer layer portion located on the second end surface side and formed by the plurality of dielectric layers located between the second end surface and the outermost surface of the inner layer portion on the second end surface side,

[0341] The first connection portion is located closer to the first end surface than 1 / 2 of the lengthwise dimension of the first end surface side outer layer portion.

[0342] The second connection portion is located closer to the second end surface than 1 / 2 of the lengthwise dimension of the second end surface side outer layer portion.

[0343] The third connection portion is located closer to the first side surface than 1 / 2 of the dimension of the first side surface outer layer portion in the width direction.

[0344] The fourth connection portion is located closer to the second side surface than 1 / 2 of the dimension of the second side surface outer layer portion in the width direction.

[0345] <7>

[0346] according to <5> or <6> The multilayer ceramic capacitor described herein, wherein

[0347] There are a plurality of the first connection portion, the second connection portion, the third connection portion, and the fourth connection portion.

[0348] <8>

[0349] according to <5> to <7> The multilayer ceramic capacitor according to any one of the preceding claims, wherein:

[0350] The first connection portion, the second connection portion, the third connection portion, and the fourth connection portion are located on at least one of the first main surface side of the inner layer portion excluding the central portion in the stacking direction and the second main surface side of the inner layer portion excluding the central portion in the stacking direction.

[0351] Description of Reference Numerals

[0352] 10: Two-terminal multilayer ceramic capacitor;

[0353] 110: Three-terminal multilayer ceramic capacitor;

[0354] 12: laminate;

[0355] 12a: 1st main side;

[0356] 12b: 2nd main side;

[0357] 12c: 1st side;

[0358] 12d: lateral side 2;

[0359] 12e: 1st end surface;

[0360] 12f: 2nd end surface;

[0361] 14: dielectric layer;

[0362] 16, 116: internal electrode layer;

[0363] 16a, 116a: first internal electrode layer;

[0364] 16b, 116b: second internal electrode layer;

[0365] 18: inner layer;

[0366] 20a: first main surface side outer layer portion;

[0367] 20b: outer layer portion on the second main surface side;

[0368] 22c: first side outer layer;

[0369] 22d: second side outer layer;

[0370] 24e: first end surface side outer layer portion;

[0371] 24f: second end surface side outer layer portion;

[0372] 26a, 126a: first opposing electrode portion;

[0373] 26b, 126b: second opposing electrode portion;

[0374] 28a, 128a: first lead-out portion;

[0375] 28b, 128b: second lead-out portion;

[0376] 128c: the third lead-out section;

[0377] 128d: 4th lead-out section;

[0378] 30: external electrode;

[0379] 30a: 1st external electrode;

[0380] 30b: second external electrode;

[0381] 30c: 3rd external electrode;

[0382] 30d: 4th external electrode;

[0383] 32: substrate electrode;

[0384] 32a: first base electrode layer;

[0385] 32b: second base electrode layer;

[0386] 32c: third base electrode layer;

[0387] 32d: 4th base electrode layer;

[0388] 34: coating layer;

[0389] 34a: first coating layer;

[0390] 34b: second coating layer;

[0391] 34c: 3rd coating layer;

[0392] 34d: 4th coating layer;

[0393] x: stacking direction;

[0394] y: width direction;

[0395] z: length direction.

Claims

1. A laminated ceramic capacitor comprising: A laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a lamination direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction and the length direction; a first external electrode disposed on the first end surface; and a second external electrode disposed on the second end surface, in, The plurality of internal electrode layers include a plurality of first internal electrode layers and a plurality of second internal electrode layers alternately arranged on different dielectric layers. The plurality of first internal electrode layers include a plurality of first opposing electrode portions opposed to the second internal electrode layers, and a plurality of first lead portions extending from the plurality of first opposing electrode portions and led to the first end surface, respectively. The second internal electrode layer includes a plurality of second opposing electrode portions opposed to the first internal electrode layer, and a plurality of second lead portions extending from the plurality of second opposing electrode portions and led to the first side surface. The first lead portion has a first connection portion connected between the first lead portions located on the different dielectric layers at least on the first main surface side or at least on the second main surface side so as to span at least two or more of the first lead portions in the stacking direction. The second lead portion includes a second connection portion connecting the second lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side so as to span over at least two or more of the second lead portions in the stacking direction.

2. The multilayer ceramic capacitor according to claim 1, wherein The laminated body has: An inner layer portion where the plurality of internal electrode layers are opposed; a first end surface side outer layer portion located on the first end surface side and formed of the plurality of dielectric layers located between the first end surface and the outermost surface of the inner layer portion on the first end surface side; and a second end surface side outer layer portion located on the second end surface side and formed by the plurality of dielectric layers located between the second end surface and the outermost surface of the inner layer portion on the second end surface side, The first connection portion is located closer to the first end surface than 1 / 2 of the length direction dimension of the first end surface side outer layer portion. The second connection portion is located closer to the second end surface than 1 / 2 of the dimension of the second end surface side outer layer portion in the longitudinal direction.

3. The multilayer ceramic capacitor according to claim 1 or 2, wherein: There are a plurality of the first connection portion and a plurality of the second connection portion.

4. The multilayer ceramic capacitor according to any one of claims 1 to 3, wherein The first connection portion and the second connection portion are located on at least one of the first main surface side of the inner layer portion excluding the central portion in the stacking direction and the second main surface side of the inner layer portion excluding the central portion in the stacking direction.

5. A laminated ceramic capacitor comprising: A laminate having a plurality of laminated dielectric layers and a plurality of internal electrode layers laminated on the dielectric layers, and having a first main surface and a second main surface opposite to each other in a lamination direction, a first end surface and a second end surface opposite to each other in a length direction perpendicular to the lamination direction, and a first side surface and a second side surface opposite to each other in a width direction perpendicular to the lamination direction and the length direction; a plurality of first internal electrode layers, arranged on the plurality of dielectric layers and led out to the first end surface and the second end surface; a plurality of second internal electrode layers, arranged on the plurality of dielectric layers and extending to the first side surface and the second side surface; a first external electrode disposed on the first end surface and connected to the first internal electrode layer; a second external electrode, disposed on the second end surface and connected to the first internal electrode layer; a third external electrode disposed on the first side surface and connected to the second internal electrode layer; as well as a fourth external electrode, disposed on the second side surface and connected to the second internal electrode layer; in, The plurality of first internal electrode layers include: a plurality of first opposing electrode portions, facing the second internal electrode layer via the dielectric layer; a plurality of first lead portions extending from the plurality of first opposing electrode portions respectively and led out to the first end surface; and a plurality of second lead portions extending from the plurality of first opposing electrode portions respectively and led out to the second end surface; The plurality of second internal electrode layers include: a plurality of second opposing electrode portions, facing the first internal electrode layer via the dielectric layer; A plurality of third lead portions extending from the plurality of second opposing electrode portions respectively and led out to the first side surface; as well as a plurality of fourth lead portions extending from the plurality of second opposing electrode portions respectively and led out to the second side surface; The first lead portion includes a first connection portion connected to at least two of the first lead portions in the stacking direction between the first lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side. The second lead portion includes a second connection portion connected to the second lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side so as to span at least two or more of the second lead portions in the stacking direction. The third lead portion has a third connection portion connected between the third lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side so as to span at least two of the third lead portions in the stacking direction. The fourth lead portion includes a fourth connection portion that connects the fourth lead portions located on different dielectric layers at least on the first main surface side or at least on the second main surface side so as to span over at least two of the fourth lead portions in the stacking direction.

6. The multilayer ceramic capacitor according to claim 5, wherein: The laminated body has: An inner layer portion where the plurality of internal electrode layers are opposed; a first side surface side outer layer portion, located on the first side surface and formed by the plurality of dielectric layers located between the first side surface and the outermost surface of the inner layer portion on the first side surface; a second side surface side outer layer portion, located on the second side surface and formed by the plurality of dielectric layers located between the second side surface and the outermost surface of the inner layer portion on the second side surface; a first end surface side outer layer portion located on the first end surface side and formed of the plurality of dielectric layers located between the first end surface and the outermost surface of the inner layer portion on the first end surface side; and a second end surface side outer layer portion located on the second end surface side and formed by the plurality of dielectric layers located between the second end surface and the outermost surface of the inner layer portion on the second end surface side, The first connection portion is located closer to the first end surface than 1 / 2 of the length direction dimension of the first end surface side outer layer portion. The second connection portion is located closer to the second end surface than 1 / 2 of the lengthwise dimension of the second end surface side outer layer portion. The third connection portion is located closer to the first side surface than 1 / 2 of the dimension of the first side surface outer layer portion in the width direction. The fourth connection portion is located closer to the second side surface than 1 / 2 of the dimension of the second side surface outer layer portion in the width direction.

7. The multilayer ceramic capacitor according to claim 5 or 6, wherein: There are a plurality of the first connection portion, the second connection portion, the third connection portion, and the fourth connection portion.

8. The multilayer ceramic capacitor according to any one of claims 5 to 7, wherein The first connection portion, the second connection portion, the third connection portion, and the fourth connection portion are located on at least one of the first main surface side of the inner layer portion excluding the height center portion and the second main surface side of the inner layer portion excluding the height center portion.

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