Process for preventing metal layer delamination

Abstract

The application discloses a process method for preventing metal layer peeling, which comprises the following steps: step one, performing a degassing process on a wafer; step two, cooling the wafer to a temperature below a first temperature, moving the cooled wafer into an ion implantation cavity, and forming an adhesion layer by using an ion implantation process, so as to adjust the adhesion between the adhesion layer and a semiconductor substrate; step three, forming a barrier layer; step four, forming a metal layer; and step five, performing a chemical mechanical polishing process on the metal layer, and the adhesion is greater than the pressure generated by the chemical mechanical polishing process. The application can improve the adhesion between the metal layer and the semiconductor substrate, and ensure that the adhesion at the weakest position is greater than the pressure generated by the chemical mechanical polishing process of the metal layer, so that the metal layer peeling can be prevented, and the product yield can be improved.

Description

Technical Field

[0001] This invention relates to a method for manufacturing semiconductor integrated circuits, and more particularly to a process method for preventing metal layer peeling. Background Technology

[0002] The back-side metal layer of a back-illuminated (BSI) CMOS image sensor (CIS) typically includes tungsten (W). After tungsten deposition, it undergoes chemical mechanical polishing (CMP) for planarization, followed by an etch-back process. During CMP polishing, metal peeling defects commonly occur. Data analysis shows that the first wafer in a particular batch is particularly prone to metal peeling defects.

[0003] like Figure 1A The image shown is a test diagram of the number of metal peeling defects after the formation of the back metal layer in an existing BSI CIS product. It can be seen that after the CMP of the back metal layer is completed on wafer 101, a large number of metal peeling defects 102 will appear.

[0004] like Figure 1B As shown, is Figure 1A Magnified photograph of metal peeling defects in the image. Figure 1B In this context, metal peeling defects are indicated separately by the designation 102a. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a process method to prevent metal layer peeling, which can improve the adhesion between the metal layer and the semiconductor substrate and ensure that the adhesion at the weakest position is greater than the pressure generated by the chemical mechanical polishing process of the metal layer, thereby preventing parametric metal layer peeling and improving product yield.

[0006] To solve the above-mentioned technical problems, the process method for preventing metal layer peeling provided by the present invention includes the following steps:

[0007] Step 1: Provide a wafer composed of a semiconductor substrate and perform a degassing process on the wafer.

[0008] Step 2: Cool the wafer to below a first temperature, move the cooled wafer into an ion implantation chamber and form an adhesion layer using an ion implantation process. Adjust the adhesion force between the adhesion layer and the semiconductor substrate by adjusting the first temperature. The lower the first temperature, the greater the adhesion force. Increase the adhesion force to prevent metal layer peeling in the subsequent step 5.

[0009] Step 3: Form a barrier layer on the surface of the adhesion layer.

[0010] Step 4: Form a metal layer on the surface of the barrier layer.

[0011] Step 5: Planarize the metal layer using a chemical mechanical polishing process, wherein the adhesion force is greater than the pressure generated by the chemical mechanical polishing process.

[0012] A further improvement is that the semiconductor substrate comprises a silicon substrate.

[0013] A further improvement is that the temperature of the degassing process is above 300°C.

[0014] A further improvement is that, in step two, the temperature of the wafer is reduced to below the first temperature by increasing the idle time between the completion of the degassing process in step one and the start of the ion implantation process in step two.

[0015] A further improvement is that the idle time is obtained based on experimental data, which includes a relationship curve between the idle time and the number of metal layer peeling defects. The time corresponding to the number of metal layer peeling defects that is less than or equal to the process requirement value in the relationship curve is selected as the idle time in step two.

[0016] A further improvement is that, in step two, the material of the adhesion layer includes Ti.

[0017] A further improvement is that, in step three, the material of the barrier layer includes TiN.

[0018] A further improvement is that, in step four, the material of the metal layer includes W.

[0019] A further improvement is that, in step one, a BSI CIS product is formed on the wafer, the front side of the wafer has completed the front-side process structure of the BSI CIS, and the front side of the wafer is bonded to the carrier wafer.

[0020] A further improvement is that, in step one, the wafer undergoes the following back-side processing:

[0021] Perform back-side thinning;

[0022] The edge-cutting process removes part or all of the thickness of the wafer's edge and forms an edge sidewall.

[0023] Forming back grooves;

[0024] Formation of a decoupled plasma oxide layer;

[0025] Alumina, tantalum oxide, and an inner oxide liner are sequentially formed on the surface of the decoupled plasma oxide layer.

[0026] In step two, the adhesion force at the edge sidewall is the minimum. In step five, the adhesion force at the edge sidewall is greater than the pressure generated by the chemical mechanical polishing process.

[0027] This invention can improve the adhesion between the metal layer and the semiconductor substrate and ensure that the adhesion at the weakest point is greater than the pressure generated by the chemical mechanical polishing process of the metal layer, thereby preventing the parametric metal layer from peeling off and improving product yield.

[0028] This invention is particularly applicable to the formation process of the back metal layer in BSI CIS products. It can prevent insufficient adhesion of the adhesion layer when the wafer, especially the first wafer, is not cooled enough after the degassing process and is directly subjected to ion implantation to form the adhesion layer. This is especially true at the steep edge sidewalls of the wafer, where the adhesion force is too weak and metal layer peeling is likely to occur in the subsequent chemical mechanical polishing process. Therefore, this invention can prevent the formation of metal layer peeling defects, especially the first wafer, and ultimately improve the yield of BSI CIS products. Attached Figure Description

[0029] The present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments:

[0030] Figure 1A This is a test chart showing the number of metal peeling defects after the formation of the back metal layer in existing BSI CIS products;

[0031] Figure 1B yes Figure 1A Enlarged photograph of metal peeling defects in the image;

[0032] Figure 2A This is a schematic diagram of the wafer structure during the formation of the back metal layer in existing BSI CIS products;

[0033] Figure 2B yes Figure 2A A magnified view of the wafer edge region;

[0034] Figure 3A yes Figure 2B Corresponding photograph of metal peeling defects in the wafer edge region;

[0035] Figure 3B yes Figure 3A Compositional analysis diagram of metal peeling defects in the sample;

[0036] Figure 4 This is a flowchart of a process for preventing metal layer peeling according to an embodiment of the present invention. Detailed Implementation

[0037] The process method for preventing metal layer peeling in this invention is derived from an in-depth analysis of the problems in the formation process of the back metal layer of existing BSI CIS products. Therefore, before describing the process method for preventing metal layer peeling in this invention in detail, we will first introduce the analysis of the problems in the formation process of the back metal layer of existing BSI CIS products, including:

[0038] like Figure 2A The diagram shown is a schematic of the wafer structure during the formation of the back metal layer in existing BSI CIS products. Figure 2B yes Figure 2A An enlarged view of the wafer edge region 206; in existing methods, an adhesion layer and a barrier layer need to be formed before the deposition of the back metal layer 205. Typically, the back metal layer 205 is made of W, the adhesion layer is made of Ti, and the barrier layer is made of TiN. The Ti layer is usually achieved by ion implantation. Before the ion implantation process of the Ti layer, the wafer 201 usually needs to be degassed at a certain temperature, such as around 300°C.

[0039] In the existing BSI CIS product backside metal layer formation process, after degassing, Ti layer ion implantation is usually performed directly. That is, after wafer 201 is removed from the degassing process chamber, if the Ti layer ion implantation process chamber is idle, wafer 201 will be directly moved to the ion implantation process chamber for Ti ion implantation. However, if the ion implantation process chamber is already occupied by a previous wafer 201 undergoing ion implantation, the current wafer 201 will need to wait until the ion implantation process chamber is idle.

[0040] After the Ti layer is completed, the TiN layer will be grown. Figure 2B The middle film layer 405 represents a superposition layer of Ti and TiN layers. The TiN layer can be grown using MOCVD technology.

[0041] Then, the back metal layer 205 is grown.

[0042] Afterwards, the back metal layer 205 is subjected to a chemical mechanical polishing process, and the back metal layer 205 can be further etched back.

[0043] Figure 2A In this process, BSI CIS products are formed on the wafer 201.

[0044] The front-side process structure of the BIS CIS is completed on the front side of the wafer 201. Figure 2A In the BSI CIS, the front-side process structure includes a device layer 202 and a front-side metal interconnect layer 203.

[0045] The front side of the wafer 201 is bonded to the carrier wafer 301. Figure 2A In the process, the wafer 201 is bonded by a bonding layer 303 formed on the front side and a bonding layer 302 formed on the surface of the carrier wafer 301.

[0046] Prior to the degassing process, wafer 201 underwent the following back-side processing:

[0047] Thinning is performed on the back side.

[0048] A trimming process is performed to remove part or all of the thickness of the edge of the wafer 201 and form an edge sidewall 207. Figure 2B In this context, the trim process is a further refinement of the edge washing process. The edge washing process is achieved using photolithography-defined wet etching; the trim process, on the other hand, is achieved using a cutting tool for mechanical cutting. d1 represents the width of the edge removed by the trim process; d2 represents the width of the edge removed by the edge washing process. Figure 2B In this context, wafer 401 represents the integral structure formed by bonding wafer 201 and carrier wafer 301. From... Figure 2A As can be seen, the edge-cutting process removes the entire thickness of the edge portion of the wafer and incorporates it into the carrier wafer 301. Typically, the wafer 201, after thinning, reaches a thickness of 100 micrometers or more, such as 150 micrometers or more, thus the edge sidewall 207 is a very steep sidewall.

[0049] Forming the back groove 204.

[0050] A decoupled plasma oxide layer (DPO)402 is formed.

[0051] Alumina (AlO), tantalum oxide (TaO), and an inner oxide layer 404 are sequentially formed on the surface of the decoupled plasma oxide layer 402. Figure 2B In the diagram, film layer 403 represents a superimposed layer of aluminum oxide and tantalum oxide.

[0052] During the production process using the existing BSI CIS product back metal layer formation process, it was found that a large number of metal peeling defects 102 often occur on the first wafer of the same batch (lot) 201, which is also known as the first wafer effect.

[0053] Comparing the first wafer with other wafers in the same batch reveals that after degassing, the ion implantation chamber of the Ti layer on the first wafer is often ready. This allows the first wafer to enter the ion implantation chamber for ion implantation in a shorter time; that is, the time interval between the start time of the ion implantation process and the completion time of the degassing process is shorter. Conversely, after degassing, the ion implantation chamber on other wafers is often not yet ready, requiring a waiting period before they can enter the chamber. Therefore, the time interval between the start time of the ion implantation process and the completion time of the degassing process is longer, resulting in fewer or no metal stripping defects 102 on subsequent wafers.

[0054] Furthermore, comparing the formation process of the back metal layer of existing BSI CIS products with the formation process of metal layers of other non-BSI CIS products such as W, it can be seen that in other processes, a precleaning process is often performed after the degassing process and before the ion implantation of the Ti layer. The Ti layer is then implanted after the precleaning is completed. Therefore, the time interval between the start time of the ion implantation process and the completion time of the degassing process is also relatively long. This also prevents metal peeling defects from occurring in the metal layer formation processes of other existing non-BSI CIS products.

[0055] The applicant's analysis revealed that the time interval between the start time of the ion implantation process and the completion time of the degassing process is related to the wafer temperature at the start of the ion implantation process. A longer time interval results in a lower wafer temperature, leading to variations in wafer temperature under different ion implantation conditions and consequently different metal peeling defects. In existing BSI CIS products, the time interval between the first wafer in the backside metal layer formation process is relatively short, indicating a higher initial ion implantation temperature for the Ti layer. This weakens the adhesion of the Ti layer. During the subsequent CMP process of metal layer 205, if the CMP pressure exceeds the adhesion force, the entire stacked structure from the Ti layer to metal layer 205 will peel off, resulting in a metal peeling defect.

[0056] In addition, by Figure 2A As shown, the edge sidewall 207 is very steep, therefore the adhesion of the Ti layer at the edge sidewall 207 is weaker, and metal peeling defects are more likely to occur at the edge sidewall 207. Figure 3A As shown, is Figure 2B Corresponding photograph of metal peeling defects in the wafer edge region; Figure 3A In this context, the edge sidewall is individually indicated by the designation 207a, and the metal peeling defect is individually indicated by the designation 102b. For example... Figure 3B As shown, is Figure 3AThe compositional analysis diagram of the metal peeling defect shows that the metal peeling defect 102b contains elements Ti, N and W. Therefore, the metal peeling defect 102b is a superposition of Ti layer, TiN layer and metal layer 205. The metal peeling starts from Ti layer, especially the Ti layer at the edge sidewall 207 is easier to peel off.

[0057] like Figure 4 The diagram shows a flowchart of a process for preventing metal layer peeling according to an embodiment of the present invention. The process for preventing metal layer peeling according to an embodiment of the present invention includes the following steps:

[0058] Step 1: Provide a wafer 201 composed of a semiconductor substrate and perform a degassing process on the wafer 201.

[0059] Please also refer to the structural schematic diagram of the wafer 201 in this embodiment of the invention. Figure 2A As shown, Figure 2B That is Figure 2A A magnified view of the edge region 206. BSI CIS products are formed on the wafer 201.

[0060] The front-side process structure of the BIS CIS is completed on the front side of the wafer 201. Figure 2A In the BSI CIS, the front-side process structure includes a device layer 202 and a front-side metal interconnect layer 203.

[0061] The front side of the wafer 201 is bonded to the carrier wafer 301. Figure 2A In the process, the wafer 201 is bonded by a bonding layer 303 formed on the front side and a bonding layer 302 formed on the surface of the carrier wafer 301.

[0062] The wafer 201 has undergone the following back-side process:

[0063] Thinning is performed on the back side.

[0064] A trimming process is performed to remove part or all of the thickness of the edge of the wafer 201 and form an edge sidewall 207. Figure 2B In this context, the trim process is a further refinement of the edge washing process. The edge washing process is achieved using photolithography-defined wet etching; the trim process, on the other hand, is achieved using a cutting tool for mechanical cutting. d1 represents the width of the edge removed by the trim process; d2 represents the width of the edge removed by the edge washing process. Figure 2B In this context, wafer 401 represents the integral structure formed by bonding wafer 201 and carrier wafer 301. From... Figure 2AAs can be seen, the edge-cutting process removes the entire thickness of the edge portion of the wafer and incorporates it into the carrier wafer 301. Typically, the wafer 201, after thinning, reaches a thickness of 100 micrometers or more, such as 150 micrometers or more, thus the edge sidewall 207 is a very steep sidewall.

[0065] Forming the back groove 204.

[0066] A decoupled plasma oxide layer (DPO)402 is formed.

[0067] Alumina (AlO), tantalum oxide (TaO), and an inner oxide layer 404 are sequentially formed on the surface of the decoupled plasma oxide layer 402. Figure 2B In the diagram, film layer 403 represents a superimposed layer of aluminum oxide and tantalum oxide.

[0068] The semiconductor substrate includes a silicon substrate.

[0069] The temperature of the degassing process is above 300℃.

[0070] Step 2: Cool the wafer 201 to below a first temperature, move the cooled wafer 201 into an ion implantation chamber and form an adhesion layer using an ion implantation process. Adjust the adhesion force between the adhesion layer and the semiconductor substrate by adjusting the first temperature. The lower the first temperature, the greater the adhesion force. By increasing the adhesion force, the peeling of the metal layer 205 in the subsequent step 5 is prevented.

[0071] In this embodiment of the invention, the temperature of the wafer 201 is reduced to below the first temperature by increasing the idle time between the completion of the degassing process in step one and the start of the ion implantation process in step two. Since this embodiment directly reduces the temperature of the wafer 201 below the first temperature by controlling the idle time, it does not require changes to other process parameters or modifications to the process equipment. Therefore, it has the advantages of being easy to implement and having low process cost.

[0072] In some preferred embodiments, the idle time is obtained based on experimental data, which includes a relationship curve between the idle time and the number of peeling defects in the metal layer 205. The time corresponding to the number of peeling defects in the metal layer 205 that is less than or equal to the process requirement value in the relationship curve is selected as the idle time in step two.

[0073] Depend on Figure 2BAs shown, in this embodiment of the invention, the adhesion force at the edge sidewall 207 is the smallest. Therefore, in this embodiment of the invention, it is necessary to ensure that the adhesion force at the edge sidewall 207 is greater than the pressure generated by the chemical mechanical polishing process in the subsequent step five.

[0074] In this embodiment of the invention, the material of the adhesion layer includes Ti.

[0075] Step 3: Form a barrier layer on the surface of the adhesion layer.

[0076] In this embodiment of the invention, the material of the barrier layer includes TiN.

[0077] In some embodiments, the barrier layer is grown using MOCVD.

[0078] Figure 2B In this context, film layer 405 represents the superposition of the adhesion layer and the barrier layer. The barrier layer is used to block the diffusion of the subsequently formed metal layer 205.

[0079] Step 4: Form a metal layer 205 on the surface of the barrier layer.

[0080] In this embodiment of the invention, the material of the metal layer 205 includes W.

[0081] Step 5: Planarize the metal layer 205 using a chemical mechanical polishing process, wherein the adhesion force is greater than the pressure generated by the chemical mechanical polishing process.

[0082] In this embodiment of the invention, the adhesion force at the edge sidewall 207 is greater than the pressure generated by the chemical mechanical polishing process.

[0083] The embodiments of the present invention can improve the adhesion between the metal layer 205 and the semiconductor substrate and ensure that the adhesion at the weakest position is greater than the pressure generated by the chemical mechanical polishing process of the metal layer 205, thereby preventing the parametric metal layer 205 from peeling off and improving product yield.

[0084] This invention is particularly applicable to the formation process of the back metal layer 205 in BSI CIS products. It can prevent insufficient adhesion of the adhesive layer when the wafer 201, especially the first wafer 201, is not cooled enough after the degassing process and is directly subjected to ion implantation to form the adhesion layer. In particular, the adhesion of the adhesion layer at the steep edge sidewalls 207 of the wafer 201 is too weak and is prone to peeling off during the subsequent chemical mechanical polishing process of the metal layer 205. Therefore, this invention can prevent the formation of metal layer 205 peeling defects, especially the first wafer 201, and ultimately improve the yield of BSI CIS products.

[0085] The present invention has been described in detail above through specific embodiments, but these are not intended to limit the invention. Many modifications and improvements can be made by those skilled in the art without departing from the principles of the invention, and these should also be considered within the scope of protection of the present invention.

Claims

1. A process for preventing metal layer peeling, characterized in that, Includes the following steps: Step 1: Provide a wafer composed of a semiconductor substrate and perform a degassing process on the wafer; Step 2: Cool the wafer to below a first temperature, move the cooled wafer into an ion implantation chamber and form an adhesion layer using an ion implantation process. Adjust the adhesion force between the adhesion layer and the semiconductor substrate by adjusting the first temperature. The lower the first temperature, the greater the adhesion force. Increase the adhesion force to prevent metal layer peeling in the subsequent step 5. Step 3: Form a barrier layer on the surface of the adhesion layer; Step 4: Form a metal layer on the surface of the barrier layer; Step 5: Planarize the metal layer using a chemical mechanical polishing process, wherein the adhesion force is greater than the pressure generated by the chemical mechanical polishing process.

2. The process for preventing metal layer peeling as described in claim 1, characterized in that: The semiconductor substrate includes a silicon substrate.

3. The process method for preventing metal layer peeling as described in claim 1, characterized in that: The temperature of the degassing process is above 300℃.

4. The process method for preventing metal layer peeling as described in claim 1, characterized in that: In step two, the temperature of the wafer is reduced to below the first temperature by increasing the idle time between the completion of the degassing process in step one and the start of the ion implantation process in step two.

5. The process method for preventing metal layer peeling as described in claim 4, characterized in that: The idle time is obtained based on experimental data, which includes a relationship curve between the idle time and the number of metal layer peeling defects. The time corresponding to the number of metal layer peeling defects that is less than or equal to the process requirement value in the relationship curve is selected as the idle time in step two.

6. The process method for preventing metal layer peeling as described in claim 1, characterized in that: In step two, the material of the adhesion layer includes Ti.

7. The process method for preventing metal layer peeling as described in claim 6, characterized in that: In step three, the material of the barrier layer includes TiN.

8. The process method for preventing metal layer peeling as described in claim 7, characterized in that: In step four, the material of the metal layer includes W.

9. The process method for preventing metal layer peeling as described in claim 8, characterized in that: In step one, a BSI CIS product is formed on the wafer, the front side of the wafer is completed with the front-side process structure of the BSI CIS, and the front side of the wafer is bonded to the carrier wafer.

10. The process method for preventing metal layer peeling as described in claim 9, characterized in that: In step one, the wafer underwent the following back-side processing: Perform back-side thinning; The edge-cutting process removes part or all of the thickness of the wafer's edge and forms an edge sidewall. Forming back grooves; Formation of a decoupled plasma oxide layer; Alumina, tantalum oxide, and an inner oxide liner are sequentially formed on the surface of the decoupled plasma oxide layer. In step two, the adhesion force at the edge sidewall is the minimum. In step five, the adhesion force at the edge sidewall is greater than the pressure generated by the chemical mechanical polishing process.

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