Epitaxial silicon channel growth

Abstract

A three dimensional NAND flash memory structure may include a solid channel core of epitaxial silicon grown directly from a silicon substrate reference (silicon substrate reference). Alternating oxide-nitride material layers may be formed in a stack, and channel holes may be etched through the material layers, the channel holes extending down to the silicon substrate. A tunnel layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate upward through the channel hole. In some implementations, a support structure may be formed in a channel hole or in a slit of a memory array to provide physical support as an epitaxial silicon core grows through the channel.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority benefit of U.S. Provisional Patent Application No. 63 / 409,697, entitled “EPITAXIAL SILICON CHANNEL GROWTH”, filed on September 23, 2022, in accordance with the Patent Law, and the contents of this patent application are incorporated into this application by reference in their entirety. This application claims the priority benefit of U.S. Provisional Patent Application No. 63 / 343,437, entitled “EPITAXIAL SILICON CHANNELGROWTH”, filed on May 18, 2022, in accordance with the Patent Law, and the contents of this patent application are incorporated into this application by reference in their entirety. Technical Field

[0003] The present disclosure generally describes memory cells having an epitaxial silicon channel core. More specifically, the present disclosure describes techniques for fabricating a 3D NAND flash memory structure having an epitaxial channel core grown from a silicon substrate. Background Art

[0004] The memory design known as NAND memory is a non-volatile flash memory storage architecture that does not require power to maintain its stored data. NAND flash memory is used in many products, such as solid-state devices and portable electronics. In order to improve the density of NAND memory and reduce the size of NAND memory, the traditional two-dimensional NAND architecture has transitioned to three-dimensional NAND stacking. Unlike 2D planar NAND technology, which stacks individual memory cells together on substrates at different levels, 3D NAND is vertically stacked using multiple layers of alternating conductive and dielectric materials and intersecting vertical channels. Summary of the invention

[0005] In some embodiments, a three-dimensional (3D) NAND memory structure may include a silicon substrate and a plurality of alternating material layers arranged in a vertical stack on the silicon substrate. A channel hole may extend through the plurality of alternating material layers to the silicon substrate, and the channel hole may be perpendicular to the plurality of alternating material layers. The memory structure may also include a channel within the channel hole, the channel may include a tunnel layer and an epitaxial silicon core, the tunnel layer surrounding the interior of the channel hole and contacting the plurality of alternating material layers, the epitaxial silicon core within the tunnel layer, and the epitaxial silicon core contacting the silicon substrate.

[0006] In some embodiments, a method of manufacturing a 3D NAND memory structure may include: forming a plurality of alternating material layers arranged in a vertical stack on a silicon substrate; etching a channel hole extending through the plurality of alternating material layers to the silicon substrate; forming a tunnel layer surrounding the channel hole and contacting the plurality of alternating material layers; and epitaxially growing an epitaxial silicon core from the silicon substrate through the channel hole within the tunnel layer.

[0007] In some embodiments, a 3D NAND memory array may include a silicon substrate and a plurality of alternating material layers arranged in a vertical stack on the silicon substrate. A plurality of channel holes may extend through the plurality of alternating material layers. The memory array may also include a plurality of support structures extending through the plurality of alternating material layers into the silicon substrate.

[0008] In some embodiments, a 3D NAND memory structure may include a layer on a silicon substrate and an oxide layer over the silicon substrate. A hole may be etched, the hole extending through the oxide layer to expose the silicon substrate. The structure may also include epitaxial silicon and a nitride layer, the epitaxial silicon grown from the substrate through the hole in the oxide layer, the nitride layer covering the oxide layer and the epitaxial silicon.

[0009] In some embodiments, a method of manufacturing a 3D NAND memory structure may include: forming a layer on a silicon substrate. The method may also include: etching a hole, the hole extending through the layer to expose the silicon substrate. The method may additionally include: epitaxially growing epitaxial silicon for a channel from the silicon substrate through the hole. The method may further include: forming the 3D NAND memory structure above the layer and the substrate, such that the channel hole in the 3D NAND memory structure includes an epitaxial silicon core grown from the epitaxial silicon.

[0010] In any embodiment, any and all of the following features may be implemented in any combination and are not limited. The silicon substrate may include single crystal silicon, and the epitaxial silicon core grows from the single crystal silicon through the channel hole. The alternating material layers may include alternating layers of oxide material and nitride material. The alternating material layers may include alternating layers of oxide material and metal, wherein the metal may form a gate electrode for a separate memory cell in the memory structure. The epitaxial silicon core may extend into the silicon substrate. The memory structure may also include an epitaxial silicon layer, the epitaxial silicon layer extending beyond the channel hole, wherein the epitaxial silicon layer may be between the silicon substrate and the plurality of alternating material layers, and the epitaxial silicon layer may connect the epitaxial silicon core to a plurality of other channels in the memory structure. The memory structure may also include a support structure, the support structure extending through the plurality of alternating material layers and the epitaxial silicon layer and extending into the silicon substrate. Slits may be etched in the memory structure, the slits extending through the plurality of alternating material layers to a sacrificial nitride layer above the silicon substrate. The sacrificial nitride layer may be exposed to an etching process configured to selectively etch the sacrificial nitride layer. A portion of the tunnel layer exposed after removing the sacrificial nitride layer may be removed. An epitaxial silicon layer may be epitaxially grown from the silicon substrate to replace the sacrificial nitride layer. A second channel hole may be etched, and the second channel hole may be filled with a gap filling material (as a support structure) to form a support structure, the second channel hole extending through the multiple alternating material layers into the silicon substrate. Multiple support structures may include a metal filling one or more of the multiple channel holes. Multiple support structures may include gap filling materials in slits in a memory array. Alternating slits in a memory array may form a support structure. Multiple support structures may include a combination of gap filling materials in one or more slits in a memory array and / or metal filling one or more of the multiple channel holes.

[0011] When an epitaxial silicon plug is formed before the alternating material layers, for example, epitaxial silicon is formed above the top surface of a silicon oxide layer above a silicon substrate, a 3D NAND memory structure can be formed on top of the epitaxial silicon. For example, the method may also include: forming a nitride layer above the layer and the epitaxial silicon and grinding the nitride layer to remove surface variations caused by the difference in height between the layer and the epitaxial silicon. The method may further include: forming a plurality of alternating nitride and oxide layers above the layer and the substrate; etching a channel hole, the channel hole passing through the plurality of alternating nitride and oxide layers to expose the epitaxial silicon; and epitaxially growing the epitaxial silicon upward through the channel hole to form the epitaxial silicon core of the channel hole. The epitaxial silicon may extend above the top surface of the oxide layer. The top surface of the nitride layer may be planarized so that the top surface of the nitride layer is flat without surface variations caused by the difference in height between the oxide layer and the epitaxial silicon. The hole may be extended below the top surface of the silicon substrate so that the epitaxial silicon extends into the silicon substrate. A plurality of alternating material layers are arranged in a vertical stack on the nitride layer. A channel hole may extend through the plurality of alternating material layers to the epitaxial silicon. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] A further understanding of the nature and advantages of the various embodiments may be achieved by reference to the remainder of the specification and drawings, wherein the same reference numerals are used in the various drawings to refer to similar components. In some cases, a sub-label associated with a reference numeral is used to represent one of a plurality of similar components. When a reference numeral is referenced without specifying an existing sub-label, it is intended to refer to all such plurality of similar components.

[0013] Figure 1 A top view of one embodiment of a processing system showing deposition, etch, bake, and cure chambers according to an embodiment is shown.

[0014] Figure 2A-2Q Incremental stages are shown for producing an array of 3D NAND flash memory cells with epitaxial silicon channels, according to some embodiments.

[0015] Figure 3A A portion of a memory array is depicted in accordance with some embodiments.

[0016] Figure 3B A portion of a memory array is depicted when a portion of the channel has been used for support structures to facilitate an epitaxial silicon channel core, according to some embodiments.

[0017] Figures 4A-4LDepicted are progressive steps in the fabrication process of a memory structure according to some embodiments that use slits separating memory blocks for support structures while growing epitaxial silicon channels for individual memory cells.

[0018] Figure 5 Depicted is a top view of a portion of a memory array in accordance with some embodiments.

[0019] Figures 6A-6H Depicted are progressive steps for forming a stack including support structures in both channel holes and slots, according to some embodiments.

[0020] Figure 7 Depicted is a top view of a portion of a memory array in accordance with some embodiments.

[0021] Figure 8 A flow chart is shown of a method for fabricating a 3D NAND memory structure according to some embodiments.

[0022] Figures 9A-9I Steps in a process for forming a channel hole are shown according to some embodiments, wherein there is epitaxial silicon at the base of the channel hole before the channel hole is formed in tiers of alternating oxide / nitride layers.

[0023] Fig.10 A flow chart 1000 is shown of a method for fabricating a 3D NAND memory structure according to some embodiments. DETAILED DESCRIPTION

[0024] Conventional three-dimensional (3D) NAND flash memory structures use channel cores made of oxide materials or polysilicon. However, epitaxial silicon exhibits much higher mobility than polysilicon or other similar materials. The present disclosure describes a 3D NAND flash memory structure using epitaxial silicon cores grown directly from a silicon substrate. Alternating oxide-nitride material layers may be formed as a stack, and channel holes may be etched through the material layers, with the channel holes extending downward to the silicon substrate. A tunnel layer may be formed around the channel hole to contact the alternating material layers, and an epitaxial silicon core may be grown from the silicon substrate upward through the channel hole. In some implementations, a support structure may be formed in the channel hole or in a slit of a memory array to provide physical support when the epitaxial silicon core grows through the channel.

[0025] Figure 1A top view of one embodiment of a processing system 100 of deposition, etching, baking and curing chambers according to an embodiment is depicted. In the figure, a pair of front-opening wafer transfer boxes 102 supply substrates of various sizes that are received by a robot arm 104 and placed into a low pressure holding area 106 before being placed into one of the substrate processing chambers 108a-f located in a tandem section 109a-c. A second robot arm 110 can be used to transport substrates from the holding area 106 to the substrate processing chambers 108a-f and back. Each substrate processing chamber 108a-f can be equipped to perform a variety of substrate processing operations, including dry etching processes described in this case in addition to cyclic layer deposition, atomic layer deposition, chemical vapor deposition, physical vapor deposition, etching, pre-cleaning, annealing, plasma treatment, degassing, orientation and other substrate processes.

[0026] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing and / or etching a material film on a substrate wafer. In one configuration, two pairs of processing chambers (such as 108c-d and 108e-f) may be used to deposit materials on a substrate, and a third pair of processing chambers (such as 108a-b) may be used to cure, anneal or treat the deposited film. In another configuration, all three pairs of chambers (such as 108a-f) may be configured to deposit and cure films on substrates. Any one or more of the processes described may be implemented in an additional chamber separate from the manufacturing system shown in different embodiments. It should be understood that the processing system 100 may consider additional configurations for deposition, etching, annealing and curing chambers for material films. In addition, any number of other processing systems may be used with the present technology and may be incorporated into chambers for performing any particular operation. In some embodiments, a chamber system that can provide access to multiple processing chambers while maintaining a vacuum environment in various portions (such as the holding and transfer areas mentioned) can allow operations to be performed in multiple chambers while maintaining a specific vacuum environment between discrete processes.

[0027] The processing system 100, or more specifically, more chambers incorporated into the processing system 100 or other processing systems, can be used to produce structures according to some embodiments of the present technology. For example, the processing system 100 can be used to produce memory arrays by performing operations such as deposition, etching, sputtering, grinding, cleaning, etc. in various substrate processing chambers 108.

[0028] Figure 2A-2Q Incremental stages are shown for producing an array of 3D NAND flash memory cells with epitaxial silicon channels, according to some embodiments. Figure 2A Depicted is a partial stack of alternating oxide-nitride layers that may be formed for a 3D NAND flash memory array. Figure 2A Each layer shown in can be formed progressively one layer above the previous layer using any deposition or layer formation technique. In this example, the layers can be formed on a substrate 200 of silicon material (such as epitaxial silicon or a single crystal silicon wafer). A silicon oxide layer 202 can be formed above the substrate 200, followed by a silicon nitride layer 204. In some embodiments, the silicon oxide layer 202 and the silicon nitride layer 204 can represent the initial layers on the substrate 200, and these layers can be thicker than the alternating oxide-nitride layers formed thereon. Next, alternating layers of silicon oxide 206 and silicon nitride 208 can be formed in a stacked form.

[0029] The substrate 200, the silicon oxide layer 206, the silicon nitride layer 208 and the bottom Figure 2A-2Q The progressive formation of other materials described in the above may be collectively referred to as stack 224. Figure 2A As shown, stack 224 may initially have a limited height. For example, the completed stack may have a very large number of layers (e.g., 128 pairs of alternating oxide and nitride layers). However, initially forming all of these layers may result in stack 224 having an aspect ratio that is too high to reliably form narrow channel holes and other vias that pass through the entire stack 224. Therefore, stack 224 may be partially formed first. The partial stack may then have a channel hole etched in the partial stack. Additional alternating oxide and nitride layers may be added to the top of the partial stack, and these additional layers may be etched in the same location to form a channel hole that passes continuously through all of the alternating oxide and nitride layers with a more uniform width, thereby maintaining a high aspect ratio without the sidewalls of the channel hole forming excessive angling.

[0030] Figure 2BHow a portion of the stack is etched to form a hole 203 that penetrates the alternating silicon oxide layers 206 and silicon nitride layers 208 is illustrated. The hole 203 may be formed by layering a mask over the portion of the stack and performing an etching process to remove the material exposed by the mask. Any etching process may be used, and some embodiments may use a dielectric etch. Because the desired aspect ratio of the hole 203 for the device channel is relatively high (i.e., the vertical depth of the hole 203 is relatively large compared to the horizontal width of the hole 203), etching through the alternating silicon oxide layers 206 and silicon nitride layers 208 may benefit from a dielectric etch. In general, the depth of the hole 203 may be controlled based on the number of silicon oxide layers 206 and the number of silicon nitride layers 208 to be etched. For example, the time allowed to run the etching process may be determined by the number of silicon oxide layers 206 and the number of silicon nitride layers 208 along the thickness of these layers. For example, some embodiments may etch the hole 203 down to the silicon nitride layer 204. Other embodiments may etch the hole 203 down to the silicon oxide layer 202 , or down to the top of the substrate 200 . Figure 2B The example shown stops the etch at the top of the silicon nitride layer 204 .

[0031] Figure 2C It illustrates how a bottom punch etch may be used to penetrate the substrate 200 to expose the silicon of the substrate 200 according to some embodiments. Figure 2B The dielectric etch used in the present invention may stop the channel hole etching before etching through the substrate 200. Some embodiments may then perform a second etching process so that the hole 203 extends downward into the substrate 200. This additional etching may be a directional etch oriented vertically toward the bottom of the hole 203, which may be referred to herein as a "bottom punch" etch. The bottom punch etch may allow the silicon material of the substrate 200 to be exposed at the bottom of the hole 203. The bottom punch etch may represent an etch separate from the etch used to form the hole. For example, the bottom punch etch may be performed in a conductor etch chamber rather than in a dielectric etch chamber, and may have better critical dimension uniformity and profile tuning than the dielectric etch used to initially form the hole 203 for the device channel. The bottom punch may thus extend the hole 203 downward into the substrate 200 to expose the silicon material. For example, the bottom punch etch may extend to the top surface of the substrate 200, or may penetrate into the substrate 200 to below the top surface of the substrate 200. Alternatively, other embodiments may use a single etching process to etch the entire length of the hole 203 down into the substrate 200, thereby Figure 2B-2C The exposed silicon material of substrate 200 can be used in a subsequent step to grow silicon by epitaxy in the channel that forms a 3D NAND flash memory cell.

[0032] Figure 2D Depicting how the stack 224 may be extended by adding additional silicon oxide layers 207 and silicon nitride layers 209 on top of a partial stack in accordance with some embodiments. These additional layers may be formed incrementally on top of the partial stack. Alternatively, these layers may be formed separately and placed on top of the partial stack. It should be understood that the partial stacks shown in these figures are greatly simplified for the sake of clarity. In reality, the stack may include a large number of layers, a large number of channel holes, and may be used to form hundreds of 3D NAND flash memory cells. However, these figures have been simplified to represent the formation of a single epitaxial silicon channel and adjacent support structures or slits in a memory array. For example, an actual stack may include thousands of channels, over 100 alternating oxide and nitride layers, and multiple slits and support structures. These layers may be formed in multiple processes, with etching operations being performed incrementally on each batch of layers as they are added to the partial stack. Therefore, although Figure 2D Only two partial stacks are shown in combination, but it should be understood that many additional partial stacks may be layered and etched to form the hole 203 through the stack 224. For example, some embodiments may include a combination of two partial stacks, each with approximately 128 alternating oxide-nitride layers for a total of 256 alternating oxide-nitride layers.

[0033] Figure 2E A stack 224 is shown formed of multiple partial stacks, each of which is etched separately, according to some embodiments. After adding the additional silicon oxide layer 207 and silicon nitride layer 209 of the second partial stack, holes 211, 219 can be etched in these layers as shown. Note that these holes 211, 219 can be formed using a mask similar to the mask previously used to etch the holes 203 in the first partial stack. By etching these layer sets progressively, very high aspect ratios can be achieved regardless of the depth of the holes 211, 219 in the full stack 224.

[0034] Figure 2FA support feature 210 is shown according to some embodiments, which may be formed in one of the holes to provide support during subsequent steps of the process. The support feature 210 may be selectively deposited in one of the holes to form a rigid structure. For example, some embodiments may use a metal such as tungsten to form the support feature 210. Some embodiments may use a dielectric filler such as SiOx or a metal-aluminum oxide-nitride-oxide-silicon (MANOS) stack as the support feature 210. Any deposition process may be used to form the support feature 210. Note that the support member 210 may extend downward into the substrate 200 by virtue of the etching process described above that overshoots the last silicon oxide layer 202. As will be demonstrated later in this disclosure, when the sacrificial nitride layer 204 is removed, the support member 210 prevents the layers of the stack 224 from collapsing. In addition, extending the support feature 210 downward into the substrate 200 prevents any movement of the upper layers of the stack 224 when the nitride layer 204 is subsequently removed.

[0035] Figure 2G An initial layer of epitaxial silicon 212 is depicted formed in one of the holes 219 in accordance with some embodiments. As described above, the additional depth of the bottom punch etching into the substrate 200 exposes the silicon material of the substrate 200 to the channel hole 219. Because the single crystal silicon of the substrate 200 is exposed, a layer of epitaxial silicon 212 may be grown in the channel hole using a process such as epitaxial deposition of silicon or epitaxy to grow a thin layer of single crystal silicon over the single crystal silicon substrate 200. For example, some embodiments may perform the epitaxial process by chemical vapor deposition. Materials such as silicon tetrachloride, trichlorosilane, dichlorosilane, silane, and other silicon chemical sources may be provided to a deposition chamber to incrementally form the epitaxial silicon 212 grown on top of the substrate 200. The height of the epitaxial silicon 212 may be above the silicon oxide layer 202, but below the next silicon oxide layer in the stack 224. For example, the height of the epitaxial silicon 212 may be within the sacrificial nitride layer 204.

[0036] exist Figure 2G At this stage shown, the channel hole 219 has been formed in the multiple tiers of alternating nitride / oxide layers such that the channel hole 219 extends downward to expose the substrate 200. After the channel hole 219 has been formed in the device stack 224, the epitaxial silicon 212 is then grown. However, an alternative embodiment may first expose the silicon of the substrate 200 and form the epitaxial silicon 212 before forming subsequent layers and etching the channel hole. This alternative process is described in detail below. Figures 9A-9I This alternative process can be freely replaced Figure 2A-2G to form the same structure.

[0037] Figure 2HDeposition of a tunneling layer 214 in the hole 219 is depicted in accordance with some embodiments. Since the hole 219 can now be used to form a channel for the vertical column of the 3D NAND memory cell, the hole 219 may also be referred to herein as a channel hole 219. The tunneling layer 214 may be formed by depositing a blocking dielectric or oxide, a charge trapping nitride such as silicon nitride, and a tunneling dielectric or oxide. In the present disclosure, these three layers may be collectively referred to as a "tunneling layer" 214. The oxide layer in the tunneling layer 214 may provide an offset for the conduction band and the valence band of the transistor device of the memory cell.

[0038] For example, a silicon nitride layer may be surrounded by inner and outer layers of silicon oxide. The various layers of tunnel layer 214 may be formed using atomic layer deposition, and thus the layers of tunnel layer 214 may be relatively thin compared to the alternating oxide-nitride layers of stack 224. This process may result in tunnel layer 214 growing on the sidewalls of channel hole 219 and along the bottom of the channel hole above the top of epitaxial silicon 212. Note that because epitaxial silicon 212 stops before the alternating silicon oxide layers 206 and silicon nitride layers 208, the interior of the channel for a 3D NAND memory cell may be covered with tunnel layer 214.

[0039] Fig.2I It is shown how the channel hole 219 may be filled with a sacrificial gap fill material 216 according to some embodiments. In order to protect the tunnel layer 214 from subsequent etching processes, the channel hole 219 may be filled with a sacrificial gap fill material 216, such as carbon.

[0040] Figure 2J Slit 218 is shown as being etched in stack 224 in accordance with some embodiments. Slit 218 may represent a relatively long trench etched in stack 224 such that slit 218 is adjacent to a plurality of individual channel holes along the length of slit 218. See below Figure 3A-3B, an overhead view of the slit relative to the channel hole in the memory array. In contrast to the etching process used to form the channel hole, the slit 218 can be etched using a single process that penetrates all layers of the stack 224. A single process can be used because the slit 218 can be wider than the channel hole. Therefore, the aspect ratio can be smaller and can therefore be achieved in a single process. In some embodiments, a carbon liner 220 can be deposited on the interior of the slit 218 to protect the inner silicon oxide layer 206 and the silicon nitride layer 208 from the subsequent chemical etching process using the slit 218. For example, the carbon liner 220 can be deposited on the sidewalls and bottom of the slit 218, and a subsequent etch can be used to remove the carbon liner 220 from the bottom of the slit 218 to expose the silicon nitride layer 204. The slit 218 can be used in a memory array of two separate different memory blocks. In subsequent processing, the slots 218 may also provide access to all nitride layers in the stack 224 so that these nitride layers can be removed and replaced with tungsten (or any other conductive material) to form conductive paths for each memory cell. These conductive paths may then form word lines or gate electrodes for the memory cells. For example, a wet etch using hot phosphoric acid may be used to remove the nitride layers from the stack 224, and then the slots 218 may provide access for precursors so that an atomic layer deposition process may be used to grow tungsten left behind from the removed nitride layers in the voids.

[0041] Figure 2K The selective removal of the nitride layer 204 is depicted in accordance with some embodiments. In order to grow the epitaxial silicon 212 in the channel hole, the nitride layer 204 may be removed to expose the portion of the tunnel layer 214 that needs to be removed so that the epitaxial silicon 212 may be exposed to the channel hole again. In this example, a wet etch may be used, such as a hot phosphoric acid chemical etch. The wet etch may access the nitride layer 204 through the slit 218 and selectively remove the nitride layer 204. The carbon liner 212 may protect the inner nitride layer from the etching process. Other embodiments may use a dry etch or other process configured to selectively remove the nitride layer 204.

[0042] Figure 2LThe selective removal of tunnel layer 214 from the bottom of the channel hole is depicted in accordance with some embodiments. Removal of the nitride layer of tunnel layer 214 may use the wet / dry etching process described above. Similar processes may be used to selectively remove dielectric or oxide layers of tunnel layer 214. Note that the gap 230 left from the removal of nitride layer 204 is lined on the top and bottom with oxide layers. These oxide layers (such as oxide layer 202) may be formed so that they are slightly thicker than the other oxide layers in stack 224. However, because the oxide and nitride layers in tunnel layer 214 may be formed as atomic layer deposition layers, these layers will be relatively thin so that they can be removed without removing a large portion of the other oxide layers that may be exposed to the etching process.

[0043] Figure 2M The removal of sacrificial gap fill material 216 from channel hole 219 is depicted in accordance with some embodiments. Note that the removal of sacrificial gap fill material 216 leaves channel hole 219 lined by tunnel layer 214 and exposed to epitaxial silicon 212.

[0044] Figure 2N The growth of epitaxial silicon 212 is depicted according to some embodiments. The epitaxial process may be performed as described above. However, because the slits 218 and the channel holes 219 are exposed to the epitaxial silicon 212, an epitaxial silicon layer 236 may be grown to fill the gaps 230 and begin to fill the channel holes 219. When the bottom of the channel holes 219 is reached, the growth of the epitaxial silicon layer 236 may be stopped to prevent the slits 218 from also being filled with epitaxial silicon.

[0045] Fig.2O The selective removal of a portion of the epitaxial silicon layer 236 at the bottom of the slot 218 is shown. An etching process may be used to remove portions of the epitaxial silicon layer 236 to perform a bottom "punch" as described above. The etching may remove portions of the epitaxial silicon layer 236 until the bottom of the slot 218 is as shown. Fig.2O A bottom oxide layer 202 is shown or the etch may go below the bottom oxide layer 202 into the substrate 200 .

[0046] Figure 2P Deposition of a sacrificial gap fill material 240 in the slots 218 is depicted in accordance with some embodiments. The sacrificial gap fill material 214 may be deposited in the slots 218 such that the epitaxial silicon layer 236 may grow in the channel holes 219 without filling the slots 218.

[0047] Figure 2QEpitaxial silicon layer 236 is depicted epitaxially grown upward through channel hole 219 in accordance with some embodiments. Thus far, previous steps in this process have been performed to provide channel holes in which epitaxial silicon can be grown as channel cores for 3D NAND flash memory cells. For example, the above steps provide a reference layer of epitaxial silicon grown from substrate 200 itself at the bottom of channel hole 219. The epitaxial process can be performed as described above to grow epitaxial silicon layer 236 upward through channel hole 219. The resulting structure can include a stack 224 with channel holes, which are filled with epitaxial silicon cores 242, rather than with oxide cores or polysilicon cores as found in conventional "macaroni" structures of 3D NAND flash memory cells. Thus, the embodiments described herein can be distinguished from conventional 3D NAND flash memory cells at least in part by the epitaxial silicon cores 242 for the channel and the physical connection between the epitaxial silicon cores 242 and substrate 200 and the angled walls of the channel and the channel hole.

[0048] refer to Figure 2Q , the 3D NAND memory structure may include a silicon substrate 200, which may be formed of single crystal silicon. The memory structure may also include a plurality of alternating material layers 275 arranged in a vertical stack on the silicon substrate 200. The alternating material layers 275 may include alternating layers of oxide materials and nitride materials (such as silicon oxide and silicon nitride). At a later stage of the manufacturing process, the alternating material layers 275 may alternatively include alternating layers of oxide materials and metals (such as tungsten). For example, the nitride material may be selectively removed and replaced with a metal to form a gate electrode for an individual memory cell in the memory structure.

[0049] The alternating material layers 275 may define a channel hole 277 extending through the plurality of alternating material layers 275 to the silicon substrate 200. This channel hole 277 may be formed using any of the processes described throughout this disclosure. As shown, the channel hole 277 may be approximately perpendicular to the plurality of alternating material layers 275. The memory structure may also include a channel within the channel hole 277. The channel may include a tunnel layer 214 surrounding the interior of the channel hole (and therefore the exterior of the channel) using the layers described above. The channel may also include an epitaxial silicon core 242 within the tunnel layer, the epitaxial silicon core 242 contacting the silicon substrate 200. In some cases, the epitaxial silicon core 242 may extend into the silicon substrate 200 so that the epitaxial silicon core 242 begins its epitaxial growth below the top horizontal surface of the silicon substrate 200.

[0050] The memory structure may also include an epitaxial silicon layer 236 extending beyond the channel hole, wherein the epitaxial silicon layer 236 may be parallel to the plurality of alternating material layers 275. Recall that Figure 2QOnly one of many channels in the memory structure is shown. Thus, the epitaxial silicon layer 236 can connect the epitaxial silicon core 242 of the illustrated channel to multiple other channels in the memory structure. For example, the epitaxial silicon core of each channel connected by the epitaxial silicon layer 236 can be grown simultaneously from the epitaxial silicon layer 236 during the same epitaxial process.

[0051] The above process can be used to selectively grow epitaxial silicon core 242 using single crystal silicon of substrate 200. 3D NAND flash memory cells using epitaxial silicon core 242 exhibit better performance than similar memory cells using oxide cores. For example, the mobility of polycrystalline silicon is 10 to 20 times less than the mobility of epitaxial silicon.

[0052] Further processing may be performed later on the stack 224 to complete the memory array. Although these operations are beyond the scope of the present disclosure, they may include: removing the sacrificial gap fill material 240 from the slits, removing the nitride layer in the stack 224, depositing a conductive metal (such as tungsten) instead of the nitride layer to form a gate electrode, performing a staircase etch on the stack, etc.

[0053] Figure 3A A portion of a memory array 300 is shown in accordance with some embodiments. This portion of the memory array 300 may represent a single memory block with several offset rows of channels 256. Slits 250, 252 may be used to separate the memory block from other memory blocks. This example uses 24 channels into the offset columns between the slits 250, 252. This portion of the memory array 300 may use conventional oxide or polysilicon cores for the channels. Thus, no support structures may be required, and each channel hole may be used to implement a memory cell.

[0054] In contrast, Figure 3B A portion of a memory array 301 is depicted when a portion of the channel has been used for support structures to facilitate an epitaxial silicon channel core in accordance with some embodiments. As described above, the process used to grow the epitaxial silicon channels of the memory cells in the memory array 301 may use a process in which a portion of the channel holes are used for support structures 254 to prevent the memory array 301 from collapsing when the sacrificial nitride layer is removed to make room for the epitaxial silicon layer. These support structures 254 may be spaced throughout the memory array to provide adequate support for the stack of layers in the array during the manufacturing process. Note that Figure 3BThe spacing shown in is provided as an example only and is not intended to be limiting. In this example, the spacing of the support structures 254 is approximately every four channel holes and every other column. This configuration does slightly reduce the bit density per area in the memory array 301 by using a portion of the channel holes of the support structures 254 that would otherwise be used for memory cells.

[0055] As described above, some embodiments may use channel holes to provide support structures during the manufacturing process. Advantages of using channel holes for support structures include the ability to increase or decrease the spacing of the support structures as needed. However, some embodiments may form the same epitaxial silicon channels using slits instead of channel holes to provide support structures. These embodiments trade an increase in channel density for the amount of support provided across the memory block.

[0056] Figures 4A-4L Depicted are progressive steps in the fabrication process of a memory structure according to some embodiments that use slits separating memory blocks for support structures while growing epitaxial silicon channels for individual memory cells. Figure 4A A channel hole 401 is depicted in a stack 400 with epitaxial silicon 406 grown from a substrate 400 according to some embodiments. Figure 2A-2G The process described above is used to form the channel hole 401 and the epitaxial silicon 406. In some embodiments, the epitaxial silicon 406 can be formed after the channel hole 401 is formed in the first set of oxide / nitride layers and before the upper set of oxide / nitride layers are formed, and the epitaxial silicon 406 can be etched to extend the channel hole 401. For example, returning to Figure 2C , after the channel hole 203 has been etched and the bottom punch etch has been used to extend the channel hole 203 into the substrate 200, epitaxial silicon 406 can be grown from the exposed substrate 200 in the channel hole 203 at this stage. After the epitaxial silicon 406 has been formed in the hole 203, upper alternating layers of oxide 207 and nitride 209 can be added and etched to increase the number of device layers and the depth of the channel hole 203 to finally form Figure 4A Alternatively, the epitaxial silicon 406 may be grown after the channel hole 401 has been completely formed, or at any stage after the silicon of the substrate 400 has been exposed.

[0057] In this example, rather than using one of the channel holes 401 for a support structure, each of the channel holes 401 may be used to form a channel for a memory cell. Figure 4B The channel hole 401 is shown after being lined with a tunnel layer 408. Figure 2H The formation of the tunnel layer is described in detail. Figure 4CThe trench hole 401 is shown filled with a sacrificial gap fill material 410, which may be as described above with respect to Fig.2I Describe the formation in detail.

[0058] Figure 4D Slits 412, 413 are shown that may be formed on either side of a memory block according to some embodiments. Figure 4D Only two channel holes are shown, but there may be many additional channels between the slits 412, 413. For example, the slits 412, 413 may surround a memory block having a block width of 24 channels. These channels may be arranged in a honeycomb pattern with two offset rows of 12 channels per row. Multiple pairs of the 24 channels of these offset rows may be present in the block. Typically, the slits 412, 413 are only etched to a depth above the substrate 400 but below the first oxide layer 417 in the alternating material layers forming the memory cells. For example, the slit 213 is etched to a depth below the first oxide layer 417 and within the sacrificial nitride layer 415. However, in order to provide a support structure when the epitaxial silicon layer and channel core are later fabricated, the slits may undergo additional or extended etching processes to increase the depth of the slits. For example, the slit 412 may be etched to a depth below the top of the substrate 400 using a bottom punch etch. This allows the slot 412 to act as a support structure anchored to the substrate 400, rather than allowing the slot 412 to float on top of the substrate.

[0059] Figure 4E Slits 412 are depicted as being designated to be used as support structures filled with gap fill material 414 in accordance with some embodiments. In this example, alternating slits may be used as support structures in a memory array. Thus, slits 413 may be maintained at a shallow depth, while slits 412 may be etched to a depth below substrate 400 and filled with gap fill material 414, which may serve as a support structure during the growth of the epitaxial silicon layer.

[0060] Figure 4F The sacrificial nitride layer 415 is shown removed according to some embodiments. Figure 2K As described above, the sacrificial nitride layer 415 may be exposed to an etching process through the slit 413 to selectively remove the sacrificial nitride layer 415. Figure 4F 4. It is not explicitly shown in the drawings, but the slot 413 may have a protective liner material (such as carbon) applied to the sidewalls of the slot 413 to prevent the etching process from removing the nitride layer from the alternating material layers later used to form the memory cell. An additional bottom punch etch may be applied to remove the protective liner from the bottom of the slot 213, exposing the sacrificial nitride layer 415 to the etching process.

[0061] Figure 4G The tunnel layer 408 is depicted being removed from the bottom of the trench in accordance with some embodiments. For example, the layers used in the tunnel layer 408 may be selectively removed by a wet and / or dry etching process as described above. After removing the exposed portion of the tunnel layer 408 at the bottom of the trench hole, the gap fill material 414 may provide a support structure for the stack 400 to prevent the stack 400 from collapsing after exposing the gap 416 between the substrate 400 and the first oxide layer 417.

[0062] Figure 4H Removal of the sacrificial gap fill material 410 from the trench hole 401 using a selective etch is shown. Fig. 4I The epitaxial growth of the epitaxial silicon layer 420 is shown in the gap 416. As described above, the epitaxial silicon layer 420 may be grown until the epitaxial silicon layer 420 begins to fill the channel hole 401. Figure 4J A hole 422 is shown formed in the epitaxial silicon layer 420 using a bottom punch etching process to extend the slit 413 . Figure 4K The slot 413 is shown filled with a gap filling material 424 . Figure 4L The growth of epitaxial silicon core 426 in each channel in the memory block is shown. Each of these steps can be combined as above Figure 2A-2Q Execute as described in detail.

[0063] Figure 4L The channels in the resulting stack 400 shown may be Figure 2Q The channels in the final stack 224 are substantially the same, with the alternating material layers 475 and the channel holes 477 lined with the tunnel layer 408 and filled with the epitaxial silicon core 426. However, in a memory structure including this stack 400, no channels need to be set aside as support structures. Instead, the maximum channel density can be achieved by using the slits as support structures during the manufacturing process. As described above, additional process steps beyond the scope of the present disclosure may then be performed on the stack 400 to complete the fabrication of the memory structure, such as removing the alternating nitride layers, forming a conductive layer (e.g., a tungsten layer) to form a gate electrode, performing a step etch, etc.

[0064] Figure 5A top view of a portion of a memory array 500 is depicted in accordance with some embodiments. In this example, all of the channel holes 456 may be used to form channels for the memory cells. Alternating slits 550 may be used to provide support structures during the manufacturing process, while the remaining slits 552 may be used to provide access to the sacrificial nitride layer during the manufacturing process as described above. Note that the use of alternating slits 550 is used only as an example and is not meant to be limiting. Depending on the block width of each memory block, other embodiments may use one of every third slit, every fourth slit, etc. as a support structure based on the number of channels in each block and the amount of support needed to prevent collapse.

[0065] Some embodiments may use a combination of slits and channel holes to provide support structures, rather than using only channel holes as support structures or only slits as support structures. This makes the spacing of the support structures extremely flexible. Using slits can still minimize the number of channel holes sacrificed as support structures, while still allowing multiple channel holes to provide additional support structures as needed.

[0066] Figures 6A-6H Depicted are progressive steps for forming a stack 600 including support structures in both channel holes and slots, according to some embodiments. Fig. 6A A stack 600 is shown with a channel hole filled with a support structure 604. Additional channel holes with support structures may also be present in the stack 600, which may be Fig. 6A The stack 600 may also include a channel hole filled with a gap fill material 602, wherein the tunnel layer 603 separates the gap fill material 602 from the epitaxial silicon 611 grown from the substrate 601. Note that there may also be gaps in the stack 600 that are not shown in FIG. Fig. 6A The stack 600 may also include a slot 606 with a liner etched to a level above the substrate 601 and contacting the sacrificial nitride layer 610. Another slot may be filled with a gap fill material 608 and may extend down into the substrate 601 to serve as a support structure.

[0067] The remaining steps of growing epitaxial silicon into the channels of stack 600 can be performed as described in detail above. For example, Figure 6B The sacrificial nitride layer 610 is shown removed to expose the gap 612 when the stack 600 is supported by a support structure. Figure 6C The portion of the tunnel layer 603 exposed in the gap 612 is shown removed. Fig.6D Removal of the gap fill material 602 in the trench hole 614 is shown. Fig. 6E The growth of an epitaxial silicon layer 616 in the gap 612 is shown. Fig. 6FThe result of a bottom punch etch is shown to extend a hole 618 through the epitaxial silicon layer 616 for the slit 606 . Figure 6G Gap-fill material 620 is shown in the slot 606 . Figure 6H The growth of epitaxial silicon core 622 in the channel hole 614 is shown.

[0068] Figure 7 A top view of a portion of a memory array 700 is depicted in accordance with some embodiments. In this example, most of the channel holes can be used to form channels for the memory cells. Alternating slits 750 can be used to provide support structures during the manufacturing process, while the remaining slits 752 can be used to provide access to the sacrificial nitride layer during the manufacturing process as described above. Rather than using only slits as support structures, this hybrid example uses a combination of slits and channel holes 756 to provide the described support structures. This makes the spacing of the support structures very configurable. Using slits minimizes the number of channel holes that are sacrificial support structures, while still allowing multiple channel holes to provide additional support structures as needed.

[0069] As shown in this embodiment, the process described in the present case can be used to form a 3D NAND memory array 700, which includes a silicon substrate and a plurality of alternating material layers arranged in a vertical stack on the silicon substrate. A plurality of channel holes can extend through the alternating material layers. A plurality of support structures extending through the plurality of alternating material layers into the silicon substrate can provide support during the manufacture of the memory array 700. The support structure can include a metal that fills one or more of the channel holes 756. The support structure can also include a gap filling material that fills the slits 750 in the memory array 700. Some embodiments can use a combination of metal-filled channel holes and / or gap filling materials in one or more slits in any combination and without limitation.

[0070] Figure 8 A flowchart 800 is shown of a method for fabricating a 3D NAND memory structure according to some embodiments. The method may be used in Figure 1 The method may include forming a plurality of alternating material layers arranged in a vertical stack on a silicon substrate (802). The alternating layers may include the Figure 2A-2E The method may also include etching a channel hole extending through the plurality of alternating material layers to the silicon substrate (804). The channel hole may be etched through the silicon substrate using bottom punch etching, as described above in Figure 2E Described in .

[0071] The method may additionally include forming a tunnel layer surrounding the channel hole and contacting the plurality of alternating material layers (806). The tunnel layer may be formed by depositing a tunnel oxide (including the layers described above) and selectively removing portions of the tunnel layer at the bottom of the channel hole that are exposed to an etching process. Figure 2H-2L A tunnel layer in the channel hole is formed as described above.

[0072] The method may further include: epitaxially growing a silicon core from the silicon substrate through the channel hole in the tunnel layer (808). The epitaxial silicon core may be grown using the steps described throughout this disclosure. For example, growing the epitaxial silicon core may include: etching a slit in the memory structure, the slit extending through the plurality of alternating material layers to a sacrificial nitride layer above the silicon substrate, such as Figure 2J The sacrificial nitride layer may be exposed to an etching process, the etching process being configured to selectively etch the sacrificial nitride layer, such as Figure 2K-2M An epitaxial silicon layer may be epitaxially grown from the silicon substrate to replace the sacrificial nitride layer, as shown in FIG. Figure 2N In some embodiments, the support structure may be formed by etching a second channel hole and filling the second channel hole with a gap filling material (as a support structure), wherein the second channel hole extends through the plurality of alternating material layers into the silicon substrate.

[0073] It should be understood that Figure 8 The specific steps in provide specific methods for manufacturing 3D NAND memory structures according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps outlined above in a different order. In addition, Figure 8 The individual steps shown may include multiple sub-steps, which may be performed in various orders suitable for the individual steps. In addition, additional steps may be added or deleted according to specific applications. Many variations, modifications, and substitutions also fall within the scope of the present disclosure.

[0074] In the above-described embodiment, before epitaxial silicon is formed at the bottom of the channel hole, at least a portion of the channel hole is first formed in the alternating nitride / oxide layers down to the substrate. However, alternative methods can also be used to form epitaxial silicon at the bottom of the channel hole at an earlier stage in the manufacturing process.

[0075] Figures 9A-9I Steps in a process for forming a channel hole are shown according to some embodiments, wherein the channel hole has epitaxial silicon at its base before forming the channel hole in tiers of alternating oxide / nitride layers. Fig. 9A A silicon substrate 902 is shown which may be formed as described above. An oxide layer 904 (such as a silicon oxide layer) may be formed on top of the substrate 902.

[0076] Fig. 9B How the bottom portion of the channel hole 905 can be etched to the silicon substrate 902 before forming subsequent oxide / nitride layers in the device stack. Since the aspect ratio is so low, any etching process can be used to form the bottom portion of the channel hole 905. For example, since the vertical depth of the channel hole 905 is so small, dielectric etching can be used to form the channel hole 905, rather than the bottom punch etching as described above. Although the bottom of the channel hole 905 is only shown in the oxide layer 904 and the substrate 902, in other embodiments, other layers may also be present on top of the oxide layer 904. As described in the alternative process above, the bottom portion of the channel hole 905 can be etched to a depth that exposes the silicon of the substrate 902. For example, the channel hole 905 can be etched at least to the top surface of the substrate 902, or can be etched below the top surface of the substrate 902 so that the bottom portion of the channel hole 905 penetrates into the substrate 902.

[0077] Fig. 9C Depicts how epitaxial silicon 906 may be formed in the bottom portion of the channel hole 905. The epitaxial silicon 906 may be epitaxially grown from the crystal structure of the exposed silicon of the substrate 902. The epitaxial silicon 906 may be grown until the epitaxial silicon 906 is above the top surface of the substrate 902, or may be grown until above the top surface of the oxide layer 904. For clarity, although the epitaxial silicon 906 is shown growing straight up from the side of the channel hole 905, because the epitaxial silicon 906 is no longer constrained by the channel hole 905, actual implementations may begin to expand. For example, the epitaxial silicon 906 may form a "mushroom" shape as it grows beyond the top surface of the oxide layer 904. This horizontal expansion is allowed because there is still considerable separation between adjacent channel holes in the device layout.

[0078] Fig.9D 906. As described above, the bottom nitride layer 908 can be thicker than other nitride layers in the device stack. The bottom nitride layer 908 can be formed on top of the oxide layer 904 and the epitaxial silicon 906 using any of the processes described above. However, because the epitaxial silicon 906 can be grown over the top surface of the oxide layer 904, the bottom nitride layer 908 may not be formed with a flat top surface. Fig.9D As shown, when the bottom nitride layer 908 protrudes above the top of the oxide layer 904, the bottom nitride layer 908 can conform to the shape and contour of the epitaxial silicon 906. Therefore, the top of the bottom nitride layer 908 can have an uneven surface after it is formed.

[0079] Fig.9E It is shown how the bottom nitride layer 908 may be processed to planarize the top surface of the nitride layer 908. For example, after forming the bottom nitride layer 908, a polishing process such as a chemical mechanical polishing process may be used to planarize the top surface of the wafer. This polishing process may remove a portion of the bottom nitride layer 908 until the top surface of the bottom nitride layer 908 is substantially planar. Flattening the bottom nitride layer 908 may provide a flat and stable surface on which the remaining alternating nitride / oxide layers in the device stack may be formed.

[0080] Fig.9F It is shown how alternating nitride / oxide layers 910 may be formed on top of the bottom nitride layer 908. These alternating nitride / oxide layers 910 may be formed using any of the processes described above. Fig.9F A single stack of alternating nitride / oxide layers 910 is shown formed on top of a bottom nitride layer 908. After the channel holes have been etched, additional stacks of layers may be formed on top of this first stack.

[0081] Figure 9G It is shown how a channel hole 912 may be etched in the alternating nitride / oxide layer 910. Instead of etching the channel hole 912 down into the silicon substrate 902, this etching process only needs to etch down to the top of the epitaxial silicon 906. A dielectric etch may be used to etch the channel hole 912. Thus, this process may eliminate the need to transfer the wafer to a conductor etch chamber to perform a bottom punch etch to extend the channel hole 912 down into the silicon substrate 902. By forming the epitaxial silicon 906 earlier in the process before forming the alternating nitride / oxide layer 910, the depth of the channel hole etch may be reduced, thereby simplifying the etching process.

[0082] Figure 9H It is shown how a subsequent stack of alternating nitride / oxide layers 914 may be formed on top of a first stack of alternating nitride / oxide layers 910 . Fig.9I It shows how the alternating nitride / oxide layer 914 in the second stack may then be etched to extend the channel hole 912 down to the alternating nitride / oxide layer 910 in the first stack.

[0083] Figures 9A-9I This alternative process shown can freely replace the above Figure 2A-2G The process shown is to form epitaxial silicon at the bottom of the channel hole.

[0084] Fig.10 A flowchart 1000 is shown of a method for fabricating a 3D NAND memory structure according to some embodiments. This method may be used as described above and Figure 81000 to form an initial epitaxial silicon for growing an epitaxial silicon core for a device. For example, in step 804, the channel hole may be etched through multiple alternating material layers down to the epitaxial silicon formed using the method of flow chart 1000, rather than etching all the way down to the silicon substrate.

[0085] The method may include forming a layer on a silicon substrate (1002). The silicon substrate may be formed of any of the silicon materials described above. The layer may include an initial oxide layer, such as a silicon oxide layer. The method may also include etching a hole extending through the layer to expose the silicon substrate (1004). A pattern may be introduced into the layer corresponding to the location of the channel hole in the 3D NAND memory structure. As described above, the hole may be etched to expose the silicon substrate. For example, the hole may be etched to expose the top surface of the silicon substrate, or the hole may be etched to penetrate below the top surface of the silicon substrate. This etching may be performed using a conductor etching process, a dielectric etching process, or any other type of etching process.

[0086] The method may further include epitaxially growing epitaxial silicon for the channel from the silicon substrate through the hole (1006). The epitaxial silicon may form a silicon plug that fills the hole in the silicon substrate and the layer. In some embodiments, the epitaxial silicon may be grown to a level above the top surface of the semiconductor substrate but below the top surface of the layer. The epitaxial silicon may also be grown above the top surface of the layer so that the top of the epitaxial silicon is higher than the top of the layer.

[0087] The method may additionally include: forming the 3D NAND memory structure above the layer and the substrate so that the channel hole in the 3D NAND memory structure includes an epitaxial silicon core grown from the epitaxial silicon (1008). For example, a bottom nitride layer, such as a silicon nitride layer, may be formed above the layer and the epitaxial silicon. The top of this nitride layer may not be smooth, but may have a surface profile affected by the height difference between the layer and the underlying epitaxial silicon. The nitride layer may then be subjected to a grinding process to flatten the top of the nitride layer to produce a smooth surface for growing subsequent device layers. The method may then include: forming a plurality of alternating material layers (such as alternating nitride and oxide layers) on top of the substrate and the layer. Channel holes may then be etched, the channel holes passing through the plurality of alternating nitride and oxide layers to expose the underlying epitaxial silicon. This epitaxial silicon may then be used to epitaxially grow epitaxial silicon cores through the channel holes.

[0088] It should be understood that Fig.10The specific steps in provide specific methods for manufacturing 3D NAND memory structures according to various embodiments. Other sequences of steps may also be performed according to alternative embodiments. For example, alternative embodiments may perform the steps outlined above in a different order. In addition, Fig.10 The individual steps shown may include multiple sub-steps, which may be performed in various orders suitable for the individual steps. In addition, additional steps may be added or deleted according to specific applications. Many variations, modifications, and substitutions also fall within the scope of the present disclosure.

[0089] As used herein, the term “about” or “approximately” or “substantially” may be interpreted as being within the range expected by those skilled in the art in the art to which the present invention belongs based on the description.

[0090] In the foregoing description, for the purpose of explanation, numerous specific details are set forth to provide a thorough understanding of the embodiments. However, it is apparent that some embodiments may be practiced without some of these specific details. In other cases, known structures and devices are represented in block diagram form.

[0091] The foregoing description provides only exemplary embodiments and is not intended to limit the scope, applicability or configuration of the present disclosure. On the contrary, the foregoing description of various embodiments will provide an enabling disclosure for implementing at least one embodiment. It should be understood that various changes may be made to the function and arrangement of elements without departing from the spirit and scope of some embodiments set forth in the appended claims.

[0092] Specific details are given in the foregoing description to provide a comprehensive understanding of the embodiments. However, it should be understood that the embodiments may be practiced without these specific details. For example, circuits, systems, networks, processes, and other components may have been represented as components in block diagram form so as not to obscure the embodiments with unnecessary detail. In other cases, known circuits, processes, algorithms, structures, and techniques may have been depicted without unnecessary detail so as not to obscure the embodiments.

[0093] In addition, please note that individual embodiments may be described as processes depicted as flow charts, schematic diagrams of processes, schematic diagrams of data flows, structure diagrams, or block diagrams. Although a flow chart may describe the operations as a sequential process, many of the operations may be performed in parallel or simultaneously. In addition, the order of the operations may be rearranged. When the operations of a process are completed, the process may be terminated, but the process may have additional steps not included in the figure. A process may correspond to a method, a function, a procedure, a subroutine, a subroutine, etc. When a process corresponds to a function, the termination of the process corresponds to a function return to the calling function or the main function.

[0094] The term "computer-readable medium" includes, but is not limited to, portable or fixed storage devices, optical storage devices, wireless channels, and various other media capable of storing, containing, or carrying instructions and / or data. A code segment or machine-executable instruction may represent a procedure, function, subroutine, program, routine, subroutine, module, software package, class, or any combination of instructions, data structures, or program descriptions. A code segment may be coupled to another code segment or hardware circuit by passing and / or receiving information, data, independent variables, parameters, or memory contents. Information, independent variables, parameters, data, etc. may be passed, forwarded, or transmitted via any suitable means, including memory sharing, message passing, token passing, network transmission, etc.

[0095] In addition, the embodiments may be implemented by hardware, software, firmware, middleware, microcode, hardware description language, or any combination thereof. When implemented in software, firmware, middleware, or microcode, program code or code segments that perform the necessary tasks may be stored in a machine-readable medium. A processor may perform the necessary tasks.

[0096] In the foregoing description, features are described with reference to specific embodiments thereof, but it should be appreciated that not all embodiments are limited thereto. Various features and aspects of some embodiments may be used individually or in combination. In addition, without departing from the broader spirit and scope of this specification, the embodiments may be used in any number of environments and applications beyond those described herein. Therefore, the description and figures should be considered illustrative rather than restrictive.

[0097] In addition, for the purpose of illustration, the methods are described in a particular order. It should be understood that in alternative embodiments, the methods may be performed in an order different from that described. It should also be understood that the above methods may be performed by hardware components, or may be implemented as a sequence of machine executable instructions, which may be used to cause a machine (such as a general or special processor or a logic circuit programmed with instructions) to perform the methods. These machine executable instructions may be stored on one or more machine readable media, such as a CD-ROM or other type of optical disk, a floppy disk, a ROM, a RAM, an EPROM, an EEPROM, a magnetic or optical card, a flash memory, or other type of machine readable media suitable for storing electronic instructions. Alternatively, the methods may be performed by a combination of hardware and software.

Claims

1. A three-dimensional (3D) NAND memory structure, comprising: layer on a silicon substrate; an oxide layer over the silicon substrate, wherein a hole is etched through the oxide layer to expose the silicon substrate; epitaxial silicon grown from the substrate through the holes in the oxide layer; and A nitride layer covers the oxide layer and the epitaxial silicon.

2. The 3D NAND memory structure of claim 1, wherein the epitaxial silicon extends above a top surface of the oxide layer.

3. The 3D NAND memory structure of claim 1, wherein a top surface of the nitride layer is planarized so that the top surface of the nitride layer is flat without surface variation caused by a difference in height between the oxide layer and the epitaxial silicon.

4. The 3D NAND memory structure of claim 1, wherein the hole extends below a top surface of the silicon substrate such that the epitaxial silicon extends into the silicon substrate.

5. The 3D NAND memory structure of claim 1 , further comprising: A plurality of alternating material layers are arranged in a vertical stack on the nitride layer.

6. The 3D NAND memory structure of claim 5, further comprising: A channel hole extends through the plurality of alternating material layers to the epitaxial silicon.

7. The 3D NAND memory structure of claim 6, further comprising: a channel, the channel being within the channel hole, wherein the channel comprises: a tunnel layer surrounding an interior of the channel hole and contacting the plurality of alternating material layers; and An epitaxial silicon core is within the tunnel layer, the epitaxial silicon core contacts and grows from the epitaxial silicon.

8. The 3D NAND memory structure of claim 1, wherein the silicon substrate comprises single crystal silicon and the epitaxial silicon is grown from the single crystal silicon.

9. The 3D NAND memory structure of claim 1 , further comprising a plurality of alternating material layers and comprising alternating layers of oxide material and metal, the plurality of alternating material layers being arranged in a vertical stack on the nitride layer, wherein the metal forms gate electrodes for individual memory cells in the memory structure.

10. The 3D NAND memory structure of claim 9, further comprising: An epitaxial silicon layer extends beyond the channel hole, wherein the epitaxial silicon layer is between the silicon substrate and the plurality of alternating material layers, and the epitaxial silicon layer connects the epitaxial silicon core to a plurality of other channels in the memory structure.

11. The 3D NAND memory structure of claim 10, further comprising: A support structure extends through the plurality of alternating material layers and the epitaxial silicon layer and into the silicon substrate.

12. A method of manufacturing a three-dimensional (3D) NAND memory structure, the method comprising: forming a layer on a silicon substrate; etching a hole extending through the layer to expose the silicon substrate; epitaxially growing epitaxial silicon for the channel from the silicon substrate through the hole; and The 3D NAND memory structure is formed over the layer and the substrate such that a channel hole in the 3D NAND memory structure includes an epitaxial silicon core grown from the epitaxial silicon.

13. The method of claim 12, wherein the epitaxial silicon is grown above a top surface of the layer. The method of claim 12 , wherein the layer comprises a silicon oxide layer.

15. The method of claim 12, wherein forming the 3D NAND memory structure over the layer and the substrate comprises: A nitride layer is formed over the layer and the epitaxial silicon.

16. The method of claim 15, wherein forming the 3D NAND memory structure over the layer and the substrate further comprises: The nitride layer is polished to remove surface variations caused by differences in height between the layer and the epitaxial silicon.

17. The method of claim 12, wherein forming the 3D NAND memory structure over the layer and the substrate comprises: A plurality of alternating nitride and oxide layers are formed over the layer and the substrate.

18. The method of claim 17, wherein forming the 3D NAND memory structure over the layer and the substrate further comprises: etching a channel hole through the plurality of alternating nitride and oxide layers to expose the epitaxial silicon; and The epitaxial silicon is epitaxially grown upward through the channel hole to form the epitaxial silicon core of the channel hole.

19. The method of claim 12, wherein forming the 3D NAND memory structure over the layer and the substrate comprises: forming a plurality of alternating material layers arranged in a vertical stack on a silicon substrate; etching a channel hole extending through the plurality of alternating material layers to the epitaxial silicon; forming a tunnel layer surrounding the channel hole and contacting the plurality of alternating material layers; and An epitaxial silicon core is epitaxially grown from the epitaxial silicon through the channel hole in the tunnel layer.

20. The method of claim 19, further comprising: etching a slit in the memory structure, the slit extending through the plurality of alternating material layers into the layer; exposing the layer to an etching process configured to selectively etch the layer; A portion of the tunnel layer exposed after removing the layer is removed.

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