High-precision reference current generating circuit and quick-start ultralow-noise LDO (Low Dropout Regulator)

Abstract

The invention relates to the technical field of power management, in particular to a high-precision reference current generating circuit and a quick-start ultra-low noise LDO (Low Dropout Regulator). The high-precision reference current generating circuit comprises an input reference current generating circuit which is configured as a negative feedback loop and generates reference current according to band-gap reference voltage VREF; the high-precision output current generating circuit is configured to be a negative feedback loop and generates two paths of output current according to proportional distribution of the reference current; and the quick start current generation circuit is configured as a comparison control circuit, controls the on-off of a switching tube by comparing voltage values obtained by converting the two paths of output current, and generates quick start current. The high-precision reference current generating circuit has the advantage of being high in output current precision. The quick-start ultralow-noise LDO can work under the low dropout voltage, has the advantages of being low in output voltage noise and high in starting speed, and meanwhile solves the problem that when the input and output dropout voltage is small, the output voltage precision is poor due to low reference current precision.

Description

Technical Field

[0001] The present invention relates to the technical field of power management in integrated circuits, and in particular to a high-precision reference current generating circuit and a fast-start ultra-low noise LDO. Background Art

[0002] Low-dropout linear regulator (LDO) is a widely used type of circuit in the field of power management technology. LDO can provide a stable power supply voltage for subsequent devices. As electronic devices develop towards lower power consumption, higher speed, and higher integration, the operating voltage of digital chips such as FPGA, DSP, CPU, GPU in high-performance electronic devices is getting lower and lower, and the interference of power supply noise on their working performance is gradually increasing. In such application scenarios, LDO is required to provide lower output voltage noise; in addition, RF amplifiers, PLLs, high-precision A / D converters and other noise-sensitive RF and analog devices also require low-noise power supplies. Therefore, ultra-low noise LDO has become an important direction for the development of LDO technology.

[0003] LDO is composed of bandgap reference, error amplifier, power tube and feedback resistor. The output voltage noise of LDO is mainly composed of bandgap reference voltage noise, error amplifier equivalent input voltage noise, feedback resistor thermal noise, etc. Since the LDO feedback coefficient β is not greater than 1, the bandgap reference voltage noise and error amplifier equivalent input voltage noise are amplified by 1 / β times and superimposed on the output voltage. The smaller β is, the greater the output voltage noise will be. In order to reduce the output voltage noise of LDO, ultra-low noise LDO adopts a unit gain negative feedback structure with β=1. While not amplifying the bandgap reference voltage noise and error amplifier equivalent input voltage noise, it eliminates the influence of feedback resistor thermal noise on output voltage noise. The error amplifier equivalent input voltage noise can be reduced by increasing the error amplifier gain, and a lower reference voltage noise can be obtained by forming a low-pass filter with external capacitors and on-chip resistors. However, in the prior art, large on-chip resistors and large off-chip capacitors prolong the reference voltage establishment time, resulting in a long LDO startup time. Summary of the invention

[0004] The purpose of the present invention is to provide a high-precision reference current generating circuit and a fast-start ultra-low noise LDO, which generates a high-precision output reference current through a high-gain current input operational amplifier, and generates an ultra-low noise reference voltage by using an RC parallel filter circuit composed of an external resistor and a capacitor. During the reference voltage establishment process, the fast-start current generating circuit composed of a comparator, a switch tube and a current source provides an additional charging path for the RC parallel filter circuit, thereby realizing fast startup of the ultra-low noise LDO.

[0005] The objective of the present invention is achieved through the following technical solutions:

[0006] In a first aspect of the present invention, the present invention provides a high-precision reference current generating circuit, comprising:

[0007] An input reference current generating circuit is configured as a negative feedback loop to generate a reference current according to a bandgap reference voltage VREF;

[0008] A high-precision output current generating circuit is configured as a negative feedback loop to generate two output currents in proportion to a reference current;

[0009] The fast-start current generating circuit is configured as a comparison control circuit, which controls the on and off of the switch tube by comparing the voltage values ​​obtained by converting the two output currents to generate a fast-start current.

[0010] Furthermore, the input reference current generating circuit includes an amplifier AMP1, an NMOS tube M0 and a resistor R0, the in-phase input terminal of the amplifier AMP1 is connected to an internal bandgap reference voltage VREF, the inverting input terminal is connected to the positive terminal of R0 and the source of M0, the output terminal of the amplifier AMP1 is connected to the gate of the tube M0; the negative terminal of the resistor R0 is grounded; the drain of the tube M0 is connected to a high-precision output current generating circuit and generates a reference current.

[0011] Furthermore, the high-precision output current generating circuit includes resistors R1 and R2, an amplifier AMP2, and PMOS tubes M1 and M2. The in-phase input terminal of the amplifier AMP2 is connected to the negative end of the resistor R1, and is also connected to the drain of the M0 tube in the input reference current generating circuit. The inverting input terminal is connected to the negative end of the resistor R2, and is also connected to the source of the M1 tube and the M2 tube. The output terminal is connected to the gate of the M1 tube and the M2 tube; the positive ends of the resistors R1 and R2 are both connected to the input power supply VIN; the drain of the M1 tube is connected to the fast start-up current generating circuit, and the drain of the M1 tube is used as the external port VFSS to generate an output current; the drain of the M2 tube is connected to the fast start-up current generating circuit, and the drain of the M2 tube is used as the external port VSET to generate an output current.

[0012] Furthermore, the amplifier AMP2 includes a resistor R3, transistors Q1 and Q2, an NMOS tube M4, a capacitor C0, and bias current sources IB1, IB2, and IB3; the negative end of R1 is connected to the emitter of the Q1 tube, the negative end of R2 is connected to the emitter of the Q2 tube, the base of the Q1 tube is connected to the base of the Q2 tube, and is connected to the positive end of the resistor R3 and one end of the capacitor C0, the other end of the capacitor C0 is connected to the collector of the Q2 tube and the gate of the M4 tube, and is connected to the positive end of the bias current source IB3, the negative end of R3 is connected to the source of the M4 tube, and is connected to the positive end of the bias current source IB2, the drain of M4 is connected to the input power supply VIN, the collector of the Q1 tube is connected to the positive end of the bias current source IB1, and an output voltage VO is generated, and the negative ends of the bias current sources IB1, IB2, and IB3 are all connected to the ground.

[0013] Furthermore, a PMOS tube M6 is added between the collector of the Q1 tube and the positive end of the bias current source IB1, a PMOS tube M7 is added between the collector of the Q2 tube and the positive end of the bias current source IB3, and a resistor R4, a PMOS tube M5 and a bias current source IB4 are also added; the source of the M6 ​​tube is connected to the collector of the Q1 tube, the drain of the M6 ​​tube is connected to the positive end of the bias current source IB1, the source of the M7 tube is connected to the collector of the Q2 tube, the drain of the M7 tube is connected to the positive end of the bias current source IB3, the gates of the M6 ​​tube and the M7 tube are short-circuited together and connected to the gate and drain of the M5 tube, and are also connected to the positive end of the bias current source IB4, the negative end of IB is grounded, the source of the M5 tube is connected to the negative end of R4, and the positive end of R4 is connected to the input power supply VIN; the resistor R4, the M5 tube and the bias current source IB4 provide bias voltages for the M6 ​​tube and the M7 tube.

[0014] Further, the external port VFSS is connected to a resistor RF. The external port VSET is connected to a capacitor CS and a resistor RS. Further, the fast start current generating circuit includes a comparator COMP1, a PMOS tube M3 and a current source IS, the in-phase input terminal of the comparator COMP1 is connected to the drain of the M2 tube and the drain of the M3 tube in the high-precision output current generating circuit, the inverting input terminal is connected to the drain of the M1 tube in the high-precision output current generating circuit, and the output terminal is connected to the gate of the M3 tube; the source of the M3 tube is connected to the negative terminal of the current source IS; the positive terminal of IS is connected to the input power supply VIN, and generates a fast start current.

[0015] In a second aspect of the present invention, the present invention provides a fast-start ultra-low noise LDO, which includes the high-precision reference current generating circuit, an error amplifier, a buffer stage, a power tube MP0 and external resistors RF, RS, and an external capacitor CS as described in the first aspect of the present invention.

[0016] Among them, the output port VFSS of the high-precision reference current generating circuit is connected to the positive end of the resistor RF, and the negative end of RF is grounded. The output port VSET is connected to the positive end of the resistor RS and the positive end of the capacitor CS, and is also connected to the inverting input end of the error amplifier, and the negative end of the resistor RS and the negative end of the capacitor CS are grounded; the non-inverting input end of the error amplifier is connected to the drain of the power tube MP0, and also serves as the output port VOUT of the LDO, the output end of the error amplifier is connected to the input end of the buffer stage, the output end of the buffer stage is connected to the gate of the power tube MP0, and the source of the MP0 tube is connected to the input power supply VIN.

[0017] Beneficial effects of the present invention:

[0018] The high-precision reference current generating circuit proposed in the present invention adopts a current amplifier to output the reference current, and has the characteristics of high output current accuracy; the fast-startup ultra-low noise LDO proposed in the present invention can work under low voltage difference, and has the characteristics of low output voltage noise and fast startup speed, and at the same time avoids the problem of poor output voltage accuracy caused by low reference current accuracy when the input-output voltage difference is small. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 It is a schematic diagram of the structure of a high-precision reference current generating circuit according to an embodiment of the present invention;

[0020] Figure 2 is a schematic structural diagram of a high-precision reference current generating circuit according to another embodiment of the present invention;

[0021] Figure 3 It is a schematic diagram of the structure of a high-precision reference current generating circuit according to a preferred embodiment of the present invention;

[0022] Figure 4 It is a schematic diagram of the structure of a current input operational amplifier according to an embodiment of the present invention;

[0023] Figure 5 It is a schematic diagram of the structure of a high-gain current-input operational amplifier according to an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of a fast-start ultra-low noise LDO structure according to an embodiment of the present invention;

[0025] Figure 7 This is a simulation diagram of the application of a high-precision reference current generating circuit according to an embodiment of the present invention;

[0026] Figure 8 4 is a simulation diagram of the ultra-low noise LDO output voltage noise spectrum of an embodiment of the present invention. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] It should be noted that, since the embodiments of the present invention focus on the current or voltage of the signal, the current or voltage input / output of each module / unit / device is used for description herein, and it should be understood by those skilled in the art that, in fact, the input / output of each module / unit / device is a signal. In order to make the technical means and creative features of the present invention easy to understand, the present invention is further described in conjunction with the accompanying drawings.

[0029] A reference current generating circuit is a circuit specially designed to generate a high-precision, low-temperature drift reference current. Its main function is to provide a stable reference current for other circuits or systems to ensure the performance and stability of the entire system. The current reference current generating circuit is generated by a current mirror structure. In order to improve the current matching accuracy, a cascode current mirror structure is usually used. However, when the LDO input-output voltage difference is low, this structure will seriously affect the current matching accuracy due to insufficient cascode tube voltage drop, resulting in poor reference current output accuracy of the LDO within a wide input voltage range. Based on this problem, an embodiment of the present invention provides a high-precision reference current generating circuit, such as Figure 1 As shown, the high-precision reference current generating circuit includes:

[0030] An input reference current generating circuit is configured as a negative feedback loop to generate a reference current according to a bandgap reference voltage VREF;

[0031] A high-precision output current generating circuit is configured as a negative feedback loop to generate two output currents in proportion to a reference current;

[0032] The fast-start current generating circuit is configured as a comparison control circuit, which controls the on and off of the switch tube by comparing the voltage values ​​obtained by converting the two output currents to generate a fast-start current.

[0033] In the embodiment of the present invention, a high-precision output reference current and a fast-start current are generated by the cooperation of an input reference current generating circuit, a high-precision output current generating circuit and a fast-start current generating circuit, thereby improving the accuracy of the reference voltage within a wide input voltage range, reducing the reference voltage establishment time, and reducing the reference voltage noise.

[0034] Figure 2 FIG. 1 is a schematic diagram of a high-precision reference current generating circuit structure according to another embodiment of the present invention; Figure 2As shown, the high-precision reference current generating circuit includes an input reference current generating circuit, a high-precision output current generating circuit, and a fast start current generating circuit. The input reference current generating circuit is composed of an amplifier AMP1, an NMOS tube M0 and a resistor R0, the high-precision output current generating circuit is composed of resistors R1 and R2, an amplifier AMP2, and PMOS tubes M1 and M2, and the fast start current generating circuit is composed of a comparator COMP1, a PMOS tube M3 and a current source IS.

[0035] In some embodiments, the input reference current generating circuit includes an amplifier AMP1, an NMOS tube M0 and a resistor R0, the in-phase input terminal of the amplifier AMP1 is connected to an internal bandgap reference voltage VREF, the inverting input terminal is connected to the positive terminal of R0 and the source of M0, the output terminal of the amplifier AMP1 is connected to the gate of the M0 tube; the negative terminal of the resistor R0 is grounded; the drain of M0 is connected to a high-precision output current generating circuit and generates a reference current.

[0036] It can be understood that the input reference current generating circuit forms a negative feedback loop through the amplifier AMP1, NMOS tube M0 and resistor R0, clamps the voltage of the inverting input terminal of the amplifier AMP1 to VREF, and the current flowing through the M0 tube is the reference current:

[0037]

[0038] In some embodiments, the high-precision output current generating circuit includes resistors R1 and R2, an amplifier AMP2, and PMOS tubes M1 and M2. The in-phase input terminal of the amplifier AMP2 is connected to the negative end of the resistor R1, and is also connected to the drain of the M0 tube in the input reference current generating circuit. The inverting input terminal is connected to the negative end of the resistor R2, and is also connected to the source of the M1 tube and the M2 tube. The output terminal is connected to the gate of the M1 tube and the M2 tube; the positive ends of the resistors R1 and R2 are both connected to the input power supply VIN; the drain of the M1 tube is connected to the fast start-up current generating circuit, and the drain of the M1 tube is used as an external port VFSS to generate an output current; the drain of the M2 tube is connected to the fast start-up current generating circuit, and the drain of the M2 tube is used as an external port VSET to generate an output current.

[0039] In some preferred embodiments, the high-precision output current generating circuit generates a constant reference current through an external resistor and a capacitor. An example of an application of a high-precision reference current generating circuit of the present invention is as follows: Figure 3As shown, the external port VFSS is connected to the resistor RF, and the external port VSET is connected to the resistor RS and the capacitor CS. The negative feedback circuit composed of resistors R1, R2, amplifier AMP2, M1 tube, M2 tube, and external resistors RF and RS distributes the input reference current Iin in proportion to generate two output currents, and converts them into voltages on resistors RF and RS. Assuming that the width-to-length ratio of M1 tube to M2 tube is 1:k, R1=R2, then the voltage at the VFSS terminal is:

[0040]

[0041] VSET terminal voltage:

[0042]

[0043] If the external resistor RF = k*RS, the voltage at the VFSS terminal is equal to the voltage at the VSET terminal.

[0044]

[0045] In some embodiments, the fast start-up current generating circuit includes a comparator COMP1, a PMOS tube M3 and a current source IS, the comparator COMP1 has a non-inverting input terminal connected to the drain of the M2 tube and the drain of the M3 tube in the high-precision output current generating circuit, an inverting input terminal connected to the drain of the M1 tube in the high-precision output current generating circuit, and an output terminal connected to the gate of the M3 tube; the source of the M3 tube is connected to the negative terminal of the current source IS; the positive terminal of the IS is connected to the input power supply VIN, and generates a fast start-up current.

[0046] It should be noted that the fast startup current generating circuit controls the on / off of the switch tube M3 by comparing the VFSS terminal voltage with the VSET terminal voltage through the comparator COMP1. During the VSET establishment process, since the VSET terminal is connected to a large capacitor, the VSET terminal voltage is less than the VFSS terminal voltage, the comparator outputs a low level, the switch tube M3 is turned on, and an additional current IS is injected into the VSET terminal, so that VSET is established quickly. When the VSET terminal voltage is close to the VFSS terminal voltage, the comparator COMP1 outputs a high level, the switch tube M3 is turned off, and the fast startup current IS no longer affects the reference output current. The VSET terminal voltage rises slowly and finally remains at a stable preset value. The input tube width-to-length ratio of the comparator COMP1 is different. The width-to-length ratio of the MOS tube connected to the positive terminal of CMOP1 is greater than the width-to-length ratio of the MOS tube connected to the negative terminal of CMOP1. The introduced comparison offset voltage determines that when the VSET terminal voltage is close to the VFSS terminal voltage, the comparator output voltage flips, and the switch tube M3 changes from on to off. After the fast startup stage of the reference current generating circuit ends, the fast startup current generating circuit no longer affects the output reference current.

[0047] In some embodiments of the present invention, for ease of description, an implementation of a current input operational amplifier composed of resistors R1, R2 and amplifier AMP2 in a high-precision output current generating circuit is as follows: Figure 4 As shown. The power input operational amplifier includes resistors R1, R2, R3, transistors Q1, Q2, NMOS tube M4, capacitor C0, and bias current sources IB1, IB2, IB3. The positive ends of R1 and R2 are short-circuited together and connected to the input power supply VIN, the negative end of R1 is connected to the emitter of Q1 tube, the negative end of R2 is connected to the emitter of Q2 tube, the base of Q1 tube is connected to the base of Q2 tube, and connected to the positive end of resistor R3 and one end of capacitor C0, the other end of capacitor C0 is connected to the collector of Q2 tube and the gate of M4 tube, and connected to the positive end of bias current source IB3, the negative end of R3 is connected to the source of M4 tube, and connected to the positive end of bias current source IB2, the drain of M4 is connected to the input power supply VIN, the collector of Q1 tube is connected to the positive end of bias current source IB1, and an output voltage VO is generated, and the negative ends of bias current sources IB1, IB2 and IB3 are all connected to ground.

[0048] In some embodiments of the present invention, for the sake of convenience of description, an implementation of a high-gain current input operational amplifier composed of resistors R1, R2 and amplifier AMP2 in a high-precision output current generating circuit is as follows: Figure 5 As shown. Figure 4 Compared with the current input operational amplifier of the embodiment, the present embodiment adds a PMOS tube M6 between the collector of the Q1 tube and the positive end of the bias current source IB1, adds a PMOS tube M7 between the collector of the Q2 tube and the positive end of the bias current source IB3, and also adds a resistor R4, a PMOS tube M5 and a bias current source IB4. The source of the M6 ​​tube is connected to the collector of the Q1 tube, the drain of the M6 ​​tube is connected to the positive end of the bias current source IB1, the source of the M7 tube is connected to the collector of the Q2 tube, the drain of the M7 tube is connected to the positive end of the bias current source IB3, the gates of the M6 ​​tube and the M7 tube are short-circuited together and connected to the gate and drain of the M5 tube, and are also connected to the positive end of the bias current source IB4, the negative end of IB is grounded, the source of the M5 tube is connected to the negative end of R4, and the positive end of R4 is connected to the input power supply VIN. The resistor R4, the M5 tube and the bias current source IB4 provide bias voltages for the M6 ​​tube and the M7 tube.

[0049] The present invention specifically implements a fast start ultra-low noise LDO, and its structural block diagram is shown in the attached figure. Figure 6As shown. LDO includes a high-precision reference current generating circuit, an error amplifier, a buffer stage, a power tube MP0 and external resistors RF, RS, and an external capacitor CS. The low-pass filter formed by RS and CS can reduce the reference voltage noise at the inverting end of the error amplifier. The unit gain negative feedback loop formed by the error amplifier, the buffer and the power tube eliminates the noise introduced by the feedback resistor, and at the same time, the reference voltage noise and the equivalent noise at the input end of the error amplifier are not amplified and output at the output end of the LDO, so the structure can achieve ultra-low noise output. In order to reduce noise, the capacitor CS connected to the VSET end will cause the LDO startup time to become longer. The high-precision reference generating circuit of the present invention will additionally inject a current IS to charge the VSET end during the LDO startup phase. The current IVFSS output by the high-precision reference current generating circuit after the LDO is stable: IVSET=1:k. By selecting the resistance value of the external resistor RF to be k times the resistance value of RS, the final VFSS end voltage is equal to the VSET end voltage and equal to the LDO output voltage VOUT. In the LDO startup phase, the voltage at the VFSS terminal immediately rises to the preset LDO output voltage, the voltage at the VSET terminal rises rapidly due to the additional injection of a current IS in the startup phase, and the LDO output voltage VOUT rises with VSET. When the voltage at the VSET terminal approaches the preset output voltage VFSS, the internal comparator COMP1 of the high-precision reference current generation circuit flips and cuts off the current IS charging path, and VSET gradually rises to the final preset voltage. The LDO of the present invention realizes ultra-low noise voltage output, and at the same time, in the startup phase, the ultra-low noise LDO fast startup is realized by increasing the startup current.

[0050] Figure 7 The present invention is a simulation waveform diagram of the comparator output, VFSS terminal voltage, and VSET terminal voltage of a high-precision reference current generating circuit under certain simulation conditions. After the input voltage VIN is powered on, the VFSS terminal voltage is immediately established, the comparator outputs a low level, and the VSET terminal voltage rises rapidly. When the VSET terminal voltage approaches the VFSS terminal voltage, the comparator flips, the fast startup current generating circuit is turned off, and VSET slowly rises to a preset value.

[0051] Figure 8 This is a noise spectrum simulation diagram of the ultra-low noise LDO output voltage under certain simulation conditions. At a frequency of 1kHz, the noise spectrum density drops to 3.89nV / √Hz. By increasing the external output capacitor, the LDO output voltage noise can be further reduced.

[0052] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A high-precision reference current generating circuit, characterized in that: include: An input reference current generating circuit is configured as a negative feedback loop to generate a reference current according to a bandgap reference voltage VREF; A high-precision output current generating circuit is configured as a negative feedback loop to generate two output currents in proportion to a reference current; The fast-start current generating circuit is configured as a comparison control circuit, which controls the on and off of the switch tube by comparing the voltage values ​​obtained by converting the two output currents to generate a fast-start current.

2. A high-precision reference current generating circuit according to claim 1, characterized in that: The input reference current generating circuit comprises an amplifier AMP1, an NMOS tube M0 and a resistor R0, wherein the in-phase input terminal of the amplifier AMP1 is connected to an internal bandgap reference voltage VREF, the inverting input terminal is connected to a positive terminal of R0 and a source of M0, the output terminal of the amplifier AMP1 is connected to a gate of the tube M0; the negative terminal of the resistor R0 is grounded; and the drain of M0 is connected to a high-precision output current generating circuit and generates a reference current.

3. A high-precision reference current generating circuit according to claim 2, characterized in that: The high-precision output current generating circuit comprises resistors R1 and R2, an amplifier AMP2, and PMOS tubes M1 and M2. The in-phase input terminal of the amplifier AMP2 is connected to the negative terminal of the resistor R1, and is also connected to the drain of the M0 tube in the input reference current generating circuit. The inverting input terminal is connected to the negative terminal of the resistor R2, and is also connected to the source of the M1 tube and the M2 tube. The output terminal is connected to the gate of the M1 tube and the M2 tube. The positive terminals of the resistors R1 and R2 are both connected to the input power supply VIN. The drain of the M1 tube is connected to the fast start-up current generating circuit, and the drain of the M1 tube is used as an external port VFSS to generate an output current. The drain of the M2 tube is connected to the fast start-up current generating circuit, and the drain of the M2 tube is used as an external port VSET to generate an output current.

4. A high-precision reference current generating circuit according to claim 3, characterized in that: The amplifier AMP2 includes a resistor R3, transistors Q1 and Q2, an NMOS tube M4, a capacitor C0, and bias current sources IB1, IB2, and IB3; the negative end of R1 is connected to the emitter of the Q1 tube, the negative end of R2 is connected to the emitter of the Q2 tube, the base of the Q1 tube is connected to the base of the Q2 tube, and is connected to the positive end of the resistor R3 and one end of the capacitor C0, the other end of the capacitor C0 is connected to the collector of the Q2 tube and the gate of the M4 tube, and is connected to the positive end of the bias current source IB3, the negative end of R3 is connected to the source of the M4 tube, and is connected to the positive end of the bias current source IB2, the drain of M4 is connected to the input power supply VIN, the collector of the Q1 tube is connected to the positive end of the bias current source IB1, and an output voltage VO is generated, and the negative ends of the bias current sources IB1, IB2, and IB3 are all connected to the ground.

5. A high-precision reference current generating circuit according to claim 4, characterized in that: A PMOS tube M6 is added between the collector of the Q1 tube and the positive end of the bias current source IB1, a PMOS tube M7 is added between the collector of the Q2 tube and the positive end of the bias current source IB3, and a resistor R4, a PMOS tube M5 and a bias current source IB4 are also added; the source of the M6 ​​tube is connected to the collector of the Q1 tube, the drain of the M6 ​​tube is connected to the positive end of the bias current source IB1, the source of the M7 tube is connected to the collector of the Q2 tube, the drain of the M7 tube is connected to the positive end of the bias current source IB3, the gates of the M6 ​​tube and the M7 tube are short-circuited together and connected to the gate and drain of the M5 tube, and are also connected to the positive end of the bias current source IB4, the negative end of IB is grounded, the source of the M5 tube is connected to the negative end of R4, and the positive end of R4 is connected to the input power supply VIN; the resistor R4, the M5 tube and the bias current source IB4 provide bias voltage for the M6 ​​tube and the M7 tube.

6. A high-precision reference current generating circuit according to claim 3, characterized in that: The fast start-up current generating circuit comprises a comparator COMP1, a PMOS tube M3 and a current source IS, wherein the in-phase input terminal of the comparator COMP1 is connected to the drain of the M2 tube and the drain of the M3 tube in the high-precision output current generating circuit, the inverting input terminal is connected to the drain of the M1 tube in the high-precision output current generating circuit, and the output terminal is connected to the gate of the M3 tube; the source of the M3 tube is connected to the negative terminal of the current source IS; the positive terminal of the IS is connected to the input power supply VIN, and generates a fast start-up current.

7. A high-precision reference current generating circuit according to claim 3, characterized in that: The external port VFSS is connected to the resistor RF.

8. The high-precision reference current generating circuit according to claim 3, characterized in that: The external port VSET is connected to the capacitor CS and the resistor RS.

9. A fast start ultra-low noise LDO, characterized in that: The LDO includes a high-precision reference current generating circuit as described in any one of claims 1-6, an error amplifier, a buffer stage, a power tube MP0 and external resistors RF, RS, and an external capacitor CS; wherein, the output port VFSS of the high-precision reference current generating circuit is connected to the positive end of the resistor RF, and the negative end of RF is grounded, the output port VSET is connected to the positive end of the resistor RS and the positive end of the capacitor CS, and is also connected to the inverting input end of the error amplifier, and the negative end of the resistor RS and the negative end of the capacitor CS are grounded; the non-inverting input end of the error amplifier is connected to the drain of the power tube MP0, and also serves as the output port VOUT of the LDO, the output end of the error amplifier is connected to the input end of the buffer stage, the output end of the buffer stage is connected to the gate of the power tube MP0, and the source of the MP0 tube is connected to the input power supply VIN.

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