Hardware thread function management method and device, equipment and medium

Abstract

The invention discloses a hardware thread function management method and device, equipment and a medium, and relates to the technical field of CPU architecture design, the method comprises the following steps: when a program executes a thread call Call instruction, obtaining a target thread entry address corresponding to the instruction; if the address is not recorded in the thread management table, skipping to and executing the thread at the address; if the address is recorded in a target data entry of the thread management table, detecting whether a target thread is in an awakening state or not according to a target awakening flag bit in the target data entry; if yes, a target thread wake-up address in the target data entry is obtained, and a target thread of the address is skipped and executed; otherwise, skipping the instruction and continuing to execute the next instruction of the Call instruction. By introducing the hardware thread record table, parameter configuration is prevented from being carried out again when the thread is called, and by designing a hardware management thread scheduling mechanism, the thread scheduling process is simplified, the system overhead is reduced, and the thread management efficiency is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of CPU architecture design, and in particular to a method, device, equipment and medium for hardware thread function management. Background Art

[0002] In general processor architectures, multithreading is usually managed at the software level, covering a series of operations such as thread creation, scheduling, and deletion.

[0003] The existing method of managing threads through software requires operating hardware registers and calling function libraries to create and manage threads. This method requires writing a lot of code to track detailed information of threads, such as ID, status, and priority, which not only takes up a lot of CPU and memory resources, but also makes the code complicated. Data needs to be saved during thread execution, which further increases the complexity of the code, increases the system overhead in thread management, and reduces the efficiency of thread management. Summary of the invention

[0004] The present invention provides a method, device, equipment and medium for hardware thread function management, so as to solve the problems of complex scheduling process, large system overhead and thread management efficiency in the thread management process.

[0005] According to one aspect of an embodiment of the present invention, a method for hardware thread function management is provided, comprising:

[0006] When the program code executes to the point where the thread calls the Call instruction, the target thread entry address corresponding to the Call instruction is obtained; if the target thread entry address is not recorded in the thread management table, the target thread is started to be executed after jumping to the target thread that matches the target thread entry address; if the target thread entry address is recorded in the target data entry of the thread management table, whether the target thread is in the awakened state is detected according to the target wake-up flag in the target data entry; if so, the target thread wake-up address in the target data entry is obtained, and after jumping to the target thread that matches the target thread wake-up address, the target thread is started to be executed; otherwise, the Call instruction is skipped and the next instruction after the Call instruction is continued to be executed.

[0007] According to another aspect of an embodiment of the present invention, there is also provided a hardware thread function management device, including:

[0008] A target thread entry address acquisition module is used to acquire the target thread entry address corresponding to the Call instruction when the program code is executed to the thread calling the Call instruction; a target thread execution module is used to start executing the target thread after jumping to the target thread matching the target thread entry address if the target thread entry address is not recorded in the thread management table; a wake-up state detection module is used to detect whether the target thread is in the wake-up state according to the target wake-up flag in the target data entry if the target thread entry address is recorded in the target data entry of the thread management table; a wake-up address target thread execution module is used to acquire the target thread wake-up address in the target data entry if the target thread is in the wake-up state, and start executing the target thread after jumping to the target thread matching the target thread wake-up address; a Call instruction skipping module is used to skip the Call instruction if the target thread is not in the wake-up state, and continue to execute the next instruction of the Call instruction.

[0009] According to another aspect of an embodiment of the present invention, an electronic device is provided, the electronic device comprising:

[0010] at least one processor; and

[0011] a memory communicatively connected to the at least one processor; wherein,

[0012] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the hardware thread function management method described in any embodiment of the present invention.

[0013] According to another aspect of an embodiment of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the hardware thread function management method described in any embodiment of the present invention when executed.

[0014] According to another aspect of an embodiment of the present invention, a computer program product is provided, comprising computer instructions, wherein when the computer instructions are executed by a processor, the steps of the method described in any embodiment of the present invention are implemented.

[0015] The technical solution of the embodiment of the present invention is to obtain the target thread entry address corresponding to the Call instruction when the program code executes to the thread calling the Call instruction; if the target thread entry address is not recorded in the thread management table, then after jumping to the target thread matching the target thread entry address, the target thread is started to be executed; if the target thread entry address is recorded in the target data entry of the thread management table, then according to the target wake-up flag in the target data entry, it is detected whether the target thread is in the wake-up state; if so, the target thread wake-up address in the target data entry is obtained, and after jumping to the target thread matching the target thread wake-up address, the target thread is started to be executed; otherwise, the Call instruction is skipped, and the next instruction of the Call instruction is continued to be executed. In the processor design, the thread scheduling is realized by hardware, and the parameters required for thread management are recorded in combination with the hardware thread record table. When the thread is awakened and called in the subsequent process, there is no need to repeat the relevant parameter settings; the hardware management thread scheduling mechanism is designed to simplify the thread scheduling process, reduce the time when the processor is running, thereby saving the system overhead in thread management and improving work efficiency.

[0016] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0018] Figure 1 is a flowchart of a hardware thread function management method provided according to Embodiment 1 of the present invention;

[0019] Figure 2 is a schematic diagram of a thread management instruction applicable to an embodiment of the present invention;

[0020] Figure 3 is a flowchart of an instruction execution applicable to an embodiment of the present invention;

[0021] Figure 4 is a structural diagram of a hardware thread function management device provided according to Embodiment 2 of the present invention;

[0022] Figure 5 It is a structural schematic diagram of an electronic device that implements the hardware thread function management method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0023] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0024] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0025] Embodiment 1

[0026] Figure 1 This is a flowchart of a hardware thread function management method provided in the first embodiment of the present invention. This embodiment is applicable to the case where the thread creation, scheduling and deletion are implemented by hardware through a hardware thread record table and a hardware-managed thread scheduling mechanism. The method can be executed by a hardware thread function management device, which can be implemented in the form of hardware and / or software and can generally be configured in an electronic device. Figure 1 As shown, the method includes:

[0027] S110. When the program code is executed to the point where the thread calls the Call instruction, the target thread entry address corresponding to the Call instruction is obtained.

[0028] In the embodiment of the present invention, the target thread entry address can be specifically understood as: the memory location where the target thread called by the Call instruction starts to execute, that is, the starting address of the target thread function.

[0029] S120, determine whether the target thread entry address is recorded in the thread management table. If not, execute S130; if yes, execute S140.

[0030] In an embodiment of the present invention, the thread management table can be specifically understood as: a data structure used in the operating system to record and manage all threads in the system, which contains all the information required by the operating system to manage threads. The thread management table may contain multiple data entries, each of which corresponds to a separate thread, and each data entry records the information of the target thread, such as a thread identifier, a target wake-up flag, a target thread entry address, and a target thread wake-up address. Among them, the thread identifier can be specifically understood as a unique identifier for each thread, or a thread number generated according to the thread generation order; the target wake-up flag indicates whether the target thread is in a wake-up state, for example, when the target wake-up flag is false, it is in a dormant state, and when the target wake-up flag is true, it is in a wake-up state. When a thread is in a dormant state due to active or passive suspension of execution for some reason, the thread will not occupy CPU resources, but it will still remain in the memory, waiting for a certain condition to be met or until it is awakened by an external event before being rescheduled for execution. When a thread is in the awake state, it means that the thread is ready to execute and is waiting to be assigned to the processor by the scheduler for execution; in multi-threaded programming, the thread may be blocked or suspended for some reasons (such as waiting for resources, waiting for I / O operations to complete, etc.). When these conditions are met, the thread may be awakened and continue to execute. The target thread wake-up address can be specifically understood as the address of the code location where the thread resumes execution after being awakened.

[0031] S130, jump to the target thread matching the target thread entry address, and start executing the target thread.

[0032] Specifically, if the target thread entry address is not recorded in the thread management table, the Call instruction operation is the same as the Call instruction operation of the general CPU, that is, when the Call instruction is executed, the address of the next instruction of the current instruction (return address) is first pushed into the stack. Then the Call instruction will modify the PC (Program Counter) to point to the starting address of the called function. PC is a register in the CPU that stores the address of the instruction currently being executed. When the CPU executes an instruction, the PC register points to a location in the memory, telling the CPU where the next instruction is. The CPU starts to execute the code of the called function or thread until it encounters a return instruction. When the called function is executed, the return instruction pops the previously saved return address from the stack and loads this address into the program counter, so that the CPU will return to the call point and continue to execute the code after the Call instruction. Among them, the return instruction is used to end the execution of the current function or subroutine and return to the location of the calling function. It is the corresponding return instruction of the Call instruction.

[0033] S140, according to the target wake-up flag in the target data entry, detect whether the target thread is in the wake-up state. If not, execute S150; if yes, execute S140.

[0034] If the target thread entry address is recorded in the target data entry of the thread management table, it means that the thread has been created but not executed before this call, which means that the thread was in a dormant state. It is also necessary to detect whether the target thread is in a awake state based on the target wake-up flag in the target data entry in the thread management table, and adopt different thread execution strategies according to the state of the target thread.

[0035] S150: Skip the Call instruction and continue to execute the instruction following the Call instruction.

[0036] Specifically, if the target thread is not in the awakened state, the thread execution will not jump, which is equivalent to a nop instruction (which means continuing to execute the next instruction without making any changes to the processor state, registers, or memory), but instead executes the next instruction following the call instruction.

[0037] S160: Obtain the target thread wake-up address in the target data entry, jump to the target thread matching the target thread wake-up address, and start executing the target thread.

[0038] Specifically, if the target thread is in the awake state, the address of the next instruction of the current instruction (return address) is pushed into the stack. The target thread wake-up address in the target data entry is obtained, and the Call instruction modifies the PC to point to the target thread wake-up address. After jumping to the target thread that matches the target thread wake-up address, the CPU starts to execute the target thread until it encounters a return instruction. When the called thread is executed, the return instruction pops the previously saved return address from the stack and loads this address into the program counter. The CPU returns to the call point and continues to execute the code after the Call instruction.

[0039] The technical solution of the embodiment of the present invention is to obtain the target thread entry address corresponding to the Call instruction when the program code executes to the thread calling the Call instruction; if the target thread entry address is not recorded in the thread management table, then after jumping to the target thread matching the target thread entry address, the target thread is started to be executed; if the target thread entry address is recorded in the target data entry of the thread management table, then according to the target wake-up flag in the target data entry, it is detected whether the target thread is in the wake-up state; if so, the target thread wake-up address in the target data entry is obtained, and after jumping to the target thread matching the target thread wake-up address, the target thread is started to be executed; otherwise, the Call instruction is skipped, and the next instruction of the Call instruction is continued to be executed. In the processor design, the thread scheduling is realized by hardware, and the parameters required for thread management are recorded in combination with the hardware thread record table. When the thread is awakened and called in the subsequent process, there is no need to repeat the relevant parameter settings; the hardware management thread scheduling mechanism is designed to simplify the thread scheduling process, reduce the time when the processor is running, thereby saving the system overhead in thread management and improving work efficiency.

[0040] Optionally, in an embodiment of the present invention, detecting whether the target thread is in the awake state according to the target awakening flag in the target data entry includes:

[0041] If the target wake-up flag in the target data entry is a sleep state flag, it is determined that the target thread is in a sleep state; if the target wake-up flag in the target data entry is a wake-up state flag, it is determined that the target thread is in a wake-up state.

[0042] Specifically, the wake-up state of the target thread is judged according to the target wake-up flag in the target data entry corresponding to the target thread in the thread management table. The target wake-up flag is a state flag used to indicate whether the thread should be considered for execution by the scheduler of the operating system. A simple binary identification system can be used to describe the state of the thread, for example, 0 indicates that the thread is in a dormant state and 1 indicates that the thread is in an awakened state. If the target wake-up flag in the target data entry is 0, it means that the thread is in a dormant state. This means that the thread has been actively or passively suspended until a certain condition is met (for example, waiting for an event to occur or the waiting time to end). If the target wake-up flag in the target data entry is 1, it means that the thread is in an awakened state. This means that the thread is ready to be scheduled for execution and is waiting to obtain a CPU time slice. Judging whether the target thread is awakened by the target wake-up flag can reduce the useless work of the thread between waiting and waking up. The thread will resume execution only when it really needs to be awakened, which can avoid unnecessary context switching and resource competition.

[0043] Furthermore, in an embodiment of the present invention, after starting to execute the target thread, the method further includes:

[0044] If the thread creation Thalt instruction is executed in the target thread, a new thread initialized to a dormant state is created according to the Thalt instruction, and a new data entry corresponding to the new thread is created in the thread management table; the execution of the target thread is terminated, and the execution of the next instruction of the Call instruction is continued.

[0045] In an embodiment of the present invention, the thread creation Thalt instruction is a 32-bit thread creation instruction designed by the present invention. A Thalt instruction is used to create a thread whose initial state is a dormant state and determine the thread wake-up method. The 32-bit instruction in the Thalt instruction can be divided into the following parts in sequence: a 6-bit operation code field OPCode, a 4-bit thread number ThreadNo, a 10-bit thread sleep time Timer, a fixed 11-bit 0 and a 1-bit field representing the return operation. Among them, according to actual business operation requirements, the form and number of bits of the instruction may be different, and the embodiment of the present invention does not specifically limit it. The Timer can be used to set the length of time a thread remains in a dormant state, so that it can be woken up and continued to execute after a specific time.

[0046] Specifically, after the target thread starts to execute, it can be divided into two situations: when the target thread entry address is not recorded in the thread management table, after jumping to the target thread that matches the target thread entry address, the target thread starts to execute; when the target thread entry address is recorded in the target data entry of the thread management table and the target thread is in the awakened state, the target thread wake-up address in the target data entry is obtained, and after jumping to the target thread that matches the target thread wake-up address, the target thread starts to execute. In these two processes of jumping to the target thread and starting execution, if the thread creation Thalt instruction is not executed, the execution continues until the return instruction is encountered, and the CPU returns to the calling point, and continue to execute the code after the Call instruction; if the thread creation Thalt instruction is executed, a new thread that meets the conditions and is initialized to a dormant state is created according to each field in the Thalt instruction, and a new data entry corresponding to the new thread is created in the thread management table, and the information of each field in the Thalt instruction is updated to the corresponding data entry, such as the operation code, thread number, and thread dormancy duration, etc. After the thread creation is completed and the corresponding data entry in the thread management table is updated, the execution of the target thread is terminated, and the same operation as return is performed (it means that although the return instruction is not encountered, the CPU is still executed to return to the call point and continue to execute the code after the Call instruction). This thread creation and calling method can ensure that some initialization work is performed before the thread is created, such as setting shared resources, configuring the environment, or performing some necessary calculations, to reduce resource competition during the initialization process. Once these preparations are completed, the thread is created again to ensure that all necessary initialization has been completed when the thread starts. By letting the thread enter a dormant state after creation, delayed startup is achieved, and the calling thread is awakened only when needed, which improves the reliability of thread management when system resources are limited.

[0047] Optionally, in an embodiment of the present invention, creating a new data entry corresponding to the new thread in the thread management table includes:

[0048] Create a blank data entry in the thread management table; set the thread entry address in the blank data entry to the instruction address called by the Call instruction, set the thread wake-up address in the blank data entry to the subsequent instruction address of the Thalt instruction, and set the wake-up flag in the blank data entry to the sleep state flag to obtain a new data entry.

[0049] Specifically, in an embodiment of the present invention, when a new thread is created, a new entry needs to be registered for it in the thread management table. This process includes creating a blank entry, which contains the thread number to be updated, the thread entry address, the thread wake-up address and the wake-up flag. The thread entry address is set to the target address called by the Call instruction, the thread wake-up address is set to the address after the thread creates the Thalt instruction, and the wake-up flag is set (for example, to 0) to indicate that the thread is in a dormant state. After completing these steps, the thread management table will contain a complete new data entry, which contains all the key information required for thread execution so that the thread scheduler can correctly manage and schedule the thread.

[0050] Further, in an embodiment of the present invention, after creating a new thread initialized to a dormant state according to the Thalt instruction, the process further includes:

[0051] A thread wake-up mode matching the new thread is set according to the Thalt instruction, where the thread wake-up mode includes at least one of a timed wake-up and an interrupt wake-up; wherein, when the new thread meets the wake-up condition matching the thread wake-up mode, the wake-up flag in the new data entry is automatically updated to a wake-up state identifier.

[0052] Specifically, in an embodiment of the present invention, the thread wake-up mode can be timed wake-up or interrupt wake-up. The Thalt instruction includes a 10-bit thread sleep duration Timer field. Therefore, by judging whether the Timer field is greater than 0, the thread wake-up mode matching the new thread is set. When the Timer field is greater than 0, the thread wake-up mode of the new thread is set to timed wake-up, and the specific delay duration is set according to the Timer field; when the Timer field is equal to 0, the thread wake-up mode of the new thread is set to interrupt wake-up. The specific interrupt signal used for interrupt wake-up thread is specified when the chip specification is specified. For example, thread 1 is awakened by external interrupt 1; thread 2 is awakened by I2C interrupt. When the timer exceeds the set time, or receives the specified interrupt signal, the new thread meets the wake-up condition matching the thread wake-up mode, and the wake-up flag in the table is automatically updated to the wake-up state identifier (for example, the wake-up flag is set to 1), indicating that the wake-up can be called for execution.

[0053] Furthermore, in an embodiment of the present invention, after obtaining the target thread wake-up address in the target data entry and jumping to the target thread matching the target thread wake-up address, the method further includes:

[0054] Delete the target data entry in the thread management table in a hardware deletion manner.

[0055] Specifically, after obtaining the target thread wake-up address in the target data entry and jumping to the target thread that matches the target thread wake-up address, the thread record data entry corresponding to this thread number is deleted by directly operating hardware resources, such as directly operating memory or registers. This ensures that the target thread will not be selected for execution again by the scheduler of the operating system when the thread record is deleted, thereby avoiding repeated wake-ups, reducing the risk of system abnormalities or crashes caused by repeated wake-ups, improving system stability and reliability, and at the same time reducing the system's overhead in processing thread wake-ups and scheduling, thereby improving the overall performance of the system.

[0056] In addition, after deleting the target data entry and jumping to execute the target thread, if a thread creation Thalt instruction is encountered during the execution of the instruction, a thread initialized to a dormant state is created according to the Thalt instruction, and an updated data entry is created in the thread management table. The same operation as return is performed, and the CPU returns to the calling point and continues to execute the code after the Call instruction.

[0057] Furthermore, in an embodiment of the present invention, before jumping to execute the target thread, the method further includes:

[0058] The instruction address recorded by the current program counter is stored in the call stack; when it is determined that the last thread instruction in the target thread has been executed, the instruction after the Call instruction is continued to be executed according to the instruction address recorded in the call stack.

[0059] Specifically, the call stack is a stack data structure used to store information when a function or thread is called, such as the return address of the Call instruction. Before jumping to the target thread, the instruction address recorded by the current program counter is stored in the call stack. After the new thread is executed, the control is returned to the calling thread. The return address is popped from the call stack and jumped to the address to execute the next instruction after the Call instruction, ensuring that the function or thread can return to the correct execution point after the call, maintaining the execution context and logical coherence of the program.

[0060] Specific application scenarios

[0061] Figure 2 A schematic diagram of a thread management instruction applicable to an embodiment of the present invention is shown in FIG. 1 , in addition to the general processor hardware, a thread management table is added. Figure 2 As shown, the thread management table includes:

[0062] The four fields are thread number ThreadNo, thread entry address TCallpoint, thread wake-up address Thaltpoint and thread wake-up flag Wake (when Wake is 0, it is not awakened, and when Wake is 1, it is awakened).

[0063] In addition, the thread management instruction mechanism also includes: PC, MTP (Multiple-Time Programmable), IR (Instruction Register), DECODER (decoder) and CORE (Central Processing Unit, CPU). Among them, the thread management table records the thread entry address, thread wake-up address and wake-up flag required for thread management; PC is used to indicate the program execution location; MTP is a memory that can be programmed multiple times, allowing users to rewrite the memory when needed; IR is the instruction currently executed by the CPU; DECODE determines how to execute the instruction IR; CORE is used to execute instructions and store and update the thread management table.

[0064] The thread creation, thread wakeup and thread deletion operations of hardware-level threads are implemented through the thread management instruction mechanism. Among them, the traditional thread management method is to directly jump into execution after the thread is created. This solution is to put the thread to sleep after the thread is created. The thread wakeup method designed in this technical solution includes timed wakeup and interrupt wakeup. The CPU jumps to the position after the thread to execute. That is, jump to the next instruction of the "Call thread name" instruction to execute.

[0065] In this processor design, all CPU instruction sets are encoded in 32-bit instruction set encoding format. The Thalt instruction related to thread creation may include, in order, a 6-bit opcode field Opcode, a 4-bit thread number ThreadNo, a 10-bit thread sleep time Timer, a fixed 11-bit 0, and a 1-bit field representing the return operation. The form and number of bits of the instruction may vary depending on actual business operation requirements.

[0066] The Thalt instruction can be applied to a single-chip microcomputer. For example, a single-chip microcomputer equipped with a 16-bit processor, a 16-bit ALU (Arithmetic Logic Unit), a 16-bit SFR (Special Function Register), and a SRAM (Static Random Access Memory) data width, a 32-bit instruction width, and a built-in 8k*32bit MTP and 512*16bit SRAM. Among them, the ALU is used to perform all arithmetic operations, logical operations, comparison operations, and shift operations; the SFR is used to control specific hardware features or functions of the microcontroller, such as timer control, serial communication control, and interrupt control; SRAM is a volatile memory that can be used as the first or second level cache of the CPU.

[0067] When the CPU encounters the thread management instruction Thalt during operation, the number ThreadNo specified by the Thalt instruction parameter will be used as the thread number, and the starting address corresponding to the current thread, that is, the memory location where the target thread called by the Call instruction starts to execute, will be written into the thread information table corresponding to ThreadNo as the thread entry address, and the current PC value where the Thalt instruction is located will be added by 1 (that is, the thread wake-up address), and written into the Thaltpoint field in the thread information table corresponding to ThreadNo. After the Thalt instruction completes the above operations, the CPU pops the address in the current PC stack as the next PC pointer, that is, the CPU pops the address in the current PC stack (that is, the instruction of the next return address of the Call instruction, the address to which the function should return after execution), jumps to this position and starts execution. Among them, PC refers to ProgramCounter, which is a register in the computer processor that is used to store the address of the next instruction to be executed. When the processor executes an instruction, the PC register will point to a location in the memory, telling the processor where to get the instruction next.

[0068] When it runs to the TCallpoint entry of the thread again and executes the Call instruction, the general CPU will push the current PC+1 (the return address of the instruction after the Call instruction, which is used to perform the return operation after the calling thread is executed, that is, to continue executing the subsequent program of the Call instruction) into the PC stack and jump to the address specified by the Call instruction to continue executing the instruction.

[0069] Figure 3 FIG. 1 is a flowchart of an instruction execution applicable to an embodiment of the present invention. Figure 3As shown in the figure, cpstack is call point stack, which is a stack that stores the return address of the target thread called by the Call instruction. The thread scheduling mechanism process of hardware management can be:

[0070] When the program code executes the Call instruction, the CPU will first determine whether the entry address specified by the Call instruction (the PC address of the target thread called by the Call instruction) is in the thread table. If not, this situation has nothing to do with the Thalt instruction and is the traditional Call instruction execution process. The general CPU will push the current PC+1 (the next instruction of the Call instruction, that is, the return address) into the PC stack and jump to the address specified by the Call instruction to continue executing the instruction. After the execution of the calling thread is completed, the return operation is executed to continue the subsequent program of the Call instruction. If the Thalt instruction is encountered during the execution process, the hardware executes the thread creation operation, and after the creation is completed, the thread enters the dormant state and performs the same operation as return, that is, after the execution of the calling thread is completed, the return operation is executed to continue the subsequent program of the Call instruction.

[0071] If the entry address specified by the Call instruction is in the thread list, it is determined whether the wake-up condition of the thread is met (the timer exceeds the specified time, or receives the specified interrupt signal, then the Wake in the table is set to 1, indicating that it has been awakened and can be called for execution). If the condition is not met (that is, Wake is 0), the thread will not jump to execute, which is equivalent to a NOP instruction (that is, an assembly language instruction used in computer programming, which does not do any operation. When the processor executes the NOP instruction, it will not make any changes to the processor's status, registers or memory), but execute the next instruction of the Call instruction; if the thread meets the awakening condition (that is, Wake is 1), it will jump to the thread management table, the instruction where the PC value specified by the corresponding thread's Thaltpoint is located, and delete the thread record corresponding to this thread number and the thread wake-up flag (that is, thread deletion operation) to avoid repeated wake-up. Since the thread name has been deleted from the thread table at this time, if a return operation is encountered, it is the relationship between the ordinary Call instruction and return, and the program after the Call instruction is executed. On the contrary, if the Thalt instruction is encountered again, the thread name that was just deleted will be put back into the thread table to form a thread, but it will not jump into the thread immediately for execution. Instead, the thread will go into sleep mode. Subsequent operations are the same as return, and the program following the Call instruction will be executed.

[0072] The technical solution proposed in the embodiment of the present invention realizes thread management through the cooperation of the hardware thread record table and the hardware-managed thread scheduling mechanism with the special instruction Thalt. This design can reduce the number of instruction lines. At the same time, when the thread is running, the required parameters will be set in the first processing. When the thread is awakened, there is no need to repeat the relevant parameter settings, which reduces the time when the processor is running and improves work efficiency. In terms of software, by reducing the number of instructions and increasing the readability of the code, the thread creation process is simplified, and the number of instructions and CPU time required to create a thread are reduced. At the same time, the thread wake-up process is simplified, and two methods of timing and interruption are provided for thread wake-up, which reduces the number of instructions and CPU time required in the thread wake-up process, and improves thread management and code utilization.

[0073] Embodiment 2

[0074] Figure 4 This is a schematic diagram of the structure of a hardware thread function management device provided by Embodiment 2 of the present invention. Figure 4 As shown, the device includes: a target thread entry address acquisition module 410, a target thread execution module 420, a wake-up state detection module 430, a wake-up address target thread execution module 440 and a Call instruction skipping module 450.

[0075] The target thread entry address acquisition module 410 is used to acquire the target thread entry address corresponding to the Call instruction when the program code is executed to the thread calling the Call instruction;

[0076] A target thread execution module 420, for starting to execute the target thread after jumping to the target thread matching the target thread entry address if the target thread entry address is not recorded in the thread management table;

[0077] A wake-up state detection module 430 is used to detect whether the target thread is in the wake-up state according to the target wake-up flag in the target data entry if the target thread entry address is recorded in the target data entry of the thread management table;

[0078] The wake-up address target thread execution module 440 is used to obtain the target thread wake-up address in the target data entry if the target thread is in the wake-up state, and jump to the target thread matching the target thread wake-up address to start executing the target thread;

[0079] The Call instruction skipping module 450 is used to skip the Call instruction if the target thread is not in the awakened state, and continue to execute the instruction following the Call instruction.

[0080] The technical solution of the embodiment of the present invention is to obtain the target thread entry address corresponding to the Call instruction when the program code executes to the thread calling the Call instruction; if the target thread entry address is not recorded in the thread management table, then after jumping to the target thread matching the target thread entry address, the target thread is started to be executed; if the target thread entry address is recorded in the target data entry of the thread management table, then according to the target wake-up flag in the target data entry, it is detected whether the target thread is in the wake-up state; if so, the target thread wake-up address in the target data entry is obtained, and after jumping to the target thread matching the target thread wake-up address, the target thread is started to be executed; otherwise, the Call instruction is skipped, and the next instruction of the Call instruction is continued to be executed. In the processor design, the thread scheduling is realized by hardware, and combined with the hardware thread record table, when the thread is awakened in the subsequent process, there is no need to repeat the relevant parameter settings; the hardware management thread scheduling mechanism is designed to simplify the thread wake-up process, reduce the time when the processor is running, thereby saving the system overhead in thread management and improving work efficiency.

[0081] In the embodiment of the present invention, the awakening state detection module 430 is specifically used for:

[0082] If the target wake-up flag in the target data entry is a sleep state flag, it is determined that the target thread is in a sleep state;

[0083] If the target wake-up flag in the target data entry is a wake-up state flag, it is determined that the target thread is in the wake-up state.

[0084] In the embodiment of the present invention, the wake-up address target thread execution module 440 is specifically used to:

[0085] After the target thread starts to execute, if a thread creation Thalt instruction is executed in the target thread, a new thread initialized to a dormant state is created according to the Thalt instruction, and a new data entry corresponding to the new thread is created in the thread management table;

[0086] End the execution of the target thread and continue executing the instruction following the Call instruction.

[0087] Optionally, in the embodiment of the present invention, the wake-up address target thread execution module 440 may include:

[0088] A blank data entry creation unit, used to create a blank data entry in the thread management table;

[0089] A data entry updating unit is used to set the thread entry address in a blank data entry to the instruction address called by the Call instruction, set the thread wake-up address in the blank data entry to the subsequent instruction address of the Thalt instruction, and set the wake-up flag in the blank data entry to the sleep state flag to obtain a new data entry.

[0090] Furthermore, in the embodiment of the present invention, the wake-up address target thread execution module 440 may further include:

[0091] The thread awakening mode setting unit, after creating a new thread initialized to a dormant state according to the Thalt instruction, sets a thread awakening mode matching the new thread according to the Thalt instruction.

[0092] Furthermore, in the embodiment of the present invention, the wake-up address target thread execution module 440 may further include:

[0093] The target data entry deletion unit is used to delete the target data entry in the thread management table by hardware deletion after obtaining the target thread wake-up address in the target data entry and jumping to the target thread matching the target thread wake-up address.

[0094] Furthermore, in the embodiment of the present invention, the wake-up address target thread execution module 440 may further include:

[0095] The instruction address recording unit is used to store the instruction address recorded by the current program counter into the call stack before jumping to the target thread for execution;

[0096] The instruction continuing execution unit is used to continue executing the next instruction after the Call instruction according to the instruction address recorded in the call stack when it is determined that the last thread instruction in the target thread has been executed.

[0097] The hardware thread function management device provided in the embodiment of the present invention can execute the hardware thread function management method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0098] In the technical solution of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0099] Embodiment 3

[0100] Figure 5A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or required herein.

[0101] like Figure 5 As shown, the electronic device 10 includes at least one processor 11, and a memory connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., wherein the memory stores a computer program that can be executed by at least one processor, and the processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 to the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0102] A number of components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0103] The processor 11 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as a hardware thread function management method.

[0104] That is:

[0105] When the program code is executed to the point where the thread calls the Call instruction, the target thread entry address corresponding to the Call instruction is obtained;

[0106] If the target thread entry address is not recorded in the thread management table, the target thread is started to be executed after jumping to the target thread matching the target thread entry address;

[0107] If the target thread entry address is recorded in the target data entry of the thread management table, then detecting whether the target thread is in the awake state according to the target awakening flag bit in the target data entry;

[0108] If yes, then obtain the target thread wake-up address in the target data entry, jump to the target thread that matches the target thread wake-up address, and start executing the target thread;

[0109] Otherwise, the Call instruction is skipped and the execution continues with the instruction following the Call instruction.

[0110] In some embodiments, the hardware thread function management method may be implemented as a computer instruction, which is tangibly contained in a computer-readable storage medium, such as a storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the hardware thread function management method described above may be performed. Alternatively, in other embodiments, the processor 11 may be configured to perform the hardware thread function management method in any other appropriate manner (e.g., by means of firmware).

[0111] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0112] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions / operations specified in the flow chart and / or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0113] In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in combination with an instruction execution system, device or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0114] To provide interaction with a user, the systems and techniques described herein may be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices may also be used to provide interaction with the user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

[0115] The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0116] A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

[0117] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0118] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A method for hardware thread function management, characterized in that: include: When the program code is executed to the point where the thread calls the Call instruction, the target thread entry address corresponding to the Call instruction is obtained; If the target thread entry address is not recorded in the thread management table, the target thread is started to be executed after jumping to the target thread matching the target thread entry address; If the target thread entry address is recorded in the target data entry of the thread management table, then detecting whether the target thread is in the awake state according to the target awakening flag bit in the target data entry; If yes, then obtain the target thread wake-up address in the target data entry, jump to the target thread that matches the target thread wake-up address, and start executing the target thread; Otherwise, the Call instruction is skipped and the execution continues with the instruction following the Call instruction.

2. The method according to claim 1, characterized in that According to the target wake-up flag in the target data entry, detect whether the target thread is in the wake-up state, including: If the target wake-up flag in the target data entry is a sleep state flag, it is determined that the target thread is in a sleep state; If the target wake-up flag in the target data entry is a wake-up state flag, it is determined that the target thread is in the wake-up state.

3. The method according to claim 2, characterized in that After starting to execute the target thread, it also includes: If the thread creation Thalt instruction is executed in the target thread, a new thread initialized to a dormant state is created according to the Thalt instruction, and a new data entry corresponding to the new thread is created in the thread management table; End the execution of the target thread and continue executing the instruction following the Call instruction.

4. The method according to claim 3, characterized in that Create a new data entry corresponding to the new thread in the thread management table, including: Create a blank data entry in the thread management table; The thread entry address in the blank data entry is set to the instruction address called by the Call instruction, the thread wake-up address in the blank data entry is set to the instruction address after the Thalt instruction, and the wake-up flag in the blank data entry is set to the sleep state flag to obtain a new data entry.

5. The method according to claim 4, characterized in that After creating a new thread initialized to a dormant state according to the Thalt instruction, it also includes: Setting a thread wake-up mode that matches the new thread according to the Thalt instruction, where the thread wake-up mode includes at least one of a timed wake-up and an interrupt wake-up; When the new thread meets the wake-up condition that matches the thread wake-up mode, the wake-up flag in the new data entry is automatically updated to the wake-up state identifier.

6. The method according to any one of claims 1 to 5, characterized in that: After obtaining the target thread wake-up address in the target data entry and jumping to the target thread matching the target thread wake-up address, the method further includes: Delete the target data entry in the thread management table in a hardware deletion manner.

7. The method according to any one of claims 1 to 6, characterized in that: Before jumping to the target thread, it also includes: Store the instruction address recorded by the current program counter into the call stack; When it is determined that the last thread instruction in the target thread has been executed, the instruction following the Call instruction is continued to be executed according to the instruction address recorded in the call stack.

8. A hardware thread function management device, characterized in that: include: The target thread entry address acquisition module is used to acquire the target thread entry address corresponding to the Call instruction when the program code is executed to the thread calling the Call instruction; a target thread execution module, for starting to execute the target thread after jumping to the target thread matching the target thread entry address if the target thread entry address is not recorded in the thread management table; A wake-up state detection module is used to detect whether the target thread is in the wake-up state according to the target wake-up flag in the target data entry if the target thread entry address is recorded in the target data entry of the thread management table; A wake-up address target thread execution module is used to obtain the target thread wake-up address in the target data entry if the target thread is in the wake-up state, and jump to the target thread matching the target thread wake-up address to start executing the target thread; The Call instruction skipping module is used to skip the Call instruction if the target thread is not in the awakened state, and continue to execute the next instruction of the Call instruction.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can perform the hardware thread function management method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the hardware thread function management method according to any one of claims 1 to 7 when executed.

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