Gpio interface circuit, configuration method and configuration device thereof

Abstract

The application discloses a GPIO interface circuit and a configuration method and device thereof, and belongs to the technical field of circuits. The GPIO interface circuit comprises a connection pin, a detection module, an output end of the detection module being connected with the connection pin, and the output end of the detection module being used for outputting a level at the connection pin, and a configuration state switching module, the configuration state switching module being connected with the connection pin and the detection module respectively, and being used for switching a configuration state of the GPIO interface circuit in the case that the level at the connection pin is a first level, until the level at the connection pin is switched from the first level to a second level or to a third level, and the first level is a level higher than the second level and lower than the third level.

Description

Technical Field

[0001] This application belongs to the field of circuit technology, specifically relating to a GPIO interface circuit and its configuration method and configuration device. Background Technology

[0002] General-purpose input / output (GPIO) is a type of universal digital input / output port. In embedded systems, GPIO is designed as a flexible pin that can be configured as either an input or an output to meet different application requirements. GPIO interface circuits can be used to connect control devices and controlled devices to enable control and information exchange between them.

[0003] In order to achieve accurate information transmission, the connection pins in the GPIO interface circuit need to output high or low levels accurately. If the level output by the connection pins in the GPIO interface circuit is between low and high, it will be judged as an uncertain state, that is, half high level. If the connection pins remain at half high level, it will affect the reliability of the device in which the GPIO interface circuit is located. Summary of the Invention

[0004] The purpose of this application is to provide a GPIO interface circuit and its configuration method and device, which can solve the problem that if the connection pin is kept at half high level, it will affect the reliability of the device where the GPIO interface circuit is located.

[0005] In a first aspect, embodiments of this application provide a GPIO interface circuit, including: a connection pin; a detection module, the input terminal of which is connected to the connection pin, and the output terminal of which is used to output the level at the connection pin; and a configuration state switching module, which is connected to both the connection pin and the detection module, and is used to switch the configuration state of the GPIO interface circuit when the level at the connection pin is a first level, until the level at the connection pin switches from the first level to a second level or to a third level, wherein the first level is a level higher than the second level and lower than the third level.

[0006] Secondly, embodiments of this application provide a configuration method for a GPIO interface circuit as described in any of the first aspects. The configuration method includes: obtaining the level at the connection pin; when the level at the connection pin is a first level, switching the configuration state of the GPIO interface circuit until the level at the connection pin switches from the first level to a second level or to a third level; wherein the first level is a level higher than the second level and lower than the third level.

[0007] Thirdly, embodiments of this application provide a configuration device for a GPIO interface circuit as described in any of the first aspects. The configuration device includes: an acquisition module for acquiring the level at a connection pin; and a switching module for switching the configuration state of the GPIO interface circuit when the level at the connection pin is a first level, until the level at the connection pin switches from the first level to a second level or to a third level; wherein the first level is a level higher than the second level and lower than the third level.

[0008] Fourthly, embodiments of this application provide an electronic device including a processor and a memory, the memory storing a program or instructions executable on the processor, the program or instructions, when executed by the processor, implementing the steps of the method as described in the second aspect.

[0009] Fifthly, embodiments of this application provide a readable storage medium on which a program or instructions are stored, which, when executed by a processor, implement the steps of the method as described in the second aspect.

[0010] In a sixth aspect, embodiments of this application provide a chip, which includes a processor and a communication interface. The communication interface and the processor are coupled, and the processor is used to run programs or instructions to implement the method as described in the second aspect.

[0011] In a seventh aspect, embodiments of this application provide a computer program product stored in a storage medium, which is executed by at least one processor to implement the method as described in the second aspect.

[0012] This application proposes a GPIO interface circuit, which includes connection pins, a detection module, and a configuration state switching module. In this process, the detection module can directly detect whether the voltage level at the connection pin is a first level, that is, whether the voltage level at the connection pin in the GPIO interface circuit is half-high. If the voltage level at the connection pin is the first level, the configuration state switching module switches the configuration state of the GPIO interface circuit, causing the voltage level at the connection pin to change to a second or third level, thereby eliminating the influence of the half-high voltage and improving the reliability of the device containing the GPIO interface circuit. Attached Figure Description

[0013] Figure 1 This is a schematic diagram illustrating the identification of high and low voltage levels in the relevant technical solutions;

[0014] Figure 2 This is a topology diagram of the first and second modules in the relevant technical solution when a half-high level is present;

[0015] Figure 3This is a topology diagram of the first and second switching transistors in the relevant technical solution when a half-high level is present.

[0016] Figure 4 This is one of the topology diagrams of the GPIO interface circuit provided in some embodiments of this application;

[0017] Figure 5 This is a second schematic diagram of the topology of the GPIO interface circuit provided in some embodiments of this application;

[0018] Figure 6 This is a topology diagram of the GPIO interface circuit in the relevant technical solution;

[0019] Figure 7 This is one of the flowcharts illustrating the configuration method provided in some embodiments of this application;

[0020] Figure 8 This is a second schematic flowchart of a configuration method provided in some embodiments of this application;

[0021] Figure 9 This is a schematic block diagram of a configuration device provided in some embodiments of this application;

[0022] Figure 10 This is a schematic block diagram of the electronic device in the embodiments of this application;

[0023] Figure 11 This is a schematic diagram of the hardware structure of the electronic device in the embodiments of this application.

[0024] Appendix Figure 2 and Figure 3 The mark:

[0025] 202' First module, 204' Second module, 302' First switch transistor, 304' Second switch transistor.

[0026] Appendix Figures 4 to 6 The mark:

[0027] PAD connection pins, R1 first resistor, R2 second resistor, R3 third resistor, R4 fourth resistor, R5 fifth resistor, R6 sixth resistor, R7 seventh resistor, R8 eighth resistor, 402 detection module, 4022 first comparator circuit, 4024 second comparator circuit, 4026 analog-to-digital converter, U AND gate, D1 first comparator, D2 second comparator, 404 configuration state switching module, 4042 output control module, 4044 input control module, 4046 configuration module, 4048 resistor control module, DVDD first power supply. Detailed Implementation

[0028] The embodiments of this application will now be described in detail. Examples of these embodiments are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application. All other embodiments obtained by those skilled in the art based on the embodiments of this application without inventive effort are within the scope of protection of this application.

[0029] The terms "first" and "second" in the specification and claims of this application may explicitly or implicitly include one or more of the features. In the description of this application, unless otherwise stated, "multiple" means two or more. Furthermore, "and / or" in the specification and claims indicates at least one of the connected objects, and the character " / " generally indicates that the preceding and following objects are in an "or" relationship.

[0030] In the description of this application, it should be noted that, unless otherwise expressly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific circumstances.

[0031] like Figure 1 As shown, the second level is also known as the low level, and the third level is also known as the high level. The recognition range of the high level is greater than or equal to 0.7Vset, and the recognition range of the low level is less than or equal to 0.3Vset. Vset is the set voltage value. If the level at the connection pin in the GPIO interface circuit is between 0.3Vset and 0.7Vset, it is an uncertain state, that is, half high level. It may be identified as a high level or a low level, which can easily cause signal misjudgment.

[0032] Specifically, such as Figure 2 As shown, a half-high level appears as the input V of the first module 202' and the second module 204'. IN At that time, the two switching transistors in the first module 202' and the second module 204' will be turned on, and the power supply V will be activated. DD A connection between the ground and the system, resulting in a large leakage current over a long period, can cause V to... OUT The reliability of the terminal is reduced.

[0033] Similarly, such as Figure 3 As shown, a half-high level is present as the input V of the first switch 302' and the second switch 304'. INWhen this happens, the first switch 302' and the second switch 304' will be turned on simultaneously, and the power supply V... DD A connection between the ground and the system, resulting in a large leakage current over a long period, can cause V to... OUT The reliability of the terminal is reduced.

[0034] To reduce the uncertainty of the output level of the connection pins in the GPIO interface circuit, it is necessary to use an oscilloscope for signal inspection. Signal inspection requires reserving test points on the circuit board. The setting of test points will affect the signal quality of the transmitted signal, occupy a large area on the circuit board, affect the flexibility of the circuit board routing, and also affect the configuration efficiency of the GPIO interface circuit.

[0035] The GPIO interface circuit, its configuration method, and its configuration device provided in this application will be described in detail below with reference to the accompanying drawings, through specific embodiments and application scenarios.

[0036] In some embodiments of this application, such as Figure 4 and Figure 5 As shown, a GPIO interface circuit is proposed, including: a connection pin PAD; a detection module 402, the input terminal of which is connected to the connection pin PAD, and the output terminal of which is used to output the level at the connection pin PAD; and a configuration state switching module 404, which is connected to both the connection pin PAD and the detection module 402, and is used to switch the configuration state of the GPIO interface circuit when the level at the connection pin PAD is a first level, until the level at the connection pin PAD switches from the first level to a second level or to a third level, wherein the first level is a level higher than the second level and lower than the third level.

[0037] The PAD pin is used to connect the control device and the controlled device. Through this pin, the control device and the controlled device are connected, thereby realizing the input and output of information.

[0038] The configuration status of the GPIO interface circuit can be understood as the working mode of the GPIO interface circuit.

[0039] This application proposes a GPIO interface circuit, which includes a connection pin PAD, a detection module 402, and a configuration state switching module 404. In this process, the detection module 402 can directly detect whether the voltage level at the connection pin PAD is a first level, that is, whether the voltage level at the connection pin PAD in the GPIO interface circuit is half-high. If the voltage level at the connection pin PAD is the first level, the configuration state switching module 404 switches the configuration state of the GPIO interface circuit, causing the voltage level at the connection pin PAD to change to a second or third level, thereby eliminating the influence of the half-high voltage and improving the reliability of the device containing the GPIO interface circuit.

[0040] Furthermore, since the detection module 402 can directly detect whether the voltage level at the PAD pin is at the first level, there is no need to reserve test points on the GPIO interface circuit board and perform signal inspection using an oscilloscope. This obviously improves the problems associated with reserving test points. In addition, the configuration state switching module 404 enables automatic configuration of the GPIO interface circuit, eliminating the need to configure the GPIO interface circuit based on the oscilloscope signal inspection results, thus improving configuration efficiency.

[0041] In some embodiments of this application, the configuration states of the GPIO interface circuit include a first output state, a second output state, a first input state, a second input state, and a third input state. The configuration state switching module 404 includes: an output control module 4042, the output terminal of which is connected to the connection pin PAD; an input control module 4044, the input terminal of which is connected to the connection pin PAD; a configuration module 4046, which includes a first resistor R1 and a second resistor R2, the first end of which is connected to the first power supply DVDD, the second end of which is connected to the connection pin PAD, the first end of which is connected to the connection pin PAD, and the second end of which is grounded to ground VSS; and a resistor control module 4048, which is connected to the first power supply DVDD, the second end of which is connected to the connection pin PAD, and the third input state of the first input state. A resistor R1 and a second resistor R2 are connected. In the first output state, the output control module 4042 outputs a third level via the connection pin PAD; in the second output state, the output control module 4042 outputs a second level via the connection pin PAD; in the first input state, the input control module 4044 inputs a signal via the connection pin PAD, and the resistor control module 4048 controls the first resistor R1 to be switched on and the second resistor R2 to be switched off; in the second input state, the input control module 4044 inputs a signal via the connection pin PAD, and the resistor control module 4048 controls the first resistor R1 to be switched off and the second resistor R2 to be switched on; in the third input state, the input control module 4044 inputs a signal via the connection pin PAD, and the resistor control module 4048 controls the first resistor R1 and the second resistor R2 to be switched off.

[0042] In this embodiment, the GPIO interface circuit serves as an input or output circuit, possessing input and output modes. The input mode includes a first input state, a second input state, and a third input state, while the output mode includes a first output state and a second output state. In input mode, information can be acquired, while in output mode, the controlled device can be controlled.

[0043] The configuration state switching module 404 includes an output control module 4042, an input control module 4044, a configuration module 4046, and a resistor control module 4048. The output control module 4042 and the input control module 4044 directly control whether the GPIO interface circuit operates in output or input mode, while the resistor control module 4048 controls the switching in and out of the first resistor R1 and the second resistor R2, enabling the GPIO interface circuit to switch between a first input state, a second input state, and a third input state.

[0044] When the output control module 4042 is enabled, the mode for controlling the operation of the GPIO interface circuit is the output mode. After the output control module 4042 is enabled, it is also used to select the configuration state of the GPIO interface circuit as the first output state or the second output state.

[0045] When the input control module 4044 is enabled, the mode for controlling the operation of the GPIO interface circuit is the input mode. After the input control module 4044 is enabled, it is also used to select the configuration state of the GPIO interface circuit as the first input state, the second input state, or the third input state.

[0046] The resistor control module 4048 is used to control one or both of the first resistor R1 and / or the second resistor R2 to switch into the GPIO interface circuit, thereby realizing the switching between the first input state, the second input state and the third input state.

[0047] The output control module 4042 has a first input terminal A. In the first output state or the second output state, when there is a signal input at the first input terminal A, the output control module 4042 outputs a third level or a second level.

[0048] Specifically, in the first output state, if there is a signal input at the first input terminal A, the output control module 4042 outputs the third level through the connection pin PAD.

[0049] Specifically, in the second output state, if there is a signal input at the first input terminal A, the output control module 4042 outputs a second level through the connection pin PAD.

[0050] The input control module 4044 has a first input terminal Y, and the resistor control module 4048 has a first control terminal PE and a second control terminal PS. The first control terminal PE is used to control the input and output of the first resistor R1, and the second control terminal PS is used to control the input and output of the second resistor R2.

[0051] Specifically, in the first input state, the input control module 4044 responds to the signal input at the first input terminal Y by inputting the signal through the connection pin PAD, and the resistor control module 4048 responds to the signals input at the first control terminal PE and the second control terminal PS, controlling the first resistor R1 to be switched in and the second resistor R2 to be switched out. Switching the first resistor R1 in can be understood as connecting the first resistor R1 between the first power supply and the connection pin PAD. Similarly, switching the second resistor R2 out can be understood as removing the second resistor R2 from between the connection pin PAD and ground. In this state, only the first resistor R1 is connected in series in the GPIO interface circuit, while the second resistor R2 is not connected in the GPIO interface circuit. This input state can be understood as an input pull-up state.

[0052] In the second input state, the input control module 4044 responds to the signal input from the first input terminal Y by inputting the signal through the connection pin PAD, and the resistor control module 4048 responds to the signals input from the first control terminal PE and the second control terminal PS, controlling the first resistor R1 to be switched out and the second resistor R2 to be switched in. Switching the first resistor R1 out can be understood as removing the first resistor R1 from between the first power supply and the connection pin PAD. Similarly, switching the second resistor R2 in can be understood as connecting the second resistor R2 between the connection pin PAD and ground. In this state, only the second resistor R2 is connected in series in the GPIO interface circuit, while the first resistor R1 is not connected in the GPIO interface circuit. This input state can be understood as an input pull-down state.

[0053] In the third input state, the input control module 4044 responds to the signal input at the first input terminal Y by inputting the signal at the connection pin PAD, and the resistor control module 4048 responds to the signals input at the first control terminal PE and the second control terminal PS, controlling the first resistor R1 and the second resistor R2 to be disconnected. Disconnecting the first resistor R1 can be understood as removing it from the connection between the first power supply and the connection pin PAD. Similarly, disconnecting the second resistor R2 can be understood as removing it from the connection pin PAD and ground. In this state, neither the first resistor R1 nor the second resistor R2 is connected in the GPIO interface circuit; this input state can be understood as a floating input state.

[0054] In this embodiment, the output control module 4042, the input control module 4044, and the resistor control module 4048 are used to automatically adjust the configuration state of the GPIO interface circuit, select the correct configuration state of the GPIO interface circuit for the actual working condition, and switch the level at the connection pin PAD from the first level to the second level, thereby eliminating the influence of large leakage current.

[0055] In some embodiments of this application, the detection module 402 includes: a first comparison circuit 4022, the input terminal of which is connected to the connection pin PAD; when the level at the connection pin PAD is lower than a third level, the first comparison circuit 4022 outputs a high-level signal; when the level at the connection pin PAD is equal to or higher than the third level, the first comparison circuit 4022 outputs a low-level signal; and a second comparison circuit 4024, the input terminal of which is connected to the connection pin PAD; when the level at the connection pin PAD is lower than the third level, the first comparison circuit 4022 outputs a high-level signal; and when the level at the connection pin PAD is equal to or higher than the third level, the first comparison circuit 4022 outputs a low-level signal. When the level is equal to or lower than the second level, the second comparator circuit 4024 outputs a low-level signal. When the level at the connection pin PAD is higher than the second level, the second comparator circuit 4024 outputs a high-level signal. AND gate U, the first input of AND gate U is connected to the output of the first comparator circuit 4022, and the second input of AND gate U is connected to the output of the second comparator circuit 4024. When both the output of the first comparator circuit 4022 and the output of the second comparator circuit 4024 output high-level signals, the level at the connection pin PAD is the first level.

[0056] In this embodiment, as described above, the detection module 402 is used to detect the level at the connection pin PAD so as to determine whether the level at the connection pin PAD is in an uncertain state based on the level at the connection pin PAD. The uncertain state is determined by comparing the level at the connection pin PAD with the third level and the second level, respectively.

[0057] Based on this, the detection module 402 includes a first comparison circuit 4022 and a second comparison circuit 4024. The first comparison circuit 4022 is used to determine whether the level at the connection pin PAD is lower than the third level, and the second comparison circuit 4024 is used to determine whether the level at the connection pin PAD is higher than the second level. The comparison results of the first comparison circuit 4022 and the second comparison circuit 4024 are respectively input to the two input terminals of the AND gate U, and the AND gate U is used to determine whether the level at the connection pin PAD is the first level.

[0058] During this process, the hardware circuit can be used to directly determine whether the level at the PAD pin is the first level, without the need to run a software program to determine it. Therefore, if the level at the PAD pin is the first level, the above situation can be detected in time, thereby switching the configuration state of the GPIO interface circuit in a timely manner, thus ensuring the reliability of the GPIO interface circuit.

[0059] In some embodiments, the recognition range of the second and third levels can be selected according to actual usage needs.

[0060] In some embodiments, the recognition range of the third level is greater than or equal to 0.7 DVDD, and the recognition range of the second level is less than or equal to 0.3 DVDD. Here, DVDD is the output voltage of the first power supply.

[0061] If the voltage level at pin PAD is 0.9DVDD, then 0.9DVDD is greater than 0.7DVDD. At this time, the first comparator circuit 4022 outputs a low-level signal, the second comparator circuit 4024 outputs a high-level signal, and when the AND gate U is simultaneously input with both low-level and high-level signals, the output terminal B outputs a low-level signal.

[0062] If the voltage level at pin PAD is 0.2DVDD, then 0.2DVDD is less than 0.7DVDD. At this time, the first comparator circuit 4022 outputs a high-level signal, and since 0.2DVDD is less than 0.3DVDD, the second comparator circuit 4024 outputs a low-level signal. When the AND gate U receives both a low-level signal and a high-level signal, its output terminal B outputs a low-level signal.

[0063] If the voltage level at pin PAD is 0.5DVDD, then 0.5DVDD is less than 0.7DVDD. At this time, the first comparator circuit 4022 outputs a high-level signal. Since 0.5DVDD is greater than 0.3DVDD, the second comparator circuit 4024 outputs a high-level signal. When the AND gate U is simultaneously input with a high-level signal, its output terminal B outputs a high-level signal. At this time, the voltage level at pin PAD is considered to be the first voltage level.

[0064] In some embodiments of this application, the first comparator circuit 4022 includes: a third resistor R3, the first end of which is connected to the connection pin PAD; a fourth resistor R4, the first end of which is connected to the second end of the third resistor R3, and the second end of the fourth resistor R4 is grounded; a first comparator D1, the negative input of which is connected to the first end of the fourth resistor R4, and the positive input of which is used to input a voltage signal corresponding to the third level; and / or the second comparator circuit 4024 includes: a fifth resistor R5, the first end of which is connected to the connection pin PAD; a sixth resistor R6, the first end of which is connected to the second end of the fifth resistor R5, and the second end of which is grounded; a second comparator D2, the positive input of which is connected to the first end of the sixth resistor R6, and the negative input of which is used to input a voltage signal corresponding to the second level.

[0065] In this embodiment, a voltage divider circuit composed of the third resistor R3 and the fourth resistor R4 is used to acquire the voltage level at the connection pin PAD in the form of a voltage, and input it to the negative input terminal of the first comparator D1. At the same time, the positive input terminal of the first comparator D1 receives a voltage signal corresponding to the third level. At this time, the first comparator D1 can compare the voltage corresponding to the level at the connection pin PAD with the voltage signal corresponding to the third level. If the voltage corresponding to the level at the connection pin PAD is lower than the voltage signal corresponding to the third level, the first comparator D1 outputs a high-level signal.

[0066] Similarly, using the voltage divider circuit formed by the fifth resistor R5 and the sixth resistor R6, the voltage level at the connection pin PAD is acquired in the form of a voltage and input to the positive input terminal of the second comparator D2. At the same time, the negative input terminal of the second comparator D2 receives a voltage signal corresponding to the second voltage level. At this time, the second comparator D2 can compare the voltage corresponding to the voltage level at the connection pin PAD with the voltage signal corresponding to the second voltage level. If the voltage corresponding to the voltage level at the connection pin PAD is higher than the voltage signal corresponding to the second voltage level, the second comparator D2 outputs a high-level signal.

[0067] In this process, the comparison results between the level at the PAD pin, the second level, and the third level are directly determined by the third resistor R3, the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the first comparator D1, and the second comparator D2, without the need to run software programs to make the judgment, thereby ensuring the reliability of the GPIO interface circuit.

[0068] For example, the voltage signal corresponding to the third level is represented by VREF1, where VREF1 = 0.7DVDD, and the voltage signal corresponding to the second level is represented by VREF2, where VREF2 = 0.3DVDD.

[0069] VREF1 and VREF2 can be generated by the circuit in the control device or by an external power supply, which will not be elaborated here.

[0070] In some embodiments of this application, the detection module 402 includes: an analog-to-digital converter 4026, the input terminal of which is connected to the connection pin PAD, and the output terminal of which is used to output the level at the connection pin PAD.

[0071] In this embodiment, the analog-to-digital converter 4026 includes a detection circuit that can detect analog signals. The analog voltage signal detected by the converter 4026 is converted into a digital signal and stored in a register. The accuracy of the voltage signal detection by the converter 4026 is limited by the number of bits it can detect; typically, the number of bits is 8 bits or more. A higher number of bits results in higher detection accuracy.

[0072] Based on this, when the input terminal of the analog-to-digital converter 4026 is connected to the connection pin PAD, the level at the connection pin PAD can be directly detected and output. Obviously, the level detection at the connection pin PAD can be achieved with fewer components, reducing the cost of the GPIO interface circuit.

[0073] In some embodiments of this application, the analog-to-digital converter 4026 further has a power supply terminal. When the voltage input to the power supply terminal is less than the output voltage of the first power supply, the detection module 402 further includes: a seventh resistor R7, connected in series between the input terminal of the analog-to-digital converter 4026 and the connection pin PAD, with the first end of the seventh resistor R7 connected to the connection pin PAD; and an eighth resistor R8, with the first end of the eighth resistor R8 connected to the second end of the seventh resistor R7, and the second end of the eighth resistor R8 grounded; wherein the voltage division value of the output voltage of the first power supply through the eighth resistor R8 is less than or equal to the voltage input to the power supply terminal.

[0074] In this embodiment, by setting a seventh resistor R7 and an eighth resistor R8, a voltage divider circuit is formed using the seventh resistor R7 and the eighth resistor R8, thereby reducing the voltage input to the analog-to-digital converter 4026 and ensuring the detection accuracy of the level at the connection pin PAD.

[0075] Specifically, when the output voltage of the first power supply is DVDD, the voltage division value of the first power supply output voltage through the eighth resistor R8 is:

[0076] VREF3 = R81 × DVDD / (R71 + R81)

[0077] Where VREF3 is the maximum value of the input voltage at the power supply terminal, R71 is the resistance value of the seventh resistor R7, R81 is the resistance value of the eighth resistor R8, and DVDD is the output voltage of the first power supply.

[0078] Specifically, if Vpad represents the voltage level at pin PAD, and this level is converted into data by an analog-to-digital converter 4026, then the formula for Vpad is:

[0079] Vadc = R81 × Vpad / (R71 + R81)

[0080] Where Vadc is the voltage at the input terminal of the analog-to-digital converter 4026.

[0081] After obtaining a data point, the voltage level at pin PAD can be obtained by data reconstruction, and its expression is as follows:

[0082] Vpad = (R71 + R81)data / R81

[0083] Figure 6 This is a topology diagram of the GPIO interface circuit in the relevant technical solution, such as... Figure 6 As shown, the GPIO interface circuit proposed in this application adds a detection circuit compared to the GPIO interface circuit proposed in related technical solutions, thereby realizing the detection of the level at the connection pin PAD.

[0084] In some embodiments of this application, such as Figure 7 As shown, a configuration method is proposed for a GPIO interface circuit as described above. The configuration method includes:

[0085] Step 702: Obtain the voltage level at the connection pin.

[0086] Step 704: When the level at the connection pin is the first level, switch the configuration state of the GPIO interface circuit until the level at the connection pin switches from the first level to the second level or to the third level.

[0087] The first level is a level that is higher than the second level and lower than the third level.

[0088] In this embodiment, the voltage level at the connection pin can be obtained and compared with a first voltage level. If the voltage level at the connection pin is the first voltage level, the configuration state of the GPIO interface circuit is switched to get rid of the influence of the half-high voltage level, thereby improving the reliability of the device where the GPIO interface circuit is located.

[0089] Since it's possible to directly detect whether the voltage level at the PAD pin is at the first level, there's no need to reserve test points on the GPIO interface circuit board and perform signal testing with an oscilloscope. This obviously improves upon the problems associated with reserving test points. Furthermore, it enables automatic configuration of the GPIO interface circuit, eliminating the need to configure it based on oscilloscope signal testing results, thus improving configuration efficiency.

[0090] In some embodiments of this application, when the level at the connection pin is a first level, the configuration state of the GPIO interface circuit is switched until the level at the connection pin switches from the first level to the second level or to the third level. Specifically, this includes: when the level at the connection pin is the first level, obtaining a first configuration state sequence, which is a sequence determined based on a first output state, a second output state, a first input state, a second input state, and a third input state; switching the configuration state of the GPIO interface circuit based on the first configuration state sequence until the level at the connection pin switches from the first level to the second level or to the third level; wherein, in the first output state, the output control module outputs the third level through the connection pin; in the second output state, the output control module outputs the second level through the connection pin; in the first input state, the input control module inputs a signal through the connection pin and controls the first resistor to be switched in and the second resistor to be switched out through the resistor control module; in the second input state, the input control module inputs a signal through the connection pin and controls the first resistor to be switched out and the second resistor to be switched in through the resistor control module; in the third input state, the input control module inputs a signal through the connection pin and controls the first resistor and the second resistor to be switched out through the resistor control module.

[0091] In this embodiment, the configuration states of the GPIO interface circuit include a first output state, a second output state, a first input state, a second input state, and a third input state. After determining the first output state, the second output state, the first input state, the second input state, and the third input state, a first configuration state sequence can be constructed according to their sequential order. The configuration state of the GPIO interface circuit is then switched according to the first configuration state sequence until the level at the connection pin switches from the first level to the second level. During this process, the configuration state of the GPIO interface circuit can be switched according to the pre-constructed first configuration state sequence, thereby achieving automatic matching of the configuration state of the GPIO interface circuit and improving configuration efficiency.

[0092] Specifically, in the process of switching the configuration state of the GPIO interface circuit according to the first configuration state sequence, the state can be switched one by one to find the correct configuration state.

[0093] In some embodiments of this application, the first configuration state sequence is a first input state, a second input state, a third input state, a first output state, and a second output state.

[0094] In some embodiments of this application, the GPIO interface circuit can be set in the master device or the slave device. The master device can be understood as the control device and the slave device can be understood as the controlled device. The configuration status between the master device and the slave device is shown in Table 1.

[0095] Table 1

[0096]

[0097] In this context, √ indicates a state without leakage, and × indicates a state with leakage.

[0098] In this embodiment, the configuration state of the GPIO interface circuit can be switched based on the configuration states shown in Table 1 until the level at the connection pin switches from the first level to the second level or to the third level.

[0099] In some embodiments of this application, such as Figure 8 As shown, the configuration methods include:

[0100] Step 802: Detect the current signal status.

[0101] The current signal state is also the state of the AND gate's output.

[0102] Step 804: Check if the output of the AND gate is 1. If the result is yes, proceed to step 806. If the result is no, proceed to step 808.

[0103] When the output of the AND gate is in the state of 1, it can be understood that when both inputs of the AND gate are simultaneously input with a high-level signal, the output of the AND gate will output a high-level signal.

[0104] Step 806: Begin iterating through the five configuration states of GPIO in sequence.

[0105] Among them, the five configuration states of GPIO are the first output state, the second output state, the first input state, the second input state, and the third input state in this application.

[0106] Step 808: Confirm that the configuration status is correct.

[0107] The correct configuration state refers to the configuration state of the GPIO interface circuit after the voltage level at the connection pin switches from the first voltage level to the second voltage level.

[0108] The configuration method provided in this application can be executed by a configuration device. This application uses a configuration device executing the configuration method as an example to illustrate the configuration device provided in this application.

[0109] In some embodiments of this application, such as Figure 9 As shown, a configuration device 900 is proposed for a GPIO interface circuit as described above. The configuration device 900 includes: an acquisition module 902 for acquiring the level at the connection pin; and a switching module 904 for switching the configuration state of the GPIO interface circuit when the level at the connection pin is a first level, until the level at the connection pin switches from the first level to a second level or to a third level; wherein the first level is a level higher than the second level and lower than the third level.

[0110] In this embodiment, the voltage level at the connection pin can be obtained and compared with a first voltage level. If the voltage level at the connection pin is the first voltage level, the configuration state of the GPIO interface circuit is switched.

[0111] This eliminates the effects of half-high level, thereby improving the reliability of the device containing the GPIO interface circuit.

[0112] Since it's possible to directly detect whether the voltage level at the PAD pin is at the first level, there's no need to reserve test points on the GPIO interface circuit board and perform signal testing with an oscilloscope. This obviously improves upon the problems associated with reserving test points. Furthermore, it enables automatic configuration of the GPIO interface circuit, eliminating the need to configure it based on oscilloscope signal testing results, thus improving configuration efficiency.

[0113] In some embodiments of this application, the switching module 904 is specifically configured to: when the level at the connection pin is a first level, acquire a first configuration state sequence, the first configuration state sequence being a sequence determined based on a first output state, a second output state, a first input state, a second input state, and a third input state; switch the configuration state of the GPIO interface circuit based on the first configuration state sequence until the level at the connection pin switches from the first level to the second level or to the third level; wherein, in the first output state, the output control module outputs the third level through the connection pin; in the second output state, the output control module outputs the second level through the connection pin; in the first input state, the input control module inputs a signal through the connection pin and controls the first resistor to be switched in and the second resistor to be switched out through the resistor control module; in the second input state, the input control module inputs a signal through the connection pin and controls the first resistor to be switched out and the second resistor to be switched in through the resistor control module; in the third input state, the input control module inputs a signal through the connection pin and controls the first resistor and the second resistor to be switched out through the resistor control module.

[0114] The configuration device in this application embodiment can be an electronic device or a component within an electronic device, such as an integrated circuit or a chip. The electronic device can be a terminal or other devices besides a terminal. For example, the electronic device can be a mobile phone, tablet computer, laptop computer, PDA, in-vehicle electronic device, mobile internet device (MID), augmented reality (AR) / virtual reality (VR) device, robot, wearable device, ultra-mobile personal computer (UMPC), netbook, or personal digital assistant (PDA), etc. It can also be a server, network attached storage (NAS), personal computer (PC), television set (TV), ATM, or self-service machine, etc. This application embodiment does not specifically limit the scope of the device.

[0115] The configuration device in this application embodiment can be a device with an operating system. This operating system can be Android, iOS, or other possible operating systems; this application embodiment does not specifically limit the specific operating system used.

[0116] The configuration device provided in this application embodiment can achieve... Figure 7 The various processes implemented in the configuration method embodiment can achieve the same technical effect, and will not be described again here to avoid repetition.

[0117] like Figure 10 As shown, this application embodiment also provides an electronic device 1000, including a processor 1002 and a memory 1004. The memory 1004 stores a program or instructions that can run on the processor 1002. When the program or instructions are executed by the processor 1002, they implement the various steps of the above configuration method embodiment and can achieve the same technical effect. To avoid repetition, they will not be described again here.

[0118] It should be noted that the electronic devices in the embodiments of this application include the aforementioned mobile electronic devices and non-mobile electronic devices.

[0119] Figure 11 A schematic diagram of the hardware structure of an electronic device to implement an embodiment of this application.

[0120] like Figure 11As shown, the electronic device 1100 includes, but is not limited to, components such as: radio frequency unit 1101, network module 1102, audio output unit 1103, input unit 1104, sensor 1105, display unit 1106, user input unit 1107, interface unit 1108, memory 1109, and processor 1110.

[0121] Those skilled in the art will understand that the electronic device 1100 may also include a power supply (such as a battery) for supplying power to various components. The power supply may be logically connected to the processor 1110 through a power management system, thereby enabling functions such as managing charging, discharging, and power consumption through the power management system. Figure 11 The electronic device structure shown does not constitute a limitation on the electronic device. The electronic device may include more or fewer components than shown, or combine certain components, or have different component arrangements, which will not be elaborated here.

[0122] In some embodiments of this application, the processor 1110 is used to obtain the level at the connection pin; when the level at the connection pin is a first level, the configuration state of the GPIO interface circuit is switched until the level at the connection pin switches from the first level to the second level or to the third level; wherein, the first level is a level higher than the second level and lower than the third level.

[0123] In some embodiments of this application, the processor 1110 is specifically configured to, when the level at the connection pin is a first level, acquire a first configuration state sequence, the first configuration state sequence being a sequence determined based on a first output state, a second output state, a first input state, a second input state, and a third input state; switch the configuration state of the GPIO interface circuit based on the first configuration state sequence until the level at the connection pin switches from the first level to the second level or to the third level; wherein, in the first output state, the output control module outputs the third level through the connection pin; in the second output state, the output control module outputs the second level through the connection pin; in the first input state, the input control module inputs a signal through the connection pin and controls the first resistor to be switched in and the second resistor to be switched out through the resistor control module; in the second input state, the input control module inputs a signal through the connection pin and controls the first resistor to be switched out and the second resistor to be switched in through the resistor control module; in the third input state, the input control module inputs a signal through the connection pin and controls the first resistor and the second resistor to be switched out through the resistor control module.

[0124] In this embodiment, the voltage level at the connection pin can be obtained and compared with a first voltage level. If the voltage level at the connection pin is the first voltage level, the configuration state of the GPIO interface circuit is switched to get rid of the influence of the half-high voltage level, thereby improving the reliability of the device where the GPIO interface circuit is located.

[0125] Since it's possible to directly detect whether the voltage level at the PAD pin is at the first level, there's no need to reserve test points on the GPIO interface circuit board and perform signal testing with an oscilloscope. This obviously improves upon the problems associated with reserving test points. Furthermore, it enables automatic configuration of the GPIO interface circuit, eliminating the need to configure it based on oscilloscope signal testing results, thus improving configuration efficiency.

[0126] It should be understood that, in this embodiment, the input unit 1104 may include a graphics processing unit (GPU) 11041 and a microphone 11042. The GPU 11041 processes image data of still images or videos obtained by an image capture device (such as a camera) in video capture mode or image capture mode. The display unit 1106 may include a display panel 11061, which may be configured in the form of a liquid crystal display, an organic light-emitting diode, or the like. The user input unit 1107 includes at least one of a touch panel 11071 and other input devices 11072. The touch panel 11071 is also called a touch screen. The touch panel 11071 may include a touch detection device and a touch controller. Other input devices 11072 may include, but are not limited to, physical keyboards, function keys (such as volume control buttons, power buttons, etc.), trackballs, mice, and joysticks, which will not be described in detail here.

[0127] The memory 1109 can be used to store software programs and various data. The memory 1109 may primarily include a first storage area for storing programs or instructions and a second storage area for storing data. The first storage area may store the operating system, application programs or instructions required for at least one function (such as sound playback, image playback, etc.). Furthermore, the memory 1109 may include volatile memory or non-volatile memory, or both. The non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory can be random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDRSDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM), and direct memory bus RAM (DRRAM). The memory 1109 in this embodiment includes, but is not limited to, these and any other suitable types of memory.

[0128] Processor 1110 may include one or more processing units; optionally, processor 1110 integrates an application processor and a modem processor, wherein the application processor mainly handles operations involving the operating system, user interface, and applications, and the modem processor mainly handles wireless communication signals, such as a baseband processor. It is understood that the aforementioned modem processor may also not be integrated into processor 1110.

[0129] This application also provides a readable storage medium storing a program or instructions. When the program or instructions are executed by a processor, they implement the various processes of the above configuration method embodiments and achieve the same technical effect. To avoid repetition, they will not be described again here.

[0130] The processor is the processor in the electronic device described in the above embodiments. The readable storage medium includes computer-readable storage media, such as computer read-only memory (ROM), random access memory (RAM), magnetic disk, or optical disk.

[0131] This application also provides a chip, which includes a processor and a communication interface. The communication interface and the processor are coupled. The processor is used to run programs or instructions to implement the various processes of the above configuration method embodiments and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0132] It should be understood that the chip mentioned in the embodiments of this application may also be referred to as a system-on-a-chip, system chip, chip system, or system-on-a-chip, etc.

[0133] This application provides a computer program product that is stored in a storage medium and executed by at least one processor to implement the various processes of the above configuration method embodiments, and can achieve the same technical effect. To avoid repetition, it will not be described again here.

[0134] It should be noted that, in this document, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one" does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element. Furthermore, it should be noted that the scope of the methods and apparatuses in the embodiments of this application is not limited to performing functions in the order shown or discussed, but may also include performing functions substantially simultaneously or in the reverse order, depending on the functions involved. For example, the described methods may be performed in a different order than described, and various steps may be added, omitted, or combined. Additionally, features described with reference to certain examples may be combined in other examples.

[0135] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the embodiments of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a computer software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0136] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims, and all of these forms are within the protection scope of this application.

Claims

1. A GPIO interface circuit, characterized in that, include: Connection pins, which are used to connect the control device and the controlled device; A detection module, wherein the input terminal of the detection module is connected to the connection pin, and the output terminal of the detection module is used to output the level at the connection pin; A configuration state switching module is connected to the connection pin and the detection module respectively. It is used to switch the configuration state of the GPIO interface circuit when the level at the connection pin is a first level, until the level at the connection pin switches from the first level to a second level or to a third level. The first level is a level that is higher than the second level and lower than the third level. The configuration states of the GPIO interface circuit include a first output state, a second output state, a first input state, a second input state, and a third input state. The configuration state switching module includes: An output control module, wherein the output terminal of the output control module is connected to the connecting pin; An input control module, wherein the input terminal of the input control module is connected to the connection pin; The configuration module includes a first resistor and a second resistor. A first end of the first resistor is connected to a first power supply, a second end of the first resistor is connected to the connection pin, a first end of the second resistor is connected to the connection pin, and a second end of the second resistor is grounded. The resistor control module is connected to the first resistor and the second resistor respectively; In the first output state, the output control module outputs the third level through the connecting pin; in the second output state, the output control module outputs the second level through the connecting pin; in the first input state, the input control module inputs a signal through the connecting pin, and the resistor control module controls the first resistor to be switched on and the second resistor to be switched off; in the second input state, the input control module inputs a signal through the connecting pin, and the resistor control module controls the first resistor to be switched off and the second resistor to be switched on; in the third input state, the input control module inputs a signal through the connecting pin, and the resistor control module controls the first resistor and the second resistor to be switched off.

2. The GPIO interface circuit according to claim 1, characterized in that, The detection module includes: A first comparator circuit, wherein the input terminal of the first comparator circuit is connected to the connection pin, outputs a high-level signal when the level at the connection pin is lower than the third level, and outputs a low-level signal when the level at the connection pin is equal to or higher than the third level. The second comparator circuit has its input terminal connected to the connection pin. When the level at the connection pin is lower than or equal to the second level, the second comparator circuit outputs a low-level signal; when the level at the connection pin is higher than the second level, the second comparator circuit outputs a high-level signal. An AND gate, wherein the first input terminal of the AND gate is connected to the output terminal of the first comparator circuit, and the second input terminal of the AND gate is connected to the output terminal of the second comparator circuit; Wherein, when the output terminals of the first comparator circuit and the second comparator circuit simultaneously output the high-level signal, the level at the connection pin is the first level.

3. The GPIO interface circuit according to claim 2, characterized in that, The first comparator circuit includes: The third resistor, the first end of which is connected to the connecting pin; A fourth resistor, wherein the first end of the fourth resistor is connected to the second end of the third resistor, and the second end of the fourth resistor is grounded; A first comparator, the negative input of which is connected to the first terminal of the fourth resistor, and the positive input of which is used to input a voltage signal corresponding to the third level; and / or The second comparator circuit includes: The fifth resistor, the first end of which is connected to the connecting pin; The sixth resistor has its first end connected to the second end of the fifth resistor, and its second end is grounded. The second comparator has its positive input terminal connected to the first terminal of the sixth resistor, and its negative input terminal used to input a voltage signal corresponding to the second level.

4. The GPIO interface circuit according to claim 1, characterized in that, The detection module includes: An analog-to-digital converter (ADC) is provided, wherein the input terminal of the ADC is connected to the connection pin, and the output terminal of the ADC is used to output the voltage level at the connection pin.

5. The GPIO interface circuit according to claim 4, characterized in that, The analog-to-digital converter also has a power supply terminal. When the voltage input to the power supply terminal is less than the output voltage of the first power supply, the detection module further includes: A seventh resistor is connected in series between the input terminal of the analog-to-digital converter and the connection pin, with the first end of the seventh resistor connected to the connection pin; The eighth resistor has its first end connected to the second end of the seventh resistor, and its second end is grounded. Wherein, the output voltage of the first power supply is less than or equal to the voltage input at the power supply terminal when the voltage of the first power supply is divided by the eighth resistor.

6. A configuration method for a GPIO interface circuit as described in any one of claims 1 to 5, characterized in that, The configuration method includes: Get the voltage level at the connection pin; When the voltage level at the connection pin is at the first voltage level, the configuration state of the GPIO interface circuit is switched until the voltage level at the connection pin switches from the first voltage level to the second voltage level or to the third voltage level. Wherein, the first level is a level that is higher than the second level and lower than the third level.

7. The configuration method according to claim 6, characterized in that, When the voltage level at the connection pin is the first voltage level, the configuration state of the GPIO interface circuit is switched until the voltage level at the connection pin switches from the first voltage level to the second voltage level or to the third voltage level, specifically including: When the voltage level at the connection pin is a first voltage level, a first configuration state sequence is obtained. The first configuration state sequence is a sequence determined based on a first output state, a second output state, a first input state, a second input state, and a third input state. The configuration state of the GPIO interface circuit is switched based on the first configuration state sequence until the level at the connection pin switches from the first level to the second level or to the third level. In the first output state, the output control module outputs the third level through the connecting pin; in the second output state, the output control module outputs the second level through the connecting pin; in the first input state, the input control module inputs a signal through the connecting pin, and the resistor control module controls the first resistor to be switched on and the second resistor to be switched off; in the second input state, the input control module inputs a signal through the connecting pin, and the resistor control module controls the first resistor to be switched off and the second resistor to be switched on; in the third input state, the input control module inputs a signal through the connecting pin, and the resistor control module controls the first resistor and the second resistor to be switched off.

8. A configuration device for a GPIO interface circuit as described in any one of claims 1 to 5, characterized in that, The configuration device includes: The acquisition module is used to acquire the voltage level at the connection pin. The switching module is used to switch the configuration state of the GPIO interface circuit when the level at the connection pin is at the first level, until the level at the connection pin switches from the first level to the second level or to the third level. Wherein, the first level is a level that is higher than the second level and lower than the third level.

9. The configuration device according to claim 8, characterized in that, The switching module is specifically used for: When the voltage level at the connection pin is a first voltage level, a first configuration state sequence is obtained. The first configuration state sequence is a sequence determined based on a first output state, a second output state, a first input state, a second input state, and a third input state. The configuration state of the GPIO interface circuit is switched based on the first configuration state sequence until the level at the connection pin switches from the first level to the second level or to the third level. In the first output state, the output control module outputs the third level through the connecting pin; in the second output state, the output control module outputs the second level through the connecting pin; in the first input state, the input control module inputs a signal through the connecting pin, and the resistor control module controls the first resistor to be switched on and the second resistor to be switched off; in the second input state, the input control module inputs a signal through the connecting pin, and the resistor control module controls the first resistor to be switched off and the second resistor to be switched on; in the third input state, the input control module inputs a signal through the connecting pin, and the resistor control module controls the first resistor and the second resistor to be switched off.

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