FPGA BRAM time sequence pulse width control method and circuit

Abstract

The invention provides an FPGA BRAM time sequence pulse width control method and circuit, a tracking circuit is used for tracking the read-write working process of a storage array of an SRAM to obtain the working time length of a global working clock signal in the storage array of the SRAM, a pulse width control circuit module is used for controlling the pulse length of a high level of the global working clock signal after a rising edge, and the pulse width of the global working clock signal after the rising edge is controlled. After the tracking circuit completes the tracking of the working duration of the SRAM storage array, a trigger signal for pulling down a high level is given, and a global clock working signal is pulled down to a low level through the pulse width control circuit module, so that the purpose of automatically controlling the FPGA BRAM time sequence pulse width is achieved.

Description

Technical Field

[0001] The invention belongs to the field of digital integrated circuits, and in particular relates to an FPGA BRAM timing pulse width control method and circuit. Background Art

[0002] Field-Programmable Gate Array (FPGA) is a general-purpose programmable logic device with the characteristics of high flexibility and high parallelism. It usually includes programmable logic blocks (CLB), programmable interconnect resources (CR), input and output blocks (IOB) and other IP resources, such as block RAM (BRAM), digital signal processor (DSP), etc. It provides users with system programmable or reconfigurable capabilities.

[0003] BRAM is the main block storage resource in FPGA. Its internal structure is mainly composed of static random access memory (SRAM). It not only provides a large amount of storage space for FPGA, but also has the advantages of flexible storage mode, high compatibility, and no need for periodic refresh, providing intrinsic support for the high flexibility function of FPGA.

[0004] The conventional design of FPGA BRAM timing pulse width control is carried out after the design of BRAM clock control circuit is completed. The process includes: Step 1, determine the port working mode of BRAM; Step 2: determine the read and write mode of the project and the specific storage location range; Step 3, determine the bit width mode used for storing data, etc.; Step 4, configure the BRAM working timing pulse width according to the establishment and maintenance time requirements of the read and write actions. The timing pulse width configuration in step 4 is based on the different time required to write data to SRAM and read data from SRAM. Under the condition that data reading and writing can be completed, the working timing pulse width of BRAM is calculated and configured. Since the pulse width of the configuration working timing must be calculated before each BRAM is used to store data, it not only increases the error rate of BRAM pulse width setting, but also limits the development efficiency of BRAM. Summary of the invention

[0005] The technical problem to be solved by the present invention is how to automatically generate a pulse width that can meet the requirements of establishing and maintaining the time for BRAM reading and writing work and improve the development efficiency. A FPGA BRAM timing pulse width control method and circuit are proposed.

[0006] In order to solve the above technical problems, the technical solution adopted by the present invention is: A FPGA BRAM timing pulse width control method comprises the following steps: Step 1: The FPGA original clock signal clk passes through the pulse width control circuit module for controlling the clock pulse length at the rising edge to generate a global working clock clkint1 signal at a high level; the original clock signal clk needs to be combined with the BRAM working enable signal and the power-on clear signal por_reset signal at its rising edge under the combination of the combinational logic switch to form a working clock signal clk1 that enables the BRAM to start working. In step 1, the global working clock clkint1 signal at a high level is generated after passing through the pulse width control circuit module for controlling the pulse length of the working clock signal at the rising edge of the working clock signal clk1; Step 2: Use a tracking circuit to simulate and track the working time of the row and column units of the BRAM storage array respectively, and the tracking circuit starts tracking at the rising edge of the global working clock clkint1 signal; Step 3: After completing the simulation tracking of the working time of the row and column units of the BRAM storage array, a trigger signal for the falling edge of the global working clock clkint1 signal at a high level is given; Step 4: The trigger signal of the falling edge pulls down the falling edge of the global working clock clkint1 signal under the action of the pulse width control circuit module to form the pulse width of the global working clock.

[0007] Furthermore, the pulse width control circuit module structure includes a third inverter 3 and a first inverter 1 with a low level retainer, and a second inverter 2 with a high level retainer. The output ends of the first inverter 1 and the second inverter 2 are connected to the third inverter 3. The output end of the third inverter 3 is the global working clock signal clkint1. The working clock signal clk1 is input into the second inverter 2, and the trigger signal of the falling edge is input into the first inverter 1.

[0008] Furthermore, the first inverter 1 with a low level keeper includes a fourth inverter 10 composed of a first NMOS tube 11 and a first PMOS tube 12, a second NMOS tube 13 and a fifth inverter 14, the source terminal of the first NMOS tube 11 is connected to the drain of the second NMOS tube 13, the source of the second NMOS tube 13 is grounded, and the output terminal of the fourth inverter 10 is connected to the fifth inverter 14 and then input to the gate of the second NMOS tube 13, and the output terminal of the fourth inverter 10 is connected to the output terminal of the second inverter 2 and then input to the third inverter 3 to form a global working clock signal clkint1.

[0009] Furthermore, the second inverter 2 with a high level keeper includes a sixth inverter 20 composed of a third NMOS tube 21 and a third PMOS tube 22, a second PMOS tube 23 and a seventh inverter 24, the source terminal of the third PMOS tube 22 is connected to the drain of the second PMOS tube 23, the source of the second PMOS tube 23 is connected to the power supply, and the output terminal of the sixth inverter 20 is connected to the seventh inverter 24 and then input to the gate of the second PMOS tube 23, the output terminal of the sixth inverter 20 is connected to the output terminal of the fourth inverter 10 and then input to the third inverter 3 to form a global working clock signal clkint1.

[0010] Further, the circuit structure of the tracking circuit includes a row decoding circuit, a row tracking analog circuit, and a column tracking analog circuit; The row decoding circuit is used to determine which row of unit cells in the static random access memory SRAM storage array is selected to generate a word line signal WL for operation, and at the same time provide a signal for tracking the operation time of the unit cells in this row; The row tracking simulation circuit uses n pairs of NMOS tubes to simulate the opening time of n unit cells in a row of a word line WL in a static random access memory SRAM storage array. The gates of the n pairs of NMOS tubes are respectively connected to a row tracking start signal. The row tracking start signal is generated by a global working clock signal after the row decoding circuit determines which row of unit cells are working and generates a high level. The source and drain of the n pairs of NMOS tubes are connected to the ground signal. After the n pairs of NMOS tubes are charged, a row tracking completion feedback signal is given. The column tracking simulation circuit uses m NMOS tubes to simulate the read and write working time of a bit line BL in a column of m units in a static random access memory SRAM storage array, and the column tracking start signal is respectively input into the source end of the m NMOS tubes, and the gate and drain of the m NMOS tubes are connected to the ground signal; The column tracking start signal is triggered by the row tracking completion feedback signal to give a column tracking start signal; The column tracking start signal completes tracking after charging of m NMOS tubes is completed, and a trigger signal of a falling edge is given.

[0011] Furthermore, the column tracking completion signal passes through two stages of inverters to provide a falling edge trigger signal Rstb1.

[0012] The present invention also provides an FPGA BRAM timing pulse width control circuit, including a clock circuit module, a pulse width control circuit module, and a tracking circuit module; The clock circuit module is used to form a working clock signal clk1 that enables the BRAM to start working under the combination of the combinational logic switch at the rising edge of the original clock signal, the BRAM working enable signal men, and the power-on clear signal por_reset; The tracking circuit module is used to track the read and write working time of the storage unit of the static random access memory SRAM in the BRAM, and after the tracking is completed, it gives a trigger signal for pulling down the global working clock level to the pulse width control circuit module; The pulse width control circuit module is used to control the pulse length of the working clock signal clk1 at a high level according to the trigger signal to form a global working clock signal; The output end of the clock circuit module is connected to the pulse width control circuit module, the output end of the pulse width control circuit module provides a global working clock signal, the output end of the pulse width control circuit module is also input to the tracking circuit, and the output end of the tracking circuit module is input to the pulse width control circuit module.

[0013] Specifically, the circuit structure of the tracking circuit includes a row decoding circuit, a row tracking analog circuit, and a column tracking analog circuit; The row decoding circuit is used to determine which row of unit cells in the static random access memory SRAM storage array is selected to generate a word line signal WL for operation, and at the same time provide a signal for tracking the operation time of the unit cells in this row; The row tracking simulation circuit uses n pairs of NMOS tubes to simulate the opening time of n unit cells in a row of a word line WL in a static random access memory SRAM storage array. The gates of the n pairs of NMOS tubes are respectively connected to a row tracking start signal. The row tracking start signal is generated by a global working clock signal after the row decoding circuit determines which row of unit cells are working and generates a high level. The source and drain of the n pairs of NMOS tubes are connected to the ground signal. After the n pairs of NMOS tubes are charged, a row tracking completion feedback signal is given. The column tracking simulation circuit uses m NMOS tubes to simulate the read and write working time of a bit line BL in a column of m units in a static random access memory SRAM storage array, and the column tracking start signal is respectively input into the source end of the m NMOS tubes, and the gate and drain of the m NMOS tubes are connected to the ground signal; The column tracking start signal is triggered by the row tracking completion feedback signal to give a column tracking start signal; The column tracking start signal completes tracking after charging of m NMOS tubes is completed, and a trigger signal of a falling edge is given.

[0014] By adopting the above technical solution, the present invention has the following beneficial effects: The present invention provides an FPGA BRAM timing pulse width control method. The method tracks the reading and writing working process of an SRAM storage array by using a tracking circuit to obtain the working time of a global working clock signal in the SRAM storage array. The method controls the global working clock signal to maintain a high level after the rising edge by using a pulse width control circuit module. When the tracking circuit completes the tracking of the working time of the SRAM storage array, a trigger signal for pulling down the high level is given. The pulse width control circuit module pulls down the global clock working signal to a low level, thereby achieving the purpose of automatically controlling the FPGA BRAM timing pulse width. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a flow chart of the system of the present invention; Figure 2 A schematic diagram of a circuit for generating a global clock working signal under the action of a pulse width control circuit; Figure 3 A schematic diagram of a circuit for generating a pull-down level trigger signal after tracking is completed under the action of a tracking circuit; Figure 4 It is a schematic diagram of the SRAM storage array; Figure 5 It is a schematic diagram of the tracking circuit structure; Figure 6 It is a schematic diagram of the structure of a unit cell in the SRAM storage array; Figure 7 is a schematic diagram of the structure of a row tracking circuit; Figure 8 is a schematic diagram of the column tracking circuit structure; Fig. 9 Schematic diagram of the bit timing pulse width control circuit; Fig.10 This is a schematic diagram of the operation of the row tracking start signal and the column tracking start signal. DETAILED DESCRIPTION

[0016] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0017] Figures 1 to 10 An embodiment of an FPGA BRAM timing pulse width control method of the present invention is given, such as Figure 1 As shown, the following steps are included: Step 1: The FPGA original clock signal clk passes through a pulse width control circuit module for controlling the length of the clock pulse at the rising edge, generating a global working clock clkint1 signal at a high level.

[0018] In this embodiment, Figure 2 The combinational logic switch in the original clock signal clk also needs to form a working clock signal clk1 that enables the BRAM to start working under the combination of the combinational logic switch at its rising edge with the BRAM work enable signal menb and the power-on clear signal por_reset. In step 1, at the rising edge of the working clock signal clk1, after passing through a pulse width control circuit module for maintaining the rising edge at a high level, a global working clock signal clkint1 at a high level is generated. When the original clock signal clk is a rising edge, the BRAM work enable signal needs to be a high level 1 and the power-on clear signal por_reset signal needs to be a low level 0 before the BRAM can start working. When the power-on clear signal por_reset signal is a high level 1, the storage array is cleared to give a working clock signal, and the rising edge of the working clock signal clk1 is maintained at a high level to obtain a global working clock signal clkint1 at a high level.

[0019] In this embodiment, Figure 2 As shown, the pulse width control circuit module structure includes a third inverter 3 and a first inverter 1 with a low level keeper, and a second inverter 2 with a high level keeper. The output ends of the first inverter 1 and the second inverter 2 are connected to the third inverter 3. The output end of the third inverter 3 is the global working clock signal clkint1. The working clock signal clk1 is input into the second inverter 2, and the trigger signal of the falling edge is input into the first inverter 1.

[0020] The first inverter 1 with a low level keeper includes a fourth inverter 10 composed of a first NMOS tube 11 and a first PMOS tube 12, a second NMOS tube 13 and a fifth inverter 14, the source terminal of the first NMOS tube 11 is connected to the drain of the second NMOS tube 13, the source of the second NMOS tube 13 is grounded, and the output terminal of the fourth inverter 10 is connected to the fifth inverter 14 and then input to the gate of the second NMOS tube 13, and the output terminal of the fourth inverter 10 is connected to the output terminal of the second inverter 2 and then input to the third inverter 3 to form a global working clock signal clkint1.

[0021] The second inverter 2 with a high level keeper includes a sixth inverter 20 composed of a third NMOS tube 21 and a third PMOS tube 22, a second PMOS tube 23 and a seventh inverter 24, the source terminal of the third PMOS tube 22 is connected to the drain of the second PMOS tube 23, the source of the second PMOS tube 23 is connected to the power supply, and the output terminal of the sixth inverter 20 is connected to the seventh inverter 24 and then input to the gate of the second PMOS tube 23, the output terminal of the sixth inverter 20 is connected to the output terminal of the fourth inverter 10 and then input to the third inverter 3 to form a global working clock signal clkint1.

[0022] By using the pulse width control circuit module, the length of the high level of the global working clock signal clkint1 at a high level can be controlled. The specific working principle is as follows: when clk1 is at a high level, it is converted to a low level through the sixth inverter 20. Figure 2 As can be seen from the figure, at this time, clkintb1 is at a low level, so the output terminal signal clkintb1 of the sixth inverter 20 is at a low level and changes to a high level after passing through the seventh inverter 24, and the second PMOS tube 23 is turned off. In the first inverter 1 with a low level maintainer, the low level signal clkintb1 is input to the fifth inverter 14 and changes to a high level, and the second NMOS tube 13 is turned on. Since the source of the second NMOS tube 13 is grounded, the output terminal signal clkintb1 of the sixth inverter 20 is always maintained at a low level, and the low level signal clkintb1 is the global clock working signal clkint1 maintained at a high level after passing through the inverter.

[0023] Step 2: Use a tracking circuit to simulate and track the working time of the row and column units of the BRAM storage array respectively, and the tracking circuit starts tracking at the rising edge of the global working clock clkint1 signal.

[0024] In this embodiment, Figure 5 As shown, the circuit structure of the tracking circuit includes a row decoding circuit, a row tracking analog circuit, and a column tracking analog circuit; it is also necessary to pre-count the number of rows m and the number of columns n of the static random access memory SRAM storage array in the BRAM, such as Figure 4 As shown, the number of NMOS tubes used in the tracking circuit can be determined according to the number of rows m and the number of columns n. Figure 5In the figure, the clock control circuit module is a circuit module that generates the rising edge of the global working clock and controls its falling edge, including the clock circuit module and the pulse width control circuit module in the FPGA BRAM timing pulse width control circuit described later. When the rising edge of the global working clock clkint1 arrives, it passes through the row decoding circuit and obtains which row of cell cells in the static random access memory SRAM storage array in the BRAM needs to be selected to work. On the one hand, the word line WL is given to open the cells in the selected row in the SRAM. On the other hand, the row decoding circuit simultaneously gives a signal TKWL1 to start the row tracking analog circuit to simulate and track the working duration of the word line WL. Therefore, the row tracking analog circuit is also called the WL tracking circuit. Fig.10 As shown, the row decoding circuit adopts the commonly used row decoding circuit, and generates the word line WL signal of the m row by the x-bit row address encoding, where the relationship between x and m is When the row decoding circuit encodes the x-bit row address to generate the word line WL signal of the m-row, the row tracking start signal TKWL1 for row tracking is triggered, so that the row tracking simulation starts when the word line WL opens a row of cells in the SRAM storage array.

[0025] like Figure 6 The schematic diagram of the structure of a unit cell in the SRAM storage array shown in the figure, when the word line WL is high, a pair of NMOS tubes PGL0 and PGR0 in a unit cell are turned on. In order to simulate the time when the word line WL turns on all NMOS tubes in a row, there are n unit cells in a row according to the previous statistics, so the row tracking simulation circuit is as follows Figure 7 As shown, n pairs of NMOS tubes are used to simulate the opening time of n unit cells on a word line WL. The gates of the n pairs of NMOS tubes are respectively connected to the line tracking start signal TKWL1, and the sources and drains of the n pairs of NMOS tubes are connected to the ground signal Tielow. When the line tracking start signal is at a high level, the n pairs, i.e., 2n NMOS tubes, start charging. The completion of charging means that the simulation of the opening time of each unit cell is completed. Figure 7 The source and drain grounding of the NMOS tube in the bank tracking simulation circuit is a wiring method for simulating the cell in the SRAM storage array. This embodiment uses the capacitance between the source and the gate to simulate the parasitic capacitance at the BL bit line in the unit cell, which has no functional effect but only charging and discharging effect.

[0026] In this embodiment, after the row tracking is completed, a row tracking completion feedback signal TKWLFB1 is given, such as Figure 5 As shown, the feedback signal TKWLFB1 completed by row tracking is used as the trigger signal of the column tracking start signal TKBL1, as shown in FIG. Fig.10As shown, the feedback signal TKWLFB1 of the row tracking completion is passed through a two-stage inverter to provide a trigger signal of the column tracking start signal TKBL1. The two-stage inverter is used to strengthen the driving force.

[0027] In this embodiment, the column tracking start signal TKBL1 starts analog tracking of the bit line BL in the SRAM memory array, so the column tracking circuit is also called a BL tracking circuit. Figure 6 In the example, each bit line BL is input and output from the source terminal of the NMOS tube PGL0, so the column tracking analog circuit is as follows Figure 8 As shown, m NMOS tubes are used to simulate the read and write working time of the PGL0 NMOS tube of m cells in a column and m rows in a SRAM storage array. Figure 6 In the figure, BL and BLN carry a pair of opposite data, which come in at the same time and are consistent in time, so there is no need to simulate BLN to PGR0. When the SRAM is working, after the row decoding circuit selects to open all the cells in the word line WL of a certain row, the column decoding circuit simultaneously opens the corresponding bit line BL according to the number of bits of data to be written. Therefore, the read and write time of multiple columns is consistent with that of one column, so it is sufficient to use m NMOS tubes in a column for simulation. The column tracking start signal TKBL1 is input to the source of the m NMOS tubes, and the gate and drain are connected to the ground signal Tielow. The reason for this design is that in this embodiment, the m NMOS tubes only use the capacitance between the source and the gate to simulate the parasitic capacitance at the BL bit line in the cell, which has no functional effect, only charging and discharging. The gate is connected to the ground signal Tielow to make the NMOS tube in a non-conducting state. Secondly, from Figure 6It can be seen from the unit cell shown that the values ​​of the two points Q and QB in the cell must be one 0 and one 1, so the drain of one of the PGL0 NMOS tube and the PGR0 NMOS tube is always connected to 0. Since the cell is symmetrical, the PGL0 NMOS tube and the PGR0 NMOS tube are operated at the same time, so the simulation of the cell working process time only needs to simulate the NMOS tube on one side, so in the column tracking circuit, the drain of the NMOS tube is also connected to the ground signal tielow. In the SRAM storage array, the BL bit line is connected to the source of the NMOS tube, so in this embodiment, the column tracking start signal TKBL1 is connected to the source of m NMOS tubes. In addition, when the BRAM is working, only one row in the SRAM storage array will be opened at a time, that is, only one of the m PGL0 NMOS tubes on the BL bit line will be opened, and the gates of the other m-1 PGL0 NMOS are all closed at low voltage. In this embodiment, since the number of rows m of cells in the SRAM is a large value of hundreds during design, and when hundreds of NMOS tubes are used in the same way, the time required for charging the source and gate capacitors when the gate of one NMOS tube is turned on and the time required for charging the source and gate capacitors when the gate of one NMOS tube is not turned on are very similar, m NMOS tube gates are connected to tielow to simulate m rows of cells.

[0028] The column tracking start signal completes the tracking after the charging of m NMOS tubes is completed. After the column simulation tracking is completed, a trigger signal Rstb1 is given to pull down the high-level global clock working signal clkint1. When the trigger signal Rstb1 is low, the global clock working signal clkint1 is pulled down to a low level to complete the control of the pulse width.

[0029] from Figure 5 It can also be seen that BRAM is completely symmetrical. Before using BRAM, it is necessary to configure whether to use a single port or a dual port. In the case of a single port, use the tracking circuit on the side corresponding to the port for tracking, using WL, BL and clkint1, or WR, BR and clkint2. If dual ports are configured, then the tracking circuits on both sides need to be used to track the ports on each side respectively.

[0030] Step 3: After completing the simulation tracking of the working time of the row and column units of the BRAM storage array, a trigger signal Rstb1 is provided to trigger the falling edge of the global working clock clkint1 signal at a high level. Figure 3 and Figure 8As shown, the trigger signal Rstb1 is given after the column tracking circuit completes tracking. At the same time, the column tracking completion signal passes through a two-stage inverter to give a falling edge trigger signal Rstb1. The two-stage inverter is used to enhance the driving force.

[0031] Step 4: The trigger signal of the falling edge pulls down the falling edge of the global working clock clkint1 signal under the action of the pulse width control circuit module to form the pulse width of the global working clock.

[0032] In this embodiment, from Figure 2 It can be seen that when the trigger signal Rstb1 of the falling edge arrives, the trigger signal Rstb1 is at a low level, then the output end of the fourth inverter 10 is clkintb1 high level, the second NMOS tube 13 is turned off, the second PMOS tube 23 is turned on, and the source of the second PMOS tube 23 is connected to the power supply, so that clkintb1 is maintained at a high level, and after the third inverter 3, the global working clock is turned from a high level to a low level falling edge, thereby forming the pulse width of the global working clock. When the rising edge of the next pulse of the original clock clk arrives to start the second reading and writing, the global working clock starts the next pulse duration.

[0033] This embodiment tracks the read and write working process of the SRAM storage array by using a tracking circuit to obtain the working time of the global working clock signal in the SRAM storage array, and uses a pulse width control circuit module to control the length of the global working clock signal at a high level. When the tracking circuit completes the tracking of the working time of the SRAM storage array, a trigger signal for pulling down the high level is given, and the global clock working signal is pulled down to a low level through the pulse width control circuit module, thereby achieving the purpose of automatically controlling the timing pulse width of the FPGABRAM.

[0034] The present invention also provides an FPGA BRAM timing pulse width control circuit, such as Fig. 9 As shown, it includes a clock circuit module, a pulse width control circuit module, and a tracking circuit; The clock circuit module is used to form a working clock signal clk1 that enables the BRAM to start working under the combination of the combinational logic switch at the rising edge of the original clock signal, the BRAM working enable signal, and the power-on clear signal por_reset signal; The pulse width control circuit module is used to maintain the working clock signal clk1 at a high level or a low level. When the working clock signal clk1 is at a high level, a global working clock signal is formed under the action of the pulse width control circuit module. The tracking circuit is used to track the read and write working time of the storage unit of the static random access memory SRAM in the BRAM, and after the tracking is completed, it gives a trigger signal for pulling down the global working clock level to the pulse width control circuit module; The output end of the clock circuit module is connected to the pulse width control circuit module, the output end of the pulse width control circuit module provides a global working clock signal, the output end of the pulse width control circuit module is also input to the tracking circuit, and the output end of the tracking circuit is input to the pulse width control circuit module.

[0035] In this embodiment, the circuit structure of the tracking circuit includes a row decoding circuit, a row tracking analog circuit, and a column tracking analog circuit; The row decoding circuit is used to determine which row of unit cells in the static random access memory SRAM storage array is selected to generate a word line signal WL for operation, and to track the operation time of the unit cells in this row; The row tracking simulation circuit uses n pairs of NMOS tubes to simulate the opening time of n unit cells in a row of a word line WL in a static random access memory SRAM storage array. The gates of the n pairs of NMOS tubes are respectively connected to a row tracking start signal. The row tracking start signal is generated by a global working clock signal after the row decoding circuit determines which row of unit cells are working and generates a high level. The source and drain of the n pairs of NMOS tubes are connected to the ground signal. After the n pairs of NMOS tubes are charged, a row tracking completion feedback signal is given. The column tracking simulation circuit uses m NMOS tubes to simulate the read and write working time of a bit line BL in a column of m units in a static random access memory SRAM storage array, and the column tracking start signal is respectively input into the source end of the m NMOS tubes, and the gate and drain of the m NMOS tubes are connected to the ground signal; The column tracking start signal is triggered by the row tracking completion feedback signal to give a column tracking start signal; The column tracking start signal completes tracking after charging of m NMOS tubes is completed, and a trigger signal of a falling edge is given.

[0036] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A FPGA BRAM timing pulse width control method, characterized in that: The following steps are involved: Step 1: The FPGA original clock signal clk passes through the pulse width control circuit module for controlling the clock pulse length at the rising edge, generating a global working clock clkint1 signal at a high level; The original clock signal clk needs to be combined with the BRAM work enable signal and the power-on clear signal por_reset signal at its rising edge under the combination of the combinational logic switch to form a working clock signal clk1 that enables the BRAM to start working. In step 1, at the rising edge of the working clock signal clk1, after passing through a pulse width control circuit module for controlling the pulse length of the working clock signal, a global working clock clkint1 signal at a high level is generated; Step 2: Use a tracking circuit to simulate and track the working time of the row and column units of the BRAM storage array respectively, and the tracking circuit starts tracking at the rising edge of the global working clock clkint1 signal; Step 3: After completing the simulation tracking of the working time of the row and column units of the BRAM storage array, a trigger signal Rstb1 is provided to trigger the falling edge of the global working clock clkint1 signal at a high level; Step 4: The trigger signal of the falling edge pulls down the falling edge of the global working clock clkint1 signal under the action of the pulse width control circuit module to form the pulse width of the global working clock; The pulse width control circuit module structure comprises a third inverter (3), a first inverter (1) with a low level keeper, and a second inverter (2) with a high level keeper, the output end of the first inverter (1) and the output end of the second inverter (2) are respectively connected to the third inverter (3), the output end of the third inverter (3) is a global working clock signal clkint1, the working clock signal clk1 is input to the second inverter (2), and the trigger signal of the falling edge is input to the first inverter (1).

2. A FPGA BRAM timing pulse width control method according to claim 1, characterized in that: The first inverter (1) with a low level keeper comprises a fourth inverter (10) composed of a first NMOS tube (11) and a first PMOS tube (12), a second NMOS tube (13) and a fifth inverter (14); the source terminal of the first NMOS tube (11) is connected to the drain of the second NMOS tube (13); the source of the second NMOS tube (13) is grounded; the output terminal of the fourth inverter (10) is connected to the fifth inverter (14) and then input to the gate of the second NMOS tube (13); the output terminal of the fourth inverter (10) is connected to the output terminal of the second inverter (2) and then input to the third inverter (3) to form a global working clock signal clkint1.

3. A FPGA BRAM timing pulse width control method according to claim 2, characterized in that: The second inverter (2) with a high level keeper comprises a sixth inverter (20) composed of a third NMOS tube (21) and a third PMOS tube (22), a second PMOS tube (23) and a seventh inverter (24); the source terminal of the third PMOS tube (22) is connected to the drain of the second PMOS tube (23); the source of the second PMOS tube (23) is connected to a power supply; the output terminal of the sixth inverter (20) is connected to the seventh inverter (24) and then input to the gate of the second PMOS tube (23); the output terminal of the sixth inverter (20) is connected to the output terminal of the fourth inverter (10) and then input to the third inverter (3) to form a global working clock signal clkint1.

4. The FPGA BRAM timing pulse width control method according to any one of claims 1 to 3, characterized in that: The circuit structure of the tracking circuit includes a row decoding circuit, a row tracking analog circuit, and a column tracking analog circuit; The row decoding circuit is used to determine which row of unit cells in the static random access memory SRAM storage array is selected to generate a word line signal WL for operation, and at the same time provide a signal for tracking the operation time of the unit cells in this row; The row tracking simulation circuit uses n pairs of NMOS tubes to simulate the opening time of n unit cells in a row of a word line WL in a static random access memory SRAM storage array. The gates of the n pairs of NMOS tubes are respectively connected to a row tracking start signal. The row tracking start signal is generated by a global working clock signal after the row decoding circuit determines which row of unit cells are working and generates a high level. The source and drain of the n pairs of NMOS tubes are connected to the ground signal. After the n pairs of NMOS tubes are charged, a row tracking completion feedback signal is given. The column tracking simulation circuit uses m NMOS tubes to simulate the read and write working time of a bit line BL in a column of m units in a static random access memory SRAM storage array, and the column tracking start signal is respectively input into the source end of the m NMOS tubes, and the gate and drain of the m NMOS tubes are connected to the ground signal; The column tracking start signal is triggered by the row tracking completion feedback signal to give a column tracking start signal; The column tracking start signal completes tracking after charging of m NMOS tubes is completed, and a trigger signal of a falling edge is given.

5. The FPGA BRAM timing pulse width control method according to claim 4, characterized in that: The column tracking completion signal passes through two stages of inverters to provide a falling edge trigger signal Rstb1.

6. An FPGA BRAM timing pulse width control circuit, characterized in that: It includes a clock circuit module, a pulse width control circuit module, and a tracking circuit module; The clock circuit module is used to form a working clock signal clk1 that enables the BRAM to start working under the combination of the combinational logic switch at the rising edge of the original clock signal, the BRAM working enable signal, and the power-on clear signal por_reset signal; The tracking circuit module is used to track the read and write working time of the storage unit of the static random access memory SRAM in the BRAM, and after the tracking is completed, it gives a trigger signal for pulling down the global working clock level to the pulse width control circuit module; The pulse width control circuit module is used to control the pulse length of the working clock signal clk1 at a high level according to the trigger signal to form a global working clock signal; The output end of the clock circuit module is connected to the pulse width control circuit module, the output end of the pulse width control circuit module provides a global working clock signal, the output end of the pulse width control circuit module is also input to the tracking circuit, and the output end of the tracking circuit module is input to the pulse width control circuit module; The circuit structure of the tracking circuit module includes a row decoding circuit, a row tracking analog circuit, and a column tracking analog circuit; The row decoding circuit is used to determine which row of unit cells in the static random access memory SRAM storage array is selected to generate a word line signal WL for operation, and at the same time provide a signal for tracking the operation time of the unit cells in this row; The row tracking simulation circuit uses n pairs of NMOS tubes to simulate the opening time of n unit cells in a row of a word line WL in a static random access memory SRAM storage array. The gates of the n pairs of NMOS tubes are respectively connected to a row tracking start signal. The row tracking start signal is generated by a global working clock signal after the row decoding circuit determines which row of unit cells are working and generates a high level. The source and drain of the n pairs of NMOS tubes are connected to the ground signal. After the n pairs of NMOS tubes are charged, a row tracking completion feedback signal is given. The column tracking simulation circuit uses m NMOS tubes to simulate the read and write working time of a bit line BL in a column of m units in a static random access memory SRAM storage array, and the column tracking start signal is respectively input into the source end of the m NMOS tubes, and the gate and drain of the m NMOS tubes are connected to the ground signal; The column tracking start signal is triggered by the row tracking completion feedback signal to give a column tracking start signal; The column tracking start signal completes tracking after charging of m NMOS tubes is completed, and a trigger signal of a falling edge is given.

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