Semiconductor device, operating method thereof, and memory system

Abstract

The invention discloses an operation method of a semiconductor device, and the semiconductor device comprises a first storage unit, a second storage unit, a first word line and a second word line which are respectively connected to the first storage unit and the second storage unit. The operation method comprises the following steps of: performing a first erasing action on the first storage unit and the second storage unit by using a first erasing voltage; and performing a second erase action on the first memory cell and the second memory cell with a second erase voltage, wherein when the second erasing action is carried out, a first bias voltage is applied to the first word line, a second bias voltage is applied to the second word line, and the first bias voltage is greater than the second bias voltage. According to the invention, the erasing depth of different layers of word lines or storage units can be more accurately controlled.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device, an operating method thereof, and a storage system. Background Art

[0002] Semiconductor memory devices include semiconductor materials such as silicon (Si), germanium (Ge), gallium arsenide (GaAs), and indium phosphide (InP). Semiconductor memory devices include volatile memory devices and nonvolatile memory devices.

[0003] In a volatile memory device, the stored data is erased when the power is cut off. Volatile memory devices include static random access memory (SRAM), dynamic random access memory (DRAM), and synchronous dynamic random access memory (SDRAM). Non-volatile memory devices are able to maintain the stored data even when the power is cut off. Non-volatile memory devices include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory devices, phase change random access memory (PRAM), magnetoresistive random access memory (MRAM), resistive random access memory (RRAM), and ferroelectric random access memory (FRAM). Flash memory devices include NOR (NOR) type flash memory devices and NAND (NAND) type flash memory devices.

[0004] As devices become smaller and smaller, erasable memory devices have always had the problem of over-erasing, which is a problem that needs to be solved in the industry. Summary of the invention

[0005] The purpose of the present application is to provide a semiconductor device, an operating method thereof, and a storage system to solve the problem that different storage cells have different erasing speeds / depths, resulting in excessive erasure of some storage cells and excessive wear.

[0006] The present application provides an operating method of a semiconductor device, wherein the semiconductor device includes a first storage unit and a second storage unit, and a first word line and a second word line connected to the first storage unit and the second storage unit, respectively. The operating method includes:

[0007] Performing a first erasing operation on the first memory cell and the second memory cell with a first erasing voltage; and

[0008] Performing a second erasing operation on the first memory cell and the second memory cell with a second erasing voltage;

[0009] When performing the second erasing operation, a first bias voltage is applied to the first word line, a second bias voltage is applied to the second word line, and the first bias voltage is greater than the second bias voltage.

[0010] In some embodiments, the operating method further includes performing an erase verification action on the first storage unit and the second storage unit after the first erase action to perform erase verification, and the first storage unit passes the erase verification, while the second storage unit fails the erase verification.

[0011] In some embodiments, the semiconductor device includes at least one storage string, the storage string is connected to multiple word lines and includes at least one first storage cell and at least one second storage cell, the multiple word lines include a first group of word lines and a second group of word lines, the first group of word lines includes at least one first word line connected to the first storage cell, and the second group of word lines includes at least one second word line connected to the second storage cell; and the operating method also includes: applying the first bias voltage to the first group of word lines, and applying the second bias voltage to the second group of word lines.

[0012] In some embodiments, the operating method further includes setting the second erase voltage to be higher than the first erase voltage.

[0013] In some embodiments, the first bias voltage invalidates the second erasing action, and the second bias voltage validates the second erasing action.

[0014] In some embodiments, the operating method further includes setting the first bias voltage to a positive potential and setting the second bias voltage to a ground potential.

[0015] In some embodiments, the operating method further includes setting the difference between the first bias voltage and the second bias voltage to N times the potential difference between the first erase voltage and the second erase voltage, where N is a positive integer.

[0016] In some embodiments, the erase verification action includes:

[0017] A first erasure verification action, performing a first erasure verification with a first erasure verification voltage; and

[0018] A second erasure verification action, performing a second erasure verification with a second erasure verification voltage, wherein the second erasure verification voltage is lower than the first erasure verification voltage;

[0019] When at least one of the first erasure verification and the second erasure verification fails, the erasure verification is set to the failed erasure verification; when the second erasure verification passes, the erasure verification is set to the passed erasure verification.

[0020] In some embodiments, the operating method further includes:

[0021] When both the first erase verification and the second erase verification fail, the second bias voltage is set to an erase full effect potential, and the erase full effect potential includes one of an erase original effect potential and an erase enhancement potential, and the erase enhancement potential is lower than the erase original effect potential.

[0022] In some embodiments, the operating method further includes:

[0023] When the first erase verification passes but the second erase verification fails, the second bias voltage is set to an erase deactivation potential, which is lower than the potential of the first bias voltage.

[0024] In some embodiments, the operating method further includes:

[0025] When both the first erase verification and the second erase verification fail, the second bias voltage is set to an erase full-effect potential, and the erase full-effect potential includes one of an erase original-effect potential and an erase enhancement potential;

[0026] When the first erase verification passes, but the second erase verification fails, setting the second bias voltage to an erase deactivation potential;

[0027] The erase reduction potential is greater than the erase full effect potential and less than the potential of the first bias voltage.

[0028] In some embodiments, the semiconductor device includes at least one memory string, the memory string includes a plurality of memory cells and is respectively connected to a plurality of word lines, and the plurality of memory cells include a plurality of groups of memory cells, each of the groups of memory cells includes at least one of the first memory cells and at least one of the second memory cells; and

[0029] The first erasure verification operation and the second erasure verification operation include: for different groups of memory cells, using different first erasure verification voltages and / or second erasure verification voltages for different groups, performing the first erasure verification and the second erasure verification on each group of memory cells.

[0030] In some embodiments, the semiconductor device includes at least one memory string, the memory string includes a plurality of memory cells and is respectively connected to a plurality of word lines, and the plurality of memory cells include a plurality of groups of memory cells, each of the groups of memory cells includes at least one of the first memory cells and at least one of the second memory cells; and

[0031] The operating method further includes: performing the second erasing operation on each of the groups of memory cells using different erase-deactivation potentials and / or erase-full-activation potentials for different groups of memory cells.

[0032] In another aspect, the present application provides a semiconductor device, comprising:

[0033] A memory array, the memory array comprising a first memory cell and a second memory cell, a first word line and a second word line connected to the first memory cell and the second memory cell respectively; and

[0034] The erasing circuit can perform a first erasing operation on the first storage unit and the second storage unit through a first erasing voltage, and perform a second erasing operation on the first storage unit and the second storage unit through a second erasing voltage. When performing the second erasing operation, a first bias voltage can be applied to the first word line and a second bias voltage can be applied to the second word line, and the first bias voltage is greater than the second bias voltage.

[0035] In some embodiments, the semiconductor device also includes an erase verification circuit, which performs erase verification on the first storage unit and the second storage unit after the first erase action, and determines that the first storage unit passes the erase verification and the second storage unit fails the erase verification.

[0036] In some embodiments, the memory includes at least one storage string, which is connected to multiple word lines and includes at least one of the first storage cells and at least one of the second storage cells, the multiple word lines include a first group of word lines and a second group of word lines, the first group of word lines includes at least one of the first word lines connected to the first storage cells, and the second group of word lines includes at least one of the second word lines connected to the second storage cells; and the erase circuit can apply the first bias voltage to the first group of word lines and apply the second bias voltage to the second group of word lines.

[0037] In some embodiments, the second erase voltage is higher than the first erase voltage.

[0038] In some embodiments, the first bias voltage invalidates the second erasing action, and the second bias voltage validates the second erasing action.

[0039] In some embodiments, the first bias voltage is a positive potential, and the second bias voltage is a ground potential.

[0040] In some embodiments, a difference between the first bias voltage and the second bias voltage is N times a voltage difference between the first erase voltage and the second erase voltage, where N is a positive integer.

[0041] In some embodiments, the erase verification circuit includes:

[0042] A first erasure verification circuit, configured to perform a first erasure verification on the memory cell by applying a first erasure verification voltage; and

[0043] A second erasure verification circuit, used for performing a second erasure verification on the storage unit through a second erasure verification voltage, wherein the second erasure verification voltage is lower than the first erasure verification voltage;

[0044] When at least one of the first erasure verification and the second erasure verification fails, the erasure verification circuit sets the erasure verification as failing the erasure verification; when the second erasure verification passes, the erasure verification circuit sets the erasure verification as passing the erasure verification.

[0045] In some embodiments, when both the first erase verification and the second erase verification fail, the erase verification circuit sets the second bias voltage to an erase full-effect potential, and the erase full-effect potential includes one of an erase original effect potential and an erase enhancement potential, and the erase enhancement potential is lower than the erase original effect potential.

[0046] In some embodiments, when the first erase verification passes but the second erase verification fails, the erase verification circuit sets the second bias voltage to an erase deactivation potential.

[0047] In some embodiments, when both the first erase verification and the second erase verification fail, the erase verification circuit sets the second bias voltage to the erase full-effect potential; and when the first erase verification passes but the second erase verification fails, the erase verification circuit sets the second bias voltage to the erase reduction potential; wherein the erase reduction potential is greater than the erase full-effect potential and less than the potential of the first bias voltage.

[0048] In some embodiments, the semiconductor device includes at least one storage string, the storage string includes a plurality of storage cells and are respectively connected to a plurality of word lines, and the plurality of storage cells include a plurality of groups of storage cells, each of the groups of storage cells includes at least one of the first storage cell and at least one of the second storage cell; and the first erasure verification circuit and the second erasure verification circuit can perform the first erasure verification and the second erasure verification on different groups of storage cells with different first erasure verification voltages and / or second erasure verification voltages for different groups.

[0049] In some embodiments, the semiconductor device includes at least one memory string, the memory string includes a plurality of memory cells and is respectively connected to a plurality of word lines, and the plurality of memory cells include a plurality of groups of memory cells, each of the groups of memory cells includes at least one of the first memory cells and at least one of the second memory cells; and

[0050] The erasing circuit may perform the second erasing operation on different groups of memory cells using different erase-deactivation potentials and / or erase-full-activation potentials for different groups of memory cells.

[0051] On the other hand, the present application provides a storage system, comprising: a memory, such as the semiconductor device described above; and a controller, wherein the controller controls the operation of the memory.

[0052] The semiconductor device, its operating method and storage system disclosed in the present application can not only more accurately control the erasure depth of different layers of word lines or storage cells; but also avoid the problem that different storage cells have different erasure speeds / depths, but also some storage cells are erased too deeply and excessively worn due to each incremental step pulse erasure operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the technical solutions in the embodiments or the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 An exemplary system block diagram of an electronic device with a storage system disclosed in an embodiment of the present application.

[0055] Figure 2a A schematic plan view of an exemplary memory card with a storage system disclosed in an embodiment of the present application.

[0056] Figure 2b A schematic plan view of a solid state drive with a storage system disclosed in an embodiment of the present application.

[0057] Figure 3 A system block diagram of an exemplary memory including a storage array and peripheral circuits disclosed in an embodiment of the present application.

[0058] Figure 4a It is a top view schematic diagram of the structural division of the three-dimensional NAND memory disclosed in the embodiment of the present application.

[0059] Figure 4b It is a three-dimensional schematic circuit diagram of the structural division of the three-dimensional NAND memory disclosed in the embodiment of the present application.

[0060] Figure 4c FIG. 1 is a voltage-time diagram of an incremental step pulse erase (ISPE) operation performed by a memory device disclosed in an embodiment of the present application.

[0061] Figure 4d Schematic diagram of threshold voltage distribution difference after an erase operation is performed on the memory shown in an embodiment of the present application.

[0062] Figure 5a and 5b They are respectively flowchart diagrams of the operating methods of the semiconductor devices shown in the embodiments of the present application.

[0063] Figure 6a and 6b They are schematic diagrams of bias configurations of single and grouped memory cells in the operating method of the semiconductor device shown in the embodiments of the present application.

[0064] Figures 7a to 7c They are schematic diagrams of the relationship between the threshold potentials of various memory cells and different verification potentials in the operating method of the semiconductor device shown in the embodiments of the present application.

[0065] Figure 8 This is a flow chart of the operation method for coarse and fine erase verification in the operation method of the semiconductor device shown in the embodiment of the present application.

[0066] Fig. 9 Schematic diagram of bias configuration of a group of memory cells in an operating method of a semiconductor device according to an embodiment of the present application.

[0067] Fig.10 It is a schematic block diagram of the structure of the semiconductor device shown in the embodiment of the present application. DETAILED DESCRIPTION

[0068] The specific structural and functional details disclosed herein are merely representative and are for the purpose of describing exemplary embodiments of the present application. However, the present application can be implemented in many alternative forms and should not be interpreted as being limited to only the embodiments set forth herein.

[0069] In the description of the present application, it should be understood that the terms "center", "lateral", "up", "down", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, which are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are used for descriptive purposes only, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, unless otherwise specified, "multiple" means two or more. In addition, the term "including" and any variation thereof are intended to cover non-exclusive inclusions.

[0070] Furthermore, when the terms "first" and "second" are added to the same type of devices, they are only used to distinguish different devices of the same type and are only for the convenience of expressing relative positions. They do not represent order or fixity. In other words, "first" and "second" are interchangeable, and one of the devices of the same type can be referred to as the "first" or the "second".

[0071] In the description of this application, it should be noted that, unless otherwise clearly specified and limited, the terms "connected" and "connection" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection, or it can be indirectly connected through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0072] The terms used herein are only for describing specific embodiments and are not intended to limit exemplary embodiments. Unless the context clearly indicates otherwise, the singular forms "one", "one" and "item" used herein are also intended to include plural numbers. It should also be understood that the terms "include" and / or "comprise" used herein specify the existence of stated features, integers, steps, operations, units and / or components, without excluding the existence or addition of one or more other features, integers, steps, operations, units, components and / or combinations thereof.

[0073] First, see Figure 1 , Figure 1 A schematic block diagram of an exemplary electronic system 100 having a storage system 110 according to some embodiments of the present application is shown. The electronic system 100 may be, for example, a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory therein.

[0074] like Figure 1 As shown, the electronic system 100 may include at least a storage system 110 and a host 120. The storage system 110 has a controller 111 and one or more memories 112. The host 120 may be a processor (e.g., a central processing unit, CPU) or a system on a chip (SoC) (e.g., an application processor, AP) of an electronic device. Specifically, the host 120 may be configured to send data to the memory 112 or receive data from the memory 112.

[0075] According to some embodiments, the controller 111 is coupled to the memory 112 and the host 120 and is configured to control the memory 112. Further, the controller 111 can manage data stored in the memory 112 and communicate with the host 120. In some embodiments, the controller 111 is designed to operate in a low duty cycle environment, which can be a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the controller 111 is designed to operate in a high duty cycle environment, which can be a Solid State Drive (SSD) or an embedded Multi Media Card (eMMC), and can be used as a data storage device for an enterprise storage array or a mobile device such as a smart phone, a tablet computer, a laptop computer, etc.

[0076] The controller 111 may be configured to control the operation of the memory 112, such as a read operation (Read), an erase operation (Erase), and a program operation (Program). The controller 111 may also be configured to manage various functions related to data stored or to be stored in the memory 112, such as but not limited to bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 111 is also configured to process error correction codes (ECC) related to data read from or written to the memory 112. In some embodiments, the controller 111 may also be configured to perform any other suitable function, such as formatting the memory 112. Further, in some embodiments, the controller 111 is configured to fully or partially perform the operating method described in detail below.

[0077] The controller 111 may communicate with an external device (e.g., the host 120) according to a specific communication protocol. For example, the controller 111 may communicate with an external device through at least one of various interface protocols, and the interface protocol may be, for example, a universal serial bus (USB) protocol, a multimedia (Multi Media Card, MMC) protocol, a peripheral component interconnect (Peripheral Component Interconnect, PCI) protocol, a high-speed PCI (Peripheral Component Interconnect Express, PCI-E) protocol, an advanced technology attachment (Advanced Technology Attachment, ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (Small Computer System Interface, SCSI) protocol, an enhanced small disk interface (Enhanced Small Device Interface, ESDI) protocol, an integrated drive electronics (Integrated Drive Electronics, IDE) protocol, and a FireWire protocol.

[0078] The controller 111 and one or more memories 112 can be integrated into various types of storage devices, for example, can be integrated into the same package. Furthermore, the above package can be a package such as a universal flash storage (UFS) package or an embedded multimedia card (eMMC) package, that is, the storage system 110 can be implemented and packaged into different types of terminal electronic products.

[0079] For example, in Figure 2a In one example shown, the controller 111 and the single memory 112 may be integrated into a memory card 200a. Further, the memory card 200a may be a card such as a PC card (Personal Computer Memory Card International Association, PCMCIA, Personal Computer Memory Card International Association), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a multimedia card (including at least: a multimedia (MMC) card, a Reduced Size MMC (RS-MMC) card, and a micro multimedia (MMC micro) card), an SD card (including at least: a Secure Digital (SD) card, a Mini-SD card, a Micro-SD card, and a Secure Digital High Capacity (SDHC) card), and a Universal Flash Storage Card (UFS). Further, as Figure 2a As shown, the memory card 200a may also include a method for connecting the memory card 200a to a host (eg, Figure 1 The memory card connector 210a is coupled to the host 120 in the memory card connector.

[0080] For example, in Figure 2b In another example shown, the controller 111 and the plurality of memories 112 may be integrated into a solid state drive (SSD) 200b. The solid state drive 200b may also include a computer that connects the solid state drive 200b to a host (e.g., Figure 1 The solid state drive connector 210b is coupled to the host 120).

[0081] In some embodiments, the storage capacity and / or operating speed of the solid state drive 200b is higher than the storage capacity and / or operating speed of the memory card 200a.

[0082] Next, please refer to Figure 3 , Figure 3 FIG. 4 shows a system block diagram of an exemplary memory 400 including a memory array 420 and a peripheral circuit 410 according to an embodiment of the present application. Figure 3 As shown, the peripheral circuit 410 may include at least a page buffer / sense amplifier 411, a column decoder / bit line driver 412, a row decoder / word line driver 413, a voltage generator 414, a control logic unit 415, a register 416, an interface 417, and a data bus 418. It should be understood that in some examples, the peripheral circuit 410 may also include Figure 3 Other circuits shown in FIG.

[0083] The page buffer / sense amplifier 411 may be configured to read data from the memory array 420 and program (also referred to as "write") data to the memory array 420 according to a control signal from the control logic unit 415. Specifically, in one example, the page buffer / sense amplifier 411 may store data to be programmed into a memory page 430 of the memory array 420. In another example, the page buffer / sense amplifier 411 may perform a program verification operation (Verify) to ensure that the data has been correctly programmed into the memory cell 421 coupled to the selected word line WL. In yet another example, the page buffer / sense amplifier 411 may also perform an operation of sensing a low-power signal from the bit line BL representing data stored in the memory cell 421, and amplify the small voltage swing of the low-power signal to a recognizable logic level in a read operation.

[0084] The column decoder / bit line driver 412 may be configured to be controlled by the control logic unit 415 and select one or more NAND memory strings 422 by applying a bit line voltage generated from the voltage generator 414 .

[0085] The row decoder / word line driver 413 can be configured to be controlled by the control logic unit 415 to select / deselect the memory block A2 in the memory array 420. The row decoder / word line driver 413 can also be configured to drive the word line WL using the word line voltage generated from the voltage generator 414. In some embodiments, the row decoder / word line driver 413 can also perform operations of selecting / deselecting and driving the drain selection gate line DSL and the source selection gate line SSL. As described in detail below, the row decoder / word line driver 413 is configured to perform operations such as programming, erasing, and verifying on the memory cells 421 coupled to one or more selected word lines WL.

[0086] The voltage generator 414 can be configured to be controlled by the control logic unit 415 and generate word line voltages (e.g., read voltages, program voltages, pass voltages, local voltages, verification voltages, erase voltages, etc.), bit line voltages, and source line voltages to be supplied to the memory array 420.

[0087] The control logic unit 415 can be coupled to each circuit in the peripheral circuit 410 as described above (e.g., the page buffer / sense amplifier 411, the column decoder / bit line driver 412, the row decoder / word line driver 413, and the voltage generator 414) and control the operation of each circuit.

[0088] The register 416 may be coupled to the control logic unit 415 and may include at least a status register, a command register and an address register to store status information, a command operation code (OP code) and a command address for controlling the operation of each of the above circuits.

[0089] Interface 417 may be coupled to control logic unit 415 and act as a control buffer to perform buffering from Figure 1 The interface 417 is configured to receive a control command received by the controller and relay the command to the control logic unit 415, and to perform an operation of buffering status information received from the control logic unit 415 and relaying the command to the controller. Further, the interface 417 can also be coupled to the column decoder / bit line driver 412 via the data bus 418, and act as a data I / O (Input / Output) interface and a data buffer to perform an operation of buffering data and relaying the data to the storage array 420, and to perform an operation of relaying or buffering data from the storage array 420.

[0090] exist Figure 3 The memory array 420 in the memory 112 shown may be, for example, a memory array of a three-dimensional NAND type memory (3D NAND Flash). Figure 4a Taking a three-dimensional NAND memory storage array 300 as an example, Figure 3 The storage array 420 shown is used as an example. Figure 4a A schematic top view of the structural division of a storage array 300 in a three-dimensional NAND memory 112 is exemplarily provided.

[0091] like Figure 4a As shown, the memory array 300 in the three-dimensional NAND memory 112 has at least one large-size block-shaped memory platform (Giant Block, GB) A1, and the memory platform A1 at least includes a plurality of memory cells 421 arranged in an array, and a first gate gap structure 310, a second gate gap structure 320, and an upper selection gate gap structure 330 for separating the plurality of memory cells 421. Specifically, the first gate gap structure 310 is disposed in the memory platform A1, and divides the memory platform A1 into a plurality of memory blocks (Blocks) A2. The second gate gap structure 320 is disposed in the memory block A2, and divides the corresponding memory block A2 into a plurality of finger storage areas (Finger areas) A3. The upper selection gate gap structure 330 is disposed in the finger storage area A3, and divides the corresponding finger storage area A3 into a plurality of page storage areas (String areas) A4. Figure 4aIn the example, a storage block A2 includes three finger storage areas A3, and a finger storage area A3 includes two page storage areas A4. That is, a storage block A2 includes six page storage areas A4. It should be noted that in actual applications, the number of page storage areas A4 in a storage block A2 is not limited thereto.

[0092] See also Figure 4b , Figure 4b FIG. 4 is a circuit diagram showing an exemplary memory array 420 including a peripheral circuit 410 according to some embodiments of the present application. The memory 400 may be Figure 1 The memory 400 is an example of the memory 112, and the memory 400 may include a peripheral circuit 410 and a storage array 420. Next, the memory 400 is taken as the above-mentioned three-dimensional NAND memory 300 as an example for description.

[0093] like Figure 4b As shown, in the memory 400, the memory array 420 includes at least a plurality of memory cells 421. Specifically, the memory cells 421 are provided in the form of an array of NAND memory strings 422, and each NAND memory string 422 is disposed vertically on an initial substrate ( Figure 4b In some embodiments, each NAND storage string 422 includes a plurality of storage cells 421 coupled in series and stacked vertically. Further, each storage cell 421 may maintain a continuous analog value, such as a voltage or a charge, which depends on the number of electrons captured by each storage cell 421 in the corresponding region. Specifically, in some embodiments, each storage cell 421 may include a gate layer, and a channel structure consisting of a tunneling insulating layer, a charge storage layer, a blocking insulating layer, and a polysilicon layer as a channel. The storage cell 421 may be a floating gate type storage cell including a floating gate transistor, or a charge trap type storage cell including a charge trap transistor.

[0094] In some embodiments, each storage cell 421 may be a single level cell (SLC), wherein the single level cell has two levels of threshold states, and therefore, each single level cell may store one bit (or referred to as "bit") of data, for example, the first level threshold state "0" may correspond to the first voltage range, and the second level threshold state "1" may correspond to the second voltage range. In other embodiments, each storage cell 421 may be a multi-level cell capable of storing more than one bit of data in more than two levels of multi-level threshold states, for example, each storage cell 421 may be a multi-level cell (MLC) capable of storing two bits of data, or a triple level cell (TLC) capable of storing three bits of data, or a quad level cell (QLC) capable of storing four bits of data. Specifically, one of the multi-level threshold states of the storage cell 421 is an erase state.

[0095] Please continue reading Figure 4b , each NAND memory string 422 has a source terminal (Source) S and a drain terminal (Drain) D, and each NAND memory string 422 includes at least a bottom select gate (Bottom Select Gate, BSG) 423 located at the source terminal S and an upper select gate (Top Select Gate, TSG) 424 located at the drain terminal D, wherein the bottom select gate 423 and the upper select gate 424 can be configured to activate the selected NAND memory string 422 during a read operation and a program operation. Further, the source terminals S of the NAND memory strings 422 in the same memory block A2 are coupled through the same source line (Source Line, SL) 425, that is, all the NAND memory strings 422 in the same memory block A2 are coupled to the array common source (Array Common Source, ACS). Further, the upper select gate 424 in each NAND memory string 422 is coupled to a corresponding bit line (Bit Line, BL) 426 (including bit lines BL0 to BLn), and can be connected to the array common source (Array Common Source, ACS) via an output bus ( Figure 4bIn some embodiments, each NAND memory string 422 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the upper selection gate 424) or a deselection voltage (e.g., 0V) to the corresponding upper selection gate 424 via one or more drain select gate lines (Drain Select Line, DSL) 427, and / or, by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having the lower selection gate 423) or a deselection voltage (e.g., 0V) to the corresponding lower selection gate 423 via one or more source select gate lines (Source Select Line, SSL) 428.

[0096] like Figure 4b As shown, each storage block A2 includes a plurality of NAND storage strings 422, and each storage block A2 has a common source line 425, which can be coupled to ground (GND). In some embodiments, a storage block A2 is the basic data unit of the erase operation, that is, the data stored in all storage cells 421 in the same storage block A2 will be completely erased in a complete erase operation. When the erase operation is performed on the storage cell 421 in the selected storage block A2, an erase voltage (Vers, which can be, for example, a higher positive voltage, illustratively, 20V or higher) can be applied to the source line 425 of the selected storage block A2. Further, the source line 425 coupled to the selected storage block A2 can also be coupled to the unselected storage block A2 at the same time. It should be understood that in some examples, the above-mentioned erase operation can also be performed at the half storage block level, at the quarter storage block level, at the level of any suitable number of storage blocks, or at any suitable fraction of the storage block.

[0097] Please continue reading Figure 4b , and please also refer to the above Figure 4aIn the memory 400, the memory array 420 further includes a plurality of word lines (WL) 429 (including word lines WL0 to WLn), and adjacent NAND memory strings 422 can be coupled through the word lines WL. Further, a plurality of memory cells 421 in a page memory area A4 coupled with a word line WL can be referred to as a memory page (expressed in English as Page) 430, and a memory page 430 is a basic data unit of a programming operation. Further, the size of a memory page 430 in bits can be related to the number of NAND memory strings 422 coupled with the word line WL in a page memory area A4. Each word line WL can include a control gate (Control Gate, also called "gate electrode") of a memory cell 421 in a corresponding memory page 430, and the control gate can be extended laterally to form a word line.

[0098] In the memory 400, the peripheral circuit 410 may be coupled to the memory array 420 via the bit lines BL, the word lines WL, the source lines 425, the drain selection gate lines DSL, and the source selection gate lines SSL. Further, the peripheral circuit 410 may include any suitable analog circuit, digital circuit, and mixed signal circuit to implement applying a voltage signal and / or a current signal to the selected memory cell 421 (also referred to as a “target memory cell”) via the bit lines BL, the word lines WL, the source lines 425, the drain selection gate lines DSL, and the source selection gate lines SSL, and sensing a voltage signal and / or a current signal from each target memory cell to perform corresponding operations of the memory array 420. Specifically, the peripheral circuit 410 may include various types of circuits formed using, for example, Metal Oxide Semiconductor (MOS) technology.

[0099] Back to Figure 3 In the illustrated embodiment, the voltage generated by the voltage generator 414 is provided to the row decoder 413, the column decoder 412, and the memory cell array 420 according to the control of the control logic unit 415. For example, in a programming operation, the program voltage Vpgm and the pass voltage Vpass are provided to the column decoder 412. In a read operation, the read voltage Vread is provided to the row decoder 413. In an erase operation of the memory cell array 110, the erase voltage Vers is provided to the memory cell array 420.

[0100] When programming a memory cell, electrons are stored in a portion of the charge storage layer associated with the memory cell. These electrons are drawn from the polysilicon body and into the charge storage layer through the tunneling insulating layer. The threshold voltage of the memory cell increases in proportion to the amount of charge stored. During the erase operation, the voltage in the polysilicon body increases due to gate induced drain leakage (GIDL), and the voltage of one or more selected word line gate layers is floated, and then the voltage of one or more selected word line layers is sharply reduced to a low level such as 0V to generate an electric field across the tunneling insulating layer, which causes holes to be injected from the body of the memory cell into the charge storage layer, resulting in a threshold voltage Vth degradation toward the erase verification level Vv-erase. This process can be repeated in continuous iterations until the verification condition is met. For unselected word lines, the word lines float but are not driven down to a low level so that the electric field across the tunnel oxide layer is relatively small, and no or very little hole tunneling occurs. The memory cells of the unselected word lines will experience little or no Vth degradation, with the result that the memory cells of the unselected word lines are not erased.

[0101] That is, the minimum unit of the erase operation is a memory block. During the erase process, a higher potential is generally applied to the bit line, and a ground potential (0V) is applied to the word line of the memory block selected for erasure, so that a larger potential difference is formed between the channel potential and the gate potential of the memory block to be erased, and then the erasure is performed in the form of hole injection. In some embodiments, the source line is connected to N+ doped polysilicon at one end, and electron-hole pairs are generated through the potential difference between the potential of the source line and the potential of the bottom select gate (BSG), and the holes in the channel are injected into the charge storage layer, and the holes are neutralized with the electrons in the charge storage layer to achieve erasure, and the potential of the word line of the memory block not selected for erasure remains floating.

[0102] In some embodiments, the control logic unit 415 includes an erase control unit (not shown), a string selection line counter (hereinafter referred to as SSL counter) (not shown), and an erase counter (not shown). The erase control unit controls the erase operation of the memory 400. For example, the erase operation of the non-volatile memory device 400 includes an erase operation and an erase verification operation. The erase operation and the erase verification operation can be performed in the selected memory block of the memory cell array 420 according to the control of the erase control unit.

[0103] The erase control unit controls the row / column decoder 412 / 413 and the voltage generator 414 to erase the selected memory block of the memory cell array 420. The erase control unit controls the row / column decoder 412 / 413, the sense amplifier 411, and the voltage generator 4140 to perform erase-verification on the selected memory block of the memory cell array 420. For example, the erase control unit controls erasure based on information stored in the erase counter. For example, the erase control unit controls erase verification based on information stored in the SSL counter.

[0104] The erase control unit identifies an erase pass or an erase fail based on the output of the pass / fail check unit, and controls continuous erase or erase verification according to the erase pass or erase fail.

[0105] The count value of the erase counter (hereinafter referred to as the erase count) corresponds to the number of times a specific memory block of the memory cell array 420 is erased in an erase operation. For example, the erase count corresponds to the number of times the erase voltage Vers is applied to the specific memory block in an erase operation. For example, the erase count corresponds to the number of times the erase voltage (or erase pulse) is applied to the specific memory block in incremental step pulse erase (ISPE).

[0106] Specifically, Figure 4c As shown, in the ISPE erasing operation, after the first erasing operation Er1, the first erasing verification operation is performed with the voltage Vve. After the first erasing verification Ve fails, the second erasing operation Er2 will be performed, and the voltage Ver2 of the second erasing operation Er2 is higher than the voltage Ver1 of the first erasing operation Er1 by a step voltage difference Vstep, and then the verification after the second erasing operation Er2 is performed. And so on, until the verification passes, or exceeds the predetermined number of erasing times, a round of erasing operation is stopped.

[0107] In some embodiments, during the erasing process, different word lines will be given a certain voltage compensation, and the verification method is to perform an erase verification (erase verify) on all word lines connected to the storage string after each erase pulse. During each pulse erase, the word line compensation voltage is constant, and even if some memory cells pass the erase verification, the erase action will continue until all memory cells pass the erase verification.

[0108] However, upon further study, the present application Figure 4d As shown in FIG. 1 , it is known that when the same erasure verification voltage is applied, the depth of erasure of the memory cells located at different gate layers is different, that is, the distance between the threshold distribution of the memory cells and the verification potential Vve is different, as shown in FIG. Figure 4dAs shown in (b) and (c), unnecessary deep erase will occur, resulting in poor wear performance and affecting the endurance and retention characteristics of the storage cell. Moreover, when the same erase verification voltage is used, there are obvious differences in the depth of erase of storage cells in different gate layers, which will also affect the read window after programming.

[0109] Therefore, according to some embodiments of the present application, a further erasing operation method is provided, which can improve the aforementioned problem. Figure 5a and 5b Some operating methods of a semiconductor device according to some embodiments of the present application are disclosed. The semiconductor device includes a first memory cell and a second memory cell, and a first word line and a second word line connected to the first memory cell and the second memory cell, respectively. The operating method includes:

[0110] Performing a first erasing operation on the first memory cell and the second memory cell with a first erasing voltage; and

[0111] Performing a second erasing operation on the first memory cell and the second memory cell with a second erasing voltage;

[0112] When performing the second erasing operation, a first bias voltage is applied to the first word line, a second bias voltage is applied to the second word line, and the first bias voltage is greater than the second bias voltage.

[0113] Specifically, Figure 6a The memory string bias configuration diagram is shown in Figure 1. Figure 4b The memory string circuit diagram shown and Figure 4c The schematic diagram of the voltage-time of the erase operation is shown, the semiconductor device 400 includes a first storage unit 421-1 and a second storage unit 421-2, which are respectively connected to a first word line 429-1 and a second word line 429-2 of the first storage unit and the second storage unit, and the operation method includes:

[0114] Step S10: performing a first erasing operation Er1 on the first storage unit 421 - 1 and the second storage unit 421 - 2 with a first erasing voltage Ver1; and

[0115] Step S20: performing a second erasing operation Er2 on the first storage unit 421-1 and the second storage unit 421-2 with a second erasing voltage Ver2;

[0116] When performing the second erasing operation, a first bias voltage Bias1 is applied to the first word line 429-1, and a second bias voltage Bias2 is applied to the second word line 429-2, and the first bias voltage Bias1 is greater than the second bias voltage Bias2. That is, Bias1=Bias2+ΔV.

[0117] In a further embodiment, Figure 5b As shown, the erasing operation method further includes:

[0118] Step S15: After the first erasing operation Er1, an erasing verification operation is performed on the first storage unit 421-1 and the second storage unit 421-2 with a verification voltage Vve to perform erasing verification, and the first storage unit 421-1 passes the erasing verification, while the second storage unit 421-2 fails the erasing verification.

[0119] As mentioned above, in the ISPE erasing operation, after the first erasing operation is performed with the first erasing voltage Ver1, the erasing verification operation is performed on the first storage unit 421-1 and the second storage unit 421-2 with the verification voltage Vve. At this time, if the first storage unit 421-1 passes the erasing verification, but the erasing verification of the second storage unit 421-2 fails, a second erasing operation Er2 will be performed, and the erasing voltage Ver2 of the second erasing operation is higher than the erasing voltage Ver1 of the first erasing operation Er2, usually by a step voltage difference Vstep, and then verification is performed after the second erasing operation.

[0120] pass Figure 5a and Figure 5bIn the method configuration shown, when performing the second erasing operation, a first bias voltage Bias1 is applied to a first word line 429-1 connected to a first storage unit 421-1 that has passed the erasing verification, and a second bias voltage Bias2 is applied to a second word line 429-2 connected to a second storage unit 421-2 that has not passed the erasing verification, and the first bias voltage Bias1 is greater than the second bias voltage Bias2, that is, Bias1=Bias2+ΔV, so that the first storage unit 421-1 cannot be erased in the form of hole injection because a small potential difference is formed between the channel potential and the gate potential that is not enough to produce an erasing effect, thereby making the erasing operation of the first storage unit for the second erasing operation invalid. However, the second storage unit 421-2 can achieve the phenomenon of hole injection because a large potential difference is still formed between the channel potential and the gate potential that is enough to produce an erasing effect, and can be effectively erased. In this way, the erasing depth of word lines or memory cells at different layers can be controlled more accurately, thereby avoiding the problem that different memory cells have different erasing speeds / depths, but some memory cells are erased too deeply and excessively worn because they have to be erased again during each incremental step pulse erasing operation.

[0121] Furthermore, in some embodiments, the erase operation method further includes: setting the first bias voltage Bias1 to a positive potential, and setting the second bias voltage Bias2 to a ground potential.

[0122] Specifically, through such a configuration, when the erase voltage is applied to the source, the erase operation of the first memory cell 421-1 is invalid due to insufficient potential difference, but the erase operation of the second memory cell 421-2 is still valid due to sufficient potential difference.

[0123] Furthermore, in some embodiments, the erase operation method further includes: setting the difference between the first bias voltage Bias1 and the second bias voltage Bias2 to N times the potential difference between the first erase voltage Ver1 and the second erase voltage Ver2, where N is a positive integer.

[0124] Specifically, through such a configuration, with each step increment of the erase voltage in the ISPE erase operation, even if the erase voltage of the Nth erase operation increases, the difference between the first bias voltage Bias1 and the second bias voltage Bias2 can be set to N times the potential difference between the (N-1)th erase voltage Ver(n-1) and the Nth erase voltage Ver(n) during the Nth erase operation, that is, N times each step increment Vstep. In this way, as the erase voltage increases, the potential of the word line of the first storage unit 421-1 that does not need to be erased is increased at the same time, and the potential difference between the channel potential and the gate potential of the first storage unit 421-1 is maintained at a small potential difference that is not enough to produce an erase effect, thereby making the second erase operation invalid for the erase operation of the first storage unit 421-1.

[0125] Further, according to some embodiments of the present application, Figure 6b Shown and referenced Figure 4b , Figure 6a The first memory cell 421-1 and the second memory cell 421-2 shown may each include a plurality of first memory cells 421-s1 and second memory cells 421-s2. That is, the semiconductor device 400 includes at least one memory string 422, the memory string is connected to a plurality of word lines 429, and includes at least one of the first memory cells 421-1 and at least one of the second memory cells 421-2, the plurality of word lines include a first group of word lines 429-s1 and a second group of word lines 429-s2, the first group of word lines 429-s1 includes at least one of the first word lines 429-1 connected to the first memory cell 421-1, and the second group of word lines 429-s2 includes at least one of the second word lines 429-2 connected to the second memory cell 421-2; and the operation method further includes: applying the first bias voltage Bias1 to the first group of word lines 429-s1, and applying the second bias voltage Bias2 to the second group of word lines 429-s2.

[0126] in other words, Figure 6b The embodiment shown is based on Figure 6a The basic principle of the embodiment shown is formed. Since the erasing action is performed on the entire memory block\storage string at the same time, after the erasure verification, in a memory string 422, the memory cells 421-2 to be erased and the memory cells 421-1 that do not need to be erased can each include a plurality of them. Therefore, by grouping the word lines 429 and setting different word line bias voltages respectively, the entire group of memory cells 421-s1 that have passed the erasure verification does not need to be erased again to avoid over-erasure; on the contrary, the entire group of memory cells 421-s2 that have not passed the erasure verification will be erased again.

[0127] exist Figure 6b In the embodiments, it can be understood that the relative configuration of the first bias voltage Bias1 and the second bias voltage Bias2 is Figure 6a The various embodiments mentioned above can also be applied to Figure 6b In the word line grouping shown, the first group of word lines 429-s1 corresponds to the first word line 429-1 / first bias voltage Bias1, and the second group of word lines 429-s2 corresponds to the second word line 429-2 / second bias voltage Bias2; the first group of storage cells 421-s1 corresponds to the first storage cell 421-1, and the second group of storage cells 421-s2 corresponds to the second storage cell 421-2.

[0128] Further, according to some embodiments of the present application, the erasure verification action shown in step S15 in the above-mentioned erasure operation method of the semiconductor device may further include:

[0129] Step S151: a first erase verification operation, performing a first erase verification with a first erase verification voltage; and

[0130] Step S155: a second erasure verification action, performing a second erasure verification with a second erasure verification voltage, and the second erasure verification voltage is smaller than the first erasure verification voltage;

[0131] When at least one of the first erasure verification and the second erasure verification fails, the erasure verification is set to the failed erasure verification; when the second erasure verification passes, the erasure verification is set to the passed erasure verification.

[0132] Specifically, Figure 7a to Figure 7c As shown, in progress Figure 4c During the erasure verification shown, the verification action Ve is divided into a first erasure verification action VER1 and a second erasure verification action VER2, and the erasure verification is performed with a first erasure verification voltage Vver1 and a second erasure verification voltage Vver2 respectively. The first erasure verification action is equivalent to a coarse verification, and the second erasure verification action is equivalent to a fine verification.

[0133] like Figure 7a to Figure 7cAs shown, after the erase operation, the threshold potential of the storage unit will have different degrees of distance relative to the verification voltage. Therefore, by setting the first erase verification voltage Vver1 and the second erase verification voltage Vver2, in addition to setting the erase verification as the failed erase verification when at least one of the first erase verification and the second erase verification fails, and setting the erase verification as the passed erase verification when both the first erase verification and the second erase verification pass, the erase depth can be further determined by whether the first (coarse) erase verification or the second (fine) erase verification passes, and then using this result, the size of the second bias voltage can be further set, that is, the second bias voltage can be set to the full-effect erase potential or the reduced-effect erase potential.

[0134] Furthermore, for a storage cell whose erase depth is not enough but still needs to be erased again, the second bias voltage is set to an erase reduction potential to perform a reduced-effect erase that is not the default full-effect erase, that is, a reduced-effect erase that has an erase effect but is not the original 100% full-effect erase (original-effect erase). In addition, for a storage cell whose erase depth is far from enough and needs to be erased again, the second bias voltage is set to an erase full-effect potential to perform the original default erase or enhanced-effect (that is, enhanced-erasure) erase. When both the first erase verification and the second erase verification are passed, that is, for a storage cell whose erase depth is sufficient and does not need to be erased again, the erase verification is set to pass, and in the next erase operation, the aforementioned first bias voltage is applied to the word line corresponding to this storage cell, and the first bias voltage is an erase invalid potential, that is, a potential that makes the next erase operation invalid for the erase operation of the storage cell.

[0135] Therefore, according to some embodiments of the present application, the operating method also includes: when both the first erase verification and the second erase verification fail, setting the second bias voltage to an erase full-effect potential, and the erase full-effect potential includes one of an erase original effect potential and an erase enhancement potential, and the erase enhancement potential is lower than the erase original effect potential.

[0136] In some further embodiments, the operating method further includes: when the first erase verification passes but the second erase verification fails, setting the second bias voltage to an erase deactivation potential, the erase deactivation potential being lower than a potential of the first bias voltage.

[0137] Therefore, in combination with the above two operating methods, in some further embodiments, the operating method of the semiconductor device further includes:

[0138] When both the first erase verification and the second erase verification fail, the second bias voltage is set to an erase full-effect potential, and the erase full-effect potential includes one of an erase original-effect potential and an erase enhancement potential;

[0139] When the first erase verification passes, but the second erase verification fails, setting the second bias voltage to an erase deactivation potential;

[0140] The erase reduction potential is greater than the erase full effect potential and less than the potential of the first bias voltage.

[0141] For details, please continue to see Figures 7a to 7c . Figure 7a The gray curve Pulse N-1 in represents the threshold potential of the memory cell after the N-1th erasing operation. The threshold potential represented by this gray curve Pulse N-1 is lower than the first erasing verification voltage Vver1 and the second erasing verification voltage Vver2, which indicates that the first erasing verification and the second erasing verification are passed. Therefore, according to the technical idea of ​​the present application, in the next erasing operation (the Nth erasing operation), these memory cells do not need to be erased again, and the word lines connected to these verified memory cells will be applied with the first bias voltage, that is, the erase invalid potential, so that the next erasing operation is invalid for these verified memory cells, and then the threshold potential of these verified memory cells after the Nth erasing operation, that is, the black curve Pulse N, can still almost overlap with the memory cell threshold potential Pulse N-1 after the N-1th erasing operation, and will not be over-erased.

[0142] exist Figure 7bIn the figure, the threshold potential of the memory cell after the N-1th erasing operation represented by the gray curve Pulse N-1 is lower than the first erasing verification voltage Vver1, but not lower than the second erasing verification voltage Vver2, which means that the first erasing verification (coarse verification) is passed, but the second erasing verification (fine verification) is not passed. Therefore, according to the technical idea of ​​the present application, in the next erasing operation (Nth erasing operation), these memory cells still need to be erased again, so the corresponding word lines are applied with a second bias voltage, but because they have passed the first erasing verification (coarse verification), only a reduced-effect erasing is required, instead of the default original-effect erasing, so the second bias voltage is set to an erase-reduced-effect potential greater than the erase-full-effect potential (e.g., 0 potential) but less than the erase-invalid potential (i.e., the first bias voltage). That is, if the increment of the first bias voltage relative to the erase full-effect potential is the first increment ΔV1, then the increment of the erase reduction potential voltage relative to the erase full-effect potential is the second increment ΔV2 which is smaller than the first increment ΔV1. By such a setting, the threshold potential of these memory cells after the Nth erase operation, that is, the black curve Pulse N, can be only slightly lower than the threshold potential Pulse N-1 of the memory cells after the N-1th erase operation, just lower than the second erase verification voltage Vver2 and pass the erase verification, but will not be over-erased.

[0143] exist Figure 7c In the figure, the threshold potential of the memory cell after the N-1th erasing operation represented by the gray curve Pulse N-1 is not lower than the first erasing verification voltage Vver1, nor is it lower than the second erasing verification voltage Vver2, which means that the first erasing verification (coarse verification) and the second erasing verification (fine verification) have not been passed. Therefore, according to the technical idea of ​​the present application, in the next erasing operation (Nth erasing operation), these memory cells still need to be erased again, and normal original effect erasing or enhanced erasing with enhanced erasing effect should be performed, that is, the second bias voltage to be applied to the word lines corresponding to these memory cells is set to the erase full effect potential, and the erase full effect potential includes the erase original effect potential (e.g., 0 potential) or the erase enhanced potential lower than the erase original effect potential (e.g., a negative potential lower than 0 potential), so as to maintain or increase the potential difference between the gate and source of the memory cell to be erased. Through such a setting, the threshold potential of these memory cells after the Nth erasing operation, that is, the black curve Pulse N, can be lower than the threshold potential Pulse N-1 of the memory cells after the N-1th erasing operation, and just lower than the second erasing verification voltage Vver2 to pass the erasing verification, but will not be over-erased.

[0144] Next, please refer to Figure 8 , Figure 8The flowchart disclosed is a flowchart of the operation method of the semiconductor device in the embodiment of the present application regarding the various rough and fine erasure verification operations described above. Figure 8 In order to facilitate understanding, the first erasure verification and the second erasure verification mentioned above are directly expressed as the names of coarse verification and fine verification, respectively, and, Figure 8 The steps that are the same as those described previously are described using the same step numbers.

[0145] like Figure 8 As shown, after performing the N-1th erasing operation (equivalent to the aforementioned first erasing operation) S10, a rough erasing verification operation S151 is first performed. If the rough erasing verification is passed, the process proceeds to step S155 for a fine erasing verification operation; if the rough erasing verification is not passed, the Nth erasing operation is performed, and the process proceeds to step S152, where the word lines corresponding to the storage cells that have not passed the rough erasing verification are set to be at a second bias voltage (usually 0V) during the Nth erasing operation, so that subsequent erasing operations are effective, and the second bias voltage is set to the full-effect potential of erasing. Then, the second erasing operation S20, i.e., the Nth erasing operation, is performed, and then the verification operation is repeated until the fine verification is passed and the process ends.

[0146] In step S151, if the coarse erase verification is passed, then the process proceeds to step S155 for fine erase verification. If the fine erase verification is passed, then it is determined whether to perform the next erase, that is, the Nth erase. As long as there are still other storage cells that have not passed the erase verification, the Nth erase operation is to be performed. If it is determined that the next erase is to be performed, then the process proceeds to step S156, and a first bias voltage is set to be applied to the word line corresponding to the storage cell that has passed the fine erase verification, and the first bias voltage is equal to the erase invalid potential. That is, in order to make the storage cell invalid for the erase operation, the potential of the word line during the Nth erase operation is set to the first bias potential, and the first bias voltage is equal to the erase full-effect potential plus the first increment ΔV1. On the contrary, if it is determined that the next erase is not required, that is, the Nth erase operation is not required, then the verification operation can be terminated.

[0147] In step S155, if the fine erase verification fails, the process proceeds to step S157, and the potential setting for the word line corresponding to the memory cell that has not passed the fine erase verification is performed during the Nth erase operation. At this time, because the memory cell has not passed the fine erase verification, the Nth erase operation must still be valid, but because it has passed the coarse erase verification, it can be erased with reduced effectiveness. That is, the word line corresponding to the memory cell that has not passed the fine erase verification is set to be at the second bias voltage during the Nth erase operation, and the second bias voltage is set to the erase reduction potential, which is equal to the erase full effectiveness potential plus the second increment ΔV2, and the second increment ΔV2 is smaller than the first increment ΔV1. In this way, the memory cell that has not passed the fine erase verification can be erased with reduced effectiveness during the next erase, that is, the Nth erase operation, thereby reducing the possibility of over-erasure.

[0148] After completing the N-1th erase operation according to the aforementioned process and there is a need to enter the word line setting of the Nth erase operation, the Nth erase operation S20 can be entered, and the aforementioned process steps are repeated until all the storage cells to be erased pass the erase verification, thus completing the erase operation.

[0149] Furthermore, according to the technical idea of ​​the present application, as the number of 3D NAND stacking layers increases, the potential difference of each memory cell in the same memory string relative to the source is different. Therefore, in addition to the aforementioned different bias voltages for different word lines or different groups of word lines during the Nth erase operation, different first bias voltage and second bias voltage combinations can be given to different groups of word lines, or different first erase verification voltage and second erase verification voltage combinations can be given to different groups of word lines. That is, for the memory cells located in the upper layer of the stacking layer, the first first bias voltage and second bias voltage combination, or at least the first second bias voltage, can be set; for the memory cells located in the lower layer of the stacking layer, the second first bias voltage and second bias voltage combination, or at least the second second bias voltage, can be set. Or, for the memory cells located in the upper layer of the stacking layer, the first first erase verification voltage and second erase verification voltage combination can be set, and for the memory cells located in the lower layer of the stacking layer, the second first erase verification voltage and second erase verification voltage combination can be set.

[0150] Therefore, according to some embodiments of the present application, a method for operating a semiconductor device is also provided, wherein the semiconductor device includes at least one memory string, the memory string includes a plurality of memory cells and is respectively connected to a plurality of word lines, and the plurality of memory cells include a plurality of groups of memory cells, each of the groups of memory cells includes at least one of the first memory cells and at least one of the second memory cells; and

[0151] The operating method further includes: performing the second erasing operation on each of the groups of memory cells using different erase-deactivation potentials and / or erase-full-activation potentials for different groups of memory cells.

[0152] Specifically, Fig. 9 As shown, the storage string 422 includes a first group of storage cells 421-g1 and a second group of storage cells 421-g2, and these storage cells are respectively connected to multiple word lines, and the multiple word lines include a first group of word lines 429-g1 and a second group of word lines 429-g2, and each group of storage cells 421-g1 and 421-g2 includes at least one first storage cell 421-1 and at least one second storage cell 421-2.

[0153] As described in some of the previous embodiments, the erase reduction potential and the erase full potential are both relative to the second bias voltage. Fig. 9 As shown, when the next erase operation is to be performed, the word line bias voltage set for the first group of memory cells 421-g1 may include one of the following three types: a first second bias voltage Bias12-1 added to the word line corresponding to the memory cell that has not passed the coarse erase verification, and the first group of second bias voltage Bias12-1 is an erase full-effect potential; a second second bias voltage Bias12-2 added to the word line corresponding to the memory cell that has passed the coarse erase verification but has not passed the fine erase verification, and the second second bias voltage Bias12-2 is an erase reduced-effect potential; and a first first bias voltage Bias11 added to the word line corresponding to the memory cell that has passed the coarse erase verification and the fine erase verification, and the first first bias voltage is an erase invalid potential. Moreover, the first bias voltage Bias11 has a first increment ΔV11 relative to the first second bias voltage Bias12-1, and the second second bias voltage Bias12-2 has a first second increment ΔV12 relative to the first second bias voltage Bias12-1. As described above, the first first increment ΔV11 is greater than the first second increment ΔV12 to invalidate erasure; but the first second increment ΔV12 still makes erasure effective, but at a reduced effect.

[0154] The word line bias voltage set for the second group of memory cells 421-g2 may include one of the following three types: a third second bias voltage Bias22-1 added to the word line corresponding to the memory cell that has not passed the coarse erase verification, and the third second bias voltage Bias22-1 is an erase full-effect potential; a fourth second bias voltage Bias22-2 added to the word line corresponding to the memory cell that has passed the coarse erase verification but has not passed the fine erase verification, and the fourth second bias voltage Bias22-2 is an erase reduction potential; and a second first bias voltage Bias21 added to the word line corresponding to the memory cell that has passed the coarse erase verification and the fine erase verification, and the second first bias voltage Bias21 is an erase invalid potential. Moreover, the second first bias voltage Bias21 has a second first increment ΔV21 relative to the third second bias voltage Bias22-1, and the fourth second bias voltage Bias22-2 has a second second increment ΔV22 relative to the third second bias voltage Bias22-1. As described above, the second first increment ΔV21 is greater than the second second increment ΔV22 to invalidate erasure, but the second second increment ΔV22 still makes erasure effective, but at a reduced efficiency. The first first increment ΔV11 can be different from the second first increment ΔV21, and the first second increment ΔV12 can be different from the second second increment ΔV22, which can be set according to the position of the memory cell.

[0155] Through the above arrangement, different bias voltages can be applied to the word lines according to the positions of the memory cells in the memory string, so that the threshold potential of each memory cell after the erase operation can be controlled at a more precise position.

[0156] Further, according to some embodiments of the present application, another method for operating a semiconductor device is provided, wherein the semiconductor device includes at least one memory string, the memory string includes a plurality of memory cells and is respectively connected to a plurality of word lines, and the plurality of memory cells include a plurality of groups of memory cells, each of the groups of memory cells includes at least one of the first memory cells and at least one of the second memory cells; and

[0157] The first erasure verification operation and the second erasure verification operation include: for different groups of memory cells, using different first erasure verification voltages and / or second erasure verification voltages for different groups, performing the first erasure verification and the second erasure verification on each group of memory cells.

[0158] Specifically, Fig. 9As shown, the memory string 422 includes a first group of memory cells 421-g1 and a second group of memory cells 421-g2, and these memory cells are respectively connected to a plurality of word lines, the plurality of word lines include a first group of word lines 429-g1 and a second group of word lines 429-g2, and each group of memory cells 421-g1 and 421-g2 includes at least one first memory cell 421-1 and at least one second memory cell 421-2. Referring again to FIG. 7, the first erase verification voltage and the second erase verification voltage include a first erase verification voltage Vver1 and a second erase verification voltage Vver2. In some embodiments, the verification voltage of the first group of memory cells can be set to include a first first erase verification voltage Vver11 and a first second erase verification voltage Vver12, and the verification voltage of the second group of memory cells can be set to include a second first erase verification voltage Vver21 and a second second erase verification voltage Vver22, that is, different combinations of the first erase verification voltage and / or the second erase verification voltage are used for each group to perform erase verification.

[0159] Through such a setting, different erase verification voltages can be applied to the memory cells according to their positions in the memory string, and the erase operation can be verified more accurately, which reduces unnecessary erase verification misjudgments, and can more finely change the compensation on the gate to achieve more precise control of the erase depth. At the same time, it can avoid the problem of different erase speeds of different word lines, which leads to excessive wear of some memory cells due to excessive erase depth. Furthermore, different groups of word lines can be set with different erase depths, which can more flexibly balance the window between the erase state and the programming state.

[0160] The above has described the operation method of the semiconductor device according to some embodiments disclosed in the present application. Correspondingly, some embodiments of the present application also provide a semiconductor device. The following is a further description of the semiconductor device.

[0161] like Fig.10 And refer to Figure 6a , Figure 6b and Figure 4c As shown, a semiconductor device 400 provided according to some embodiments of the present application includes: a memory array 420, the memory array 420 includes a first memory cell 421-1 and a second memory cell 421-2, a first word line 429-1 and a second word line 429-2 connected to the first memory cell and the second memory cell respectively; and,

[0162] The erasing circuit 4151 can perform a first erasing operation on the first storage unit 421-1 and the second storage unit 421-2 through a first erasing voltage Ver1, and can perform a second erasing operation on the first storage unit 421-1 and the second storage unit 421-2 through a second erasing voltage Ver2. When performing the second erasing operation, a first bias voltage Bias1 can be applied to the first word line and a second bias voltage Bias2 can be applied to the second word line, and the first bias voltage Bias1 is greater than the second bias voltage Bias2.

[0163] The semiconductor device 400 further includes an erasure verification circuit 4152 for performing erasure verification on the first storage unit 421-1 and the second storage unit 421-2 after the first erasure operation, and determining whether the first storage unit passes the erasure verification and whether the second storage unit fails the erasure verification.

[0164] In some embodiments, the memory array 420 includes at least one memory string 422, the memory string 422 is connected to a plurality of word lines 429, and includes at least one of the first memory cells 421-1 and at least one of the second memory cells 421-2, the plurality of word lines include a first group of word lines 429-s1 and a second group of word lines 429-s2, the first group of word lines includes at least one of the first word lines 429-1 connected to the first memory cells, and the second group of word lines includes at least one of the second word lines 429-2 connected to the second memory cells; and the erase circuit 4151 can apply the first bias voltage Bias1 to the first group of word lines 429-s1, and apply the second bias voltage Bias2 to the second group of word lines 429-s2.

[0165] In some embodiments, the second erase voltage Ver2 is higher than the first erase voltage Ver1.

[0166] In some embodiments, the first bias voltage Bias1 is a positive potential, and the second bias voltage Bias2 is a ground potential. Thus, the first bias voltage Bias1 will invalidate the second erasing action, and the second bias voltage Bias2 will validate the second erasing action.

[0167] In some embodiments, the difference between the first bias voltage Bias1 and the second bias voltage Bias2 is N times the potential difference between the first erase voltage Ver1 and the second erase voltage Ver2, where N is a positive integer.

[0168] As mentioned above, such a design can more accurately control the erasing depth of word lines or memory cells at different layers, thereby avoiding the problem that different memory cells have different erasing speeds / depths, but some memory cells are erased too deeply and excessively worn because they have to be erased again during each incremental step pulse erasing operation.

[0169] In some embodiments, the erase verification circuit 4152 includes:

[0170] A first erasure verification circuit 4152a, configured to perform a first erasure verification on the storage unit 421 through a first erasure verification voltage Vver1; and

[0171] A second erasure verification circuit 4152b, configured to perform a second erasure verification on the storage unit 421 through a second erasure verification voltage Vver2, wherein the second erasure verification voltage Vver2 is lower than the first erasure verification voltage Vver1;

[0172] When at least one of the first erasure verification and the second erasure verification fails, the erasure verification circuit 4152 sets the erasure verification as failing the erasure verification; when the second erasure verification passes, the erasure verification circuit 4152 sets the erasure verification as passing the erasure verification.

[0173] In some embodiments, when both the first erase verification and the second erase verification fail, the erase verification circuit 4152 sets the second bias voltage Bias2 to an erase full-effect potential, and the erase full-effect potential includes one of an erase original effect potential and an erase enhancement potential, and the erase enhancement potential is lower than the erase original effect potential.

[0174] In some embodiments, when the first erase verification passes but the second erase verification fails, the erase verification circuit 4152 sets the second bias voltage Bias2 to an erase deactivation potential.

[0175] In some embodiments, when both the first erase verification and the second erase verification fail, the erase verification circuit 4152 sets the second bias voltage Bias2 to the erase full-effect potential; and when the first erase verification passes but the second erase verification fails, the second bias voltage Bias2 is set to the erase reduction potential; wherein the erase reduction potential is greater than the erase full-effect potential and less than the potential of the first bias voltage.

[0176] Through such a setting, no matter how the memory cell threshold potential Pulse N-1 after the N-1th erasing operation is distributed, the memory cell threshold potential of these memory cells after the Nth erasing operation, that is, the black curve Pulse N, can be just lower than the second erasing verification voltage Vver2 and pass the erasure verification without being over-erased.

[0177] In some embodiments, the semiconductor device 400 includes at least one storage string 422, the storage string 422 includes a plurality of storage cells 421 and are respectively connected to a plurality of word lines 429, and the plurality of storage cells 421 include a plurality of groups of storage cells 421-g1 / 421-g2, each of the groups of storage cells 421-g1 / 421-g2 includes at least one of the first storage cells 421-1 and at least one of the second storage cells 421-2; and the first erasure verification circuit 4152a and the second erasure verification circuit 4152b can perform the first erasure verification and the second erasure verification on different groups of storage cells with different first erasure verification voltages Vver1 and / or second erasure verification voltages Vver2 according to the groups, respectively.

[0178] Through such a setting, different erase verification voltages can be applied to the memory cells according to their positions in the memory string, and the erase operation can be verified more accurately, which reduces unnecessary erase verification misjudgments, and can more finely change the compensation on the gate to achieve more precise control of the erase depth. At the same time, it can avoid the problem of different erase speeds of different word lines, which leads to excessive wear of some memory cells due to excessive erase depth. Furthermore, different groups of word lines can be set with different erase depths, which can more flexibly balance the window between the erase state and the programming state.

[0179] In some embodiments, the semiconductor device 400 includes at least one storage string 422, the storage string 422 includes a plurality of storage cells 421 and are respectively connected to a plurality of word lines 429, and the plurality of storage cells 421 include a plurality of groups of storage cells 421-g1 / 421-g2, each of the groups of storage cells 421-g1 / 421-g2 includes at least one of the first storage cells 421-1 and at least one of the second storage cells 421-2; and the erase circuit 4151 can perform the second erase operation on each of the groups of storage cells with different erase reduction potentials and / or erase full-effect potentials according to the groups.

[0180] Through the above arrangement, different bias voltage combinations can be applied to the word lines according to the positions of the memory cells in the memory string, so that the threshold potential of each memory cell after the erase operation can be controlled at a more precise position.

[0181] According to yet another aspect of the present application, Figure 1 As shown, an embodiment of the present application further provides a storage system 110, and the storage system 110 includes: a memory 111, such as the semiconductor device described above; and a controller 112, which controls the operation of the memory.

[0182] Further, according to yet another aspect of the present application, Figure 1 As shown, an embodiment of the present application also provides an electronic device, which includes the above-mentioned storage system provided by some embodiments of the present application. Specifically, the electronic device can be a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device, a mobile power supply, and any other device that can store data.

[0183] Some embodiments of the present application provide an electronic device, which has the same beneficial effects as the above-mentioned storage system and memory or semiconductor device due to the provision of the storage system provided by some embodiments of the present application.

[0184] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0185] The above is a detailed introduction to a semiconductor device and its operation method and storage system provided by some embodiments of the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein by equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application. Therefore, all technical solutions formed by equivalent replacement or equivalent replacement fall within the scope of protection required by the present application, and therefore the scope of protection of the present application shall be based on the scope defined by the claims.

Claims

1. A method for operating a semiconductor device, characterized in that: The semiconductor device comprises a first storage unit and a second storage unit, and a first word line and a second word line connected to the first storage unit and the second storage unit respectively, and the operating method comprises: Performing a first erasing operation on the first memory cell and the second memory cell with a first erasing voltage; and Performing a second erasing operation on the first memory cell and the second memory cell with a second erasing voltage; When performing the second erasing operation, a first bias voltage is applied to the first word line, a second bias voltage is applied to the second word line, and the first bias voltage is greater than the second bias voltage.

2. The method for operating a semiconductor device according to claim 1, wherein: The operation method further includes performing an erasure verification operation on the first storage unit and the second storage unit after the first erasure operation to perform erasure verification, and the first storage unit passes the erasure verification, while the second storage unit fails the erasure verification.

3. The method for operating a semiconductor device according to claim 1, wherein: The semiconductor device comprises at least one memory string, the memory string is connected to a plurality of word lines and comprises at least one of the first memory cells and at least one of the second memory cells, the plurality of word lines comprises a first group of word lines and a second group of word lines, the first group of word lines comprises at least one of the first word lines connected to the first memory cells, and the second group of word lines comprises at least one of the second word lines connected to the second memory cells; And the operating method further includes: applying the first bias voltage to the first group of word lines, and applying the second bias voltage to the second group of word lines.

4. The method for operating a semiconductor device according to claim 1, wherein: The operating method also includes setting the second erase voltage to be higher than the first erase voltage.

5. The method for operating a semiconductor device according to claim 1, wherein: The first bias voltage invalidates the second erasing action, and the second bias voltage validates the second erasing action.

6. The method for operating a semiconductor device according to claim 1, wherein: The operating method further includes setting the first bias voltage to a positive potential and setting the second bias voltage to a ground potential.

7. The method for operating a semiconductor device according to claim 1, wherein: The operating method further includes setting the difference between the first bias voltage and the second bias voltage to N times the potential difference between the first erase voltage and the second erase voltage, where N is a positive integer.

8. The method for operating a semiconductor device according to claim 2, wherein: The erasure verification action includes: A first erasure verification action, performing a first erasure verification with a first erasure verification voltage; and A second erasure verification action, performing a second erasure verification with a second erasure verification voltage, wherein the second erasure verification voltage is lower than the first erasure verification voltage; When at least one of the first erasure verification and the second erasure verification fails, the erasure verification is set to the failed erasure verification; when the second erasure verification passes, the erasure verification is set to the passed erasure verification.

9. The method for operating a semiconductor device according to claim 8, wherein: The operation method also includes: When both the first erase verification and the second erase verification fail, the second bias voltage is set to an erase full effect potential, and the erase full effect potential includes one of an erase original effect potential and an erase enhancement potential, and the erase enhancement potential is lower than the erase original effect potential.

10. The method for operating a semiconductor device according to claim 8, wherein: The operation method also includes: When the first erase verification passes but the second erase verification fails, the second bias voltage is set to an erase deactivation potential, which is lower than the potential of the first bias voltage.

11. The method for operating a semiconductor device according to claim 8, wherein: The operation method also includes: When both the first erase verification and the second erase verification fail, the second bias voltage is set to an erase full-effect potential, and the erase full-effect potential includes one of an erase original-effect potential and an erase enhancement potential; When the first erase verification passes, but the second erase verification fails, setting the second bias voltage to an erase deactivation potential; The erase reduction potential is greater than the erase full effect potential and less than the potential of the first bias voltage.

12. The method for operating a semiconductor device according to claim 8, wherein: The semiconductor device comprises at least one memory string, wherein the memory string comprises a plurality of memory cells and is respectively connected to a plurality of word lines, and the plurality of memory cells comprises a plurality of groups of memory cells, each of the groups of memory cells comprises at least one of the first memory cells and at least one of the second memory cells; and The first erasure verification operation and the second erasure verification operation include: for different groups of memory cells, using different first erasure verification voltages and / or second erasure verification voltages for different groups, performing the first erasure verification and the second erasure verification on each group of memory cells.

13. The method for operating a semiconductor device according to claim 11, characterized in that: The semiconductor device comprises at least one memory string, wherein the memory string comprises a plurality of memory cells and is respectively connected to a plurality of word lines, and the plurality of memory cells comprises a plurality of groups of memory cells, each of the groups of memory cells comprises at least one of the first memory cells and at least one of the second memory cells; and The operating method further includes: performing the second erasing operation on each of the groups of memory cells using different erase-deactivation potentials and / or erase-full-activation potentials for different groups of memory cells.

14. A semiconductor device, characterized in that: The semiconductor device comprises: A memory array, the memory array comprising a first memory cell and a second memory cell, a first word line and a second word line connected to the first memory cell and the second memory cell respectively; and The erasing circuit can perform a first erasing operation on the first storage unit and the second storage unit through a first erasing voltage, and perform a second erasing operation on the first storage unit and the second storage unit through a second erasing voltage. When performing the second erasing operation, a first bias voltage can be applied to the first word line and a second bias voltage can be applied to the second word line, and the first bias voltage is greater than the second bias voltage.

15. The semiconductor device according to claim 14, characterized in that The semiconductor device also includes an erasure verification circuit for performing erasure verification on the first storage unit and the second storage unit after the first erasure action, and determining that the first storage unit passes the erasure verification and the second storage unit fails the erasure verification.

16. The semiconductor device according to claim 14, characterized in that The memory comprises at least one memory string, the memory string is connected to a plurality of word lines and comprises at least one of the first memory cells and at least one of the second memory cells, the plurality of word lines comprises a first group of word lines and a second group of word lines, the first group of word lines comprises at least one of the first word lines connected to the first memory cells, and the second group of word lines comprises at least one of the second word lines connected to the second memory cells; And the erase circuit may apply the first bias voltage to the first group of word lines, and apply the second bias voltage to the second group of word lines.

17. The semiconductor device according to claim 14, characterized in that The second erase voltage is higher than the first erase voltage.

18. The semiconductor device according to claim 14, wherein: The first bias voltage invalidates the second erasing action, and the second bias voltage validates the second erasing action.

19. The semiconductor device according to claim 14, characterized in that The first bias voltage is a positive potential, and the second bias voltage is a ground potential.

20. The semiconductor device according to claim 14, wherein: The difference between the first bias voltage and the second bias voltage is N times the potential difference between the first erase voltage and the second erase voltage, where N is a positive integer.

21. The semiconductor device according to claim 15, characterized in that The erase verification circuit comprises: A first erasure verification circuit, configured to perform a first erasure verification on the memory cell by applying a first erasure verification voltage; and A second erasure verification circuit, used for performing a second erasure verification on the storage unit through a second erasure verification voltage, wherein the second erasure verification voltage is lower than the first erasure verification voltage; When at least one of the first erasure verification and the second erasure verification fails, the erasure verification circuit sets the erasure verification as failing the erasure verification; when the second erasure verification passes, the erasure verification circuit sets the erasure verification as passing the erasure verification.

22. The semiconductor device according to claim 21, characterized in that When both the first erase verification and the second erase verification fail, the erase verification circuit sets the second bias voltage to an erase full-effect potential, and the erase full-effect potential includes one of an erase original effect potential and an erase enhancement potential, and the erase enhancement potential is lower than the erase original effect potential.

23. The semiconductor device according to claim 21, characterized in that The erase verification circuit sets the second bias voltage to an erase deactivation potential when the first erase verification passes but the second erase verification fails.

24. The semiconductor device according to claim 21, characterized in that When both the first erase verification and the second erase verification fail, the erase verification circuit sets the second bias voltage to the erase full-effect potential; and when the first erase verification passes but the second erase verification fails, the erase verification circuit sets the second bias voltage to the erase reduction potential; wherein the erase reduction potential is greater than the erase full-effect potential and less than the potential of the first bias voltage.

25. The semiconductor device according to claim 21, characterized in that The semiconductor device includes at least one storage string, the storage string includes a plurality of storage cells and are respectively connected to a plurality of word lines, and the plurality of storage cells include a plurality of groups of storage cells, each of the groups of storage cells includes at least one of the first storage cell and at least one of the second storage cell; and the first erasure verification circuit and the second erasure verification circuit can perform the first erasure verification and the second erasure verification on different groups of storage cells with different first erasure verification voltages and / or second erasure verification voltages for different groups.

26. The semiconductor device according to claim 24, characterized in that The semiconductor device includes at least one memory string, the memory string includes a plurality of memory cells and is respectively connected to a plurality of word lines, and the plurality of memory cells include a plurality of groups of memory cells, each of the groups of memory cells includes at least one of the first memory cells and at least one of the second memory cells; and The erasing circuit may perform the second erasing operation on different groups of memory cells using different erase-deactivation potentials and / or erase-full-activation potentials for different groups of memory cells.

27. A storage system comprising: A memory, a semiconductor device as claimed in any one of claims 14 to 26; as well as, A controller controls the operation of the memory.

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