Mask structure, manufacturing method of mask structure, semiconductor device and manufacturing method of semiconductor device
By using doping and etching technology in the memory process to form a large -sized hole, the structural defects and low yields caused by the small hole size are solved, and the quality of the product is improved.
Patent Information
- Application Number
- CN202410765298.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-06-13
- Publication Date
- 2025-01-28
AI Technical Summary
During the memory process, due to the limitations of the mask structure production method, the holes formed are smaller in size, resulting in structural defects and low product yield.
By forming a stacking structure and light resistance layer, the doped mask layer and etching are performed, and multiple openings are separated from the first and second parts of different doping concentrations. The cavity with a large size is used to form a large -sized pore with different erosion rates.
The size of the holes is improved, the structural defects are reduced, and the product yield is improved.
Smart Images
Figure CN119381249A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a mask structure and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof. Background Art
[0002] Memory is widely used in mobile devices such as mobile phones and tablets due to its advantages of small size, high integration and fast transmission speed. In the memory manufacturing process, it is usually necessary to use a mask structure to form corresponding holes. However, due to the limitations of the manufacturing method of the mask structure, the size of the holes finally made by the mask structure is small, which in turn causes structural defects and low product yield.
[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention
[0004] The present disclosure provides a mask structure and a manufacturing method thereof, a semiconductor device and a manufacturing method thereof, which can reduce structural defects and improve product yield.
[0005] According to one aspect of the present disclosure, a method for manufacturing a mask structure is provided, comprising:
[0006] Forming a stacked structure and a photoresist layer on the stacked structure, wherein the photoresist layer comprises a plurality of spaced photoresist portions, and the photoresist portion comprises a first side wall and a second side wall that are oppositely disposed;
[0007] forming a mask layer on a surface of a structure formed by the stacked structure and the photoresist portion;
[0008] doping the mask layer so that a doping concentration of a first portion of the mask layer located on the first sidewall is different from a doping concentration of a second portion of the mask layer located on the second sidewall;
[0009] Etching the photoresist portion and the mask layer to remove the photoresist portion and form a plurality of openings separated by the first portion and the second portion;
[0010] When etching the photoresist portion and the mask layer, an etching rate of the first portion is different from an etching rate of the second portion.
[0011] In an exemplary embodiment of the present disclosure, the step of doping the mask layer includes:
[0012] The mask layer is ion doped at a preset angle, where the preset angle is an angle between the normal line of the first side wall or the normal line of the second side wall and the ion beam, and the preset angle is 5° to 60°.
[0013] In an exemplary embodiment of the present disclosure, etching the light blocking portion and the mask layer to remove the light blocking portion and form a plurality of openings separated by the first portion and the second portion includes:
[0014] Using a dry etching process to remove the photoresist portion and other portions of the mask layer except the first portion and the second portion;
[0015] The first portion and the second portion are etched using a wet etching process, wherein a wet etching rate of the first portion is different from a wet etching rate of the second portion, so that after the wet etching, the widths of the first portion and the second portion located on both sides of the opening are different.
[0016] In an exemplary embodiment of the present disclosure, etching the light blocking portion and the mask layer to remove the light blocking portion and form a plurality of openings separated by the first portion and the second portion includes:
[0017] Etching the mask layer by a wet etching process, wherein a wet etching rate of the first portion is different from a wet etching rate of the second portion, so that the widths of the first portion remaining after the wet etching are different from the widths of the second portion remaining after the wet etching;
[0018] A dry etching process is used to remove the photoresist portion and other portions of the mask layer except the first portion and the second portion after the wet etching.
[0019] In an exemplary embodiment of the present disclosure, the material of the mask layer is silicon oxide, and the etching solution of the wet etching is an acidic solution;
[0020] When removing the other parts of the mask layer except the first part and the second part, the etching gas used is a fluorine-containing gas;
[0021] When removing the photoresist portion, the etching gas used is oxygen.
[0022] In an exemplary embodiment of the present disclosure, the ions doped in the mask layer include one or more of phosphorus ions, boron ions, arsenic ions or gallium ions.
[0023] In an exemplary embodiment of the present disclosure, the doping concentration of the first portion is 0.
[0024] According to one aspect of the present disclosure, there is provided a method for manufacturing a semiconductor device, comprising:
[0025] Forming a stacked film layer on a substrate, wherein the stacked film layer includes a sacrificial layer and a supporting layer stacked in sequence along a vertical direction;
[0026] A first mask layer is formed on the stacked film layer by using any one of the above-mentioned methods for manufacturing a mask structure, and the first portion and the second portion of the first mask layer located on both sides of the opening are defined as a first mask structure and a second mask structure, respectively. The first mask structure and the second mask structure both extend along a first direction and are spaced apart along a second direction, and the width of the second mask structure is greater than the width of the first mask structure; and the second direction intersects with the first direction;
[0027] A second mask layer is formed on a side of the first mask layer away from the substrate by using any of the above-mentioned methods for manufacturing a mask structure, and the first portion and the second portion of the second mask layer located on both sides of the opening are defined as a third mask structure and a fourth mask structure, respectively. The third mask structure and the fourth mask structure both extend along the second direction and are spaced apart along the first direction, and the width of the fourth mask structure is greater than the width of the third mask structure.
[0028] Using the first mask layer and the second mask layer as masks, etching the support layer and the sacrificial layer to form a plurality of capacitor holes distributed at intervals;
[0029] removing the first mask layer and the second mask layer, and forming a lower electrode layer in the capacitor hole;
[0030] Removing a portion of the support layer that is opposite to an overlapping region of the second mask structure and the fourth mask structure to form a through hole exposing the sacrificial layer;
[0031] The sacrificial layer is removed by a wet etching process.
[0032] In an exemplary embodiment of the present disclosure, the step of forming a lower electrode layer in the capacitor hole includes:
[0033] forming a conductive material layer on a side of the support layer away from the substrate, wherein the conductive material layer fills the capacitor hole;
[0034] The conductive material layer is planarized to remove the conductive material layer on the surface of the support layer, and the top surface of the conductive material layer in the capacitor hole is flush with the top surface of the support layer, and the remaining conductive material layer in the capacitor hole is defined as a lower electrode layer.
[0035] In an exemplary embodiment of the present disclosure, after removing the sacrificial layer, the method for manufacturing the semiconductor device further includes:
[0036] forming a capacitor dielectric layer conformally covering the surface of the structure formed by the substrate, the lower electrode layer and the support layer;
[0037] An upper electrode layer is formed on the surface of the capacitor dielectric layer.
[0038] In an exemplary embodiment of the present disclosure, the substrate includes an insulating layer, a bottom supporting layer and a plurality of conductive parts distributed at intervals, the insulating layer fills the gaps between the conductive parts; the bottom supporting layer covers the surfaces of the insulating layer and the conductive parts, and when the supporting layer and the sacrificial layer are etched using the first mask layer and the second mask layer as masks, the bottom supporting layer is etched at the same time, so that the capacitor holes simultaneously penetrate the bottom supporting layer and expose the conductive parts; the lower electrode layer is in contact and connected with the conductive parts.
[0039] According to one aspect of the present disclosure, a semiconductor device is provided, wherein the semiconductor device is manufactured by any one of the above-mentioned methods for manufacturing a semiconductor device.
[0040] According to one aspect of the present disclosure, a mask structure is provided, wherein the mask structure is manufactured using any of the above-described methods for manufacturing a mask structure.
[0041] The mask structure and the manufacturing method thereof disclosed in the present invention dope the first part located on the first side wall of the photoresist portion and the second part located on the second side wall with different concentrations, so that the first part and the second part exhibit different etching rates during the etching process, and the openings finally formed exhibit different spacing sizes; at the same time, under the same etching time, the mask layer of the part with a relatively large etching rate consumes more and its width is smaller, leaving a larger space for the formation of the opening, so that the size of the opening finally formed is also increased accordingly; in the subsequent process of forming a hole using the mask structure, the size of the hole formed with the opening as the mask pattern will also increase accordingly, which can reduce the structural defects caused by the small hole size.
[0042] The semiconductor device and the manufacturing method thereof disclosed in the present invention have relatively large widths of the second mask structure and the fourth mask structure, and the second mask structure and the fourth mask structure intersect, so that the area of the region where the second mask structure and the fourth mask structure intersect is relatively large compared with the case where other mask structures intersect; after the patterns of the first mask layer and the second mask layer are transferred to the stacked film layer, the area of the portion of the support layer that is opposite to the region where the second mask structure and the fourth mask structure intersect is relatively large, so that the area of the sacrificial layer exposed after the portion of the support layer that is opposite to the region where the second mask structure and the fourth mask structure intersect is removed is relatively large; when the sacrificial layer is subsequently wet-etched, the process space (i.e., the hole) of the wet etching is relatively large, the liquid tension is small, the bubbles are small, and the liquid in the wet etching can fully enter the sacrificial layer, which helps to reduce etching residues, reduce defects, and improve product yield.
[0043] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS
[0044] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.
[0045] Figure 1 Flow chart of a method for manufacturing a mask structure in an embodiment of the present disclosure.
[0046] Figure 2 Schematic diagram of the stacked structure and the photoresist layer in the embodiment of the present disclosure.
[0047] Figure 3 Schematic diagram of the mask layer in the example of the present disclosure.
[0048] Figure 4 Schematic diagram of ion implantation in an embodiment of the present disclosure.
[0049] Figure 5 It is a schematic diagram of the structure after completing step S140 in the embodiment of the present disclosure.
[0050] Figure 6 It is a schematic diagram of the structure after completing step S210 in the embodiment of the present disclosure.
[0051] Figure 7 It is a schematic diagram of the structure after completing step S310 in the embodiment of the present disclosure.
[0052] Figure 8The flowchart is a method for manufacturing a semiconductor device in an embodiment of the present disclosure.
[0053] Fig. 9 Schematic diagram of a first mask structure, a second mask structure, a third mask structure and a fourth mask structure in an embodiment of the present disclosure.
[0054] Fig.10 In the embodiment of the present disclosure, Fig. 9 Cross-section view cut by the dashed line.
[0055] Fig.11 FIG. 1 is a top view of the capacitor hole and the support layer in the embodiment of the present disclosure.
[0056] Fig.12 In the embodiment of the present disclosure, Fig.11 Cross-section view cut by the dashed line.
[0057] Fig.13 It is a schematic diagram of the structure after completing step S450 in the embodiment of the present disclosure.
[0058] Fig.14 It is a top view after completing step S450 in the embodiment of the present disclosure.
[0059] Fig.15 It is a schematic diagram of the structure after completing step S510 in the embodiment of the present disclosure.
[0060] Fig.16 It is a top view after completing step S510 in the embodiment of the present disclosure.
[0061] Fig.17 FIG. 1 is a top view of a developing area in an embodiment of the present disclosure.
[0062] Fig.18 In the embodiment of the present disclosure, Fig.17 Cross-section view cut by the dashed line.
[0063] Fig.19 Schematic diagram of a developing area in another embodiment of the present disclosure.
[0064] Fig. 20 It is a schematic diagram of the structure after completing step S460 in the embodiment of the present disclosure.
[0065] Fig.21 It is a schematic diagram of the structure after completing step S470 in the embodiment of the present disclosure.
[0066] Fig. 22 It is a schematic diagram of the structure after completing step S610 in the embodiment of the present disclosure.
[0067] Fig.23 It is a schematic diagram of the structure after completing step S620 in the embodiment of the present disclosure.
[0068] Description of reference numerals:
[0069] 1. stacked structure; 11. polysilicon layer; 12. silicon oxide layer; 13. spin-coated organic carbon layer; 14. anti-reflection layer; 2. photoresist layer; 21. photoresist portion; 211. first side wall; 212. second side wall; 3. mask layer; 310. opening; 31. first portion; 32. second portion; 100. substrate; 101. base; 102. insulating layer; 103. conductive portion; 104. bottom support layer; 200. stacked film layer; 201. sacrificial layer; 202 , supporting layer; 2001, through hole; 210, capacitor hole; 300, first mask layer; 301, first mask structure; 302, second mask structure; 400, second mask layer; 401, third mask structure; 402, fourth mask structure; 500, lower electrode layer; 510, conductive material layer; 600, photoresist layer; 601, developing area; 700, capacitor dielectric layer; 800, upper electrode layer; B, intersecting area; x, first direction; y, second direction. DETAILED DESCRIPTION
[0070] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in a variety of forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that the present disclosure will be comprehensive and complete and fully convey the concepts of the example embodiments to those skilled in the art. The same reference numerals in the figures represent the same or similar structures, and thus their detailed description will be omitted. In addition, the drawings are only schematic illustrations of the present disclosure and are not necessarily drawn to scale.
[0071] Although relative terms such as "upper" and "lower" are used in this specification to describe the relative relationship of one component of the illustration to another component, these terms are used in this specification only for convenience, such as according to the orientation of the examples described in the drawings. It is understood that if the device of the illustration is turned upside down, the component described as "upper" will become the component "lower". When a structure is "on" other structures, it may mean that the structure is formed integrally on the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure through another structure.
[0072] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express an open-ended inclusive meaning and mean that additional elements / components / etc. may exist in addition to the listed elements / components / etc.; the terms "first", "second", "third" and "fourth" etc. are used merely as labels and are not intended to limit the quantity of their objects.
[0073] During the semiconductor device manufacturing process, a mask structure is usually used. However, the size of the holes or openings in the mask structure formed by the conventional mask structure manufacturing method is relatively small, or the spacing between the openings is relatively small, so that in the subsequent wet process, due to the small process space (holes or openings), it is easy to be restricted by the liquid surface tension or bubbles, resulting in structural defects such as incomplete etching.
[0074] Based on this, the present disclosure provides a method for manufacturing a mask structure, such as Figure 1 As shown, the method for manufacturing the mask structure of the present disclosure may include steps S110 to S140, wherein:
[0075] Step S110, forming a stacked structure and a photoresist layer on the stacked structure, wherein the photoresist layer includes a plurality of spaced photoresist portions, and the photoresist portion includes a first side wall and a second side wall that are oppositely distributed;
[0076] Step S120, forming a mask layer on the surface of the structure formed by the stacked structure and the photoresist portion;
[0077] Step S130, doping the mask layer so that a doping concentration of a first portion of the mask layer located on the first sidewall is different from a doping concentration of a second portion of the mask layer located on the second sidewall;
[0078] Step S140, etching the photoresist portion and the mask layer to remove the photoresist portion and form a plurality of openings separated by the first portion and the second portion; wherein, when etching the photoresist portion and the mask layer, an etching rate of the first portion is different from an etching rate of the second portion.
[0079] The manufacturing method of the mask structure disclosed in the present invention performs doping of different concentrations on the first part located on the first side wall of the photoresist portion and the second part located on the second side wall, so that the first part and the second part exhibit different etching rates during the etching process, and the openings finally formed exhibit different spacing sizes; at the same time, under the same etching time, the mask layer of the part with a relatively large etching rate consumes more and its width is smaller, leaving a larger space for the formation of the opening, so that the size of the opening finally formed is also increased accordingly; in the subsequent process of forming a hole using the mask structure, the size of the hole formed with the opening as the mask pattern will also increase accordingly, which can reduce the structural defects caused by the small hole size.
[0080] The steps and specific details of the method for making the mask structure disclosed in the present invention are described in detail below:
[0081] like Figure 1As shown, in step S110, a stacked structure and a photoresist layer located on the stacked structure are formed, the photoresist layer includes a plurality of spaced-apart photoresist portions, and the photoresist portion includes a first side wall and a second side wall that are oppositely distributed.
[0082] like Figure 2 As shown, the stacked structure 1 may include multiple film layers, for example, it may include at least two film layers of a polysilicon layer 11, a silicon oxide layer 12, a spin-on organic carbon layer 13 (Spin On Carbon, referred to as SOC) and an anti-reflective layer 14 (Dielectric Anti-Reflective Coating, referred to as DARC). A photoresist layer 2 may be formed on the surface of the stacked structure 1 by spin coating or other methods, and the material of the photoresist layer 2 may be a positive photoresist or a negative photoresist, which is not specifically limited here. The photoresist layer 2 may be exposed using a mask, and the pattern of the mask may match the pattern required for the photoresist portion 21. Subsequently, the exposed photoresist layer 2 may be developed to form a plurality of spaced photoresist portions 21. In an exemplary embodiment of the present disclosure, the photoresist portion 21 may be in the shape of a strip, and a plurality of photoresist portions 21 may be spaced apart and distributed in a direction perpendicular to the extension direction of the photoresist portion 21. The light blocking portion 21 may have a first side wall 211 and a second side wall 212 that are opposite to each other. The surfaces of the first side wall 211 and the second side wall 212 may be planes, and the first side wall 211 and the second side wall 212 may be parallel to each other.
[0083] like Figure 1 As shown, in step S120 , a mask layer 3 is formed on the surface of the structure formed by the stacked structure 1 and the photoresist portion 21 .
[0084] In an exemplary embodiment of the present disclosure, Figure 3 As shown, the material of the mask layer 3 may be silicon oxide or polysilicon. The mask layer 3 that conformally covers the surface of the structure formed by the stacked structure 1 and each photoresist portion 21 may be formed by atomic layer deposition, physical vapor deposition, or chemical vapor deposition. Of course, the mask layer 3 may also be formed by other methods, and the method for forming the mask layer 3 is not particularly limited here.
[0085] like Figure 1 As shown, in step S130 , the mask layer 3 is doped so that the doping concentration of the first portion 31 of the mask layer 3 located on the first sidewall 211 is different from the doping concentration of the second portion 32 of the mask layer 3 located on the second sidewall 212 .
[0086] like Figure 4As shown, the mask layer 3 may be ion doped by an ion implantation process. The doped ions may be elements in the III main group or the V main group in the periodic table, for example, the ions doped in the mask layer 3 may include one or more of phosphorus ions, boron ions, arsenic ions or gallium ions.
[0087] For example, the first portion 31 located on the first side wall 211 of the photoresist portion 21 can be ion-doped at a preset angle on the side of the first side wall 211 close to the photoresist portion 21 through an ion implantation process, and the preset angle can be the angle between the normal of the first side wall 211 and the ion beam; after ion doping, the ion doping concentration of the first portion 31 on the first side wall 211 is greater than the ion doping concentration of the second portion 32 on the second side wall 212. For example, the doping concentration of the second portion 32 on the second side wall 212 can be 0. It should be noted that the ions generated by the ion source during the ion implantation process are accelerated to a higher energy by an accelerator, and the energy range can be 10keV to 900keV. At the same time, during the ion implantation process, the machine can drive the photoresist portion 21 to rotate back and forth, and its rotation angle can be between 1 degree and 89 degrees.
[0088] Alternatively, the second portion 32 located on the second side wall 212 of the photoresist portion 21 may be ion doped at a preset angle on the side of the second side wall 212 close to the photoresist portion 21 through an ion implantation process, and the preset angle may be the angle between the normal of the second side wall 212 and the ion beam; after ion doping, the ion doping concentration of the second portion 32 on the second side wall 212 is greater than the ion doping concentration of the first portion 31 on the first side wall 211. For example, the doping concentration of the first portion 31 on the first side wall 211 may be 0. It should be noted that, during the ion implantation process, in order to facilitate the process, the mask layer 3 located on the top of the photoresist portion 21 may be ion implanted at the same time, and / or, the mask layer 3 located between two adjacent photoresist portions 21 may also be ion implanted; that is, in order to facilitate the process, ion implantation may also be performed on other portions of the mask layer 3 except the first portion 31 and the second portion 32 at the same time.
[0089] In some embodiments of the present disclosure, the preset angle may be 5° to 60°. For example, it may be 5°, 10°, 20°, 30°, 40°, 50° or 60°. Of course, it may also be other angles, which are not listed here one by one.
[0090] like Figure 1As shown, in step S140, the photoresist portion 21 and the mask layer 3 are etched to remove the photoresist portion 21 and form a plurality of openings 310 separated by the first portion 31 and the second portion 32; wherein, when etching the photoresist portion 21 and the mask layer 3, the etching rate of the first portion 31 is different from the etching rate of the second portion 32.
[0091] In the present disclosure, the photoresist portion 21 and the other portions of the mask layer 3 except the first portion 31 and the second portion 32 can be removed by combining dry etching and wet etching, and the width of the first portion 31 and the width of the second portion 32 are differentiated. It should be noted that after removing each photoresist portion 21, each first portion 31 and each second portion 32 originally located on both sides of each photoresist portion 21 are arranged alternately, and two adjacent first portions 31 and second portions 32 surround the above-mentioned opening 310. In the embodiment of the present disclosure, the structure after completing step S140 is as follows: Figure 5 shown.
[0092] In an exemplary embodiment of the present disclosure, etching the photoresist portion 21 and the mask layer 3 to remove the photoresist portion 21 and form a plurality of openings separated by the first portion 31 and the second portion 32 (i.e., step S140) includes steps S210 and S220, wherein:
[0093] Step S210 , removing the photoresist portion 21 and other portions of the mask layer 3 except the first portion 31 and the second portion 32 by a dry etching process.
[0094] The mask layer 3 can be etched by dry etching. Since dry etching is anisotropic etching, the other parts of the mask layer 3 except the first part 31 and the second part 32 (i.e., the mask layer 3 located at the top of the photoresist portion 21 and between two adjacent photoresist portions 21) can be removed. In this process, even if the tops of the first part 31 and the second part 32 are slightly damaged, the overall profile is not greatly affected, so the first part 31 and the second part 32 located on both sides of the photoresist portion 21 will be retained. Taking the material of the mask layer 3 as silicon oxide as an example, the etching gas used in the process of dry etching the mask layer 3 can be a fluorine-containing gas.
[0095] After etching the other parts of the mask layer 3 except the first part 31 and the second part 32, the etching gas can be switched to perform dry etching on the photoresist portion 21. The etching rate of the switched etching gas on the photoresist portion 21 is much greater than the etching rate on the first part 31 and the second part 32, that is, the first part 31 and the second part 32 are hardly damaged during the etching of the photoresist portion 21; for example, when dry etching the photoresist portion 21, the etching selectivity ratio of the photoresist portion 21 to the first part 31 and the second part 32 is greater than 100:1. Taking the material of the photoresist portion 21 as photoresist as an example, the etching gas can be switched to oxygen. That is, the photoresist portion 21 can be dry etched by oxygen, and at this time, the oxygen can burn the photoresist portion 21. In the embodiment of the present disclosure, the structure after completing step S210 is as follows: Figure 6 shown.
[0096] Step S220, etching the first part 31 and the second part 32 using a wet etching process, wherein the wet etching rate of the first part 31 is different from the wet etching rate of the second part 32, so that the widths of the first part 31 and the second part 32 located on both sides of the opening 310 are different after the wet etching.
[0097] After removing the photoresist portion 21, the remaining mask layer 3 may be etched by a wet etching process. For example, when the material of the mask layer 3 is silicon oxide, the mask layer 3 may be etched by an acidic solution, for example, the acidic solution may be diluted hydrofluoric acid (DHF) (the dilution ratio may be 100:1 to 2000:1) or a mixture of diluted sulfuric acid, hydrofluoric acid and hydrogen peroxide. During the wet etching process, since ion implantation destroys the covalent bonds in the mask layer 3, the etching rate of the mask layer 3 with a larger ion doping concentration is accelerated, and the etching rate of the mask layer 3 with a smaller ion doping concentration or without ion doping is relatively slow. Therefore, after wet etching, the first part 31 and the second part 32 show different etching rates, and the openings 310 finally formed have different spacing sizes. At the same time, under the same etching time, the mask layer 3 with a relatively larger etching rate is consumed more and its width is smaller, leaving a larger space for the formation of the opening 310, so that the size of the opening 310 finally formed is also increased accordingly, that is, compared with the prior art, at the same process node, the size of the opening 310 in the present application is larger than the size of the opening 310 in the prior art.
[0098] In an exemplary embodiment of the present disclosure, etching the photoresist portion 21 and the mask layer 3 to remove the photoresist portion 21 and form a plurality of openings separated by the first portion 31 and the second portion 32 (ie, step S140) may include steps S310 and S320, wherein:
[0099] Step S310, etching the mask layer 3 using a wet etching process, wherein the wet etching rate of the first portion 31 is different from the wet etching rate of the second portion 32, so that the widths of the remaining first portion 31 and the remaining second portion 32 after the wet etching are different.
[0100] The mask layer 3 can be first etched by a wet etching process. During this process, since ion implantation destroys the covalent bonds in the mask layer 3, the first part 31 and the second part 32 exhibit different etching rates. Under the same etching time, the mask layer 3 of the part with a relatively large etching rate consumes more and has a smaller width, so that the width of the remaining first part 31 after wet etching is different from the width of the remaining second part 32 (that is, the width of the first part 31 is different from the width of the second part 32). It should be noted that other details in step S310 (for example, the material of the mask layer 3, the wet etching solution, etc.) are similar to those of step S220, and therefore, they are not repeated here. In the embodiment of the present disclosure, the structure after completing step S310 is as follows: Figure 7 shown.
[0101] Step S320 , using a dry etching process to remove the photoresist portion 21 and other portions of the mask layer 3 except the first portion 31 and the second portion 32 after the wet etching.
[0102] After wet etching, the mask layer 3 located at the top of the photoresist portion 21 and between two adjacent photoresist portions 21 (i.e., the other portions of the mask layer 3 except the first portion 31 and the second portion 32) can be removed by dry etching. Taking the material of the mask layer 3 as silicon oxide as an example, the etching gas used in the process of dry etching the mask layer 3 can be a fluorine-containing gas.
[0103] After etching the mask layer 3 located at the top of the photoresist portion 21 and between two adjacent photoresist portions 21, the etching gas can be switched to dry-etch the photoresist portion 21. Taking the material of the photoresist portion 21 as an example, the etching gas can be switched to oxygen. That is, the photoresist portion 21 can be dry-etched by oxygen to remove the photoresist portion 21. It should be noted that other details in step S320 (for example, the etching selectivity of the photoresist portion 21 to the first portion 31 and the second portion 32, etc.) are similar to step S210, so they are not repeated here.
[0104] The present disclosure also provides a method for manufacturing a semiconductor device. The method for manufacturing a semiconductor device may include steps S410 to S470, wherein:
[0105] Step S410, forming a stacked film layer 200 on a substrate 100, wherein the stacked film layer 200 includes a sacrificial layer 201 and a supporting layer 202 stacked in sequence along a vertical direction;
[0106] Step S420, forming a first mask layer 300 on the stacked film layer 200 by using the method for manufacturing a mask structure in any of the above embodiments, defining the first portion 31 and the second portion 32 located on both sides of the opening 310 in the first mask layer 300 as a first mask structure 301 and a second mask structure 302, respectively, the first mask structure 301 and the second mask structure 302 both extend along a first direction x, and are spaced apart along a second direction y, the width of the second mask structure 302 is greater than the width of the first mask structure 301; the second direction y intersects with the first direction x;
[0107] Step S430, forming a second mask layer 400 on a side of the first mask layer 300 away from the substrate 100 by using the method for manufacturing the mask structure in any of the above embodiments, defining the first portion 31 and the second portion 32 located on both sides of the opening 310 in the second mask layer 400 as a third mask structure 401 and a fourth mask structure 402, respectively, wherein the third mask structure 401 and the fourth mask structure 402 both extend along the second direction y and are spaced apart along the first direction x, and the width of the fourth mask structure 402 is greater than the width of the third mask structure 401;
[0108] Step S440, etching the support layer 202 and the sacrificial layer 201 using the first mask layer 300 and the second mask layer 400 as masks to form a plurality of capacitor holes 210 distributed at intervals;
[0109] Step S450, removing the first mask layer 300 and the second mask layer 400, and forming a lower electrode layer 500 in the capacitor hole 210;
[0110] Step S460, removing a portion of the support layer 202 that is opposite to the overlapping region of the second mask structure 302 and the fourth mask structure 402 to expose the through hole 2001 of the sacrificial layer 201;
[0111] Step S470: removing the sacrificial layer 201 by a wet etching process.
[0112] In the method for manufacturing a semiconductor device disclosed in the present invention, since the widths of the second mask structure 302 and the fourth mask structure 402 are relatively large, and the second mask structure 302 and the fourth mask structure 402 intersect, compared with the case where other mask structures intersect, the area of the region A where the second mask structure 302 and the fourth mask structure 402 intersect is relatively large; after the patterns of the first mask layer 300 and the second mask layer 400 are transferred to the stacked film layer 200, the support layer 202 that is connected to the second mask structure 302 and the fourth mask structure 402 is formed. The area of the portion directly opposite to region A where the structure 402 intersects is relatively large, so that the area of the sacrificial layer 201 exposed after removing the portion of the support layer 202 directly opposite to the overlapping area of the second mask structure 302 and the fourth mask structure 402 is relatively large; when the sacrificial layer 201 is subsequently wet-etched, the process space (i.e., the hole) of the wet etching is relatively large, the liquid tension is small, and the bubbles are small. The liquid in the wet etching can fully enter the sacrificial layer 201, which helps to reduce etching residues, reduce defects, and improve product yield.
[0113] The following is a detailed description of the steps and specific details of the method for manufacturing a semiconductor device disclosed in the present invention:
[0114] like Figure 8 As shown, in step S410 , a stacked film layer 200 is formed on a substrate 100 , and the stacked film layer 200 includes a sacrificial layer 201 and a supporting layer 202 which are sequentially stacked in a vertical direction.
[0115] In an exemplary embodiment of the present disclosure, Fig. 9 As shown, the substrate 100 may include a base 101. The base 101 may be a flat plate structure, which may be rectangular, circular, elliptical, polygonal or irregular in shape. Its material may be silicon or other semiconductor materials. The shape and material of the base 101 are not particularly limited herein.
[0116] In some embodiments of the present disclosure, please continue to refer to Fig. 9As shown, the substrate 100 may also include an insulating layer 102, a bottom support layer 104 and a plurality of conductive portions 103 distributed at intervals, and the insulating layer 102 may fill the gaps between the conductive portions 103. For example, the material of the insulating layer 102 may be an insulating material, for example, its material may be silicon oxide, silicon nitride, or silicon dioxide formed by chemical vapor deposition using electronic grade tetraethyl orthosilicate (TEOS). In the present disclosure, the insulating layer 102 may be formed on the surface of the substrate 101 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition, and a plurality of vias arranged at intervals may be formed in the insulating layer 102 by a hole-opening process, and then a conductive material may be deposited in each via by chemical vapor deposition, physical vapor deposition, or atomic layer deposition to form a conductive portion 103 in each via. Of course, the conductive portion 103 may also be formed by other methods, which are not specifically limited here. The material of the conductive portion 103 may be tungsten, titanium, titanium nitride, or the like, and may also be doped polysilicon. The bottom supporting layer 104 may cover the surfaces of the insulating layer 102 and the conductive portion 103 . The bottom supporting layer 104 may be made of an insulating material, such as silicon nitride, silicon carbide, or silicon boron nitride.
[0117] Please continue to see Fig. 9 As shown, a stacked film layer 200 may be formed on the surface of the substrate 100 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. For example, a sacrificial layer 201 may be formed on the surface of the substrate 100, and then a support layer 202 may be formed on the surface of the sacrificial layer 201. The material of the sacrificial layer 201 may be silicon oxide, tetraethyl orthosilicate, etc.; the material of the support layer 202 may be silicon nitride, silicon carbide or silicon boron nitride, etc.
[0118] like Figure 8 As shown, in step S420, a first mask layer 300 is formed on the stacked film layer 200 using the method for manufacturing a mask structure in any of the above embodiments, and the first portion 31 and the second portion 32 located on both sides of the opening 310 in the first mask layer 300 are respectively defined as a first mask structure 301 and a second mask structure 302, wherein the first mask structure 301 and the second mask structure 302 both extend along a first direction x and are spaced apart along a second direction y, and the width of the second mask structure 302 is greater than the width of the first mask structure 301. For example, the width of the second mask structure 302 may be 1.05 to 1.5 times the width of the first mask structure 301. For example, the width of the second mask structure 302 may be 1.05, 1.1, 1.2, 1.3, 1.4 or 1.5 times the width of the first mask structure 301.
[0119] For example, the stacked structure 1 in the method for manufacturing the mask structure in any of the above embodiments can be formed on the surface of the stacked film layer 200. Fig. 9 and Fig.10 As shown, the stacked structure 1 may include a polysilicon layer 11, a silicon oxide layer 12, and a spin-coated organic carbon layer 13 sequentially formed on the stacked film layer 200. The first portion 31 and the second portion 32 finally formed in the method for making the mask structure in any of the above embodiments may be formed on the surface of the spin-coated organic carbon layer 13. For the sake of distinction, the portion with a relatively small width in the first portion 31 and the second portion 32 finally formed in the method for making the mask structure in any of the above embodiments may be used as the first mask structure 301, and the portion with a relatively large width may be used as the second mask structure 302. Please continue to refer to Fig. 9 As shown, the first mask structure 301 and the second mask structure 302 may both be strip-shaped, and the first mask structure 301 and the second mask structure 302 may both extend along the first direction x and be spaced apart along the second direction y.
[0120] The second direction y may intersect with the first direction x. For example, the second direction y and the first direction x may be perpendicular to each other. It should be noted that perpendicularity may be absolutely perpendicular or approximately perpendicular. Deviations are inevitable during the manufacturing process. In the present disclosure, the angle deviation may be caused by manufacturing process limitations, so that the angle between the second direction y and the first direction x has a certain deviation. As long as the angle deviation between the second direction y and the first direction x is within a preset range, the second direction y can be considered perpendicular to the first direction x. For example, the preset range may be 10°, that is, when the angle between the second direction y and the first direction x is greater than or equal to 80° and less than or equal to 100°, the second direction y can be considered perpendicular to the first direction x.
[0121] It should be noted that the structure composed of the polysilicon layer 11 , the silicon oxide layer 12 , the spin-on organic carbon layer 13 , the first mask structure 301 and the second mask structure 302 may be used as the first mask layer 300 .
[0122] like Figure 8As shown, in step S430, a second mask layer 400 is formed on a side of the first mask layer 300 away from the substrate 100 by using the method for manufacturing a mask structure in any of the above embodiments, and the first portion 31 and the second portion 32 located on both sides of the opening 310 in the second mask layer 400 are defined as a third mask structure 401 and a fourth mask structure 402, respectively. The third mask structure 401 and the fourth mask structure 402 both extend along the second direction y and are spaced apart along the first direction x, and the width of the fourth mask structure 402 is greater than the width of the third mask structure 401. For example, the width of the fourth mask structure 402 may be 1.05 to 1.5 times the width of the third mask structure 401, for example, the width of the fourth mask structure 402 may be 1.05, 1.1, 1.2, 1.3, 1.4 or 1.5 times the width of the third mask structure 401.
[0123] Please continue to see Fig.10 As shown, the stacked structure 1 in the method for manufacturing the mask structure in any of the above embodiments may be formed on the surface of the first mask layer 300. Here, the stacked structure 1 may include a spin-coated organic carbon layer 13 and an anti-reflection layer 14 sequentially formed on the first mask layer 300. The first portion 31 and the second portion 32 finally formed in the method for manufacturing the mask structure in any of the above embodiments may be formed on the surface of the anti-reflection layer 14. For ease of distinction, the portion with a relatively small width in the first portion 31 and the second portion 32 finally formed in the method for manufacturing the mask structure in any of the above embodiments may be used as the third mask structure 401, and the portion with a relatively large width may be used as the fourth mask structure 402. Please continue to refer to Fig. 9 As shown, the third mask structure 401 and the fourth mask structure 402 can both be strip-shaped, and the third mask structure 401 and the fourth mask structure 402 can both extend along the second direction y and be spaced apart along the first direction x. That is, the orthographic projection of the third mask structure 401 on the substrate 100 intersects with the orthographic projections of the first mask structure 301 and the second mask structure 302 on the substrate 100; at the same time, the orthographic projection of the fourth mask structure 402 on the substrate 100 also intersects with the orthographic projections of the first mask structure 301 and the second mask structure 302 on the substrate 100.
[0124] like Figure 8 As shown, in step S440, the support layer 202 and the sacrificial layer 201 are etched using the first mask layer 300 and the second mask layer 400 as masks to form a plurality of capacitor holes 210 distributed at intervals.
[0125] The capacitor hole 210 can be formed by dry etching. In this process, since the orthographic projection of the third mask structure 401 on the substrate 100 intersects with the orthographic projections of the first mask structure 301 and the second mask structure 302 on the substrate 100; at the same time, the orthographic projection of the fourth mask structure 402 on the substrate 100 also intersects with the orthographic projections of the first mask structure 301 and the second mask structure 302 on the substrate 100, the first mask structure 301, the second mask structure 302, the third mask structure 401 and the fourth mask structure 402 can define a mesh structure. When the pattern of the mesh structure is transferred to the stacked film layer 200, a plurality of spaced capacitor holes 210 can be divided in the stacked film layer 200. Fig.11 and Fig.12 As shown, the capacitor hole 210 can penetrate the supporting layer 202 and the sacrificial layer 201, and when the substrate 100 of the present disclosure includes a conductive portion 103 and a bottom supporting layer 104, when the supporting layer 202 and the sacrificial layer 201 are etched using the first mask layer 300 and the second mask layer 400 as masks, the bottom supporting layer 104 can also be etched at the same time, so that the capacitor hole 210 simultaneously penetrates the bottom supporting layer 104 and exposes the conductive portion 103.
[0126] It should be noted that, in the process of etching the support layer 202 and the sacrificial layer 201 using the first mask layer 300 and the second mask layer 400 as masks, affected by the actual situation of the etching process, the ions will gather on the surface of the structure around the hole during the etching process, causing the shape of the sidewall in contact with the hole to change. Therefore, the capacitor hole 210 finally formed is circular or elliptical, such as Fig.11 shown.
[0127] like Figure 8 As shown, in step S450 , the first mask layer 300 and the second mask layer 400 are removed, and a lower electrode layer 500 is formed in the capacitor hole 210 .
[0128] After forming the capacitor hole 210, the first mask layer 300 and the second mask layer 400 can be removed to expose the surface of the support layer 202. Then, a lower electrode layer 500 can be formed. The material of the lower electrode layer 500 can be titanium nitride or a composite film layer of titanium and titanium nitride. The lower electrode layer 500 can fill the capacitor hole 210 and contact and connect with the conductive part 103. In the embodiment of the present disclosure, the structure after completing step S450 is as follows: Fig.13 In the embodiment of the present disclosure, the top view after completing step S450 is as shown in Fig.14 shown.
[0129] In an exemplary embodiment of the present disclosure, forming the lower electrode layer 500 in the capacitor hole 210 (ie, step S450) may include steps S510 and S520, wherein:
[0130] In step S510 , a conductive material layer 510 is formed on a side of the support layer 202 away from the substrate 100 , and the conductive material layer 510 fills the capacitor hole 210 .
[0131] For example, the material of the conductive material layer 510 may be titanium nitride, and the conductive material may be deposited on the side of the support layer 202 away from the substrate 100 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition until the conductive material fills the capacitor hole 210. The conductive material filling the capacitor hole 210 and the conductive material covering the surface of the support layer 202 may be collectively defined as the conductive material layer 510. In the embodiment of the present disclosure, the structure after completing step S510 is as follows: Fig.15 In the embodiment of the present disclosure, the top view after completing step S510 is as shown in Fig.16 shown.
[0132] Step S520, flattening the conductive material layer 510 to remove the conductive material layer 510 located on the surface of the support layer 202, and make the top surface of the conductive material layer 510 located in the capacitor hole 210 flush with the top surface of the support layer 202, and define the remaining conductive material layer 510 in the capacitor hole 210 as the lower electrode layer 500.
[0133] The conductive material layer 510 may be planarized by chemical mechanical polishing to remove the conductive material layer 510 on the surface of the support layer 202 and make the top surface of the conductive material layer 510 in the capacitor hole 210 flush with the top surface of the support layer 202. Of course, the conductive material layer 510 may also be etched back by etching back to remove the conductive material layer 510 on the surface of the support layer 202 and make the top surface of the conductive material layer 510 in the capacitor hole 210 flush with the top surface of the support layer 202. The method for removing the conductive material layer 510 is not particularly limited herein.
[0134] like Figure 8 As shown, in step S460 , a portion of the support layer 202 that is opposite to the overlapping region of the second mask structure 302 and the fourth mask structure 402 is removed to form a through hole 2001 that exposes the sacrificial layer 201 .
[0135] like Fig.17 and Fig.18 As shown, a photoresist layer 600 can be formed on the surface of the structure formed by the support layer 202 and the lower electrode layer 500 by spin coating or other methods, and the photoresist layer 600 can be exposed and developed using a mask to form a development area 601, such as Fig.18 and Fig.19As shown in FIG. 6 , the developing area 601 can expose the portion of the support layer 202 that is directly opposite to the overlapping area of the second mask structure 302 and the fourth mask structure 402. The support layer 202 can be etched in the developing area 601 to form a through hole 2001 that exposes the sacrificial layer 201. In this process, due to the intersection of the second mask structure 302 and the fourth mask structure 402, the area B (such as Fig.11 The area of the sacrificial layer 201 exposed by the through hole 2001 formed after removing the portion of the support layer 202 that is opposite to the overlapping area of the second mask structure 302 and the fourth mask structure 402 is relatively large. In the embodiment of the present disclosure, the structure after completing step S460 is as follows: Fig. 20 shown.
[0136] like Figure 8 As shown, in step S470, the sacrificial layer 201 is removed by a wet etching process.
[0137] The sacrificial layer 201 can be removed by wet etching process using an acidic solution. When wet etching the sacrificial layer 201, since the exposed area of the sacrificial layer 201 is relatively large, the process space (i.e., the hole) of wet etching is relatively large, the liquid tension is small, and the bubbles are small. The liquid in the wet etching can fully enter the sacrificial layer 201, which helps to reduce etching residues, reduce defects, and improve product yield. In the embodiment of the present disclosure, the structure after completing step S470 is as follows Fig.21 shown.
[0138] In an exemplary embodiment of the present disclosure, after removing the sacrificial layer 201, the method for manufacturing a semiconductor device of the present disclosure may further include step S610 and step S620, wherein:
[0139] Step S610 , forming a capacitor dielectric layer 700 conformally covering the surface of the structure formed by the substrate 100 , the lower electrode layer 500 and the support layer 202 .
[0140] The material of the capacitor dielectric layer 700 may be an insulating material with a high dielectric constant, for example, it may be aluminum oxide, hafnium oxide, lanthanum oxide, titanium oxide, zirconium oxide, tantalum oxide, niobium oxide, strontium oxide or a mixture thereof. Of course, it may also be other materials with relatively high dielectric constants, which are not listed here one by one. The capacitor dielectric layer 700 may be formed by chemical vapor deposition, physical vapor deposition or atomic layer deposition, and the capacitor dielectric layer 700 may conformally cover the outer surface and inner surface of the structure formed by the substrate 100, the lower electrode layer 500 and the support layer 202. In the embodiment of the present disclosure, the structure after completing step S610 is as follows: Fig. 22 shown.
[0141] Step S620 , forming an upper electrode layer 800 on the surface of the capacitor dielectric layer 700 .
[0142] The material of the upper electrode layer 800 can be titanium nitride or a composite film layer of titanium and titanium nitride. The upper electrode layer 800 can cover the surface of the capacitor dielectric layer 700 in a conformal manner, or fill the remaining space in the structure, which is not specifically limited here. The upper electrode layer 800, the capacitor dielectric layer 700 and the lower electrode layer 500 can together form a complete capacitor. In the embodiment of the present disclosure, the structure after completing step S620 is as follows: Fig.23 shown.
[0143] It should be noted that, although the steps of the method for manufacturing a mask structure and a method for manufacturing a semiconductor device in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired result. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.
[0144] The embodiments of the present disclosure also provide a semiconductor device, which can be manufactured using the manufacturing method of the semiconductor device in any of the above embodiments. The specific details, formation process and beneficial effects have been described in detail in the embodiments of the corresponding semiconductor device manufacturing method, and will not be repeated here.
[0145] For example, the semiconductor device may be a Junction Field-Effect Transistor (JFET), a Dynamic Random Access Memory (DRAM) or a Static Random Access Memory (SRAM), etc. Of course, it may also be other storage devices, which are not listed here one by one.
[0146] The embodiments of the present disclosure also provide a mask structure, which can be manufactured using the manufacturing method of the mask structure in any of the above embodiments. The specific details, formation process and beneficial effects have been described in detail in the embodiments of the corresponding mask structure manufacturing method, and will not be repeated here.
[0147] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.
Claims
1. A method for manufacturing a mask structure, characterized in that: include: Forming a stacked structure and a photoresist layer on the stacked structure, wherein the photoresist layer comprises a plurality of spaced photoresist portions, and the photoresist portions comprise a first side wall and a second side wall that are oppositely disposed; forming a mask layer on a surface of a structure formed by the stacked structure and the photoresist portion; doping the mask layer so that a doping concentration of a first portion of the mask layer located on the first sidewall is different from a doping concentration of a second portion of the mask layer located on the second sidewall; Etching the photoresist portion and the mask layer to remove the photoresist portion and form a plurality of openings separated by the first portion and the second portion; When etching the photoresist portion and the mask layer, an etching rate of the first portion is different from an etching rate of the second portion.
2. The method for manufacturing a mask structure according to claim 1, characterized in that: The step of doping the mask layer comprises: The mask layer is ion doped at a preset angle, where the preset angle is an angle between the normal line of the first side wall or the normal line of the second side wall and the ion beam, and the preset angle is 5° to 60°.
3. The method for manufacturing a mask structure according to claim 1, characterized in that: The etching of the photoresist portion and the mask layer to remove the photoresist portion and form a plurality of openings separated by the first portion and the second portion comprises: Using a dry etching process to remove the photoresist portion and other portions of the mask layer except the first portion and the second portion; The first portion and the second portion are etched using a wet etching process, wherein a wet etching rate of the first portion is different from a wet etching rate of the second portion, so that after the wet etching, the widths of the first portion and the second portion located on both sides of the opening are different.
4. The method for manufacturing a mask structure according to claim 1, characterized in that: The photoresist portion and the mask layer are etched to remove the photoresist portion and form a plurality of openings separated by the first portion and the second portion, comprising: Etching the mask layer by a wet etching process, wherein a wet etching rate of the first portion is different from a wet etching rate of the second portion, so that the widths of the first portion remaining after the wet etching are different from the widths of the second portion remaining after the wet etching; A dry etching process is used to remove the photoresist portion and other portions of the mask layer except the first portion and the second portion after the wet etching.
5. The method for manufacturing a mask structure according to claim 3 or 4, characterized in that: The material of the mask layer is silicon oxide, and the etching solution of the wet etching is an acidic solution; When removing the other parts of the mask layer except the first part and the second part, the etching gas used is a fluorine-containing gas; When removing the photoresist portion, the etching gas used is oxygen.
6. The method for manufacturing a mask structure according to claim 1, characterized in that: The ions doped in the mask layer include one or more of phosphorus ions, boron ions, arsenic ions or gallium ions.
7. The method for manufacturing a mask structure according to claim 1, characterized in that: The doping concentration of the first portion is 0.
8. A method for manufacturing a semiconductor device, characterized in that: include: Forming a stacked film layer on a substrate, wherein the stacked film layer includes a sacrificial layer and a supporting layer stacked in sequence along a vertical direction; A first mask layer is formed on the stacked film layer using the method for manufacturing a mask structure according to any one of claims 1 to 7, the first portion and the second portion of the first mask layer located on both sides of the opening are defined as a first mask structure and a second mask structure, respectively, the first mask structure and the second mask structure both extend along a first direction and are spaced apart along a second direction, the width of the second mask structure is greater than the width of the first mask structure; the second direction intersects with the first direction; A second mask layer is formed on a side of the first mask layer away from the substrate by using the method for manufacturing the mask structure according to any one of claims 1 to 7, and the first portion and the second portion of the second mask layer located on both sides of the opening are defined as a third mask structure and a fourth mask structure, respectively, the third mask structure and the fourth mask structure both extend along the second direction and are spaced apart along the first direction, and the width of the fourth mask structure is greater than the width of the third mask structure; Using the first mask layer and the second mask layer as masks, etching the support layer and the sacrificial layer to form a plurality of capacitor holes distributed at intervals; removing the first mask layer and the second mask layer, and forming a lower electrode layer in the capacitor hole; Removing a portion of the support layer that is opposite to an overlapping region of the second mask structure and the fourth mask structure to form a through hole exposing the sacrificial layer; The sacrificial layer is removed by a wet etching process.
9. The method for manufacturing a semiconductor device according to claim 8, characterized in that: The forming of the lower electrode layer in the capacitor hole comprises: forming a conductive material layer on a side of the support layer away from the substrate, wherein the conductive material layer fills the capacitor hole; The conductive material layer is planarized to remove the conductive material layer on the surface of the support layer, and the top surface of the conductive material layer in the capacitor hole is flush with the top surface of the support layer, and the remaining conductive material layer in the capacitor hole is defined as a lower electrode layer.
10. The method for manufacturing a semiconductor device according to claim 9, characterized in that: After removing the sacrificial layer, the method for manufacturing the semiconductor device further includes: forming a capacitor dielectric layer conformally covering the surface of the structure formed by the substrate, the lower electrode layer and the support layer; An upper electrode layer is formed on the surface of the capacitor dielectric layer.
11. The method for manufacturing a semiconductor device according to claim 9, wherein: The substrate includes an insulating layer, a bottom supporting layer and a plurality of conductive parts distributed at intervals, wherein the insulating layer fills the gaps between the conductive parts; the bottom supporting layer covers the surfaces of the insulating layer and the conductive parts, and when the supporting layer and the sacrificial layer are etched using the first mask layer and the second mask layer as masks, the bottom supporting layer is etched at the same time, so that the capacitor holes simultaneously penetrate the bottom supporting layer and expose the conductive parts; the lower electrode layer is in contact and connected with the conductive parts.
12. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method for manufacturing a semiconductor device according to any one of claims 8 to 11.
13. A mask structure, characterized in that: The mask structure is manufactured by the method for manufacturing a mask structure according to any one of claims 1 to 7.