Method for manufacturing SiC chip

Abstract

In a method for manufacturing a SiC chip (40), a process-modified layer removal step for removing a process-modified layer generated on the surface and inside of the SiC chip (40) is performed, and the SiC chip (40) from which at least a portion of the process-modified layer has been removed is manufactured. In the processing-modified layer removal step, the SiC chip (40) after the polishing step in which a reaction product is generated on the SiC chip (40) using an oxidizing agent while abrasive grains are used to remove the processing-modified layer by etching the SiC chip (40) at an etching amount of 10 [mu] m or less by heating the SiC chip (40) under Si vapor pressure. In the SiC chip (40) after the polishing step, internal stress is generated in the interior deeper than the process-modified layer due to the process-modified layer, and the process-modified layer is removed by the process-modified layer removal step to reduce the internal stress of the SiC chip (40).

Description

[0001] This case is a divisional application of the application date of July 25, 2019, application number 201980054946.7 (PCT / JP 2019 / 029161), and invention name "Method for manufacturing SiC chip". Technical Field

[0002] The present invention mainly relates to a method for manufacturing a SiC chip from which a processing-deteriorated layer has been removed. Background Art

[0003] Patent Document 1 states that mechanical grinding of a SiC chip, for example, may produce grinding scratches on the surface of the SiC chip and latent scratches inside the chip. Patent Document 1 also discloses a method in which the surface of the SiC chip is etched by heating under Si vapor pressure to remove latent scratches.

[0004] Prior art literature

[0005] Patent Literature

[0006] Patent Document 1: International Publication No. 2015 / 151413 Summary of the invention

[0007] Problems to be solved by the invention

[0008] Among them, when removing the process-degraded layer such as latent damage by etching as in Patent Document 1, it is preferred to remove the process-degraded layer with a small amount of etching. This is because by reducing the amount of etching, the time required to remove the process-degraded layer can be reduced, the single crystal SiC as the raw material can be used efficiently, and the degradation of the processing device used for etching can be reduced.

[0009] The present invention has been made in view of the above-mentioned situation, and a main object of the present invention is to provide a method for manufacturing a SiC chip, which can sufficiently remove a processed altered layer with a small amount of etching.

[0010] Technical solutions to solve problems

[0011] The problem to be solved by the present invention is as described above. The means for solving the problem and their effects are described below.

[0012] According to aspects of the present invention, a method for manufacturing a SiC chip is provided. That is, in the method for manufacturing a SiC chip, a machining-degraded layer removal step is performed to remove the machining-degraded layer generated on the surface and inside of the SiC chip, and a SiC chip with at least a portion of the machining-degraded layer removed is manufactured. In the machining-degraded layer removal step, the polished chip is etched by heating under Si vapor pressure to remove the machining-degraded layer by an amount less than or equal to 10 μm, wherein the polished chip is obtained by polishing the surface by using an oxidant to generate reaction products on the SiC chip while using abrasives to remove the reaction products. On the polished chip, stress is generated inside deeper than the machining-degraded layer due to the machining-degraded layer, and the machining-degraded layer is removed by using the machining-degraded layer removal step to reduce the internal stress of the SiC chip.

[0013] Since the relatively soft reaction products produced by the use of an oxidant are removed by using abrasive grains, a process-degraded layer is less likely to be produced than in the case of grinding by other methods. Therefore, even if the etching amount is less than or equal to 10 μm, the process-degraded layer can be sufficiently removed. In addition, since the etching amount is reduced compared to the prior art, the time required for processing can be reduced, and the burden on the processing device can be reduced.

[0014] In the method for manufacturing the SiC chip, it is preferred that the arithmetic surface roughness (Ra) of the surface of the chip after grinding is less than or equal to 0.7 nm.

[0015] As the surface roughness of the chip after grinding decreases, it is less likely that a process-degraded layer such as scratches will be generated after the subsequent process-degraded layer removal step, and thus high-quality SiC chips can be manufactured.

[0016] In the SiC chip manufacturing method, it is preferred that etching with an etching amount of 20 nm or more is performed in the process-affected layer removal step.

[0017] This makes it possible to fully remove the processed altered layer included in the chip after grinding.

[0018] In the method for manufacturing the SiC chip, the following steps are preferably performed. That is, the method for manufacturing the SiC chip includes a grinding step, which is performed before the process-degraded layer removal step. In the grinding step, the surface is ground by using the oxidant to generate the reaction product on the SiC chip while using the abrasive to remove the reaction product.

[0019] Thus, since the relatively soft reaction products produced by the use of the oxidant are removed by the abrasive grains, a machine-degraded layer is less likely to be produced on the SiC chip than in the case of polishing by other methods. Therefore, the machine-degraded layer can be easily removed.

[0020] In the method for manufacturing the SiC chip, preferably, in the polishing step, polishing is performed using the abrasive grains having a lower hardness than SiC.

[0021] Thus, since the hardness of the reaction product generated by using the oxidizing agent is lower than that of SiC, the use of the abrasive grains can suppress the occurrence of scratches on the SiC portion while removing the reaction product. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A diagram illustrating an overview of a high-temperature vacuum furnace used in Si vapor pressure etching according to an embodiment of the present invention;

[0023] Figure 2 is a diagram schematically showing the manufacturing process of the SiC chip of the present embodiment;

[0024] Figure 3 is a perspective view showing the structure of a grinding device used in a grinding process;

[0025] Figure 4 A diagram for explaining how a process-degraded layer and a stress layer generated on a SiC chip after a grinding step are removed by a process-degraded layer removal step;

[0026] Figure 5 A diagram showing scratch images of a SiC chip after a grinding process and a SiC chip after a process-altered layer removal process;

[0027] Figure 6 is a diagram showing scratch images of SiC chips having different etching amounts in a process-deteriorated layer removal step; and

[0028] Figure 7 This is a graph comparing the surface roughness of the SiC chip after the polishing step and the amount of scratches after the process-affected layer removal step.

[0029] Explanation of symbols

[0030] 10 High temperature vacuum furnace

[0031] 40 SiC chips DETAILED DESCRIPTION

[0032] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. Figure 1 , a high-temperature vacuum furnace 10 used in the method for manufacturing a SiC chip according to the present embodiment is described.

[0033] like Figure 1 As shown, the high temperature vacuum furnace 10 includes a main heating chamber 21 and a preheating chamber 22. The main heating chamber 21 is capable of heating a SiC chip 40 (single crystal SiC substrate) whose surface is at least composed of single crystal SiC (e.g., 4H-SiC or 6H-SiC) to a temperature greater than or equal to 1000° C. and less than or equal to 2300° C. The preheating chamber 22 is a space for preheating the SiC chip 40 before heating the SiC chip 40 in the main heating chamber 21.

[0034] The main heating chamber 21 is connected to a vacuum forming valve 23, an inert gas injection valve 24, and a vacuum gauge 25. The vacuum forming valve 23 can adjust the vacuum degree of the main heating chamber 21. The inert gas injection valve 24 can adjust the pressure of the inert gas in the main heating chamber 21. In this embodiment, the inert gas is a gas of a Group 18 element (rare gas element) such as Ar, that is, a gas that has a poor reactivity with solid SiC and does not contain nitrogen. The vacuum gauge 25 can measure the vacuum degree in the main heating chamber 21.

[0035] A heater 26 is provided inside the main heating chamber 21. In addition, a heat-reflecting metal plate (not shown) is fixed to the side wall and ceiling of the main heating chamber 21, and the heat-reflecting metal plate is configured to reflect the heat of the heater 26 toward the center of the main heating chamber 21. Thus, the SiC chip 40 can be heated strongly and uniformly, and the temperature can be raised to a temperature greater than or equal to 1000° C. and less than or equal to 2300° C. As the heater 26, for example, a resistance heating type heater or a high-frequency induction heating type heater can be used.

[0036] The high-temperature vacuum furnace 10 heats the SiC chip 40 contained in the crucible (container) 30. The containment container 30 is placed on a suitable support table, etc., and is configured to be able to move at least from the preliminary heating chamber to the main heating chamber by moving the support table. The containment container 30 includes an upper container 31 and a lower container 32 that can be interlocked with each other. The support portion 33 provided in the lower container 32 of the containment container 30 can support the SiC chip 40 in a manner that exposes both the main surface and the back surface of the SiC chip 40. The main surface of the SiC chip 40 is the Si surface, which is the (0001) surface when expressed as a crystal surface. The back surface of the SiC chip 40 is the C surface, which is the (000-1) surface when expressed as a crystal surface. In addition, the SiC chip 40 can also have an offset angle relative to the Si surface and the C surface, or the C surface can also be used as the main surface. Among them, the main surface is the two surfaces with the largest area among the surfaces of the SiC chip 40 ( Figure 1 The back surface is one of the upper and lower surfaces of the main surface, and is a surface on which an epitaxial layer is formed in a later process. The back surface is a surface on the back side of the main surface.

[0037] The storage container 30 is the part of the wall (top, side, bottom) that constitutes the internal space that accommodates the SiC chip 40, and is composed of a tantalum layer (Ta), a tantalum carbide layer (TaC and Ta2C), and a tantalum silicide layer (TaSi2 or Ta5Si3, etc.) in sequence from the outside to the internal space side.

[0038] The tantalum silicide layer is heated to supply Si to the internal space of the storage container 30. In addition, since the storage container 30 contains a tantalum layer and a tantalum carbide layer, it is possible to take in surrounding C vapor. As a result, the internal space can be set to a high-purity Si atmosphere during heating. Furthermore, a Si source such as solid Si can be arranged in the internal space instead of providing a tantalum silicide layer. In this case, the solid Si sublimates during heating, and the internal space can be set to a high-purity Si vapor pressure.

[0039] When heating the SiC chip 40, first, as Figure 1 As shown by the dotted line, the storage container 30 is arranged in the preheating chamber 22 of the high-temperature vacuum furnace 10, and preheated at an appropriate temperature (for example, about 800°C). Next, the storage container 30 is moved to the main heating chamber 21 which is preheated to a set temperature (for example, about 1800°C). Then, the SiC chip 40 is heated while adjusting the pressure, etc. Furthermore, the preheating can also be omitted.

[0040] Secondly, refer to Figure 2 , a manufacturing process of the SiC chip 40 of the present embodiment (especially the SiC chip 40 having an epitaxial layer formed thereon) will be described. Figure 2 It is a diagram schematically showing the manufacturing process of the SiC chip 40 according to the present embodiment.

[0041] The SiC chip 40 is made of a crystal ingot 4. The crystal ingot 4 is a single crystal SiC block made by a known sublimation method or solution growth method. Figure 2 As shown, the SiC ingot 4 is cut at predetermined intervals by a cutting means such as a diamond wire, and a plurality of SiC chips 40 are produced from the ingot 4 (chip production process). Furthermore, the SiC chip 40 can also be produced by other methods. For example, it is also possible to form a chip shape and take it out after a damaged layer is set on the ingot 4 by laser irradiation or the like. In addition, it is possible to produce a SiC chip 40 whose surface is at least single crystal SiC by bonding a single crystal SiC substrate obtained from the ingot etc. to a polycrystalline SiC substrate and then performing a peeling process or the like as needed. Furthermore, the SiC chip 40 after being produced from the ingot 4 and before the following mechanical processing process is performed can also be referred to as an original sliced ​​chip or a pre-processed chip.

[0042] Next, the SiC chip 40 is subjected to a machining process. In the machining process, for example, the following treatment (grinding) is performed: at least the main surface of the SiC chip 40 is mechanically ground by a diamond grinding wheel or the like. The machining process is a process performed to make the SiC chip 40 to a target thickness. The machining process can also be performed in multiple stages using tools with different abrasive grain sizes. Furthermore, the SiC chip 40 after the machining process and before the following grinding process can also be referred to as a ground SiC chip.

[0043] Next, the SiC chip 40 is subjected to a grinding process. In the past, chemical mechanical polishing (Chemical Mechanical Polishing) using a predetermined slurry was performed on the SiC chip 40 after the machining process. Slurry refers to an abrasive mixed with abrasive particles in a liquid. In this embodiment, although slurry is also used for grinding, the liquid of the slurry used in this embodiment has an oxidizing effect (details will be described later). This type of grinding is called chemical mechanical polishing (ChemoMechanical Polishing).

[0044] Below, refer to Figure 3 , the grinding process of this embodiment is described in detail. Figure 3 It is a perspective view showing the structure of the polishing device 50 used in the polishing process.

[0045] like Figure 3 As shown, the polishing device 50 includes a rotating support table 51, a polishing pad 52, a slurry supply pipe 53, a chip carrier 55 and a pad conditioner 56. Figure 3 The configuration in the following description, the shape and configuration of each part may also be different from that in the present embodiment.

[0046] The rotating support table 51 is a disc-shaped component and is Figure 3 The rotating support 51 is configured to be rotatable with the axial direction as the rotation center. A disk-shaped polishing pad 52 is mounted on the rotating support 51. The disk-shaped polishing pad 52 is made of polyurethane foam or other materials. The slurry is supplied to the polishing pad 52 from the slurry supply pipe 53. The details of the slurry used in this embodiment and the effects of the slurry will be described later.

[0047] The chip carrier 55 is configured to fix the SiC chip 40 at the bottom. The chip carrier 55 presses the main surface (polishing target surface) of the SiC chip 40 fixed at the bottom onto the polishing pad 52. In addition, the chip carrier 55 is configured to press the SiC chip 40 at the bottom onto the polishing pad 52. Figure 3As shown, the polishing pad 52 rotates with the axial direction as the rotation center. Furthermore, the rotation support table 51 and the chip carrier 55 have different rotation centers. With this structure, the slurry can act on the SiC chip 40. In addition, as the grinding proceeds, processing debris and reaction products will be blocked in the micropores of the polishing pad 52. The pad conditioner 56 scrapes the surface of the polishing pad 52 to remove the blockage.

[0048] Here, the slurry of this embodiment contains an oxidant for oxidizing the SiC chip 40. As described above, the slurry is composed of a liquid medicine and abrasive grains. The slurry is, for example, aluminum oxide slurry, cerium oxide slurry, manganese oxide slurry, or iron oxide slurry, the liquid medicine is, for example, potassium permanganate, hydrogen peroxide solution, or ammonium peroxide, and the abrasive grains are, for example, aluminum oxide, cerium oxide, manganese oxide, or iron oxide. In the slurry of this embodiment, the liquid medicine acts as an oxidant.

[0049] The SiC chip 40 is oxidized by the slurry, thereby generating a reaction product (oxide of oxide film, etc.). The reaction product is, for example, an oxide of silicon (e.g., silicon dioxide). The reaction product is removed by abrasive grains, so that the surface of the SiC chip 40 can be removed and ground. Thus, the surface roughness of the SiC chip 40 is reduced. Among them, the reaction product produced by the oxidation of SiC has a hardness lower than that of SiC. In addition, the hardness of the abrasive grains such as aluminum oxide contained in the slurry used in the present embodiment is lower than the hardness of SiC, and higher than the hardness of the reaction product (e.g., silicon dioxide). Furthermore, the hardness measurement method is not particularly limited, for example, Vickers hardness, Mohs hardness, or Knoop hardness can be used. In this way, by using the abrasive grains of the hardness between the reaction product and SiC to perform a grinding process, it is possible to remove the reaction product produced in the SiC chip 40 while suppressing the scratches in the SiC portion of the SiC chip 40, and it is also possible to suppress the large force acting on the SiC chip 40. In addition, the SiC chip 40 after the polishing step and before the following process-affected layer removal step can also be referred to as a polished SiC chip.

[0050] Next, the process of removing the altered layer will be described. Figure 4 The processed deteriorated layer and the like generated on the SiC chip 40 (SiC chip after grinding) will be described. Figure 4 The diagram is for explaining how the process-degraded layer and the stress layer generated in the SiC chip 40 (SiC chip after polishing) are removed by the process-degraded layer removing step.

[0051] like Figure 4As shown, a machined altered layer and a stress layer are formed on the SiC chip 40 after the grinding process. The machined altered layer is a region where deformation occurs due to the generation of internal stress and crystal fracture or dislocation occurs. The machined altered layer is generated by the force acting on the surface and the inside of the SiC chip 40, or the surface of the SiC chip 40 is ground in at least one of the chip manufacturing process, the machining process, and the grinding process. The machined altered layer is the part of the SiC chip 40 where the SiC cannot be reversed (plastic deformation).

[0052] In addition, the portion of the machined altered layer with a large degree of crystal fracture or dislocation is called a latent flaw. Unlike machined altered layers such as grinding scratches that only occur near the surface of the SiC chip 40, latent flaws have the characteristic of being generated inside the SiC chip 40. In addition, latent flaws also have the characteristic of becoming apparent during heat treatment. Specifically, even when the surface of the SiC 40 is sufficiently flat when observed under a microscope, when latent flaws remain inside, heating the SiC chip 40 (for example, Si vapor pressure etching or formation of an epitaxial layer described later) will make the latent flaws apparent, thereby generating large surface roughness on the SiC chip 40. Since latent flaws have these characteristics, in order to remove the latent flaws, it is necessary to increase the amount of SiC chip 40 removed, and it is not easy to confirm whether the latent flaws can be removed, so compared with other machined altered layers, it is difficult to remove.

[0053] The stress layer is generated on the inner side deeper than the machined metamorphic layer (the opposite side of the main surface, the lower side of the machined metamorphic layer). The stress layer is the same as the machined metamorphic layer, and is a part that is deformed due to the generation of internal stress. However, in the stress layer, unlike the machined metamorphic layer, almost no crystal fracture or dislocation occurs. The reason for the generation of the stress layer is the same as the reason for the generation of the machined metamorphic layer. Further explanation, the stress layer has a machined metamorphic layer due to the above reasons, so internal stress remains. The stress layer is the part of the SiC chip 40 that can reverse the change (elastic deformation). Therefore, by removing the machined metamorphic layer, the internal stress generated in the stress layer is released, returning to a state where no distortion occurs.

[0054] In addition, in the present embodiment, since a reaction product is generated in the grinding process and the reaction product is removed, as described above, it is possible to suppress a large force from acting on the SiC chip 40 in the grinding process. Therefore, it becomes difficult to generate a machined altered layer and a stress layer, or a stress layer is preferentially generated rather than a machined altered layer. As a result, the machined altered layer and the stress layer can be removed with a smaller etching amount than in the past. Furthermore, in the present embodiment, the etching amount refers to the amount of etching of the main surface of the SiC chip 40 in the thickness direction (thickness reduction, i.e., etching depth).

[0055] In the present embodiment, the machining altered layer removal process is performed by Si vapor pressure etching by heating the SiC chip 40 under Si vapor pressure. Specifically, for example, the SiC chip 40 having an offset angle is contained in a containment container 30, and is heated using a high-temperature vacuum furnace 10 under Si vapor pressure and in a temperature range of greater than or equal to 1500°C and less than or equal to 2200°C, preferably greater than or equal to 1600°C and less than or equal to 2000°C. Furthermore, during this heating, an inert gas can be supplied in addition to Si vapor. By supplying an inert gas, the etching rate of the SiC chip 40 can be reduced. Furthermore, no other vapor generation source is used except Si vapor and inert gas. By heating the SiC chip 40 under this condition, etching is performed while flattening the surface. Specifically, the reaction shown below is performed. A brief explanation is as follows: by heating the SiC chip 40 under Si vapor pressure, the SiC in the SiC chip 40 is thermally decomposed and chemically reacts with Si to become Si2C or SiC2, etc., and then sublimates. At the same time, the Si in the Si atmosphere combines with C on the surface of the SiC chip 40 to self-organize and is flattened.

[0056] (1) SiC(s) → Si(v) + C(s)

[0057] (2) 2SiC(s) → Si(v) + SiC2(v)

[0058] (3) SiC(s) + Si(v) → Si2C(v)

[0059] Since Si vapor pressure etching is thermochemical etching rather than mechanical processing such as grinding and polishing, it will not cause the generation of process-degraded layers and stress layers. Therefore, unlike mechanical processing, it can remove the existing process-degraded layers and stress layers without forming new process-degraded layers and stress layers.

[0060] Figure 4 The top part shows the SiC chip 40 after the grinding process (chip after grinding). A machined-degraded layer and a stress layer including latent damage are generated in the SiC chip 40. In the machined-degraded layer removal process, Si vapor pressure etching with an etching amount less than or equal to 10 μm is performed. Since it is estimated that the machined-degraded layer can be made less than or equal to 10 μm by performing the grinding process of this embodiment, all or most of the machined-degraded layer (including latent damage) can be removed by performing the machined-degraded layer removal process of this embodiment.

[0061] Figure 4The center and the bottom of the figure show the SiC chip 40 after the process of removing the altered layer. As described above, the stress layer is caused by the altered layer, and the stress layer disappears by removing the altered layer. Therefore, by performing the process of removing the altered layer, it is possible to manufacture a SiC chip 40 that does not have any altered layer or stress layer at all or substantially.

[0062] Figure 5 The results of the following experiment are shown, which confirm that a high-quality SiC chip 40 can be obtained by processing by the method of this embodiment. In this experiment, the formation of scratches on the main surface of the following SiC chip 40 was observed, wherein these SiC chips 40 were SiC chips 40 after a grinding process using an aluminum oxide slurry as a slurry, and SiC chips 40 after a processing-deteriorated layer removal process with an etching amount of 3.4μm. Scratches are linear flaws and are a type of processing-deteriorated layers.

[0063] like Figure 5 As shown in FIG. 1 , there are a large number of scratches in the SiC chip 40 after the grinding process. Moreover, almost all of the large number of scratches can be removed by etching with an etching amount of 3.4 μm. Thus, it is confirmed that the SiC chip 40 with basically no processing altered layer and stress layer can be manufactured with an etching amount significantly reduced than in the past.

[0064] Furthermore, since the thickness of the processed degraded layer varies depending on the conditions of the polishing process, although the minimum required etching amount is different, the required etching amount in this embodiment is less than the minimum required etching amount (10 μm) in the case of performing the conventional polishing process. Figure 6 The scratch images after the degraded layer removal process are shown for each SiC chip 40 with different etching amounts in the degraded layer removal process. The ED on the upper side of each scratch image shows the etching amount, and the Ra on the lower side shows the surface roughness after the degraded layer removal process (the arithmetic mean roughness Ra in detail, the same below). Figure 6As shown, in the scratch image of any etching amount, there are basically or completely no scratches. That is, by using the method of this embodiment, as long as the etching amount of 20nm, which is the minimum etching amount, is performed, SiC40 with basically or completely no scratches can be manufactured. Furthermore, after considering the experimental results, the lower limit of the etching amount of the processing metamorphic layer removal process is preferably, for example, any one of 20nm, 50nm, 75nm, 0.1μm, 0.15μm, 0.5μm, 1μm, 3μm, or 5μm, and the upper limit of the etching amount of the processing metamorphic layer removal process is preferably, for example, any one of 1μm, 3μm, 5μm, and 10μm. By using the method of this embodiment, SiC chips 40 with basically no processing metamorphic layers and stress layers can be manufactured with less etching amount than in the past. Therefore, the time required for the processing of the SiC chip 40 can be reduced, and the burden on the high-temperature vacuum furnace 10 can be reduced.

[0065] Furthermore, when compared with the amount of removal in the machining process, it is preferable that the etching amount in the process-affected layer removal process is smaller than the amount of removal in the machining process.

[0066] Next, an epitaxial layer forming process of forming an epitaxial layer 41 is performed on the main surface of the SiC chip 40. In the epitaxial layer forming process, the SiC chip 40 is set on a crystal seat, and the crystal seat is placed in a heating container for chemical vapor deposition (CVD method). Then, by introducing raw material gas, etc. in a high temperature environment, an epitaxial layer 41 composed of single crystal SiC is formed on the SiC substrate. Furthermore, the epitaxial layer 41 can be formed by different methods. For example, the epitaxial layer 41 can also be formed by a solution growth method such as the MSE method or a proximity sublimation method. The MSE method is also called a metastable solvent epitaxy method, and is a growth method using a SiC chip, a feed substrate with a higher free energy than the SiC chip, and a Si melt. By arranging the SiC chip and the feed substrate in an opposing manner, and heating them under vacuum in a state where the Si melt is separated, single crystal SiC can be grown on the surface of the SiC chip.

[0067] Next, refer to Figure 7 The following experiment is described, which examines the relationship between the surface roughness of the SiC chip 40 after the polishing step and the amount of scratches after the subsequent process-affected layer removal step.

[0068] In this experiment, three types of SiC chips 40 with different surface roughness after the grinding process were prepared. The surface roughness after the grinding process varies depending on the grinding conditions (the size of the abrasive grains, the rotation speed of the polishing pad 52, and the pressing force of the chip carrier 55). Furthermore, the slurry used in the grinding process is an aluminum oxide slurry. In addition, the three types of SiC chips 40 were subjected to a processing altered layer removal process under the same conditions. In the processing altered layer removal process, the etching amount was 3.4μm.

[0069] Figure 7 The two sets of photos at the top and the center are obtained by observing the SiC chip 40 under a microscope, wherein the SiC chip 40 is a SiC chip 40 having a surface roughness of 0.46nm and 0.64nm respectively after the grinding process, and a SiC chip 40 after the processing metamorphic layer removal process. In addition, the scratches on the surface of the SiC chip 40 are represented by fine lines. In the case where the surface roughness after the grinding process is 0.46nm and 0.64nm, scratches can hardly be confirmed after the processing metamorphic layer removal process. Furthermore, the SiC chip 40 with a surface roughness of 0.46nm after the grinding process can be confirmed, and there are fewer scratches after the processing metamorphic layer removal process.

[0070] on the other hand, Figure 7 The bottom group of photos was obtained by observing the SiC chip 40 under a microscope, wherein the SiC chip 40 is a SiC chip 40 with a surface roughness of 0.91nm after the grinding process, and a SiC chip 40 after the processing metamorphic layer removal process. In addition, the conditions of the processing metamorphic layer removal process are the same. When the surface roughness after the grinding process is 0.91nm, a large number of scratches can be confirmed after the processing metamorphic layer removal process. In addition, in the SiC chip 40, a large scratch can be confirmed in the part slightly to the left of the center in the left-right direction.

[0071] It can be seen from this that when the surface roughness after the grinding process is small, scratches are not easy to be generated after the processing altered layer removal process. In addition, by setting the surface roughness of the SiC chip 40 after the grinding process to less than or equal to 0.7nm, it is possible to manufacture a SiC chip 40 with sufficiently few scratches. In addition, by setting the surface roughness of the SiC chip 40 after the grinding process to less than or equal to 0.5nm, it is possible to manufacture a SiC chip 40 with fewer scratches.

[0072] As described above, in the manufacturing method of the SiC chip 40 of the present embodiment, a process-degraded layer removal step is performed to remove the process-degraded layer generated on the surface and inside of the SiC chip 40, and a SiC chip 40 from which at least a portion of the process-degraded layer has been removed is manufactured. In the process-degraded layer removal step, the SiC chip 40 after the grinding step is etched by heating under Si vapor pressure with an etching amount less than or equal to 10 μm to remove the process-degraded layer, wherein in the grinding step, an oxidant is used to generate a reaction product on the SiC chip 40 while abrasive grains are used to remove the reaction product. On the SiC chip 40 after the grinding step, stress is generated inside deeper than the process-degraded layer due to the process-degraded layer, and the process-degraded layer is removed in the process-degraded layer removal step to reduce the internal pressure of the SiC chip 40.

[0073] Since abrasive grains are used to remove relatively soft reaction products produced by using an oxidant, it is less likely to produce a process-degraded layer than in the case of grinding by other methods. Therefore, even if the etching amount is less than or equal to 10 μm, the process-degraded layer can be fully removed. In addition, since the etching amount is reduced compared to the past, the time required for processing can be reduced, and the burden on the processing device can be reduced.

[0074] In addition, in the method for manufacturing the SiC chip 40 of the present embodiment, the arithmetic surface roughness (Ra) of the surface of the SiC chip 40 after the polishing step is less than or equal to 0.7 nm.

[0075] As the surface roughness of the SiC chip 40 after the polishing step decreases, a process-degraded layer such as scratches is less likely to remain after the subsequent process-degraded layer removal step, and thus a high-quality SiC chip 40 can be manufactured.

[0076] In the method for manufacturing the SiC chip 40 of the present embodiment, etching is performed with an etching amount of 5 nm or more in the process-affected layer removal step.

[0077] Thus, the processed altered layer included in the SiC chip 40 after the polishing step can be sufficiently removed.

[0078] The method for manufacturing the SiC chip 40 of the present embodiment includes a polishing step performed before the process-degraded layer removal step. In the polishing step, the surface of the SiC chip 40 is polished by using an oxidizing agent to generate reaction products and removing the reaction products using abrasive grains.

[0079] Thus, since the relatively soft reaction products produced by the oxidant are removed by the abrasive grains, a machine-degraded layer is less likely to be produced in the SiC chip 40 compared to the case of polishing by other methods. Therefore, the machine-degraded layer can be easily removed.

[0080] In the method for manufacturing the SiC chip 40 of the present embodiment, polishing is performed using abrasive grains having a lower hardness than SiC in the polishing step.

[0081] Thus, since the hardness of the reaction product generated by using the oxidizing agent is lower than that of SiC, the use of the abrasive grains can suppress the generation of scratches on the SiC portion while removing the reaction product.

[0082] Although the preferred embodiment of the present invention has been described above, the above configuration can be modified as follows, for example.

[0083] The manufacturing process described in the above embodiment is only an example, and the order of the processes may be changed, some processes may be omitted, or other processes may be added. For example, a surface cleaning process of hydrogen etching may be performed before the epitaxial layer forming process.

[0084] The temperature conditions and pressure conditions described above are only examples and can be changed as appropriate. In addition, it is also possible to use a heating device other than the high temperature vacuum 10, or to use a polycrystalline SiC chip 40, or to use a container of a shape or material different from that of the storage container 30. For example, the shape of the storage container is not limited to a cylindrical shape, and can also be a cubic shape or a rectangular parallelepiped shape.

Claims

1. A method for manufacturing a SiC chip from which a modified layer has been removed, the method comprising performing a modified layer removal step to remove a modified layer generated on a surface of and inside the SiC chip, and manufacturing a SiC chip from which at least a portion of the modified layer has been removed, characterized in that: In the process of removing the altered layer, the chip after grinding is etched by heating under Si vapor pressure to an amount of less than or equal to 10 μm to remove the altered layer, wherein the chip after grinding is obtained by grinding the surface of the SiC chip while using an oxidant to generate a reaction product on the SiC chip and using abrasive grains to remove the reaction product. In the polished chip, stress is generated inside the chip deeper than the processed degraded layer due to the processed degraded layer. The processed degraded layer is removed by the processed degraded layer removal step, thereby reducing the internal stress of the SiC chip.

2. The method for manufacturing a SiC chip from which a processing-degraded layer has been removed according to claim 1, wherein: The arithmetic surface roughness (Ra) of the chip surface after grinding is less than or equal to 0.7 nm.

3. The method for manufacturing a SiC chip from which a processing-degraded layer has been removed according to claim 1, wherein: In the process of removing the damaged layer, etching is performed with an etching amount greater than or equal to 20 nm.

4. The method for manufacturing a SiC chip from which a processing-degraded layer has been removed according to claim 1, wherein: The method comprises a grinding step, which is performed before the machining altered layer removal step. In the polishing step, the reaction product is generated on the SiC chip using the oxidizing agent, and the reaction product is removed using the abrasive to polish the surface.

5. The method for manufacturing a SiC chip from which a processing-degraded layer has been removed according to claim 4, wherein: In the polishing step, polishing is performed using the abrasive grains having a lower hardness than SiC.

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