Semiconductor device and method of forming semiconductor package having RF antenna interposer with high dielectric seal

Abstract

A semiconductor device has a substrate and an electrical component disposed on a surface of the substrate. The antenna interposer is disposed on the substrate. A first encapsulant is deposited around the antenna interposer. The first encapsulant has a high dielectric constant. The antenna interposer has a conductive layer operating as an antenna and an insulating layer having a low dielectric constant less than the high dielectric constant of the first encapsulant. The antenna interposer is made of an antenna substrate having a plurality of antenna interposers. Bumps are formed on an antenna substrate, and the antenna substrate is singulated to fabricate a plurality of antenna interposers. A second encapsulant is deposited on the electrical component. The second sealant has a low dielectric constant that is less than a high dielectric constant of the first sealant. A shielding layer is disposed on the second encapsulant.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices and, more particularly, to a semiconductor device and method of forming a semiconductor package having an RF antenna interposer with a high dielectric constant seal. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronics, optoelectronics, and creating visual images for television displays. Semiconductor devices are found in the fields of communications, power conversion, networking, computers, entertainment, and consumer products. Semiconductor devices are also found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor devices, especially in high-frequency applications such as radio frequency (RF) wireless communications, typically contain one or more integrated passive devices (IPDs) to perform necessary electrical functions, such as RF signal processing. Semiconductor devices must be connected to an RF antenna to transmit and receive RF signals. The RF antenna may be located outside the semiconductor device, such as on a PCB. Alternatively, the RF antenna may be integrated in a semiconductor package. Integrated RF antennas are typically embedded in the case of semiconductor packages and / or occupy a relatively small area of ​​the package. Integrated RF antennas known in the prior art lack RF transmission and reception performance and quality. In particular, for multi-functional integration and signal input / output stability in high-speed devices such as antennas on packages (AoP), the number of substrate layers has been continuously increased. A higher number of substrate layers increases manufacturing costs and lead times. A higher number of substrate layers may cause warping and introduce defects, thereby reducing yield and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1a-1c illustrates a semiconductor wafer having a plurality of semiconductor dies separated by saw streets;

[0005] Figure 2a-2h A process for forming an interposer substrate for an RF antenna having a high dielectric constant seal is illustrated;

[0006] Figure 3a-3h illustrates a process of forming a semiconductor package having a semiconductor die, an interconnect substrate, and an RF antenna interposer;

[0007] Figure 4a-4b The diagram shows planarization of an RF antenna interposer;

[0008] Figure 5a-5eAnother process of forming a semiconductor package having a semiconductor die, an interconnect substrate, and an RF antenna interposer is illustrated;

[0009] Figure 6a-6c illustrates a process of forming a semiconductor package having a semiconductor die, an interconnect substrate, and a full-width RF antenna substrate;

[0010] Figure 7 An integrated RF antenna interposer and a semiconductor package with an encapsulant bump on the encapsulation are illustrated;

[0011] Figure 8 An integrated RF antenna interposer and a semiconductor package with encapsulant bumps on the RF antenna interposer are illustrated; and

[0012] Fig. 9 A printed circuit board (PCB) is illustrated with different types of packages mounted to a surface of the PCB. DETAILED DESCRIPTION

[0013] In the following description with reference to the accompanying drawings, the present invention is described in one or more embodiments, wherein like numbers represent the same or similar elements. Although the present invention is described in terms of the best mode for achieving the purposes of the present invention, it will be appreciated by those skilled in the art that the present invention is intended to cover alternatives, modifications and equivalents that may be included within the spirit and scope of the present invention as defined by the appended claims and their equivalents, which are supported by the following disclosure and the accompanying drawings. The term "semiconductor die" as used herein refers to both the singular and plural forms of the word, and thus may refer to both a single semiconductor device and a plurality of semiconductor devices.

[0014] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components, such as transistors and diodes, have the ability to control the flow of current. Passive electrical components, such as capacitors, inductors, and resistors, create the relationship between voltage and current necessary to perform the circuit function.

[0015] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor dies, and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to singulate the semiconductor dies, the wafer is scored and broken along the non-functional areas of the wafer called saw streets or scribe lines. The wafer is singulated using a laser cutting tool or a saw blade. After singulation, the individual semiconductor dies are mounted to a package substrate, which includes pins or contact pads for interconnection with other system components. The contact pads formed on the semiconductor die are then connected to the contact pads within the package. Electrical connections can be made with conductive layers, bumps, stud bumps, conductive glue, or wire bonding. Encapsulants or other molding materials are deposited on the package to provide physical support and electrical isolation. The completed package is then inserted into the electrical system, and the functions of the semiconductor device are made available to other system components.

[0016] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or components 104 are formed on the wafer 100, separated by non-active inter-die wafer regions or saw streets 106. The saw streets 106 provide dicing areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0017] Figure 1b A cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110, wherein the active surface 110 contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers, which are formed within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as digital signal processors (DSPs), application specific integrated circuits (ASICs), memories, or other signal processing circuits. The semiconductor die 104 may also include IPDs (such as inductors, capacitors, and resistors) and other circuits for RF signal processing. The surface 108 may be subjected to back grinding to planarize the semiconductor die 104.

[0018] Conductive layer 112 is formed on active surface 110 using PVD, CVD, electrolytic plating, electroless plating process or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag) or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to the circuit on active surface 110.

[0019] Conductive bump material is deposited on conductive layer 112 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 114. In one embodiment, bump 114 is formed on an under-bump metallization (UBM) having a wetting layer, a barrier layer and an adhesive layer. Bump 114 can also be crimped or hot-pressed to conductive layer 112. Bump 114 represents a type of interconnect structure that can be formed on conductive layer 112. The interconnect structure can also use bonding wires, conductive glue, stud bumps, microbumps or other electrical interconnects.

[0020] exist Figure 1c In the process, semiconductor wafer 100 is singulated through saw streets 106 using a saw blade or laser cutting tool 118 into individual semiconductor die 104. Individual semiconductor die 104 may be inspected and electrically tested for identification of post-singulation KGDs.

[0021] Figure 2a-2h The process of forming an interposer substrate for an RF antenna with a high dielectric constant seal is illustrated. Figure 2aIn the embodiment, the insulating layer 120 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polymer, pre-impregnated polytetrafluoroethylene (PTFE) (prepreg), polyimide, benzocyclobutene (BCB), polybenzoxazole (PBO), and other materials with similar insulating and structural properties. Conductive layer 122 is formed on surface 125 of insulating layer 120. Conductive layer 122 can be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Conductive layer 122 provides horizontal electrical interconnection across insulating layer 120 (including surface 125). A plurality of through holes are formed through insulating layer 120 by etching, drilling or LDA. The through holes are filled with conductive material to form conductive vias 124 for vertical electrical interconnection from insulating layer 120 to conductive layer 122.

[0022] exist Figure 2b , a conductive layer 126 is formed on the insulating layer 120 and electrically connected to the conductive via 124. The conductive layer 126 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The conductive layer 126 provides horizontal electrical interconnection across the insulating layer 120. An insulating layer 127 is formed on the conductive layer 126. The insulating layer 127 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, prepreg, polyimide, polymer, BCB, PBO and other materials having similar insulating and structural properties. A plurality of vias are formed through the insulating layer 127 by etching, drilling or LDA. The vias are filled with a conductive material to form a conductive via 128 for vertical electrical interconnection through the insulating layer 127 to the conductive layer 126. A conductive layer 129 is formed on the insulating layer 127 and electrically connected to the conductive via 128. Conductive layer 129 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. In one embodiment, conductive layer 129 provides a ground plane and horizontal electrical interconnect across insulating layer 127 .

[0023] exist Figure 2c, an insulating layer 130 is formed on the conductive layer 129. The insulating layer 130 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, prepreg, polyimide, polymer, BCB, PBO, and other materials having similar insulating and structural properties. A plurality of through holes are formed through the insulating layer 130 by etching, drilling, or LDA. The through holes are filled with a conductive material to form a conductive via 131 for vertical electrical interconnection through the insulating layer 130 to the conductive layer 129. A conductive layer 132 is formed on the insulating layer 130 and electrically connected to the conductive via 131. The conductive layer 132 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 132 provides horizontal electrical interconnection across the insulating layer 130. The conductive layer 132 may be configured as an RF antenna embedded in an RF antenna interposer substrate 138, similar to the RF antenna 137. An insulating layer 133 is formed on the conductive layer 132. The insulating layer 133 includes one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, prepreg, polyimide, polymer, BCB, PBO, and other materials having similar insulating and structural properties. A plurality of through holes are formed through the insulating layer 133 by etching, drilling, or LDA. The through holes are filled with a conductive material to form a conductive via 134 for vertical electrical interconnection through the insulating layer 133 to the conductive layer 132. A conductive layer 135 is formed on a surface 136 of the insulating layer 133 and is electrically connected to the conductive via 134. The conductive layer 135 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. The conductive layer 135 operates as a plurality of RF antennas 137a-137b exposed from a surface 136 of an RF antenna interposer substrate 138. In one embodiment, the RF antenna interposer substrate 138 has eight or more conductive layers, such as 126, 129, 132, and 135, separated by insulating layers, such as 120, 127, 130, and 133. Fewer conductive layers reduce manufacturing costs and lead times while managing warpage with lower product heights and minimizing other product defects. The insulating layers 120, 127, 130, and 133 have low dielectric constants (Dk) and low dielectric factors (Df). For example, the insulating layers 120, 127, 130, and 133 have a Dk of 3.2-3.7, and a Df of 0.002-0.007 at 1 GHz and a Df of 0.003-0.008 at 10 GHz.

[0024] Conductive bump material is deposited on conductive layer 122 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing process. The bump material can be Al, Sn, Ni, Au, Ag, Pb, Bi, Cu, solder and combinations thereof, with optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to conductive layer 122 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 123. In one embodiment, bump 123 is formed on a UBM having a wetting layer, a barrier layer and an adhesive layer. Bump 123 can also be crimped or hot pressed to conductive layer 122. In one embodiment, bump 123 is a copper core bump for durability and to maintain its height. Bump 123 represents a type of interconnect structure that can be formed on conductive layer 122. The interconnect structure may also use bonding wires, conductive glue, stud bumps, micro bumps, or other electrical interconnects.

[0025] Figure 2d 1 is a top view of an RF antenna interposer substrate 138. The conductive layer 135 includes an array of islands of conductive material in the form of the conductive layer 135 suitable for providing transmission and reception of RF signals, i.e., an RF antenna. In particular, the array of islands of the conductive layer 135 is exposed from the surface 136 to improve RF transmission and reception performance and quality. In one embodiment, a first group of islands 139a of conductive material is used as a first antenna 137a, which is electrically connected through the conductive layers 122, 126, 129, 132 and the conductive vias 124, 128, 131, 134 and the bumps 123 to provide RF transmission and reception for the first electrical component. A second group of islands 139b of conductive material is used as a second antenna 137b, which is electrically connected through the conductive layers 122, 126, 129, 132 and the conductive vias 124, 128, 131, 134 and the bumps 123 to provide RF transmission and reception for the second electrical component. Although for the purpose of simplifying the description, in Figure 2d-2e Two RF antennas 137 a - 137 b are shown in FIG. 1 , but the RF antenna substrate 138 may have any number of RF antenna interposers 140 .

[0026] Figure 2e1 is a top view of another embodiment of an RF antenna interposer substrate 138. Conductive layer 135 includes a plurality of spirally shaped conductive materials suitable for providing transmission and reception of RF signals. In particular, the spiral shapes of conductive layer 135 are exposed from surface 136 to improve RF transmission and reception performance and quality. In one embodiment, conductive layer 135a is used as a first spiral RF antenna 137a, which is electrically connected through conductive layers 122, 126, 129, 132 and conductive vias 124, 128, 131, 134 and bumps 123 to provide RF transmission and reception for a first electrical component. Conductive layer 135b is used as a second spiral RF antenna 137b, which is electrically connected through conductive layers 122, 126, 129, 132 and conductive vias 124, 128, 131, 134 and bumps 123 to provide RF transmission and reception for a second electrical component.

[0027] Figure 2f A top view of an RF antenna interposer substrate 138 is shown having an RF antenna interposer 140 and bumps 123 formed on a surface 125 using solder ball mounting (SBM).

[0028] exist Figure 2g In the embodiment of the present invention, the RF antenna interposer substrate 138 is singulated into discrete RF antenna interposers 140 using a saw blade or laser cutting tool 141. The discrete RF antenna interposers 140 may be loaded on tape and reel for later assembly. Figure 2h A top view of the discrete RF antenna interposer 140 with bumps 123 after singulation is shown.

[0029] Figure 3a-3h A process of forming a semiconductor package having electrical components and an interconnect substrate and a discrete RF antenna interposer is illustrated. Figure 3aA cross-sectional view of an interconnect substrate or PCB 142 including a conductive layer 143 and an insulating layer 144 is shown. The conductive layer 143 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The conductive layer 143 may be formed by solder paste printing or flux printing. The conductive layer 143 provides horizontal electrical interconnections across the substrate 142, and vertical electrical interconnections between the top surface 146 and the bottom surface 148 of the substrate 142. Depending on the design and function of the electrical component, portions of the conductive layer 143 may be electrically common or electrically isolated. The insulating layer 144 comprises one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, prepreg, polyimide, polymer, BCB, PBO, and other materials having similar insulating and structural properties. The insulating layer 144 provides isolation between the conductive layers 143. In one embodiment, the interconnect substrate 142 has eight or more conductive layers 143 separated by insulating layers 144. The insulating layer 144 has low Dk and low Df. For example, the insulating layer 144 has a Dk of 3.2-3.7, a Df of 0.002-0.007 at 1 GHz, and a Df of 0.003-0.008 at 10 GHz.

[0030] exist Figure 3b In the embodiment of the present invention, a pick and place operation using bumps 123 oriented toward surface 146 is used to place the bumps 123 from the Figure 2a-2h The discrete RF antenna interposer 140 is positioned on the substrate 142. The discrete RF antenna interposer 140 may be mounted using the tape and reel mentioned above. Figure 3c Discrete RF antenna interposer 140 is shown mounted to interconnect substrate 142 , with bumps 123 making mechanical and electrical connections to conductive layer 143 .

[0031] exist Figure 3d In the embodiment of the present invention, a sealant or molding compound 150 is deposited on the surface 146 of the discrete RF antenna interposer 140 and the interconnect substrate 142 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating or other suitable applicators. The sealant 150 can be a polymer composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with appropriate filler. The sealant 150 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. The sealant 150 has a high Dk and a low Df. For example, the sealant 150 has a Dk of 14-21 and a Df of 0.006-0.012 at 25 GHz. The higher Dk of the sealant 150 is greater than the lower Dk of the insulating layers 120, 127, 130, 133 and 144.

[0032] exist Figure 3e In, from Figure 3d The structure is inverted, and electrical components 152a-152d are positioned on substrate 142 using a pick and place operation. Electrical components 152a-152d may be discrete transistors, diodes, or IPDs. Electrical components 152a-152d may also be semiconductor dies, semiconductor packages, surface mount devices, or other electrical devices. For example, electrical component 152d may be from Figure 1c Semiconductor die 104 with active surface 110 and bumps 114 oriented toward surface 146 of substrate 142 and electrically connected to conductive layer 143. In one embodiment, electrical components 152a-152d are RF signal processing components. Figure 3f Electrical components 152a-152d are shown mounted to interconnect substrate 142, with bumps 114 and terminals 154 making mechanical and electrical connections to conductive layer 143. Connector 156 may be a board-to-board (B2B) connector.

[0033] exist Figure 3g In the embodiment of the present invention, a sealant or molding compound 160 is deposited on the surface 148 of the electrical components 152a-152d and the interconnect substrate 142 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating or other suitable applicators. The sealant 160 can be a polymer composite material, such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with appropriate fillers. The sealant 160 is non-conductive, provides structural support, and protects the semiconductor device from external elements and pollutants in the environment. The sealant 160 has a low Dk and a low Df. For example, the sealant 160 has a Dk of 3.9 and a Df of 0.005 at 25GHz. In any case, the Dk of the sealant 160 is less than the Dk of the sealant 150.

[0034] The electrical components 152a-152d may include IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs included in the electrical components 152a-152d provide electrical characteristics required for high-frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetrical Hi-Q resonant transformers, and tuning capacitors. In another embodiment, the electrical components 152a-152d include digital circuits that switch at high frequencies, which may interfere with the operation of the IPDs in the semiconductor package.

[0035] exist Figure 3hIn the embodiment of the present invention, an electromagnetic shielding layer 162 is formed or provided on a surface 163 of the sealant 160 by conformal application of the shielding material. The shielding layer 162 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Alternatively, the shielding layer 162 may be carbonyl iron, stainless steel, nickel silver, low carbon steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI and other inter-device interference. In addition, the shielding layer 162 covers the side surface 165 of the sealant 160 and the side surface of the semiconductor package 164.

[0036] The combination of semiconductor package 164 and discrete RF antenna interposer 140 is designated as AoP 167. When integrated into AoP 167, discrete RF antenna interposer 140 provides antenna functionality for RF electrical components 152a-152d in semiconductor package 164. AoP 167 is suitable for 5G / millimeter wave RF products. In one embodiment, a first group of islands 139a of conductive material are used as a first antenna patch 140, which is electrically connected through conductive layers 122, 126, 129, 132, 143 and conductive vias 124, 128, 131, 134 and bumps 123 to provide RF transmission and reception for the first electrical components 152a-152d in semiconductor package 164. The second set of islands 139b of conductive material serve as a second antenna patch 140, which is electrically connected through conductive layers 122, 126, 129, 132, 143 and conductive vias 124, 128, 131, 134 and bumps 123 to provide RF transmission and reception for second electrical components 152a-152d in semiconductor package 164. When configured as an RF antenna, conductive layer 132 can be electrically connected through conductive layers 122, 126, 129, 143 and conductive vias 124, 128, 131 and bumps 123 to provide RF transmission and reception for third electrical components 152a-152d in semiconductor package 164. The encapsulant 150 deposited around the discrete RF antenna interposer 140 has a high Dk and a low Df. The higher the value of Dk, the smaller the antenna patch width of conductive layer 135, and more antenna patches can be placed on AoP 167, as shown by equation (1).

[0037]

[0038] in:

[0039] w is the antenna patch width

[0040] v0 is the speed of light

[0041] fr is the resonant frequency

[0042] Dk is the dielectric constant.

[0043] exist Figure 4a-4b In another embodiment shown in FIG. 1 , a portion of the encapsulant 150 is removed by a grinder 166 to expose a surface 168 of the encapsulant 150 and the discrete RF antenna interposer 140. The grinder 166 planarizes the surface 168 of the encapsulant 150 and the discrete RF antenna interposer 140 in the semiconductor package 170, as shown in FIG. Figure 4b as shown in .

[0044] Figure 5a-5e Another process of forming a semiconductor package having electrical components and an interconnect substrate and a discrete RF antenna interposer is illustrated. Figure 5a A cross-sectional view of an interconnect substrate or PCB 180 including a conductive layer 182 and an insulating layer 184 is shown. The conductive layer 182 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. The conductive layer 182 may be formed by solder paste printing or flux printing. The conductive layer 182 provides horizontal electrical interconnections across the substrate 180, and vertical electrical interconnections between the top surface 186 and the bottom surface 188 of the substrate 180. Depending on the design and function of the electrical component, portions of the conductive layer 182 may be electrically common or electrically isolated. The insulating layer 184 may include one or more layers of SiO2, Si3N4, SiON, Ta2O5, Al2O3, solder resist, prepreg, polyimide, polymer, BCB, PBO, and other materials having similar insulating and structural properties. The insulating layer 184 provides isolation between the conductive layers 182. In one embodiment, the interconnect substrate 180 has eight or more conductive layers 182 separated by insulating layers 184. The insulating layer 184 has low Dk and low Df. For example, the insulating layer 184 has a Dk of 3.2-3.7, a Df of 0.002-0.007 at 1 GHz, and a Df of 0.003-0.008 at 10 GHz.

[0045] Similar to Figure 3e-3f , electrical components 190a-190d are positioned on substrate 180 using a pick and place operation. Electrical components 190a-190d may be discrete transistors, diodes, or IPDs. Electrical components 190a-190d may also be semiconductor dies, semiconductor packages, surface mount devices, or other electrical devices. For example, electrical component 190d may be from Figure 1c The semiconductor die 104 has an active surface 110 and bumps 114 oriented toward a surface 186 of the substrate 180 and electrically connected to the conductive layer 182. In one embodiment, the electrical components 190a-190d are RF signal processing components. The connector 192 may be a B2B connector.

[0046] exist Figure 5bIn the embodiment of the present invention, a sealant or molding compound 196 is deposited on the surface 186 of the electrical components 190a-190d and the interconnect substrate 180 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating or other suitable applicators. The sealant 196 can be a polymer composite material, such as an epoxy resin with fillers, an epoxy acrylate with fillers, or a polymer with appropriate fillers. The sealant 196 is non-conductive, provides structural support, and protects the semiconductor device from external elements and contaminants in the environment. The sealant 196 has a low Dk and a low Df. For example, the sealant 196 has a Dk of 3.9 and a Df of 0.005 at 25 GHz.

[0047] exist Figure 5c In, from Figure 5b The structure is inverted and a pick and place operation using bumps 123 oriented toward surface 188 is used to place the Figure 2f The discrete RF antenna interposer 140 is positioned on the interconnect substrate 180, similar to Figure 3b-3c Bumps 123 make mechanical and electrical connections to conductive layer 182 .

[0048] exist Figure 5d In the process, a sealant or molding compound 200 is deposited on the surface 188 of the discrete RF antenna interposer 140 and the interconnect substrate 180 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating or other suitable applicators. The sealant 200 can be a polymer composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with appropriate filler. The sealant 200 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. The sealant 200 has a high Dk and a low Df. For example, the sealant 200 has a Dk of 14-21 and a Df of 0.006 to 0.012 at 25 GHz. In any case, the Dk of the sealant 200 is greater than the Dk of the sealant 196 and the insulating layers 120, 127, 130, 133 and 144, respectively.

[0049] The electrical components 190a-190d may include IPDs that are susceptible to or generate EMI, RFI, harmonic distortion, and inter-device interference. For example, the IPDs included in the electrical components 190a-190d provide electrical characteristics required for high-frequency applications, such as resonators, high-pass filters, low-pass filters, band-pass filters, symmetrical Hi-Q resonant transformers, and tuning capacitors. In another embodiment, the electrical components 190a-190d include digital circuits that switch at high frequencies, which may interfere with the operation of the IPDs in the semiconductor package.

[0050] exist Figure 5e In the embodiment of the present invention, an electromagnetic shielding layer 202 is formed or provided on a surface 204 of the sealant 196 by conformal application of the shielding material. The shielding layer 202 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag or other suitable conductive materials. Alternatively, the shielding layer 202 may be carbonyl iron, stainless steel, nickel silver, low carbon steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites capable of reducing or suppressing the effects of EMI, RFI and other inter-device interference. In addition, the shielding layer 202 covers the side surface 206 of the sealant 196 and the side surface of the semiconductor package 210.

[0051] The combination of semiconductor package 210 and discrete RF antenna interposer 140 is designated as AoP 214. When integrated into AoP 214, discrete RF antenna interposer 140 provides antenna functionality for RF electrical components 190a-190d in semiconductor package 210. Encapsulant 200 deposited around discrete RF antenna interposer 140 has a high Df and a low Dk. The higher the value of Dk, the smaller the antenna patch width of conductive layer 135, and more antenna patches can be placed on AoP 214, as shown by equation (1).

[0052] In from Figure 3a In another embodiment, the RF antenna substrate 220 is positioned on the interconnect substrate 180 using a pick and place operation using the bumps 224 oriented toward the surface 188, such as Figure 6a . Conductive layer 226 provides electrical interconnect, ground plane, and RF antenna, similar to conductive layers 122, 126, 129, 132, 135 in discrete RF antenna interposer 140. Insulating layer 228 provides isolation for conductive layer 226, similar to insulating layers 120, 127, 130, 133. In this case, RF antenna substrate 220 acts as RF antenna 230. Instead of multiple discrete RF antenna interposers 140, RF antenna substrate 220 is a single integral body that substantially covers interconnect substrate 180. RF antenna substrate 220 may have multiple RF antennas, similar to Figure 2d and 2e , to provide RF transmission and reception for multiple electrical components 190a-190d. Figure 6b The RF antenna substrate 220 is shown mounted to the interconnect substrate 180 , with bumps 224 making mechanical and electrical connections to the conductive layer 182 .

[0053] exist Figure 6cIn the embodiment of the present invention, a sealant or molding compound 240 is deposited on the surface 188 of the RF antenna substrate 220 and the interconnect substrate 180 using paste printing, compression molding, transfer molding, liquid sealant molding, vacuum lamination, spin coating or other suitable applicators. The sealant 240 can be a polymer composite material, such as an epoxy resin with filler, an epoxy acrylate with filler, or a polymer with appropriate filler. The sealant 240 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external elements and contaminants. The sealant 240 has a high Dk and a low Df. For example, the sealant 240 has a Dk of 14-21 and a Df of 0.006 to 0.012 at 25 GHz. In any case, the Dk of the sealant 240 is greater than the Dk of the sealant 196 and the insulating layers 120, 127, 130, 133 and 144, respectively.

[0054] By conformal application of the shielding material, an electromagnetic shielding layer 242 is formed or disposed on a surface 244 of the sealant 196. The shielding layer 242 may be one or more layers of Al, Cu, Sn, Ni, Au, Ag, or other suitable conductive materials. Alternatively, the shielding layer 242 may be carbonyl iron, stainless steel, nickel silver, low carbon steel, ferrosilicon steel, foil, conductive resin, carbon black, aluminum sheet, and other metals and composites that can reduce or suppress the effects of EMI, RFI, and other inter-device interference. In addition, the shielding layer 242 covers the side surface 246 of the sealant 196 and the side surface of the semiconductor package 248.

[0055] The combination of semiconductor package 248 and RF antenna substrate 220 is designated as AoP 250. When integrated into AoP 250, RF antenna substrate 220 provides antenna functionality for RF electrical components 190a-190d in semiconductor package 248. Encapsulant 240 deposited around discrete RF antenna interposer 140 has a high Df and a low Dk. The higher the value of Dk, the smaller the antenna patch width of conductive layer 226, and more antenna patches can be placed on AoP 250, as shown by equation (1).

[0056] Figure 7 Shows something like Figure 3h An embodiment in which encapsulant bump 254 is formed in encapsulant 150 .

[0057] Figure 8 Shows something like Figure 4b An embodiment in which the encapsulant bump 260 is formed in a separate RF antenna interposer 140 .

[0058] Fig. 9An electronic device 400 is illustrated having a chip carrier substrate or PCB 402 with multiple semiconductor packages mounted on a surface of the PCB 402, including AoPs 167, 214, and 250. The electronic device 400 may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application.

[0059] Electronic device 400 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, electronic device 400 may be a subcomponent of a larger system. For example, electronic device 400 may be a part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electronic device. Alternatively, electronic device 400 may be a graphics card, a network interface card, or other signal processing cards that may be inserted into a computer. Semiconductor packages may include microprocessors, memories, ASICs, logic circuits, analog circuits, RF circuits, discrete devices, or other semiconductor die or electrical components. Miniaturization and lightweighting are essential for making products accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density.

[0060] exist Fig. 9 4, PCB 402 provides a common substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 404 are formed on the surface or within layers of PCB 402 using evaporation, electrolytic plating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 404 provide electrical communication between each of the semiconductor packages, mounted components, and other external system components. Traces 404 also provide power and ground connections to each of the semiconductor packages.

[0061] In some embodiments, the semiconductor device has two packaging levels. The first level packaging is a technology for mechanically and electrically attaching a semiconductor die to an intermediate substrate. The second level packaging involves mechanically and electrically attaching an intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first level packaging, in which the die is mechanically and electrically mounted directly to the PCB. For illustrative purposes, several types of first level packaging are shown on PCB 402, including wire bonding packages 406 and flip chips 408. In addition, several types of second level packaging are shown mounted on PCB 402, including ball grid arrays (BGA) 410, bump chip carriers (BCC) 412, land grid arrays (LGA) 416, multi-chip modules (MCM) or SIP modules 418, quad flat packages (QFN) 420, quad flat packages 422, embedded wafer-level ball grid arrays (eWLB) 424, and wafer-level chip scale packages (WLCSP) 426. In one embodiment, eWLB 424 is a fan-out wafer level package (Fo-WLP) and WLCSP 426 is a fan-in wafer level package (Fi-WLP). Depending on the system requirements, any combination of semiconductor packages configured in any combination of first and second level packaging styles and other electronic components can be connected to PCB 402. In some embodiments, electronic device 400 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and simplified manufacturing processes. The resulting devices are less likely to fail and less expensive to manufacture, resulting in lower costs for consumers.

[0062] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to those embodiments without departing from the scope of the invention as set forth in the following claims.

Claims

1. A semiconductor device, comprising: substrate; an electrical component disposed on the first surface of the substrate; a first encapsulant deposited on the electrical component; a shielding layer disposed on the first sealant; as well as An antenna interposer is disposed on a second surface of the substrate opposite the first surface of the substrate, wherein the antenna interposer is a unitary body substantially covering the substrate. 2 . The semiconductor device of claim 1 , further comprising a second encapsulant deposited on the antenna interposer. 3 . The semiconductor device according to claim 2 , wherein the second encapsulant comprises a high dielectric constant in the range of 14 to 21. 4 . 4 . The semiconductor device of claim 2 , wherein the first encapsulant comprises a low dielectric constant that is smaller than a high dielectric constant of the second encapsulant. 5 . The semiconductor device according to claim 2 , further comprising a sealant bump disposed on the second sealant.

6. A semiconductor device comprising: substrate; A shielding layer disposed on the substrate; as well as An antenna interposer is disposed on the first surface of the substrate, wherein the antenna interposer is a unitary body substantially covering the substrate.

7. The semiconductor device according to claim 6, further comprising: an electrical component disposed on a second surface of the substrate opposite the first surface of the substrate; a first encapsulant deposited on the electrical component; as well as A second encapsulant is deposited on the antenna interposer. 8 . The semiconductor device of claim 7 , wherein the second encapsulant comprises a high dielectric constant in the range of 14 to 21. 9 . The semiconductor device of claim 7 , wherein the first encapsulant comprises a low dielectric constant that is smaller than a high dielectric constant of the second encapsulant. 10 . The semiconductor device according to claim 7 , further comprising a sealant bump disposed on the second sealant.

11. A method for manufacturing a semiconductor device, comprising: providing a substrate; disposing an electrical component on the first surface of the substrate; Provide shielding layers on electrical components; as well as An antenna interposer is disposed on a second surface of the substrate opposite the first surface of the substrate, wherein the antenna interposer is a unitary body substantially covering the substrate.

12. The method according to claim 11, further comprising: depositing a first encapsulant on the electrical component; as well as A second encapsulant is deposited on the antenna interposer. 13 . The method of claim 12 , wherein the second encapsulant comprises a high dielectric constant in the range of 14 to 21.

14. The method of claim 12, wherein the first encapsulant comprises a low dielectric constant that is less than a high dielectric constant of the second encapsulant.

15. The method of claim 12, further comprising providing an encapsulant bump on the second encapsulant.

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