Semiconductor device

Abstract

The invention provides a semiconductor device in which generation of electromigration in a solder layer is suppressed. The semiconductor device includes: a semiconductor chip having an upper surface, a lower surface, and transistor regions and diode regions alternately arranged in a direction along the upper surface and the lower surface; a lead frame containing copper and disposed at a position on the upper surface side of the semiconductor chip; a plating layer that contains nickel and is formed on the semiconductor chip-side surface of the lead frame; a solder layer containing tin and joining the upper surface of the semiconductor chip and the plating layer; an insulating circuit board that is disposed so as to face the lower surface of the semiconductor chip, and that forms a wiring layer containing copper on the semiconductor chip-side surface; a plating layer that contains nickel and is formed on the semiconductor chip-side surface of the wiring layer; and a solder layer containing tin and joining the lower surface of the semiconductor chip and the plating layer.

Description

Technical Field

[0001] This invention relates to a semiconductor device. Background Technology

[0002] Semiconductor power modules exist where an insulating substrate and / or lead frame are soldered to a semiconductor chip (e.g., see Patent Document 1). Additionally, a semiconductor device is proposed comprising: a wiring layer disposed on an insulating substrate; a cover layer covering the wiring layer such that a portion of the upper surface of the wiring layer is exposed at an opening; and a bonding layer bonded to the wiring layer at the opening and formed of solder (e.g., see Patent Document 2). Furthermore, examples of power device elements used in semiconductor power modules include RC (Reverse-Conducting)-IGBT (Insulated Gate Bipolar Transistor) (e.g., see Non-Patent Document 1).

[0003] Existing technical documents

[0004] Patent documents

[0005] Patent Document 1: International Publication No. 2016 / 079881

[0006] Patent Document 2: International Publication No. 2022 / 244395

[0007] Non-patent literature

[0008] Non-Patent Literature 1: Yushi Sato and 5 others, “(Advantage of Lead-Frame Wiring and High Reliable to Electromigration Package for High Power Density Automotive Power Module),” PCIM Europe 2023, May 2023. Summary of the Invention

[0009] Technical issues

[0010] The purpose of this invention is to provide a semiconductor device capable of suppressing electromigration in a solder layer.

[0011] Technical solution

[0012] According to one aspect of the invention, a semiconductor device is provided, comprising: a semiconductor chip having an upper surface and a lower surface, and transistor regions and diode regions alternately arranged in a direction along the upper surface and the lower surface; a lead frame containing copper and disposed at a position on the upper surface side of the semiconductor chip; a first plating layer containing nickel and formed on the semiconductor chip side surface of the lead frame; a first solder layer containing tin and bonding the upper surface of the semiconductor chip to the first plating layer; an insulating circuit substrate disposed opposite to the lower surface of the semiconductor chip, and having a copper-containing wiring layer formed on the semiconductor chip side surface; a second plating layer containing nickel and formed on the semiconductor chip side surface of the wiring layer; and a second solder layer containing tin and bonding the lower surface of the semiconductor chip to the second plating layer.

[0013] The thickness of the second coating can be greater than the thickness of the first coating.

[0014] In the first plating layer, the thickness of the first region opposite the transistor region and the thickness of the second region opposite the diode region on the semiconductor chip side of the lead frame may be different. In the second plating layer, the thickness of the third region opposite the transistor region and the thickness of the fourth region opposite the diode region on the semiconductor chip side of the insulating circuit substrate may be different.

[0015] In the first coating, the thickness of the second region can be greater than the thickness of the first region, and in the second coating, the thickness of the fourth region can be greater than the thickness of the third region.

[0016] In the semiconductor chip, the current density when the diode region is energized can be greater than the current density when the transistor region is energized.

[0017] In the first coating, the thickness of the first region can be greater than the thickness of the second region, and in the second coating, the thickness of the fourth region can be greater than the thickness of the third region.

[0018] The first plating layer may be formed only in the first region on the semiconductor chip side of the lead frame, and the second plating layer may be formed only in the fourth region on the semiconductor chip side of the insulating circuit substrate.

[0019] The lead frame can be connected to the emitter of the semiconductor chip via the first solder layer, and the wiring layer of the insulating circuit board can be connected to the collector of the semiconductor chip via the second solder layer.

[0020] The semiconductor device described above may further include: a third plating layer containing nickel and formed on the surface of the semiconductor chip opposite to the first solder layer on the upper surface; and a fourth plating layer containing nickel and formed on the surface of the semiconductor chip opposite to the second solder layer on the lower surface.

[0021] It should be noted that the above description of the invention does not list all the features of the invention. Furthermore, sub-combinations of these feature groups can also constitute an invention.

[0022] Technical effect

[0023] According to the publicly available technology, electromigration in the solder layer is suppressed, and the long-term reliability of the semiconductor device is improved. Attached Figure Description

[0024] Figure 1 This is a top view of the semiconductor device according to the embodiment.

[0025] Figure 2 This is a side view of the semiconductor device according to the embodiment.

[0026] Figure 3 It is a top view of the semiconductor units included in a semiconductor device.

[0027] Figure 4 It is a cross-sectional view of the semiconductor units included in a semiconductor device.

[0028] Figure 5 This is a top view of a semiconductor chip.

[0029] Figure 6 It is a diagram used to illustrate electromigration.

[0030] Figure 7 This is a diagram showing a comparative example of the cross-sectional configuration of a semiconductor cell.

[0031] Figure 8 This is the first figure showing an example of the formation of a tin-copper alloy layer in a comparative example.

[0032] Figure 9 This is the second figure showing an example of the formation of the tin-copper alloy layer in the comparative example.

[0033] Figure 10 This is a diagram showing a first example of the formation of a coating in a semiconductor cell.

[0034] Figure 11 This is a diagram showing a second example of the formation of a coating in a semiconductor cell.

[0035] Figure 12 This is a diagram showing a third example of the formation of a coating in a semiconductor cell.

[0036] Figure 13 This is a diagram showing a fourth example of the formation of a coating in a semiconductor cell.

[0037] Figure 14 This is a diagram showing a fifth example of the formation of a plating layer in a semiconductor cell.

[0038] Symbol Explanation

[0039] 1. Semiconductor device

[0040] 2 Semiconductor Modules

[0041] 3. Cooling device

[0042] 4. Conductors

[0043] 10, 10a, 10b, 10c semiconductor units

[0044] 11 Insulated circuit board

[0045] 11a Insulation Board

[0046] 11b1, 11b2, 11c wiring boards

[0047] 11d metal plate

[0048] 12, 12a, 12b semiconductor chips

[0049] 12a1, 12b1 gate electrodes

[0050] 12a2, 12b2 emitters

[0051] 12a3 collector

[0052] 12a4 Active Unit

[0053] 12a5 pressure-resistant structural section

[0054] 12a6 protective ring

[0055] 13a, 13b lead frames

[0056] 14a and 14b solder layers

[0057] 15a, 15b, 18a, 18b coatings

[0058] 16a, 16b, 16c tin-copper alloy layers

[0059] Local alloy layers of 16a1, 16a2, 16b1, 16b2, and 16c2

[0060] Areas 17a and 17b

[0061] 18a1, 18a2, 18b1, 18b2 partial coatings

[0062] 20. Housing

[0063] 21 Outer Frame

[0064] Sidewalls 21a, 21b, 21c, and 21d

[0065] 21e, 21f, 21g Unit Storage Section

[0066] 22, 22a, 22b, 22c First connecting terminals

[0067] 23, 23a, 23b, 23c Second connection terminals

[0068] 24 Output terminals

[0069] 24a U-phase output terminal

[0070] 24b V-phase output terminal

[0071] 24c W-phase output terminal

[0072] Control terminals 25, 25a, 25b, and 25c

[0073] 26 bond wires

[0074] 31 Top Plate

[0075] 32 Sidewalls

[0076] 33 Cooling base plate

[0077] 33a Inlet

[0078] 33b Outlet Detailed Implementation

[0079] The embodiments will now be described with reference to the accompanying drawings. It should be noted that in the following description, "front" and "upper surface" refer to the XY plane facing upwards (+Z direction) in the power conversion device shown in the figures. Similarly, "upper" indicates the direction facing upwards (+Z direction) in the power conversion device shown in the figures. "Back" and "lower surface" refer to the XY plane facing downwards (-Z direction) in the power conversion device shown in the figures. Similarly, "lower" indicates the direction facing downwards (-Z direction) in the power conversion device shown in the figures. The same directionality may be indicated in other figures as needed. "Front," "upper surface," "upper," "back," "lower surface," "lower," and "side" are merely convenient expressions for determining relative positional relationships and do not limit the technical concept of the invention. For example, "upper" and "lower" do not necessarily refer to the vertical direction relative to the ground. That is, the directions of "upper" and "lower" are not limited to the direction of gravity.

[0080] First, use Figure 1 and Figure 2 An example of the overall configuration of the semiconductor device in the implementation method will be described. Figure 1 This is a top view of the semiconductor device according to the embodiment. Figure 2 This is a side view of the semiconductor device according to the embodiment. It should be noted that... Figure 2 It is observed along the Y direction. Figure 1 A side view of the semiconductor device 1.

[0081] Semiconductor device 1 includes semiconductor module 2 and cooling device 3. Semiconductor module 2 includes semiconductor units 10a, 10b, and 10c, and a housing 20 for housing semiconductor units 10a, 10b, and 10c. Semiconductor units 10a, 10b, and 10c are arranged in a row in the cooling device 3. The housing 20 is provided in the cooling device 3, and the semiconductor units 10a, 10b, and 10c are housed in the housing 20. The semiconductor units 10a, 10b, and 10c housed in the housing 20 are sealed by a sealing member (not shown).

[0082] It should be noted that semiconductor units 10a, 10b, and 10c all have the same configuration. Semiconductor units 10a, 10b, and 10c will be described as semiconductor unit 10 without distinction. Details regarding semiconductor unit 10 will be described later.

[0083] The housing 20 includes an outer frame 21, first connection terminals 22a, 22b, 22c, second connection terminals 23a, 23b, 23c, U-phase output terminal 24a, V-phase output terminal 24b, W-phase output terminal 24c, and control terminals 25a, 25b, 25c.

[0084] The outer frame 21 is rectangular when viewed from above, and is surrounded by side walls 21a, 21b, 21c, and 21d. It should be noted that side walls 21a and 21c are the longer sides of the outer frame 21, and side walls 21b and 21d are the shorter sides. Furthermore, when viewed from above, the corners where the side walls 21a, 21b, 21c, and 21d connect do not necessarily have to be right angles. Such connecting parts are, for example, as shown below. Figure 1 As shown, a chamfered radius (R) can be applied. The back faces of the outer frame 21 (side walls 21a, 21b, 21c, 21d) can form a single plane and be parallel to the XY plane.

[0085] The outer frame 21 includes cell housing portions 21e, 21f, and 21g along the sidewalls 21a and 21c (±X directions) at the center of its front side in the ±Y direction. The cell housing portions 21e, 21f, and 21g, when viewed from above, define the front side of the outer frame 21 as a rectangle and are open. Semiconductor cells 10a, 10b, and 10c are housed in the cell housing portions 21e, 21f, and 21g, respectively. Therefore, the dimensions of the cell housing portions 21e, 21f, and 21g can be dimensions capable of accommodating semiconductor cells 10a, 10b, and 10c.

[0086] When viewed from above, the outer frame 21 has first connecting terminals 22a, 22b, 22c and second connecting terminals 23a, 23b, 23c along the side wall 21a (±X direction) on the front side. The first connecting terminals 22a, 22b, 22c are positive side input terminals (P terminals), and the second connecting terminals 23a, 23b, 23c are negative side input terminals (N terminals).

[0087] Furthermore, the outer frame 21 has a U-phase output terminal 24a, a V-phase output terminal 24b, and a W-phase output terminal 24c along the side wall 21c (±X direction) on the front side. At this time, the first connection terminal 22a and the second connection terminal 23a are separated from the U-phase output terminal 24a by the unit storage portion 21e. The first connection terminal 22b and the second connection terminal 23b are separated from the V-phase output terminal 24b by the unit storage portion 21f. The first connection terminal 22c and the second connection terminal 23c are separated from the W-phase output terminal 24c by the unit storage portion 21g.

[0088] Additionally, when viewed from above, control terminals 25a, 25b, and 25c are respectively provided between the unit storage sections 21e, 21f, and 21g on the front of the outer frame 21 and the U-phase output terminal 24a, V-phase output terminal 24b, and W-phase output terminal 24c. For example... Figure 1 and Figure 2 As shown in the example, the control terminals 25a, 25b, and 25c can be configured to be divided into two for each unit storage section 21e, 21f, and 21g.

[0089] Such an outer frame 21 includes first connecting terminals 22a, 22b, 22c, second connecting terminals 23a, 23b, 23c, a U-phase output terminal 24a, a V-phase output terminal 24b, a W-phase output terminal 24c, and control terminals 25a, 25b, 25c, and is integrally molded using thermoplastic resin by injection molding. This constitutes the housing 20. The thermoplastic resin is, for example, polyphenylene sulfide resin, polybutylene terephthalate resin, polybutylene succinate resin, polyamide resin, or acrylonitrile butadiene styrene resin.

[0090] Furthermore, the first connecting terminals 22a, 22b, 22c, the second connecting terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, 25c are made of a metal with excellent conductivity. Such a metal is, for example, copper, aluminum, or an alloy with at least one of these as its main component. The surfaces of the first connecting terminals 22a, 22b, 22c, the second connecting terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, 25c may also be plated. In this case, the plating material used is, for example, nickel, a nickel-phosphorus alloy, or a nickel-boron alloy. The corrosion resistance of the first connecting terminals 22a, 22b, 22c, the second connecting terminals 23a, 23b, 23c, the U-phase output terminal 24a, the V-phase output terminal 24b, the W-phase output terminal 24c, and the control terminals 25a, 25b, 25c, after plating treatment, is improved.

[0091] It should be noted that, unless otherwise specified, the first connection terminals 22a, 22b, and 22c are referred to as first connection terminal 22. Similarly, the second connection terminals 23a, 23b, and 23c are also referred to as second connection terminals 23, and the U-phase output terminals 24a, V-phase output terminals 24b, and W-phase output terminals 24c are also referred to as output terminals 24. Similarly, the control terminals 25a, 25b, and 25c are also referred to as control terminals 25.

[0092] The sealing member that seals the semiconductor units 10a, 10b, and 10c can be a thermosetting resin. Examples of thermosetting resins include epoxy resin, phenolic resin, maleimide resin, and polyester resin. Epoxy resin is preferred. Furthermore, the sealing member may contain filler. The filler can be an insulating ceramic with high thermal conductivity.

[0093] The cooling device 3 includes an inlet 33a for refrigerant to flow into the interior and an outlet 33b for refrigerant flowing out of the interior. The cooling device 3 cools the semiconductor unit 10 by allowing heat from the semiconductor unit 10 to flow out via the refrigerant. The refrigerant used here may be, for example, water, antifreeze (ethylene glycol aqueous solution), or a long-lasting coolant. Additionally, the cooling device 3 may include a pump and a heat dissipation device (radiator). The pump draws refrigerant into the inlet 33a of the cooling device 3 and returns refrigerant flowing out of the outlet 33b to the inlet 33a, thus circulating the refrigerant. The heat dissipation device receives the refrigerant flowing out of the cooling device 3 and dissipates the heat from the refrigerant that has conducted heat from the semiconductor unit 10 to the outside.

[0094] Such a cooling device 3 has a top plate 31, an annular sidewall 32 connected to the back of the top plate 31, and a cooling base plate 33 opposite the top plate 31 and connected to the back of the sidewall 32. In top view, the top plate 31 is a rectangle surrounded by its long and short sides. The corners of the top plate 31 can be chamfered (R-shaped) in top view. Semiconductor units 10a, 10b, and 10c are bonded to the front of the top plate 31 along the ±X directions. The sidewall 32 is annular and continuously formed on the back of the top plate 31. The cooling base plate 33 is flat and has the same shape as the top plate 31 in top view. The corners of the cooling base plate 33 can also be chamfered (R-shaped).

[0095] Multiple heat sinks (not shown) are formed on the back side of the top plate 31 corresponding to the area where semiconductor units 10a, 10b, and 10c are arranged. Each heat sink is, for example, a flat plate shape parallel to the XZ plane and arranged side by side in the Y direction. Additionally, the bottom surface of the cooling base plate 33 has inlet 33a and outlet 33b for refrigerant to flow in and out. At the inlet 33a and outlet 33b, a water supply head is installed in the sealing area surrounding the inlet 33a and outlet 33b via an annular rubber gasket. A water supply pipe connected to a pump is installed at the water supply head.

[0096] Next, use Figure 3 and Figure 4 The semiconductor unit 10 will be described. Figure 3 It is a top view of the semiconductor units included in a semiconductor device. Figure 4 This is a cross-sectional view of the semiconductor units included in a semiconductor device. It should be noted that... Figure 3 The diagram shows the connection of the first connection terminal 22, the second connection terminal 23, and the output terminal 24 to the semiconductor unit 10. Figure 4 yes Figure 3 A cross-sectional view at the point marked by a single-dotted line XX.

[0097] The semiconductor unit 10 includes an insulating circuit board 11, semiconductor chips 12a and 12b, and lead frames 13a and 13b. Semiconductor chips 12a and 12b are bonded to the insulating circuit board 11 via solder layers. Lead frames 13a and 13b are bonded to semiconductor chips 12a and 12b via solder layers, respectively.

[0098] The insulating circuit board 11 includes an insulating plate 11a, wiring boards 11b1, 11b2, and 11c, and a metal plate 11d. The insulating plate 11a and the metal plate 11d are rectangular when viewed from above. Furthermore, the corners of the insulating plate 11a and the metal plate 11d can be chamfered (R-shaped or C-shaped). The metal plate 11d is smaller than the insulating plate 11a when viewed from above and is formed inside the insulating plate 11a.

[0099] The insulating board 11a is made of a material with excellent insulation and thermal conductivity. Such an insulating board 11a can be made of ceramic or insulating resin. Examples of ceramics include alumina, aluminum nitride, and silicon nitride. Examples of insulating resins include phenolic paper substrates, epoxy paper substrates, glass composite substrates, and glass epoxy boards.

[0100] Wiring boards 11b1, 11b2, and 11c are formed on the front side of insulating plate 11a. Wiring boards 11b1, 11b2, and 11c are made of a copper-containing metal with excellent conductivity. Such a metal may be, for example, an alloy containing aluminum in addition to copper.

[0101] Wiring board 11b2 occupies half of the front surface of insulating board 11a on the +X direction side, and is the entire area from the -Y direction edge to the +Y direction edge. Wiring board 11b1 occupies half of the front surface of insulating board 11a on the -X direction side. Wiring board 11c is formed from the +Y direction edge towards the -Y direction edge, and is spaced apart from the -Y direction edge. Wiring board 11c occupies the area of ​​the front surface of insulating board 11a surrounded by wiring boards 11b1 and 11b2.

[0102] Wiring boards 11b1, 11b2, and 11c are formed on the front side of the insulating plate 11a as described below. A metal plate is formed on the front side of the insulating plate 11a, and the wiring boards 11b1, 11b2, and 11c of a predetermined shape are obtained by etching or other processes on the metal plate. Alternatively, wiring boards 11b1, 11b2, and 11c, pre-cut from the metal plate, can be pressed onto the front side of the insulating plate 11a. It should be noted that wiring boards 11b1, 11b2, and 11c are just one example. The number, shape, size, and position of the wiring boards can be appropriately selected as needed.

[0103] A metal plate 11d is formed on the back side of the insulating plate 11a. The metal plate 11d is rectangular. The area of ​​the metal plate 11d in top view is smaller than the area of ​​the insulating plate 11a, but larger than the area of ​​the region where the wiring boards 11b1, 11b2, and 11c are formed. The corners of the metal plate 11d may be chamfered (R-shaped or C-shaped). For example, the metal plate 11d is formed on the entire surface of the insulating plate 11a, excluding the edge portion. The metal plate 11d is configured with a metal with excellent thermal conductivity as the main component. The metal is, for example, copper, aluminum, or an alloy containing at least one of these.

[0104] The insulating circuit board 11 with such a configuration can be, for example, a DCB (Direct Copper Bonding) substrate, an AMB (Active Metal Brazed) substrate, or a resin insulating substrate. The insulating circuit board 11 can be mounted on the front side of the top plate 31 of the cooling device 3 via bonding members (not shown). Heat generated on the semiconductor chips 12a and 12b can be conducted to the cooling device 3 via wiring boards 11b1 and 11b2, insulating plate 11a, and metal plate 11d for heat dissipation.

[0105] Semiconductor chips 12a and 12b include power device elements made of silicon. The power device element is an RC-IGBT. The RC-IGBT combines the functions of an IGBT as a switching element and a FWD (Free Wheeling Diode) as a diode element.

[0106] The front side of the semiconductor chip 12a is rectangular when viewed from above, and it has a gate electrode 12a1 and an emitter 12a2 (output electrode) serving as the main electrode. In this example, the gate electrode 12a1 is disposed on one short side of the front side of the semiconductor chip 12a. The gate electrode 12a1 is connected to an electrode connected to a control terminal 25 via a bonding wire 26. The emitter 12a2 is disposed on the other short side of the front side of the semiconductor chip 12a. In addition, a collector electrode 12a3 (input electrode) serving as the main electrode is provided on the back side of the semiconductor chip 12a.

[0107] Semiconductor chip 12b also has the same configuration as semiconductor chip 12a. A gate electrode 12b1 and an emitter 12b2 are provided on the front side of semiconductor chip 12b, and a collector electrode (not shown) is provided on the back side of semiconductor chip 12b.

[0108] Leadframe 13a connects the emitter 12a2 on the front side of semiconductor chip 12a to wiring board 11c. Leadframe 13a is bonded to emitter 12a2 via solder layer 14a. Additionally, a second connection terminal 23 is connected to wiring board 11c. Conversely, leadframe 13b connects the emitter 12b2 on the front side of semiconductor chip 12b to wiring board 11b1. Leadframe 13b is bonded to emitter 12b2 of semiconductor chip 12b via solder layer (not shown). Additionally, an output terminal 24 is connected to wiring board 11b1.

[0109] Lead frames 13a and 13b are made of a copper-containing metal with excellent electrical conductivity. Such a metal could be, for example, an alloy containing aluminum in addition to copper.

[0110] The collector 12a3 on the back side of semiconductor chip 12a is bonded to wiring board 11b1 via solder layer 14b. The collector on the back side of semiconductor chip 12b is bonded to wiring board 11b1 via solder layer.

[0111] With the above configuration, the semiconductor unit 10 constitutes a single-phase inverter circuit. The upper arm of the half-bridge circuit is formed by wiring board 11b2, semiconductor chip 12b, lead frame 13b, and wiring board 11b1. The lower arm of the half-bridge circuit is formed by wiring board 11b1, semiconductor chip 12a, lead frame 13a, and wiring board 11c. The upper and lower arms are connected by wiring board 11b1, and the output terminal 24 connected to wiring board 11b1 becomes the M terminal, which is the output terminal of the half-bridge circuit. The first connection terminal 22 connected to wiring board 11b2 becomes the P terminal, which is the positive input terminal of the half-bridge circuit, and the second connection terminal 23 connected to wiring board 11c becomes the N terminal, which is the negative output terminal of the half-bridge circuit. Furthermore, the switching operation of semiconductor chips 12a and 12b is controlled by a control signal input from control terminal 25 to the gate electrodes 12a1 and 12b1.

[0112] Next, use Figure 5 Further explanation of the composition of semiconductor chips 12a and 12b. Figure 5 This is a top view of a semiconductor chip.

[0113] An active portion 12a4 is provided on the semiconductor chip 12a. The active portion 12a4 is a region where a main current flows between the front and back surfaces of the semiconductor chip 12a when the semiconductor device 1 is operating. It should be noted that an emitter 12a2 is provided on the front surface of the active portion 12a4, but... Figure 5 Omitted in .

[0114] The active portion 12a4 includes a transistor region I containing an IGBT (Integrated Geometric Spectrometer) and a diode region F containing a diode element (FWD). Figure 5 In this example, transistor region I and diode region F are arranged alternately in the X direction. Transistor region I has a P+ type collector region in the area connected to the back side of semiconductor chip 12a. Diode region F has an N+ type cathode region in the area connected to the back side of semiconductor chip 12a. In this specification, the area where the collector region is provided is referred to as transistor region I. That is, transistor region I is the area that overlaps with the collector region when viewed from above. In addition, an N-type emitter region, a P-type base region, and a gate structure including a gate conductive portion and a gate insulating film are periodically arranged on the front side of transistor region I.

[0115] The gate electrode 12a1, which is disposed on the front side of the semiconductor chip 12a, is electrically connected to the conductive portion of the gate trench portion of the active portion 12a4. It should be noted that, in addition to the gate electrode 12a1 for inputting gate control signals, electrodes for current detection and / or temperature detection may also be disposed on the front side of the semiconductor chip 12a.

[0116] Furthermore, the semiconductor chip 12a includes a voltage-resistant structure 12a5 disposed on the outer periphery of the active portion 12a4. The voltage-resistant structure 12a5 mitigates electric field concentration on the front side of the semiconductor chip 12a. Additionally, the voltage-resistant structure 12a5 may also include a protective ring 12a6. The protective ring 12a6 is a P-type region in contact with the front side of the semiconductor chip 12a.

[0117] It should be noted that, Figure 5 The configuration of semiconductor chip 12a is shown in the figure, but semiconductor chip 12b also has the same configuration as semiconductor chip 12a.

[0118] However, the front sides of semiconductor chips 12a and 12b are connected to lead frames 13a and 13b via a solder layer. Additionally, the back sides of semiconductor chips 12a and 12b are also connected to wiring boards 11b1 and 11b2 via a solder layer. Electromigration can occur within this solder layer.

[0119] Figure 6 It is a diagram used to illustrate electromigration.

[0120] Electromigration is the phenomenon of metal atoms moving within a conductor when an electric current flows through it. For example... Figure 6 As shown, when current flows through conductor 4, electrons move in the opposite direction to the current. At this time, metal atoms collide with electrons and move in the same direction as the electrons. Vacancies are created in the traces left by the moving metal atoms, and the proliferation of vacancies leads to cracks. If vacancies and / or cracks occur, thermal resistance and / or wiring resistance may increase, temperature may rise, and / or the circuit may become unable to conduct electricity.

[0121] The primary cause of electromigration is high temperature and current density. In recent years, with the miniaturization of power modules such as the aforementioned semiconductor device 1, there has been a tendency for increased temperature and / or current density at the junctions of semiconductor chips, potentially leading to electromigration at these junctions. Specifically, in the aforementioned semiconductor device 1, electromigration occurs in the solder layers between the front side (active portion 12a4) of the semiconductor chips 12a and 12b and the lead frames 13a and 13b, and between the back side of the semiconductor chips 12a and 12b and the wiring boards 11b1 and 11b2, respectively. In these solder layers, copper atoms contained in the lead frames 13a and 13b and / or the wiring boards 11b1 and 11b2 move within the solder layers, and the moving copper alloys with the tin contained in the solder layers to form the solder layer. Along with the solder layer, electromigration also occurs in the alloy layer within the solder layer and at the interfaces between the solder layer and the lead frames 13a and 13b and the wiring boards 11b1 and 11b2. These can also lead to vacancies in the traces of copper movement, and increase thermal resistance and wiring resistance. In addition, lead frames 13a, 13b and / or wiring boards 11b1, 11b2 can also lead to vacancies in the traces of copper atomic movement, and increase thermal resistance and wiring resistance.

[0122] Here, use Figure 7 A comparative example illustrating the cross-sectional configuration of the semiconductor unit 10 included in the semiconductor device 1 is described, and using... Figure 8 and Figure 9 Explain the formation of the alloy layer in the comparative example.

[0123] Figure 7 This is a diagram showing a comparative example of the cross-sectional configuration of a semiconductor cell. Figure 7 Show Figure 3 A portion of the cross section at the single-dotted dashed line YY.

[0124] First, the stacked structure of the front and back sides of the semiconductor chip 12a will be explained. The emitter 12a2 formed on the front side of the semiconductor chip 12a (see reference) Figure 3 and Figure 4 The semiconductor chip 12a is covered by a plating layer 15a (third plating layer). Additionally, a collector electrode 12a3 (see reference 15a3) is formed on the back side of the semiconductor chip 12a. Figure 4 The semiconductor chip 12a is covered by plating layer 15b (the fourth plating layer). Plating layers 15a and 15b are primarily composed of nickel or nickel-containing alloys (such as nickel-phosphorus alloys). The plating materials constituting plating layers 15a and 15b do not contain tin. It should be noted that because the semiconductor chip 12a is shaped to bulge downwards due to heating during plating bonding, plating layer 15a becomes thicker than plating layer 15b.

[0125] Furthermore, on the front side of the semiconductor chip 12a, the lead frame 13a and the plating layer 15a are bonded via a solder layer 14a (first solder layer). On the back side of the semiconductor chip 12a, the wiring board 11b1 of the insulating circuit board 11 and the plating layer 15b are bonded via a solder layer 14b (second solder layer). The solder material constituting the solder layers 14a and 14b is mainly composed of a tin-containing alloy. The lead frame 13a and the wiring board 11b1 are made of a copper-containing alloy (such as a copper-aluminum alloy).

[0126] Here, when solder layer 14a is used to bond lead frame 13a and plating layer 15a, a tin-copper alloy layer 16a (IMC layer, IMC: Intermetallic Compound) is formed at the bonding interface between solder layer 14a and lead frame 13a as a reaction layer through interfacial reaction between molten solder material and copper base material of lead frame 13a. At this time, a tin-copper alloy layer 16b is also formed at the bonding interface between solder layer 14a and plating layer 15a due to the diffusion of copper atoms due to thermal migration.

[0127] Furthermore, when solder layer 14b is used to bond wiring board 11b1 and plating layer 15b, a tin-copper alloy layer 16c (IMC layer) as a reaction layer is formed at the bonding interface between solder layer 14b and wiring board 11b1 through an interfacial reaction between the molten solder material and the copper base material of wiring board 11b1. Such tin-copper alloy layers 16a to 16c become brittle, especially when they are thick. For example, if stress is generated at the bonding interface through thermal cycling and / or ΔTjP / C, cracks may occur in the tin-copper alloy layers 16a to 16c, and peeling may occur due to crack propagation.

[0128] Next, use Figure 8 and Figure 9 Describe the state of the tin-copper alloy layers 16a to 16c when energized.

[0129] Figure 8 This is the first figure showing an example of the formation of a tin-copper alloy layer in a comparative example. Figure 8 Shown in Figure 7 In the comparative example, an example of the state change of the tin-copper alloy layers 16a to 16c when the transistor region I of the semiconductor chip 12a is energized. When the transistor region I is energized, the current flows in the upward direction (+Z direction) as shown in the figure, and the electrons move in the downward direction (-Z direction) as shown in the figure.

[0130] At this time, in region 17a of solder layer 14a opposite to transistor region I (the region overlapping transistor region I when viewed from above), copper atoms migrate from lead frame 13a by electromigration and react with the tin in solder layer 14a. As a result, a local alloy layer 16a1 corresponding to region 17a grows in tin-copper alloy layer 16a, increasing its thickness. Furthermore, local alloy layer 16a1 also grows through the migration of copper atoms contained within it. Additionally, in region 17a of solder layer 14a, copper atoms from lead frame 13a and / or local alloy layer 16a1 are transported to semiconductor chip 12a side by electromigration. As a result, a local alloy layer 16b1 corresponding to region 17a also grows in tin-copper alloy layer 16b, increasing its thickness. It is believed that, along with this, the number of vacancies in the lead frame 13a, the interface between the lead frame 13a and the solder layer 14a, and the local alloy layers 16a1 and 16b1 increases.

[0131] Thus, through electromigration accompanying current flow, the tin-copper alloy layer in solder layer 14a grows and thickens, becoming more prone to cracking. This cracking in the tin-copper alloy layer, along with the proliferation of vacancies in lead frame 13a, solder layer 14a, and local alloy layers 16a1 and 16b1, leads to increased thermal resistance and wiring resistance in region 17a.

[0132] It should be noted that the local alloy layer 16b2 in the tin-copper alloy layer 16b, corresponding to region 17b opposite to diode region F (the region overlapping diode region F when viewed from above), grows thicker through diffusion of copper atoms via thermal migration. Therefore, region 17b also becomes more prone to developing cracks and vacancies, similar to region 17a.

[0133] Figure 9 This is the second figure showing an example of the formation of the tin-copper alloy layer in the comparative example. Figure 9 Shown in Figure 7 In the comparative example, an example of the state change of the tin-copper alloy layers 16a to 16c when the diode region F of the semiconductor chip 12a is energized. When the diode region F is energized, the current flows in the downward direction (-Z direction) as shown in the figure, and the electrons move in the upward direction (+Z direction) as shown in the figure.

[0134] At this time, in region 17b (the region overlapping with diode region F when viewed from above) of solder layer 14b opposite to diode region F, copper atoms migrate from wiring board 11b1 through electromigration and react with tin atoms in solder layer 14b. As a result, a local alloy layer 16c2 corresponding to region 17b grows in tin-copper alloy layer 16c, its thickness increases, and it becomes more prone to cracking. Furthermore, local alloy layer 16c2 also grows through the migration of copper atoms contained within it. It is believed that this is accompanied by an increase in vacancies in wiring board 11b1, the interface between wiring board 11b1 and solder layer 14b, and local alloy layer 16c2. There is a problem that the thermal resistance and wiring resistance of region 17b will increase due to the generation of cracks in the tin-copper alloy layer and the increased number of vacancies in wiring board 11b1, solder layer 14b, and local alloy layer 16c2.

[0135] It should be noted that even in region 17b of solder layer 14a, opposite to diode region F, although the amount is small, copper atoms are transported from local alloy layer 16b2 to lead frame 13a side via electromigration. As a result, the local alloy layer 16a2 corresponding to region 17b in tin-copper alloy layer 16a grows, and its thickness increases. Furthermore, in region 17a of solder layer 14a, opposite transistor region I, copper atoms also diffuse via thermal migration. As a result, the local alloy layer 16b1 corresponding to region 17a in tin-copper alloy layer 16b grows, and its thickness increases. Therefore, region 17a also becomes more prone to cracking and vacancies, similar to region 17b.

[0136] As described above, in the semiconductor chip 12a containing the RC-IGBT, current flows bidirectionally. Therefore, electromigration occurs in both the solder layer 14a on the front side and the solder layer 14b on the back side of the semiconductor chip 12a, which may lead to an increase in thermal resistance and wiring resistance on both the front and back sides of the semiconductor chip 12a.

[0137] To address this issue, in this embodiment, at least the surface of the lead frame 13a that bonds to the front side of the semiconductor chip 12a, and the surface of the wiring board 11b1 that bonds to the back side of the semiconductor chip 12a, are covered with a nickel-containing plating layer. This suppresses electromigration phenomena such as the movement of copper atoms in the solder layers 14a and 14b, and also suppresses the expansion of the tin-copper alloy layer and the proliferation of vacancies in the solder layer, alloy layer, lead frame 13a, and wiring board 11b1. As a result, it prevents an increase in thermal resistance and wiring resistance, and improves the long-term reliability of the semiconductor device 1.

[0138] The following uses Figures 10-14 An example of the configuration of the semiconductor unit 10 in the embodiment is described.

[0139] Figure 10 This is a diagram illustrating a first example of the formation of a plating layer in a semiconductor cell. Figure 10 In the example, relative to Figure 7 The comparative example adds plating layer 18a (first plating layer) and plating layer 18b (second plating layer). Specifically, the surface of the semiconductor chip 12a in the lead frame 13a is covered by plating layer 18a. Additionally, the surface of the wiring board 11b1 is covered by plating layer 18b. Plating layers 18a and 18b are primarily composed of nickel or nickel-containing alloys (such as nickel-phosphorus alloys). The plating materials constituting plating layers 18a and 18b do not contain tin.

[0140] By forming the plating layer 18a as described above, when the transistor region I is energized, copper atoms in the lead frame 13a become less likely to migrate to the solder layer 14a, and the possibility of electromigration in the solder layer 14a is reduced. Furthermore, by forming the plating layer 18b as described above, when the diode region F is energized, copper atoms in the wiring board 11b1 become less likely to migrate to the solder layer 14b, and the possibility of electromigration in the solder layer 14b is reduced. As a result, while suppressing the formation / expansion of the tin-copper alloy layer in the solder layers 14a and 14b, the formation of vacancies in the solder layers 14a and 14b, the alloy layer, the lead frame 13a, and the wiring board 11b1 is suppressed, thereby reducing the increase in thermal resistance and wiring resistance. Therefore, the long-term reliability of the semiconductor device 1 can be improved.

[0141] Furthermore, during the formation of solder layers 14a and 14b, the possibility of copper atoms diffusing into solder layers 14a and 14b due to thermal migration can be reduced. As a result, the movement and / or expansion of the tin-copper alloy layer in solder layers 14a and 14b are suppressed, and the generation of vacancies in solder layers 14a and 14b, alloy layers, lead frame 13a, and wiring board 11b1 is suppressed, thereby reducing the increase in thermal resistance and wiring resistance.

[0142] Figure 11 This is a diagram illustrating a second example of the formation of a plating layer in a semiconductor cell. Figure 11 In the example, with Figure 10 The plating layers 18a and 18b are formed in such a way that the thickness D2 of plating layer 18b is greater than the thickness D1 of plating layer 18a. For example, when the thickness of semiconductor chip 12a is about 50 μm or more and about 100 μm or less, the thickness D2 of plating layer 18b is several tens of μm, and the thickness D1 of plating layer 18a can be set to be more than 1 / 2 and less than 1 / 3 of the thickness D2.

[0143] In semiconductor chip 12a, the current density in diode region F becomes greater than the current density in transistor region I. Therefore, the amount of copper atoms moving from wiring board 11b1 to solder layer 14b when diode region F is energized is greater than the amount of copper atoms moving from lead frame 13a to solder layer 14a when transistor region I is energized. As a result, the thermal resistance and wiring resistance caused by electromigration are more likely to increase when diode region F is energized compared to when transistor region I is energized.

[0144] Through such Figure 11 As shown, the thickness D2 of plating 18b is made greater than the thickness D1 of plating 18a, thereby increasing the suppression effect of electromigration when the diode region F is energized. As a result, the increase in thermal resistance and wiring resistance can be prevented more reliably.

[0145] Figure 12 This is a diagram showing a third example of the formation of a coating in a semiconductor cell.

[0146] exist Figure 12 In the example, it is constituted as follows: Figure 12 The thickness of the local plating 18a1 in region 17a (first region) opposite to transistor region I and the thickness of the local plating 18a2 in region 17b (second region) opposite to diode region F are different. Specifically, the local plating 18a2 corresponding to diode region F is formed to be thicker than the local plating 18a1 corresponding to transistor region I.

[0147] In addition, it constitutes Figure 12 The thickness of the local plating 18b1 in region 17a (third region) opposite to transistor region I and the thickness of the local plating 18b2 in region 17b (fourth region) opposite to diode region F are different. Specifically, the local plating 18b2 corresponding to diode region F is formed to be thicker than the local plating 18b1 corresponding to transistor region I.

[0148] As described above, in semiconductor chip 12a, the current density in diode region F becomes greater than the current density in transistor region I. Figure 12 As shown, by making the plating thickness corresponding to diode region F thicker than the plating thickness corresponding to transistor region I, the suppression effect of electromigration during diode region F when energized can be increased. As a result, in regions 17a and 17b, the increase in thermal resistance and wiring resistance can be prevented more reliably.

[0149] Furthermore, with the thickness of the plating layers 18a and 18b, when forming the solder layers 14a and 14b, the region 17b corresponding to the diode region F becomes less susceptible to copper atom diffusion due to thermal migration compared to the region 17a corresponding to the transistor region I. Therefore, the latter becomes less likely to form a tin-copper alloy layer compared to the former. Consequently, after the semiconductor chip 12a is powered on, the region 17b corresponding to the diode region F takes longer to grow a substantial tin-copper alloy layer compared to the region 17a corresponding to the transistor region I in the solder layers 14a and 14b. As a result, the time before thermal resistance and wiring resistance increase to the point of affecting the characteristics of the semiconductor device 1 can be extended, thereby improving the reliability of the semiconductor device 1.

[0150] Figure 13 This is a diagram showing a fourth example of the formation of a coating in a semiconductor cell.

[0151] and Figure 12 Similarly, in Figure 13 In the example, the thicknesses of the partial plating layer 18a1 in region 17a opposite to transistor region I and the partial plating layer 18a2 in region 17b opposite to diode region F are different. However, compared with Figure 12 Unlike the transistor region I, the local plating layer 18a1 is formed thicker than the local plating layer 18a2 corresponding to the diode region F. On the other hand, with… Figure 12 Similarly, in the plating layer 18b, one of the local plating layers 18b2 corresponding to the diode region F is formed to be thicker than the local plating layer 18b1 corresponding to the transistor region I.

[0152] like Figure 8 As shown, when current is applied to transistor region I, electrons move in the downward direction (-Z direction). Therefore, electromigration is observed as the movement of copper atoms contained in lead frame 13a towards solder layer 14a. Figure 13 As shown, by making the local plating layer 18a1 corresponding to the transistor region I in the plating layer 18a thicker than the local plating layer 18a2 corresponding to the diode region F, it becomes difficult for copper atoms to move from the lead frame 13a to the solder layer 14a.

[0153] In addition, such as Figure 9 As shown, when current is applied to diode region F, electrons move in the upward direction (+Z direction) as illustrated. Therefore, electromigration is observed as the movement of copper atoms contained in wiring board 11b1 towards solder layer 14b. Figure 13As shown, by making the local plating layer 18b2 corresponding to the diode region F in the plating layer 18b thicker than the local plating layer 18b1 corresponding to the transistor region I, it becomes difficult for copper atoms to move from the lead-in board 11b1 to the solder layer 14b.

[0154] Therefore, through Figure 13 The structure can suppress electromigration and more reliably prevent the increase of thermal resistance and wiring resistance in regions 17a and 17b.

[0155] Figure 14 This is a diagram showing a fifth example of the formation of a plating layer in a semiconductor cell.

[0156] exist Figure 14 In this example, plating 18a is not formed on the entire surface of lead frame 13a, but only in region 17a opposite to transistor region I, forming a partial plating 18a1. Similarly, plating 18b is not formed on the entire surface of wiring board 11b1, but only in diode region F, forming a partial plating 18b2.

[0157] As described above, when transistor region I is energized, electromigration is observed as the movement of copper atoms contained in lead frame 13a towards solder layer 14a. Figure 14 As shown, by forming a local plating layer 18a1 only in the region 17a opposite to the transistor region I, it is possible to make it difficult for copper atoms to move from the lead frame 13a to the solder layer 14a.

[0158] Furthermore, as described above, when the diode region F is energized, electromigration is observed as the movement of copper atoms contained in the wiring board 11b1 towards the solder layer 14b. Figure 14 As shown, by forming a local plating layer 18b2 only in the diode region F, it is possible to make it difficult for copper atoms to move from the wiring board 11b1 to the solder layer 14b.

[0159] Therefore, through Figure 14 The structure can suppress electromigration and more reliably prevent the increase of thermal resistance and wiring resistance in regions 17a and 17b.

[0160] It should be noted that, in the above Figures 10-14 The diagram illustrates the stacked structure on both sides of semiconductor chip 12a, but the stacked structure on both sides of semiconductor chip 12b can also be the same.

Claims

1. A semiconductor device, characterized in that: have: A semiconductor chip having an upper surface and a lower surface, and transistor regions and diode regions arranged alternately in a direction along the upper surface and the lower surface; a lead frame containing copper and arranged at a position on the upper surface side of the semiconductor chip; a first plating layer containing nickel and formed on a surface of the lead frame on the semiconductor chip side; a first solder layer containing tin and bonding the upper surface of the semiconductor chip to the first plating layer; an insulating circuit substrate arranged to face the lower surface of the semiconductor chip and having a wiring layer containing copper formed on a surface on the semiconductor chip side; a second plating layer containing nickel and formed on a surface of the wiring layer on the semiconductor chip side; and The second solder layer contains tin and bonds the lower surface of the semiconductor chip to the second plating layer.

2. The semiconductor device according to claim 1, wherein: The thickness of the second plating layer is greater than the thickness of the first plating layer.

3. The semiconductor device according to claim 1, wherein: In the first plating layer, a first region of the surface of the lead frame on the semiconductor chip side facing the transistor region has a different thickness from a second region facing the diode region. In the second plating layer, a thickness of a third region facing the transistor region and a thickness of a fourth region facing the diode region on the surface of the insulating circuit substrate on the semiconductor chip side are different from each other.

4. The semiconductor device according to claim 3, wherein: In the first plating layer, the thickness of the second region is greater than the thickness of the first region, In the second plating layer, a thickness of the fourth region is greater than a thickness of the third region.

5. The semiconductor device according to claim 4, wherein: In the semiconductor chip, a current density when the diode region is energized is greater than a current density when the transistor region is energized.

6. The semiconductor device according to claim 3, wherein: In the first plating layer, the thickness of the first region is greater than the thickness of the second region, In the second plating layer, a thickness of the fourth region is greater than a thickness of the third region.

7. The semiconductor device according to claim 3, wherein: The first plating layer is formed only in the first region of the surface of the lead frame on the semiconductor chip side. The second plating layer is formed only in the fourth region of the surface of the insulating circuit substrate on the semiconductor chip side.

8. The semiconductor device according to claim 1, wherein: The lead frame is connected to the emitter of the semiconductor chip via the first solder layer. The wiring layer of the insulating circuit substrate is connected to the collector electrode of the semiconductor chip via the second solder layer.

9. The semiconductor device according to claim 8, wherein: The semiconductor device further comprises: a third plating layer containing nickel and formed on a surface of the semiconductor chip that is opposite to the first solder layer on the upper surface; as well as A fourth plating layer contains nickel and is formed on a surface of the semiconductor chip that faces the second solder layer on the lower surface.

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