Semiconductor device and manufacturing method thereof

Abstract

The invention provides a semiconductor device and a manufacturing method thereof, and the semiconductor device comprises a substrate, a first dielectric layer is formed on the substrate, a plurality of first conductive structures and a first metal layer are formed in the first dielectric layer, and the plurality of first conductive structures are electrically connected with the first metal layer; the lower pole plate, the second dielectric layer and the upper pole plate are formed on the first dielectric layer from bottom to top, and the lower pole plate is electrically connected with the plurality of first conductive structures; and a plurality of third conductive structures and a fourth conductive structure, the plurality of third conductive structures are formed on the upper pole plate and are electrically connected with the upper pole plate, and the fourth conductive structure is electrically connected with the first metal layer. According to the technical scheme, the quality factor of the capacitor is improved, and TDDB failure is avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor integrated circuit manufacturing, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In existing RF devices, when making MIM (Metal Insulator Metal) capacitors, the material of the electrode plate is mostly metal nitride or metal. For PIP capacitors, the material of the electrode plate is polysilicon. When the material of the electrode plate is metal nitride or polysilicon, the resistance of the electrode plate is relatively high, resulting in a low quality factor of the MIM capacitor and less gain for the LNA (low noise amplifier); when the material of the electrode plate is metal, although the resistance of the electrode plate is low, during the manufacturing process of the MIM capacitor, the metal is prone to irregular crystallization in the high-temperature process, resulting in poor surface roughness of the electrode plate, which leads to a thinning of the dielectric layer thickness at the abnormal protruding position and easy occurrence of tip discharge, which in turn causes the protruding position to be easily broken down, that is, leading to TDDB (time dependent dielectric breakdown) failure.

[0003] Therefore, how to improve the quality factor of the capacitor while avoiding TDDB failure is an urgent problem to be solved. Summary of the invention

[0004] The object of the present invention is to provide a semiconductor device and a method for manufacturing the same, so as to improve the quality factor of the capacitor while avoiding TDDB failure.

[0005] To achieve the above object, the present invention provides a semiconductor device, comprising:

[0006] A substrate, a first dielectric layer formed on the substrate, a plurality of first conductive structures and a first metal layer formed in the first dielectric layer, the plurality of first conductive structures being electrically connected to the first metal layer;

[0007] A lower electrode plate, a second dielectric layer and an upper electrode plate are formed from bottom to top on the first dielectric layer, and the lower electrode plate is electrically connected to the plurality of first conductive structures;

[0008] A plurality of third conductive structures and a fourth conductive structure, wherein the plurality of third conductive structures are formed on the upper electrode plate and are electrically connected to the upper electrode plate, and the fourth conductive structure is electrically connected to the first metal layer.

[0009] Optionally, the upper plate, the second dielectric layer and the lower plate have the same area.

[0010] Optionally, the top surface area of ​​each of the first conductive structures is 0.1 to 0.2 times the area of ​​the lower electrode plate.

[0011] Optionally, the material of the lower electrode plate and the upper electrode plate is metal nitride or polysilicon.

[0012] Optionally, the semiconductor device further includes:

[0013] An etch stop layer is formed on the first dielectric layer, the etch stop layer has openings exposing the plurality of first conductive structures, and the lower electrode plate at least fills the openings.

[0014] Optionally, a second conductive structure is further formed in the first dielectric layer, and the fourth conductive structure is electrically connected to the first metal layer via the second conductive structure. The present invention also provides a method for manufacturing a semiconductor device, comprising:

[0015] Providing a substrate, wherein a first dielectric layer is formed on the substrate, a plurality of first conductive structures and a first metal layer are formed in the first dielectric layer, and the plurality of first conductive structures are electrically connected to the first metal layer;

[0016] Forming a lower electrode plate, a second dielectric layer and an upper electrode plate from bottom to top on the first dielectric layer, wherein the lower electrode plate is electrically connected to the plurality of first conductive structures;

[0017] A plurality of third conductive structures and a fourth conductive structure are formed, wherein the plurality of third conductive structures are formed on the upper electrode plate and are electrically connected to the upper electrode plate, and the fourth conductive structure is electrically connected to the first metal layer.

[0018] Optionally, the upper plate, the second dielectric layer and the lower plate have the same area.

[0019] Optionally, the top surface area of ​​each of the first conductive structures is 0.1 to 0.2 times the area of ​​the lower electrode plate.

[0020] Optionally, the material of the lower electrode plate and the upper electrode plate is metal nitride or polysilicon.

[0021] Optionally, before forming the lower electrode plate, the second dielectric layer and the upper electrode plate from bottom to top, the method for manufacturing the semiconductor device includes:

[0022] forming an etch stop layer on the first dielectric layer, wherein the etch stop layer covers the plurality of first conductive structures;

[0023] etching the etch stop layer to form openings exposing the plurality of first conductive structures;

[0024] Wherein, the lower electrode plate at least fills the opening. Optionally, a second conductive structure is further formed in the first dielectric layer, and the fourth conductive structure is electrically connected to the first metal layer through the second conductive structure.

[0025] Compared with the prior art, the technical solution of the present invention has the following beneficial effects:

[0026] 1. The semiconductor device of the present invention comprises: a substrate, a first dielectric layer is formed on the substrate, a plurality of first conductive structures and a first metal layer are formed in the first dielectric layer, and the plurality of first conductive structures are electrically connected to the first metal layer; a lower plate, a second dielectric layer and an upper plate from bottom to top are formed on the first dielectric layer, and the lower plate is electrically connected to the plurality of first conductive structures; a plurality of third conductive structures and a fourth conductive structure, the plurality of third conductive structures are formed on the upper plate and are electrically connected to the upper plate, and the fourth conductive structure is electrically connected to the first metal layer. The first conductive structure can be arranged below the entire area of ​​the lower plate, which can improve the quality factor of the capacitor while avoiding TDDB failure.

[0027] 2. The manufacturing method of the semiconductor device of the present invention comprises providing a substrate, on which a first dielectric layer is formed, in which a plurality of first conductive structures and a first metal layer are formed, and the plurality of first conductive structures are electrically connected to the first metal layer; forming a lower plate, a second dielectric layer and an upper plate from bottom to top on the first dielectric layer, and the lower plate is electrically connected to the plurality of first conductive structures; forming a plurality of third conductive structures and a fourth conductive structure, the plurality of third conductive structures are formed on the upper plate and are electrically connected to the upper plate, and the fourth conductive structure is electrically connected to the first metal layer. The first conductive structure can be arranged below the entire area of ​​the lower plate, which can improve the quality factor of the capacitor while avoiding TDDB failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a schematic structural diagram of a semiconductor device according to an embodiment of the present invention;

[0029] Figure 2 is a schematic structural diagram of a semiconductor device according to another embodiment of the present invention;

[0030] Figure 3 yes Figure 1 and Figure 2 A schematic top view of a capacitor in the semiconductor device shown;

[0031] Figure 4 is a flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;

[0032] Figure 5a to Figure 5h yes Figure 4 A schematic diagram of a device in a method for manufacturing a semiconductor device is shown.

[0033] Among them, Figure 1 to Figure 5h The reference numerals are described as follows:

[0034] 10-substrate; 11-first dielectric layer; 111-first metal layer; 112-etching stop layer; 113-opening; 12-first conductive structure; 121-first conductive layer; 122-first conductive plug; 13-second conductive structure; 131-second conductive layer; 132-second conductive plug; 14-lower plate; 141-lower plate material layer; 15-second dielectric layer; 151-second dielectric material layer; 16-upper plate; 161-upper plate material layer; 162-patterned photoresist layer; 17-third dielectric layer; 18-third conductive structure; 19-fourth conductive structure. DETAILED DESCRIPTION

[0035] In order to make the purpose, advantages and features of the present invention more clear, the semiconductor device and its manufacturing method and working method proposed by the present invention are further described in detail below. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention.

[0036] An embodiment of the present invention provides a semiconductor device, comprising: a substrate, a first dielectric layer formed on the substrate, a plurality of first conductive structures and a first metal layer formed in the first dielectric layer, the plurality of first conductive structures being electrically connected to the first metal layer; a lower electrode plate, a second dielectric layer and an upper electrode plate from bottom to top, formed on the first dielectric layer, the lower electrode plate being electrically connected to the plurality of first conductive structures; a plurality of third conductive structures and a fourth conductive structure, the plurality of third conductive structures being formed on the upper electrode plate and electrically connected to the upper electrode plate, the fourth conductive structure being electrically connected to the first metal layer.

[0037] See below Figure 1 to Figure 3 The semiconductor device provided by this embodiment is described in detail.

[0038] A first dielectric layer 11 is formed on the substrate 10 , a first metal layer 111 , a plurality of first conductive structures 12 and a second conductive structure 13 are formed in the first dielectric layer 11 , and the second conductive structure 13 is electrically connected to the plurality of first conductive structures 12 through the first metal layer 111 .

[0039] In another embodiment, the second conductive structure 13 may not be formed in the first dielectric layer 11 , and when the fourth conductive structure 19 is subsequently formed, it is directly connected to the first metal layer 111 , so that the fourth conductive structure 19 can be connected to the lower electrode 14 through the first metal layer 111 and multiple first conductive structures 12 .

[0040] The material of the substrate 10 can be any suitable base material known to those skilled in the art, for example, it can be at least one of the following materials: silicon, germanium, silicon germanium, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or semiconductor on insulator (SOI, such as silicon on insulator), etc.

[0041] A device structure such as a transistor (not shown) may be formed on the substrate 10, and the first dielectric layer 11 covers the device structure. The device structure is connected to an interconnection structure (not shown).

[0042] The second conductive structure 13 is located at one side of the plurality of first conductive structures 12 , and the number of the second conductive structure 13 may be one or more.

[0043] The first dielectric layer 11 exposes top surfaces of the plurality of first conductive structures 12 and the second conductive structure 13 .

[0044] The first metal layer 111 can be manufactured simultaneously with a metal layer (not shown) in the interconnect structure, and the first conductive structure 12 and the second conductive structure 13 can be manufactured simultaneously.

[0045] The first conductive structure 12 and the second conductive structure 13 may both include a conductive plug and a conductive layer, the first dielectric layer 11 exposes the top surface of the conductive layer, and the conductive layer is electrically connected to the first metal layer 111 through the conductive plug. Figure 1 As shown, the first conductive structure 12 includes a first conductive plug 122 and a first conductive layer 121, the second conductive structure 13 includes a second conductive plug 132 and a second conductive layer 131, the first conductive layer 121 is electrically connected to the first metal layer 111 through the first conductive plug 122, and the second conductive layer 131 is electrically connected to the first metal layer 111 through the second conductive plug 132. In this embodiment, the first conductive layer 121 and the second conductive layer 131 can be manufactured simultaneously with another metal layer (not shown) in the interconnect structure.

[0046] Alternatively, the first conductive structure 12 and the second conductive structure 13 each only include the conductive plug, and the first dielectric layer 11 exposes the top surface of the conductive plug. Figure 2As shown, the first conductive structure 12 only includes the first conductive plug 122 , and the second conductive structure 13 only includes the second conductive plug 132 .

[0047] A lower electrode plate 14 , a second dielectric layer 15 and an upper electrode plate 16 are formed from bottom to top on the first dielectric layer 11 , and the lower electrode plate 14 is electrically connected to the plurality of first conductive structures 12 .

[0048] Preferably, the semiconductor device further comprises: an etch stop layer 112 formed on the first dielectric layer 11, the etch stop layer 112 having openings (ie, Figure 5b The lower electrode plate 14 at least fills the opening 113. The opening 113 may also expose the top surface of the first dielectric layer 11 between adjacent first conductive structures 12.

[0049] Since the semiconductor device includes the etch stop layer 112, the etching can be stopped in the etch stop layer 112 when etching to form the upper plate 16, the second dielectric layer 15 and the lower plate 14, thereby preventing the first dielectric layer 11 from being etched. In other embodiments, the etch stop layer 112 may not be formed.

[0050] When the material of the lower electrode plate 14 and the upper electrode plate 16 is an opaque material, by forming the opening 113 in the etch stop layer 112, it is possible to identify and record the position of the opening 113, and align them according to the position of the opening 113 when executing the corresponding photolithography process for forming the upper electrode plate 16, the second dielectric layer 15 and the lower electrode plate 14, thereby avoiding the offset of the photolithography, thereby avoiding the offset of the positions of the upper electrode plate 16, the second dielectric layer 15 and the lower electrode plate 14 formed after etching.

[0051] The upper plate 16 , the second dielectric layer 15 and the lower plate 14 can be formed by the same photolithography process, so that the upper plate 16 , the second dielectric layer 15 and the lower plate 14 have the same area in a direction parallel to the surface of the substrate 10 .

[0052] The area of ​​the upper plate 16, the second dielectric layer 15 and the lower plate 14 in a direction parallel to the surface of the substrate 10 may be the same as the area of ​​the opening 113 in a direction parallel to the surface of the substrate 10, that is, the upper plate 16, the second dielectric layer 15 and the lower plate 14 are only located in the area where the opening 113 is located, and do not extend to the etching stop layer 112 outside the opening 113, that is, the upper and lower plates 16 / 14 are formed using the same mask as the opening 113; or, as Figure 1 and Figure 2 As shown, the area of ​​the upper plate 16, the second dielectric layer 15 and the lower plate 14 in a direction parallel to the surface of the substrate 10 can be larger than the area of ​​the opening 113 in a direction parallel to the surface of the substrate 10, that is, the upper plate 16, the second dielectric layer 15 and the lower plate 14 extend from the area where the opening 113 is located to the etching stop layer 112 outside the opening 113.

[0053] When the first conductive structure 12 includes the first conductive plug 122 and the first conductive layer 121, the bottom surface of the lower electrode plate 14 contacts the top surface of the first conductive layer 121, and the lower electrode plate 14 is electrically connected to the first conductive layer 121 in the first conductive structure 12; when the first conductive structure 12 only includes the first conductive plug 122, the bottom surface of the lower electrode plate 14 contacts the top surface of the first conductive plug 122, and the lower electrode plate 14 is electrically connected to the first conductive plug 122 in the first conductive structure 12.

[0054] Preferably, the material of the lower plate 14 and the upper plate 16 is metal nitride or polysilicon. When the material of the lower plate 14 and the upper plate 16 is metal, since the area of ​​the lower plate 14 and the upper plate 16 is large, the large area of ​​metal will easily produce irregular crystallization in the high temperature process, which will lead to poor surface roughness of the lower plate 14 and the upper plate 16, and the thickness of the second dielectric layer 15 at the abnormal protrusion on the surface of the lower plate 14 will be affected (for example, the thickness becomes thinner), and the abnormal protrusion on the surface of the lower plate 14 is prone to tip discharge, which will lead to the capacitor at the abnormal protrusion being easily broken down, that is, causing the TDDB (time dependent dielectric breakdown) failure of the capacitor. Therefore, the material of the lower plate 14 and the upper plate 16 is metal nitride or polysilicon, which can avoid the TDDB failure problem of the capacitor caused by the material of the lower plate 14 and the upper plate 16 being metal.

[0055] The metal nitride is, for example, a nitride of a metal such as aluminum, copper, tantalum, titanium or tungsten.

[0056] When the material of the lower electrode plate 14 and the upper electrode plate 16 is metal nitride, the capacitor is a MIM capacitor; when the material of the upper electrode plate 16 and the lower electrode plate 14 is polysilicon, the capacitor is a PIP capacitor.

[0057] The material of the second dielectric layer 15 is preferably a high-K (relative dielectric constant) dielectric, such as at least one of zinc oxide, hafnium oxide, titanium oxide, and zirconium oxide. It should be noted that the material of the second dielectric layer 15 can also be at least one of silicon oxide, silicon oxynitride, silicon nitride, and ONO (silicon oxide-silicon nitride-silicon oxide).

[0058] Preferably, the top surface area of ​​each of the first conductive structures 12 is 0.1 to 0.2 times the area of ​​the lower electrode plate 14 .

[0059] When the material of the first conductive structure 12 is metal (for example, aluminum, copper, tantalum, titanium or tungsten, etc.), since a large area of ​​metal is more likely to produce irregular crystallization in a high-temperature process, the top surface roughness of a large area of ​​metal is poor. If the top surface of the first conductive structure 12 is a large area of ​​metal, the thickness or roughness of the lower electrode 14, the second dielectric layer 15 and the upper electrode 16 above the abnormal protrusion on the top surface of the first conductive structure 12 will be affected (for example, the thickness becomes thinner), and the abnormal protrusion on the top surface of the first conductive structure 12 is prone to tip discharge, which in turn causes the capacitor at the abnormal protrusion to be easily broken down, that is, causing the TDDB (time dependent dielectric breakdown) failure of the capacitor. Therefore, by defining the top surface area of ​​each first conductive structure 12 as 0.1 to 0.2 times the area of ​​the lower electrode 14, that is, significantly reducing the top surface area of ​​a single first conductive structure 12, the irregular crystallization of each first conductive structure 12 in the high-temperature process can be significantly alleviated, avoiding the deterioration of the top surface roughness of the first conductive structure 12, thereby avoiding TDDB failure of the capacitor.

[0060] The semiconductor device further includes: a third dielectric layer 17 formed on the first dielectric layer 11 , and the third dielectric layer 17 covers the upper electrode plate 16 , the second dielectric layer 15 , the lower electrode plate 14 and the second conductive structure 13 .

[0061] If the etch stop layer 112 is formed on the first dielectric layer 11 , the third dielectric layer 17 is formed on the etch stop layer 112 .

[0062] The third dielectric layer 17 may be a single-layer structure or a multi-layer stacked structure.

[0063] The material of the first dielectric layer 11 and the third dielectric layer 17 may be at least one of silicon oxide, silicon oxynitride, silicon nitride and ONO (silicon oxide-silicon nitride-silicon oxide).

[0064] The plurality of third conductive structures 18 are formed on the upper electrode plate 16 , and the plurality of third conductive structures 18 are electrically connected to the upper electrode plate 16 , and the fourth conductive structure 19 is electrically connected to the first metal layer 111 .

[0065] The plurality of third conductive structures 18 and the fourth conductive structure 19 are formed in the third dielectric layer 17, the plurality of third conductive structures 18 are electrically connected to the upper electrode plate 16, the fourth conductive structure 19 can be electrically connected to the first metal layer 111 through the second conductive structure 13, the third dielectric layer 17 exposes the top surfaces of the third conductive structures 18 and the fourth conductive structures 19, the plurality of third conductive structures 18 are used to connect to the upper electrode plate 16, and the fourth conductive structure 19 is used to connect to the lower electrode plate 14. Since the second conductive structure 13 is electrically connected to the plurality of first conductive structures 12, and the plurality of first conductive structures 12 are electrically connected to the lower electrode plate 14, the fourth conductive structure 19 can be connected to the lower electrode plate 14.

[0066] In the existing capacitor, in order to connect the lower plate, the area of ​​the lower plate is larger than that of the upper plate, and the conductive structure for connecting the upper plate is formed on the top surface of the upper plate, and the conductive structure for connecting the lower plate is formed on the top surface of the lower plate outside the upper plate; because the effective area for providing the capacitance value is the area directly facing the upper plate and the lower plate, the area of ​​the lower plate facing the upper plate will be designed to be very large, and the area of ​​the lower plate outside the upper plate is designed to be very small, resulting in a small number of conductive structures set for connecting the lower plate and a small contact area, which results in a high contact resistance between the conductive structure for connecting the lower plate and the lower plate when the material of the lower plate is metal nitride or polysilicon, which in turn leads to a low quality factor of the capacitor.

[0067] In the present invention, since the lower electrode plate 14 is connected through the plurality of first conductive structures 12 below it, the first conductive structure 12 can be set below the entire area of ​​the lower electrode plate 14, that is, a large number of the first conductive structures 12 can be set below the entire area of ​​the lower electrode plate 14. Compared with the existing capacitor, the area of ​​the lower electrode plate 14 for setting the conductive structure is significantly increased, so that the number of conductive structures for connecting the lower electrode plate 14 is significantly increased, and thus the contact area between the conductive structure for connecting the lower electrode plate 14 and the lower electrode plate 14 is significantly increased, so that when the material of the lower electrode plate 14 is metal nitride or polysilicon, the contact resistance between the conductive structure for connecting the lower electrode plate 14 and the lower electrode plate 14 can be significantly reduced, thereby improving the quality factor of the capacitor. In one embodiment, the quality factor of the capacitor when the material of the lower electrode plate 14 is metal nitride or polysilicon can be close to or equal to the quality factor of the capacitor when the material of the lower electrode plate 14 is metal.

[0068] Therefore, it can be seen from the above content that since the lower electrode plate 14 is connected through the multiple first conductive structures 12 below it, and the upper electrode plate 16 is connected through the multiple third conductive structures 18 above it, the quality factor of the capacitor can still be improved when the material of the upper electrode plate 16 and the lower electrode plate 14 is selected from metal nitride or polysilicon. At the same time, the TDDB failure problem of the capacitor caused by the selection of metal as the material of the upper electrode plate 16 and the lower electrode plate 14 can be avoided.

[0069] Among them, Figure 3 As shown, in the direction perpendicular to the surface of the substrate 10, the area of ​​the lower electrode plate 14 is the same as that of the upper electrode plate 16, a large number of the first conductive structures 12 can be arranged below the area of ​​the lower electrode plate 14, and a large number of the third conductive structures 18 can be arranged above the area of ​​the upper electrode plate 16.

[0070] It should be noted that, since a large number of the third conductive structures 18 can be arranged above the area of ​​the upper plate 16, when the material of the upper plate 16 is metal nitride or polysilicon, the contact resistance between the conductive structure connecting the upper plate 16 and the upper plate 16 can also be significantly reduced, thereby improving the quality factor of the capacitor.

[0071] In addition, in the existing capacitors, since the area of ​​the lower plate is larger than the area of ​​the upper plate, and the effective area for providing the capacitance value is the area directly opposite the upper plate and the lower plate, then the area of ​​the lower plate outside the upper plate cannot provide the capacitance value; in the present invention, since the lower plate 14 is connected through the multiple first conductive structures 12 below it, the area of ​​the lower plate 14 does not need to be larger than the area of ​​the upper plate 16, that is, the area of ​​the lower plate 14 is equal to the area of ​​the upper plate 16, and the entire area of ​​the lower plate 14 can provide the capacitance value. Then, when providing the same capacitance value, compared with the existing capacitors, the area of ​​the lower plate 14 of the capacitor of the present invention is reduced, that is, the area occupied by the capacitor is reduced.

[0072] In summary, the present invention provides a semiconductor device, comprising: a substrate, a first dielectric layer is formed on the substrate, a plurality of first conductive structures and a first metal layer are formed in the first dielectric layer, and the plurality of first conductive structures are electrically connected to the first metal layer; a lower electrode plate, a second dielectric layer and an upper electrode plate from bottom to top are formed on the first dielectric layer, and the lower electrode plate is electrically connected to the plurality of first conductive structures; a plurality of third conductive structures and a fourth conductive structure, the plurality of third conductive structures are formed on the upper electrode plate and are electrically connected to the upper electrode plate, and the fourth conductive structure is electrically connected to the first metal layer. The semiconductor device provided by the present invention enables the first conductive structure to be arranged below the entire area of ​​the lower electrode plate, which can improve the quality factor of the capacitor while avoiding TDDB failure.

[0073] Based on the same inventive concept, an embodiment of the present invention provides a method for manufacturing a semiconductor device, referring to Figure 4 ,from Figure 4 It can be seen that the method for manufacturing the semiconductor device includes:

[0074] Step S1, providing a substrate, wherein a first dielectric layer is formed on the substrate, a plurality of first conductive structures and a first metal layer are formed in the first dielectric layer, and the plurality of first conductive structures are electrically connected to the first metal layer;

[0075] Step S2, forming a lower electrode plate, a second dielectric layer and an upper electrode plate from bottom to top on the first dielectric layer, wherein the lower electrode plate is electrically connected to the plurality of first conductive structures;

[0076] Step S3, forming a plurality of third conductive structures and a fourth conductive structure, wherein the plurality of third conductive structures are formed on the upper electrode plate and are electrically connected to the upper electrode plate, and the fourth conductive structure is electrically connected to the first metal layer.

[0077] See below Figure 1 to Figure 3 , Figure 5a to Figure 5hThe method for manufacturing the semiconductor device provided in this embodiment is described in detail.

[0078] According to step S1, Figure 5a As shown, a substrate 10 is provided, a first dielectric layer 11 is formed on the substrate 10 , a plurality of first conductive structures 12 and a first metal layer 111 are formed in the first dielectric layer 11 , and the plurality of first conductive structures 12 are electrically connected to the first metal layer 111 .

[0079] In another embodiment, the second conductive structure 13 may not be formed in the first dielectric layer 11 , and when the fourth conductive structure 19 is subsequently formed, it is made to directly contact the first metal layer 111 , so that the fourth conductive structure 19 can be connected to the subsequently formed lower electrode 14 through the first metal layer 111 and multiple first conductive structures 12 .

[0080] The material of the substrate 10 can be any suitable base material known to those skilled in the art, for example, it can be at least one of the following materials: silicon, germanium, silicon germanium, carbon silicon, carbon germanium silicon, indium arsenide, gallium arsenide, indium phosphide or semiconductor on insulator (SOI, such as silicon on insulator), etc.

[0081] A device structure such as a transistor (not shown) may be formed on the substrate 10, and the first dielectric layer 11 covers the device structure. The device structure is connected to an interconnection structure (not shown).

[0082] In one embodiment, a second conductive structure 13 may be further formed in the first dielectric layer 11 , and the second conductive structure 13 is electrically connected to the plurality of first conductive structures 12 through the first metal layer 111 .

[0083] The second conductive structure 13 is located at one side of the plurality of first conductive structures 12 , and the number of the second conductive structure 13 may be one or more.

[0084] The first dielectric layer 11 exposes top surfaces of the plurality of first conductive structures 12 and the second conductive structure 13 .

[0085] The first metal layer 111 can be manufactured simultaneously with a metal layer (not shown) in the interconnect structure, and the first conductive structure 12 and the second conductive structure 13 can be manufactured simultaneously.

[0086] The first conductive structure 12 and the second conductive structure 13 may both include a conductive plug and a conductive layer, the first dielectric layer 11 exposes the top surface of the conductive layer, and the conductive layer is electrically connected to the first metal layer 111 through the conductive plug. Figure 5aAs shown, the first conductive structure 12 includes a first conductive plug 122 and a first conductive layer 121, the second conductive structure 13 includes a second conductive plug 132 and a second conductive layer 131, the first conductive layer 121 is electrically connected to the first metal layer 111 through the first conductive plug 122, and the second conductive layer 131 is electrically connected to the first metal layer 111 through the second conductive plug 132. In this embodiment, the first conductive layer 121 and the second conductive layer 131 can be manufactured simultaneously with another metal layer (not shown) in the interconnect structure.

[0087] Alternatively, the first conductive structure 12 and the second conductive structure 13 each only include the conductive plug, and the first dielectric layer 11 exposes the top surface of the conductive plug. Figure 2 As shown, the first conductive structure 12 only includes the first conductive plug 122 , and the second conductive structure 13 only includes the second conductive plug 132 .

[0088] According to step S2, Figure 5f As shown, a lower electrode plate 14 , a second dielectric layer 15 and an upper electrode plate 16 are formed from bottom to top on the first dielectric layer 11 , and the lower electrode plate 14 is electrically connected to the plurality of first conductive structures 12 .

[0089] In one embodiment, the steps of forming the lower electrode plate 14, the second dielectric layer 15 and the upper electrode plate 16 from bottom to top may include:

[0090] First, if Figure 5a As shown, an etch stop layer 112 is formed on the first dielectric layer 11, and the etch stop layer 112 covers the plurality of first conductive structures 12 and the second conductive structure 13;

[0091] Then, if Figure 5b As shown, the etch stop layer 112 is etched to form openings 113 in the etch stop layer 112 that expose the plurality of first conductive structures 12; wherein the openings 113 may also expose the top surface of the first dielectric layer 11 between adjacent first conductive structures 12;

[0092] Then, if Figure 5c and Figure 5d As shown, a lower plate material layer 141, a second dielectric material layer 151 and an upper plate material layer 161 are formed from bottom to top on the etching stop layer 112, and the lower plate material layer 141 fills the opening 113;

[0093] Then, if Figure 5e As shown, a photolithography process is performed to form a patterned photoresist layer 162 on the upper plate material layer 161;

[0094] Then, if Figure 5f As shown, the patterned photoresist layer 162 is used as a mask to etch the upper plate material layer 161, the second dielectric material layer 151 and the lower plate material layer 141 to remove at least a portion of the upper plate material layer 161, the second dielectric material layer 151 and the lower plate material layer 141 on the etch stop layer 112 outside the opening 113, and the remaining upper plate material layer 161, the second dielectric material layer 151 and the lower plate material layer 161 serve as the upper plate 16, the second dielectric layer 15 and the lower plate 14, respectively; then, the patterned photoresist layer 162 is removed.

[0095] In the step of forming the lower plate 14, the second dielectric layer 15 and the upper plate 16, the etching stop layer 112 is preferably formed so that when etching the upper plate material layer 161, the second dielectric material layer 151 and the lower plate material layer 141, the etching can stop in the etching stop layer 112 to prevent the first dielectric layer 11 from being etched. In other embodiments, the etching stop layer 112 may not be formed.

[0096] When the material of the lower electrode plate 14 and the upper electrode plate 16 is an opaque material, by forming the opening 113 in the etch stop layer 112 before forming the lower electrode material layer 141, it is possible to identify and record the position of the opening 113, and align it according to the position of the opening 113 when forming the patterned photoresist layer 162 by photolithography, thereby preventing the formed patterned photoresist layer 162 from shifting, thereby preventing the upper electrode plate 16, the second dielectric layer 15 and the lower electrode plate 14 formed after etching from shifting their positions.

[0097] Since the upper electrode plate 16 , the second dielectric layer 15 and the lower electrode plate 14 are formed by the same photolithography process, the areas of the upper electrode plate 16 , the second dielectric layer 15 and the lower electrode plate 14 are the same.

[0098] The area of ​​the upper plate 16, the second dielectric layer 15 and the lower plate 14 may be the same as the area of ​​the opening 113, that is, the upper plate 16, the second dielectric layer 15 and the lower plate 14 are only located in the area where the opening 113 is located, and do not extend to the etching stop layer 112 outside the opening 113, that is, the upper and lower plates 16 / 14 are formed using the same mask as the opening 113; or Figure 5fAs shown, the area of ​​the upper plate 16, the second dielectric layer 15 and the lower plate 14 can be larger than the area of ​​the opening 113, that is, the upper plate 16, the second dielectric layer 15 and the lower plate 14 extend from the area where the opening 113 is located to the etching stop layer 112 outside the opening 113.

[0099] When the first conductive structure 12 includes the first conductive plug 122 and the first conductive layer 121, the bottom surface of the lower electrode plate 14 contacts the top surface of the first conductive layer 121, and the lower electrode plate 14 is electrically connected to the first conductive layer 121 in the first conductive structure 12; when the first conductive structure 12 only includes the first conductive plug 122, the bottom surface of the lower electrode plate 14 contacts the top surface of the first conductive plug 122, and the lower electrode plate 14 is electrically connected to the first conductive plug 122 in the first conductive structure 12.

[0100] Preferably, the material of the lower plate 14 and the upper plate 16 is metal nitride or polysilicon. When the material of the lower plate 14 and the upper plate 16 is metal, since the area of ​​the lower plate 14 and the upper plate 16 is large, the large area of ​​metal will easily produce irregular crystallization in the high temperature process, which will lead to poor surface roughness of the lower plate 14 and the upper plate 16, and the thickness of the second dielectric layer 15 at the abnormal protrusion on the surface of the lower plate 14 will be affected (for example, the thickness becomes thinner), and the abnormal protrusion on the surface of the lower plate 14 is prone to tip discharge, which will lead to the capacitor at the abnormal protrusion being easily broken down, that is, causing the TDDB (time dependent dielectric breakdown) failure of the capacitor. Therefore, the material of the lower plate 14 and the upper plate 16 is metal nitride or polysilicon, which can avoid the TDDB failure problem of the capacitor caused by the material of the lower plate 14 and the upper plate 16 being metal.

[0101] The metal nitride is, for example, a nitride of a metal such as aluminum, copper, tantalum, titanium or tungsten.

[0102] When the material of the lower electrode plate 14 and the upper electrode plate 16 is metal nitride, the capacitor is a MIM capacitor; when the material of the upper electrode plate 16 and the lower electrode plate 14 is polysilicon, the capacitor is a PIP capacitor.

[0103] The material of the second dielectric layer 15 is preferably a high-K (relative dielectric constant) dielectric, such as at least one of zinc oxide, hafnium oxide, titanium oxide, and zirconium oxide. It should be noted that the material of the second dielectric layer 15 can also be at least one of silicon oxide, silicon oxynitride, silicon nitride, and ONO (silicon oxide-silicon nitride-silicon oxide).

[0104] Preferably, the top surface area of ​​each of the first conductive structures 12 is 0.1 to 0.2 times the area of ​​the lower electrode plate 14 .

[0105] When the material of the first conductive structure 12 is metal (for example, aluminum, copper, tantalum, titanium or tungsten, etc.), since a large area of ​​metal is more likely to produce irregular crystallization in a high-temperature process, the top surface roughness of a large area of ​​metal is poor. If the top surface of the first conductive structure 12 is a large area of ​​metal, the thickness or roughness of the lower electrode 14, the second dielectric layer 15 and the upper electrode 16 above the abnormal protrusion on the top surface of the first conductive structure 12 will be affected (for example, the thickness becomes thinner), and the abnormal protrusion on the top surface of the first conductive structure 12 is prone to tip discharge, which in turn causes the capacitor at the abnormal protrusion to be easily broken down, that is, causing the TDDB (time dependent dielectric breakdown) failure of the capacitor. Therefore, by defining the top surface area of ​​each first conductive structure 12 as 0.1 to 0.2 times the area of ​​the lower electrode 14, that is, significantly reducing the top surface area of ​​a single first conductive structure 12, the irregular crystallization of each first conductive structure 12 in the high-temperature process can be significantly alleviated, avoiding the deterioration of the top surface roughness of the first conductive structure 12, thereby avoiding TDDB failure of the capacitor.

[0106] like Figure 5g As shown, after forming the lower electrode 14, the second dielectric layer 15 and the upper electrode 16 from bottom to top, the manufacturing method of the semiconductor device also includes: forming a third dielectric layer 17 on the first dielectric layer 11, and the third dielectric layer 17 covers the upper electrode 16, the second dielectric layer 15, the lower electrode 14 and the second conductive structure 13.

[0107] If the etch stop layer 112 is formed on the first dielectric layer 11 , the third dielectric layer 17 is formed on the etch stop layer 112 .

[0108] The third dielectric layer 17 may be a single-layer structure or a multi-layer stacked structure.

[0109] The material of the first dielectric layer 11 and the third dielectric layer 17 may be at least one of silicon oxide, silicon oxynitride, silicon nitride and ONO (silicon oxide-silicon nitride-silicon oxide).

[0110] According to step S3, Figure 5h and Figure 2 As shown, a plurality of third conductive structures 18 and a fourth conductive structure 19 are formed. The plurality of third conductive structures 18 are formed on the upper electrode plate 16 and are electrically connected to the upper electrode plate 16 . The fourth conductive structure 19 is electrically connected to the first metal layer 111 .

[0111] The plurality of third conductive structures 18 and the fourth conductive structure 19 are formed in the third dielectric layer 17, the plurality of third conductive structures 18 are electrically connected to the upper electrode plate 16, the fourth conductive structure 19 can be electrically connected to the first metal layer 111 through the second conductive structure 13, the third dielectric layer 17 exposes the top surfaces of the third conductive structures 18 and the fourth conductive structures 19, the plurality of third conductive structures 18 are used to connect to the upper electrode plate 16, and the fourth conductive structure 19 is used to connect to the lower electrode plate 14. Since the second conductive structure 13 is electrically connected to the plurality of first conductive structures 12, and the plurality of first conductive structures 12 are electrically connected to the lower electrode plate 14, the fourth conductive structure 19 can be connected to the lower electrode plate 14.

[0112] In the existing capacitor, in order to connect the lower plate, the area of ​​the lower plate is larger than that of the upper plate, and the conductive structure for connecting the upper plate is formed on the top surface of the upper plate, and the conductive structure for connecting the lower plate is formed on the top surface of the lower plate outside the upper plate; because the effective area for providing the capacitance value is the area directly facing the upper plate and the lower plate, the area of ​​the lower plate facing the upper plate will be designed to be very large, and the area of ​​the lower plate outside the upper plate is designed to be very small, resulting in a small number of conductive structures set for connecting the lower plate and a small contact area, which results in a high contact resistance between the conductive structure for connecting the lower plate and the lower plate when the material of the lower plate is metal nitride or polysilicon, which in turn leads to a low quality factor of the capacitor.

[0113] In the present invention, since the lower electrode plate 14 is connected through the plurality of first conductive structures 12 below it, the first conductive structure 12 can be set below the entire area of ​​the lower electrode plate 14, that is, a large number of the first conductive structures 12 can be set below the entire area of ​​the lower electrode plate 14. Compared with the existing capacitor, the area of ​​the lower electrode plate 14 for setting the conductive structure is significantly increased, so that the number of conductive structures for connecting the lower electrode plate 14 is significantly increased, and thus the contact area between the conductive structure for connecting the lower electrode plate 14 and the lower electrode plate 14 is significantly increased, so that when the material of the lower electrode plate 14 is metal nitride or polysilicon, the contact resistance between the conductive structure for connecting the lower electrode plate 14 and the lower electrode plate 14 can be significantly reduced, thereby improving the quality factor of the capacitor. In one embodiment, the quality factor of the capacitor when the material of the lower electrode plate 14 is metal nitride or polysilicon can be close to or equal to the quality factor of the capacitor when the material of the lower electrode plate 14 is metal.

[0114] Therefore, it can be seen from the above content that since the lower electrode plate 14 is connected through the multiple first conductive structures 12 below it, and the upper electrode plate 16 is connected through the multiple third conductive structures 18 above it, the quality factor of the capacitor can still be improved when the material of the upper electrode plate 16 and the lower electrode plate 14 is selected from metal nitride or polysilicon. At the same time, the TDDB failure problem of the capacitor caused by the selection of metal as the material of the upper electrode plate 16 and the lower electrode plate 14 can be avoided.

[0115] Among them, Figure 3 As shown, in the direction perpendicular to the surface of the substrate 10, the area of ​​the lower electrode plate 14 is the same as that of the upper electrode plate 16, a large number of the first conductive structures 12 can be arranged below the area of ​​the lower electrode plate 14, and a large number of the third conductive structures 18 can be arranged above the area of ​​the upper electrode plate 16.

[0116] It should be noted that, since a large number of the third conductive structures 18 can be arranged above the area of ​​the upper plate 16, when the material of the upper plate 16 is metal nitride or polysilicon, the contact resistance between the conductive structure connecting the upper plate 16 and the upper plate 16 can also be significantly reduced, thereby improving the quality factor of the capacitor.

[0117] In addition, in the existing capacitors, since the area of ​​the lower plate is larger than that of the upper plate, different masks are required to form the lower plate and the upper plate, and two photolithography processes are required; in the present invention, the upper plate 16 and the lower plate 14 are formed using the same mask and the same photolithography process. Compared with the existing capacitors, one mask and one photolithography process are saved, thereby reducing costs.

[0118] In addition, in the existing capacitors, since the area of ​​the lower plate is larger than the area of ​​the upper plate, and the effective area for providing the capacitance value is the area directly opposite the upper plate and the lower plate, then the area of ​​the lower plate outside the upper plate cannot provide the capacitance value; in the present invention, since the lower plate 14 is connected through the multiple first conductive structures 12 below it, the area of ​​the lower plate 14 does not need to be larger than the area of ​​the upper plate 16, that is, the area of ​​the lower plate 14 is equal to the area of ​​the upper plate 16, and the entire area of ​​the lower plate 14 can provide the capacitance value. Then, when providing the same capacitance value, compared with the existing capacitors, the area of ​​the lower plate 14 of the capacitor of the present invention is reduced, that is, the area occupied by the capacitor is reduced.

[0119] In summary, the present invention provides a method for manufacturing a semiconductor device, including: providing a substrate, a first dielectric layer is formed on the substrate, a plurality of first conductive structures and a first metal layer are formed in the first dielectric layer, and the plurality of first conductive structures are electrically connected to the first metal layer; forming a lower electrode plate, a second dielectric layer and an upper electrode plate from bottom to top on the first dielectric layer, and the lower electrode plate is electrically connected to the plurality of first conductive structures; forming a plurality of third conductive structures and a fourth conductive structure, the plurality of third conductive structures are formed on the upper electrode plate and are electrically connected to the upper electrode plate, and the fourth conductive structure is electrically connected to the first metal layer. The method for manufacturing a semiconductor device provided by the present invention enables the first conductive structure to be arranged below the entire area of ​​the lower electrode plate, which can improve the quality factor of the capacitor while avoiding TDDB failure.

[0120] The above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. Any changes or modifications made by a person skilled in the art in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A semiconductor device, characterized in that: include: A substrate, a first dielectric layer formed on the substrate, a plurality of first conductive structures and a first metal layer formed in the first dielectric layer, the plurality of first conductive structures being electrically connected to the first metal layer; A lower electrode plate, a second dielectric layer and an upper electrode plate are formed from bottom to top on the first dielectric layer, and the lower electrode plate is electrically connected to the plurality of first conductive structures; A plurality of third conductive structures and a fourth conductive structure, wherein the plurality of third conductive structures are formed on the upper electrode plate and are electrically connected to the upper electrode plate, and the fourth conductive structure is electrically connected to the first metal layer.

2. The semiconductor device according to claim 1, wherein The upper electrode plate, the second dielectric layer and the lower electrode plate have the same area.

3. The semiconductor device according to claim 1, wherein The top surface area of ​​each of the first conductive structures is 0.1 to 0.2 times the area of ​​the lower electrode plate.

4. The semiconductor device according to claim 1, wherein The material of the lower electrode plate and the upper electrode plate is metal nitride or polysilicon.

5. The semiconductor device according to claim 1, wherein: The semiconductor device further comprises: An etch stop layer is formed on the first dielectric layer, the etch stop layer has openings exposing the plurality of first conductive structures, and the lower electrode plate at least fills the openings.

6. The semiconductor device according to claim 1, wherein: A second conductive structure is also formed in the first dielectric layer, and the fourth conductive structure is electrically connected to the first metal layer through the second conductive structure.

7. A method for manufacturing a semiconductor device, characterized in that: include: Providing a substrate, wherein a first dielectric layer is formed on the substrate, a plurality of first conductive structures and a first metal layer are formed in the first dielectric layer, and the plurality of first conductive structures are electrically connected to the first metal layer; Forming a lower electrode plate, a second dielectric layer and an upper electrode plate from bottom to top on the first dielectric layer, wherein the lower electrode plate is electrically connected to the plurality of first conductive structures; A plurality of third conductive structures and a fourth conductive structure are formed, wherein the plurality of third conductive structures are formed on the upper electrode plate and are electrically connected to the upper electrode plate, and the fourth conductive structure is electrically connected to the first metal layer.

8. The method for manufacturing a semiconductor device according to claim 7, wherein: The upper electrode plate, the second dielectric layer and the lower electrode plate have the same area.

9. The method for manufacturing a semiconductor device according to claim 7, wherein: The top surface area of ​​each of the first conductive structures is 0.1 to 0.2 times the area of ​​the lower electrode plate.

10. The method for manufacturing a semiconductor device according to claim 7, wherein: The material of the lower electrode plate and the upper electrode plate is metal nitride or polysilicon.

11. The method for manufacturing a semiconductor device according to claim 7, wherein: Before forming the lower electrode plate, the second dielectric layer and the upper electrode plate from bottom to top, the method for manufacturing the semiconductor device includes: forming an etch stop layer on the first dielectric layer, wherein the etch stop layer covers the plurality of first conductive structures; etching the etch stop layer to form openings exposing the plurality of first conductive structures; Wherein, the lower electrode plate at least fills the opening.

12. The method for manufacturing a semiconductor device according to claim 7, wherein: A second conductive structure is also formed in the first dielectric layer, and the fourth conductive structure is electrically connected to the first metal layer through the second conductive structure.

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