Preparation method of semiconductor device

Abstract

The invention provides a preparation method of a semiconductor device, and the method comprises the steps: providing a substrate, and forming an exposed connecting piece in the substrate; forming a protective layer to cover the substrate; executing a first photoetching process to etch the protection layer and the substrate so as to form a groove in the substrate; executing a chemical mechanical polishing process, and removing at least partial thickness of the protective layer; forming a storage material layer to cover the substrate and the inner wall of the groove; and taking the groove as a photoetching alignment mark, executing a second photoetching process to carry out patterning on the storage material layer to obtain a storage pattern, and covering the connecting piece with the storage pattern. According to the method, the substrate is protected by the protection layer when the first photoetching process is executed, the substrate is prevented from being damaged by the first photoetching process, at least part of the thickness of the protection layer is removed by adopting the chemical mechanical polishing process, and the yield of the semiconductor device is improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a method for preparing a semiconductor device. Background Art

[0002] The storage material layer in the new memory is generally made of opaque material, such as the phase change material of phase change memory, the resistive material of resistive memory and the magnetoresistive material of magnetoresistive memory, all of which contain one or more layers of opaque material. When the storage material layer is subjected to the photolithography process, it is necessary to form additional specific photolithography alignment marks beforehand. When the photolithography process is subsequently performed, the specific photolithography alignment marks are used to achieve alignment exposure. The additional formation of specific photolithography alignment marks adds a photolithography process. Although this photolithography process forms specific photolithography alignment marks, it adds the process steps of spin coating photoresist, patterning photoresist, etching and removing photoresist. The plasma bombardment during the spin coating of photoresist and the removal of photoresist is likely to damage the substrate, that is, damage the device part in the substrate, resulting in a reduction in the yield of the semiconductor device. Summary of the invention

[0003] The object of the present invention is to provide a method for preparing a semiconductor device to improve the yield of the semiconductor device.

[0004] In order to achieve the above object, the present invention provides a method for preparing a semiconductor device, comprising:

[0005] providing a substrate having exposed connectors formed therein;

[0006] forming a protective layer to cover the substrate;

[0007] Performing a first photolithography process to etch the protective layer and the substrate to form a groove in the substrate;

[0008] performing a chemical mechanical polishing process to remove at least a portion of the thickness of the protective layer;

[0009] forming a storage material layer to cover the substrate and the inner wall of the groove; and,

[0010] The groove is used as a photolithography alignment mark, and a second photolithography process is performed to pattern the storage material layer to obtain a storage pattern, wherein the storage pattern covers the connecting member.

[0011] Optionally, the connecting member is located in a device region of the substrate, and the groove is located in a dicing lane of the substrate.

[0012] Optionally, the depth of the groove is greater than 1200 angstroms.

[0013] Optionally, the material of the protective layer is an insulating material.

[0014] Optionally, the protective layer is removed when performing a chemical mechanical polishing process.

[0015] Optionally, the protective layer is made of metal.

[0016] Optionally, when performing the chemical mechanical polishing process, a portion of the thickness of the protective layer is removed.

[0017] Optionally, after removing part of the thickness of the protective layer, the formed storage material layer covers the retained protective layer; and when performing a second photolithography process to pattern the storage material layer, the retained protective layer is patterned simultaneously.

[0018] Optionally, after removing part of the thickness of the protective layer, the thickness of the remaining protective layer is greater than 50 angstroms.

[0019] Optionally, the protective layer has a thickness of 100 angstroms to 300 angstroms.

[0020] In the method for preparing a semiconductor device provided by the present invention, a substrate is provided, in which an exposed connector is formed; a protective layer is formed to cover the substrate; a first photolithography process is performed to etch the protective layer and the substrate to form a groove in the substrate; a chemical mechanical polishing process is performed to remove at least part of the thickness of the protective layer; a storage material layer is formed to cover the substrate and the inner wall of the groove; and a second photolithography process is performed to pattern the storage material layer using the groove as a photolithography alignment mark to obtain a storage pattern, wherein the storage pattern covers the connector. In the present invention, the protective layer is used to protect the substrate when the first photolithography process is performed to prevent the first photolithography process from causing damage to the substrate, and then a chemical mechanical polishing process is used to remove at least part of the thickness of the protective layer, thereby improving the yield of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A flow chart of a method for preparing a semiconductor device provided by the present invention;

[0022] Figures 2A to 2F A schematic cross-sectional view of corresponding steps in the method for preparing a semiconductor device provided in the first embodiment of the present invention;

[0023] Figures 3A to 3D It is a cross-sectional schematic diagram of corresponding steps in the method for preparing a semiconductor device provided in the second embodiment of the present invention.

[0024] Wherein, the accompanying drawings are marked as follows:

[0025] 10-substrate; 11-device area; 12-slicing road; 20-connector; 30-protective layer; 32-electrode buried layer; 41-first patterned photoresist layer; 42-second patterned photoresist layer; 50-groove; 60-storage material layer; 62-storage pattern; 70-dielectric layer; 81-intermediate connector; 82-electrode. DETAILED DESCRIPTION

[0026] In order to make the purpose, advantages and features of the present invention clearer, the present invention is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. In addition, the structure shown in the drawings is often a part of the actual structure. In particular, the emphasis of each drawing is different, and sometimes different scales are used.

[0027] As used in the present invention, the singular forms "one", "an", and "the" include plural objects, the term "or" is usually used to include the meaning of "and / or", the term "several" is usually used to include the meaning of "at least one", and the term "at least two" is usually used to include the meaning of "two or more". In addition, the terms "first", "second", and "third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first", "second", and "third" may explicitly or implicitly include one or at least two of the features, and "one end" and "the other end" generally refer to two corresponding parts. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0028] Figure 1 This is a flow chart of the method for preparing a semiconductor device provided by the present invention. Please refer to Figure 1 The present invention provides a method for preparing a semiconductor device, comprising:

[0029] Step S1: providing a substrate, wherein exposed connectors are formed in the substrate;

[0030] Step S2: forming a protective layer to cover the substrate;

[0031] Step S3: performing a first photolithography process to etch the protective layer and the substrate to form a groove in the substrate;

[0032] Step S4: performing a chemical mechanical polishing process to remove at least a portion of the thickness of the protective layer;

[0033] Step S5: forming a storage material layer to cover the substrate and the inner wall of the groove;

[0034] Step S6: using the groove as a photolithography alignment mark, performing a second photolithography process to pattern the storage material layer to obtain a storage pattern, wherein the storage pattern covers the connector.

[0035] Embodiment 1

[0036] Figures 2A to 2F The cross-sectional schematic diagram of the corresponding steps in the method for preparing the semiconductor device provided in this embodiment is shown below in combination with Figures 2A to 2F The method for preparing the semiconductor device provided in this embodiment is described in detail.

[0037] Please refer to Figure 2A , perform step S1: provide a substrate 10, the substrate 10 may include a semiconductor material, such as a silicon substrate, a gallium arsenide substrate, a germanium substrate, a germanium silicon substrate, a fully depleted silicon substrate on an insulating layer; the substrate 10 may also include an integrated circuit, such as a MOS tube, a triode, a diode; the substrate 10 may also include an interconnection layer, such as a copper interconnection layer, a graphene interconnection layer; the substrate 10 may also include an insulating dielectric layer, such as a silicon oxide layer, a silicon nitride layer. An exposed connector 20 is formed in the substrate 10, that is, the top of the connector 20 is exposed on the surface of the substrate 10, the substrate 10 includes a device area 11 and a scribe line 12, the device area 11 and the scribe line 12 may be adjacent or not adjacent (adjacent in the figure), the connector 20 is located in the device area 11, and the connector 20 is electrically connected to the integrated circuit or the interconnection layer (not shown in the figure) in the substrate 10. In this embodiment, the width of the connector 20 may be 50nm to 100nm, and the cross-section (the cross-section is not a profile, but a top view) of the connector 20 is preferably circular, and is not limited to the above width range and shape.

[0038] Please continue to refer to Figure 2A , step S2 is performed: depositing a protective layer 30 to cover the substrate 10 (covering the device area 11 and the scribe line 12), and also covering the connector 20. In this embodiment, the material of the protective layer 30 is an insulating material, including silicon oxide or silicon nitride; the thickness of the protective layer 30 is preferably 100 angstroms to 300 angstroms, which is conducive to protecting the substrate 10.

[0039] Please refer to Figure 2B, executing step S3: performing a first photolithography process to etch the protective layer 30 and the substrate 10 to form a groove 50 in the substrate 10, the step includes: spin coating a photoresist on the surface of the substrate 10 to form a photoresist layer, and after curing, patterning the photoresist layer to form a patterned photoresist layer 41. Using the patterned photoresist layer 41 as a mask, etching the protective layer 30 and the substrate 10 to form a groove 50 in the substrate 10, the sidewall of the groove 50 is vertical and the groove 50 is located in the scribe line, the scribe line is the position for subsequent chip cutting, and the groove 50 will be used as a photolithography alignment mark later; in this embodiment, the width of the groove 50 can be 1μm to 3μm, the cross-sectional shape of the groove 50 is preferably rectangular (long strip), and the depth of the groove 50 can be 150nm to 200nm, which is not limited to the above width range, depth range and shape. Then, the patterned photoresist layer 41 is removed, and plasma bombards the patterned photoresist layer 41 to remove the patterned photoresist layer 41. If there is no protective layer 30, the plasma will damage the substrate 10 when bombarding and removing the patterned photoresist layer 41, causing the circuit structure of the device area 11 to be damaged. In this embodiment, due to the presence of the protective layer 30, the protective layer 30 is used to protect the substrate 10 when performing the first photolithography process, thereby preventing the first photolithography process from directly damaging the substrate 10, thereby improving the yield of the semiconductor device.

[0040] Please refer to Figure 2C , execute step S4: perform a chemical mechanical polishing process to remove the protective layer 30. Since a storage pattern is to be formed to be electrically connected to the connector 20 later, and the material of the protective layer 30 is an insulating material, it is necessary to completely remove the protective layer 30 to expose the surface of the substrate 10 to ensure the connectivity of the circuit. The chemical mechanical polishing process will not damage the circuit structure of the device area 11.

[0041] Please refer to Figure 2D, step S5 is performed: depositing a storage material layer 60 to cover the substrate 10 and the inner wall (side wall and bottom) of the groove 50, and to cover the connector 20. In this embodiment, the storage material layer 60 does not fill the groove 50, but only covers the inner wall of the groove 50, so that the groove 50 can be exposed. Since the groove 50 is formed by a separate photolithography process, the groove 50 has photolithography alignment recognition. In this embodiment, the material of the storage material layer 60 includes a phase change memory storage material, a resistive memory storage material or a magnetoresistive memory storage material, wherein the phase change memory storage material includes one of sulfur alloy materials such as Ge2Sb2Te5, Ge2Sb2Te5 doping, GeSbTe series alloys, SbTe series alloy materials, GeTe series alloy materials, etc. The resistive memory storage material includes one or more of Ta2O5, TaOx, HfOx, TiOx, AlOx, ZnOx, CuOx and a combined material layer of metal materials such as TaN, TiN, Pt, Ir, Ti, Ta, etc. The magnetoresistive memory storage material includes a combination of multiple materials such as MgOx, CoFeB, Co, CoPt, Pt, Ru, Ni, Cr, Ta, etc.

[0042] Please refer to Figure 2E , execute step S6: use the groove 50 as a photolithography alignment mark, identify the groove 50 for exposure alignment, and perform a second photolithography process to pattern the storage material layer 60 to obtain a storage pattern 62, specifically, form a second patterned photoresist layer 42 to cover the storage material layer 60, and use the second patterned photoresist layer 42 as a mask to etch the storage material layer 60 to form a storage pattern 62, and the storage pattern 62 covers the connector 20 to contact the connector 20 to form an electrical connection.

[0043] For further information, please refer to Figure 2F After forming the storage pattern 62, a dielectric layer 70 is formed to cover the substrate 10 and the storage pattern 62 and fill the groove 50; then, an intermediate connector 81 and an electrode 82 are formed in the dielectric layer 70, and the intermediate connector 81 connects the storage pattern 62 and the electrode 82, so that the connector 20, the storage pattern 62, the intermediate connector 81 and the electrode 82 are electrically connected.

[0044] Embodiment 2

[0045] Figures 3A to 3D The cross-sectional schematic diagram of the corresponding steps in the method for preparing the semiconductor device provided in this embodiment is shown below in combination with Figures 3A to 3D The method for preparing the semiconductor device provided in this embodiment is described in detail. The difference between this embodiment and the first embodiment lies in steps S4 to S6 and the material of the protective layer, and steps S1 to S3 are the same as the first embodiment, and will not be described in detail here.

[0046] In this embodiment, the material of the protection layer 30 is a metal material, including titanium nitride or tantalum nitride; the thickness of the protection layer 30 is preferably 100 angstroms to 300 angstroms, which is beneficial for protecting the substrate 10 .

[0047] Please refer to Figure 3A , execute step S4: perform a chemical mechanical polishing process to remove part of the thickness of the protective layer 30. In this embodiment, the material of the protective layer 30 is a metal material, so part of the thickness of the protective layer 30 can be removed, and the retained protective layer 30 can be used as an electrode buried layer to ensure the connectivity of the circuit; and the thickness of the retained protective layer 30 in this embodiment is preferably greater than 50 angstroms.

[0048] Please refer to Figure 3B , step S5 is performed: depositing a storage material layer 60 to cover the substrate 10 and the inner wall (side wall and bottom) of the groove 50, and to cover the retained protection layer 30. In this embodiment, the storage material layer 60 does not fill the groove 50, but only covers the inner wall of the groove 50, so that the groove 50 can be exposed. Since the groove 50 is formed by a separate photolithography process, the groove 50 has photolithography alignment recognition. In this embodiment, the material of the storage material layer 60 includes a phase change memory storage material, a resistive memory storage material or a magnetoresistive memory storage material, wherein the phase change memory storage material includes one of sulfur alloy materials such as Ge2Sb2Te5, Ge2Sb2Te5 doping, GeSbTe series alloys, SbTe series alloy materials, GeTe series alloy materials, etc. The resistive memory storage material includes one or more of Ta2O5, TaOx, HfOx, TiOx, AlOx, ZnOx, CuOx and a combined material layer of metal materials such as TaN, TiN, Pt, Ir, Ti, Ta, etc. The magnetoresistive memory storage material includes a combination of multiple materials such as MgOx, CoFeB, Co, CoPt, Pt, Ru, Ni, Cr, Ta, etc.

[0049] Please refer to Figure 3C , execute step S6: use the groove 50 as a photolithography alignment mark, identify the groove 50 for exposure alignment, and perform a second photolithography process to pattern the storage material layer 60 to obtain a storage pattern 62, and simultaneously pattern the retained protection layer 30, specifically, forming a second patterned photoresist layer 42 to cover the storage material layer 60, using the second patterned photoresist layer 42 as a mask to etch the storage material layer 60 to form the storage pattern 62 and synchronously etching the retained protection layer 30 to form an electrode buried layer 32, the storage pattern 62 covers the electrode buried layer 32 to contact the connector 20 through the electrode buried layer 32 to form an electrical connection.

[0050] For further information, please refer to Figure 3DAfter forming the storage pattern 62, a dielectric layer 70 is formed to cover the substrate 10 and the storage pattern 62 and fill the groove 50; then, an intermediate connector 81 and an electrode 82 are formed in the dielectric layer 70, and the intermediate connector 81 connects the storage pattern 62 and the electrode 82, so that the connector 20, the electrode buried layer 32, the storage pattern 62, the intermediate connector 81 and the electrode 82 form an electrical connection.

[0051] In summary, in the method for preparing a semiconductor device provided by the present invention, a substrate is provided, in which an exposed connector is formed; a protective layer is formed to cover the substrate; a first photolithography process is performed to etch the protective layer and the substrate to form a groove in the substrate; a chemical mechanical polishing process is performed to remove at least part of the thickness of the protective layer; a storage material layer is formed to cover the substrate and the inner wall of the groove; and, using the groove as a photolithography alignment mark, a second photolithography process is performed to pattern the storage material layer to obtain a storage pattern, and the storage pattern covers the connector. In the present invention, the protective layer is used to protect the substrate when the first photolithography process is performed to prevent the first photolithography process from causing damage to the substrate, and then a chemical mechanical polishing process is used to remove at least part of the thickness of the protective layer, thereby improving the yield of the semiconductor device.

[0052] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: providing a substrate having exposed connectors formed therein; forming a protective layer to cover the substrate; Performing a first photolithography process to etch the protective layer and the substrate to form a groove in the substrate; Performing a chemical mechanical polishing process to remove at least a portion of the thickness of the protective layer; forming a storage material layer to cover the substrate and the inner wall of the groove; as well as, The groove is used as a photolithography alignment mark, and a second photolithography process is performed to pattern the storage material layer to obtain a storage pattern, wherein the storage pattern covers the connecting member.

2. The method for preparing a semiconductor device according to claim 1, wherein: The connecting member is located in a device region of the substrate, and the groove is located in a dicing street of the substrate.

3. The method for preparing a semiconductor device according to claim 2, wherein: The depth of the groove is greater than 1200 angstroms.

4. The method for preparing a semiconductor device according to claim 1, wherein: The material of the protective layer is insulating material.

5. The method for preparing a semiconductor device according to claim 4, characterized in that: When the chemical mechanical polishing process is performed, the protective layer is removed.

6. The method for preparing a semiconductor device according to claim 1, wherein: The material of the protective layer is metal.

7. The method for preparing a semiconductor device according to claim 6, wherein: When the chemical mechanical polishing process is performed, a portion of the thickness of the protective layer is removed.

8. The method for preparing a semiconductor device according to claim 7, wherein: After removing part of the thickness of the protective layer, the formed storage material layer covers the retained protective layer; and when performing a second photolithography process to pattern the storage material layer, the retained protective layer is patterned simultaneously.

9. The method for preparing a semiconductor device according to claim 7, wherein: After removing part of the thickness of the protective layer, the thickness of the remaining protective layer is greater than 50 angstroms.

10. The method for preparing a semiconductor device according to claim 4 or 6, characterized in that: The thickness of the protective layer is 100 angstroms to 300 angstroms.

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