Soft switching circuit and full-digital PWM (Pulse Width Modulation) control method thereof

Abstract

A soft switching circuit disclosed by the present invention comprises a main circuit, a sampling module, an adjusting module, a clock module, a synchronizing signal generation module and a PWM output module, the sampling module is connected with the output end of the main circuit and the input end of the adjusting module, and the synchronizing signal generation module is connected with the output end of the adjusting module and the input end of the PWM output module. The adjusting module and the sampling module are both integrated in a digital signal processor (DSP), the adjusting module comprises a digital PI regulator, the digital PI regulator is connected with a synchronous signal generation module, the sampling module comprises a general purpose input / output (GPIO) pin, an analog-to-digital conversion (ADC) module and a soft start voltage regulator, the GPIO pin is connected with the ADC module, and the soft start voltage regulator is connected with the analog-to-digital conversion (ADC) module. A data register in the ADC module is connected with the soft start voltage regulator, and the soft start voltage regulator is connected with the digital PI regulator. The quasi-resonance circuit can solve the problems that an existing quasi-resonance circuit is long in resonance period, large in energy loss, low in response speed and limited in duty ratio adjusting range.

Description

Technical Field

[0001] The present invention belongs to the field of high-power electronic conversion control, and more specifically, relates to a soft switching circuit and a fully digital PWM control method thereof. Background Art

[0002] In recent years, in the research of high-power power electronic conversion control, the traditional pulse width modulation (PWM) control circuit usually works in a hard switching state due to the lack of auxiliary switches. This state has obvious switching losses during the opening and closing process, which reduces the energy efficiency of the system. Especially under high-frequency operation, this problem is particularly prominent, and the loss may even reach more than 20% of the total energy of the system. At the same time, high-frequency switching action is prone to cause electromagnetic interference (EMI), which has a negative impact on the electromagnetic compatibility (EMC) of surrounding equipment. Soft switching circuits can overcome the above limitations. They minimize the losses in the switching process through zero voltage switching (ZVS) or zero current switching (ZCS), thereby improving the efficiency of power conversion.

[0003] The PWM control of the soft switching circuit adopted includes quasi-resonant circuit, zero-switching PWM control, zero-conversion PWM control, and PWM control of soft switching circuit realized by digitalization. Quasi-resonant circuit introduces resonance in the switching process, which greatly reduces switching loss and switching noise; zero-switching PWM control controls the resonance start time by introducing auxiliary switches so that resonance only occurs before and after the switch state changes; the characteristic of zero-conversion PWM control is that the converter works in PWM mode, and the auxiliary resonant circuit only works for a period of time when the main power tube is switched to realize the soft switching of the power tube, and stops working at other times; PWM control of soft switching circuit realized by digitalization is usually based on PWM parameters, using digital signal processors (Digital signal processor, referred to as DSP) and field programmable gate arrays (Field Programmable Gate Array, referred to as FPGA) and other processors to generate PWM waveforms to realize the control of soft switching circuits.

[0004] However, the above-mentioned existing PWM control methods for soft switching circuits all have some technical defects that cannot be ignored:

[0005] (1) Auxiliary switches are introduced in quasi-resonant circuits, zero-switch PWM control, and zero-conversion PWM control, but the coordination between the main switch and the auxiliary switch is insufficient. The PWM control accuracy and response speed are low;

[0006] (2) Both zero-switching PWM control and zero-conversion PWM control are configured with inductor-capacitor (LC). However, due to the influence of environment and time, LC parameters are prone to change, which may cause drift of inductance and capacitance values, thereby affecting the resonant frequency and overall performance of the circuit. In addition, the long resonant period of these circuits limits their adaptability to changes in duty cycle.

[0007] (3) In the process of realizing PWM control of soft switching circuits through digitalization, signal processing usually needs to go through multiple stages, such as sampling, adjustment, calculation and output. Each stage will introduce delays, which can easily lead to deviations in the timing of the generated PWM control signal, thereby increasing the switching loss of the soft switching circuit and reducing the overall efficiency.

[0008] (4) PWM control of soft switching circuits is realized through digitalization. Digital signal processors (DSP) or programmable gate arrays (FPGA) are often used to perform PWM control of soft switching circuits. However, the clock frequency of DSP is not high enough, which limits the accuracy of its control of PWM waveform. In complex PWM control applications, the sequential processing capability of DSP makes its processing efficiency easily affected. However, FPGA has some shortcomings in the applicability of implementation method optimization. Its programming complexity is relatively high, and it is not as efficient as DSP in processing complex conditional branch operations. Summary of the invention

[0009] In view of the above defects or improvement needs of the prior art, the present invention provides a soft switching circuit and a fully digital PWM control method thereof, the purpose of which is to solve the technical problems of low PWM control accuracy and response speed existing in the quasi-resonant circuit, zero-switch PWM control, and zero-conversion PWM control methods of the existing soft switching circuit, as well as the drift problem of inductance and capacitance values ​​when LC parameters change in the existing zero-switch PWM control and zero-conversion PWM control methods, and the technical problem that the long resonant cycle is limited to the change of duty cycle, and the technical problem that the existing PWM control method for realizing the soft switching circuit through digitalization causes errors due to inconsistent timing, thereby increasing the switching loss of the soft switching circuit and reducing the overall efficiency, and the technical problems that the existing PWM control method for realizing the soft switching circuit through digitalization has low accuracy of DSP for PWM waveform control and insufficient applicability of FPGA in optimizing the implementation method.

[0010] To achieve the above-mentioned purpose, according to one aspect of the present invention, a soft switching circuit is provided, comprising a main circuit, a sampling module, an adjustment module, a clock module, a synchronization signal generating module, and a PWM output module, wherein the sampling module is respectively connected to the output end of the main circuit and the input end of the adjustment module, and the synchronization signal generating module is respectively connected to the output end of the adjustment module and the input end of the PWM output module.

[0011] The adjustment module and the sampling module are integrated in the digital signal processor DSP;

[0012] The regulating module includes a digital PI regulator, and the digital PI regulator is connected to the synchronization signal generating module;

[0013] The sampling module includes a general purpose input and output GPIO pin, an analog-to-digital conversion ADC module, and a soft-start voltage regulator;

[0014] The GPIO pins are connected to the ADC module, the data register in the ADC module is connected to the soft-start voltage regulator, and the soft-start voltage regulator is connected to the digital PI regulator.

[0015] The clock module, synchronization signal generation module and PWM output module are all integrated in the field programmable gate array FPGA;

[0016] The clock module is connected to the synchronization signal generation module and the PWM output module respectively, and the synchronization signal generation module is connected to the synchronization signal register in the PWM output module.

[0017] Preferably, the main circuit includes an input voltage source, a filter inductor, a resonant inductor, a resonant capacitor, a main switch tube, and an auxiliary switch tube;

[0018] The positive electrode of the input voltage is connected to the positive electrode of the main switch tube and the negative electrode of the resonant capacitor respectively;

[0019] The negative electrode of the main switch tube is connected to the positive electrode of the resonant inductor and the positive electrode of the filter inductor respectively;

[0020] The positive electrode of the auxiliary switch tube is connected to the resonant capacitor, and the negative electrode is connected to the negative electrode of the input voltage;

[0021] The resonant inductor and the resonant capacitor are connected to the sampling module.

[0022] According to another aspect of the present invention, a fully digital PWM control method for a soft switching circuit is provided, comprising the following steps:

[0023] (1) Obtaining circuit parameters of the soft switching circuit, and optimizing the obtained circuit parameters to obtain characteristic parameters of the main circuit in the soft switching circuit and a resonance period of the main switch in the main circuit.

[0024] (2) Using a digital signal processing method, the characteristic parameters of the main circuit in the soft switching circuit obtained in step (1) are subjected to analog-to-digital conversion (ADC) processing to obtain converted sampling current values ​​and sampling voltage values.

[0025] (3) Using a digital PI regulator, an error adjustment operation is performed on the converted sampled voltage value obtained in step (2) to obtain a voltage control value.

[0026] (4) According to the sampled current value and the sampled voltage value obtained in step (2) and the voltage control value obtained in step (3), the real-time resonance period of the auxiliary switch tube and the main switch tube of the main circuit in the soft switching circuit after the LC parameters change.

[0027] (5) Generate a synchronization signal of the auxiliary switch tube and a synchronization signal of the main switch tube according to the real-time resonance period of the auxiliary switch tube and the main switch tube after the LC parameters change obtained in step (4).

[0028] (6) Dynamically adjust the PWM duty cycle of the synchronization signal of the main switch tube obtained in step (5) to obtain the PWM signal of the main switch tube.

[0029] (7) Generate a PWM signal for the auxiliary switch tube according to the synchronization signal of the auxiliary switch tube obtained in step (5) and the PWM signal of the main switch tube obtained in step (6).

[0030] Preferably, step (1) specifically comprises:

[0031] First, obtain the circuit parameters of the main circuit in the soft switching circuit, including: input voltage V in and filter inductor L f The current value I f .

[0032] Then, according to the input voltage V in and filter inductor L f The current value I f Obtain the resonant inductance L on the auxiliary branch that satisfies the following inequality (1): a and resonant capacitor C a .

[0033]

[0034] The resulting input voltage V in , resonant inductance L on auxiliary branch a The voltage V La and current I La , resonant capacitor C a The voltage V Ca and current I Ca , resonant inductor La , and the resonant capacitor C a Together they constitute the characteristic parameters of the main circuit of the soft switching circuit.

[0035] Then, according to the obtained resonant inductance L a and resonant capacitor C a , and the resonance period T of the auxiliary switch tube in the main circuit is obtained by the following formula (2): a :

[0036]

[0037] Finally, according to the obtained resonance period of the auxiliary switch tube in the main circuit, the resonance period T of the main switch tube in the main circuit is obtained by the following formula (3): s :

[0038]

[0039] The proportional coefficient α=0.1.

[0040] Preferably, step (2) is specifically,

[0041] First, the resonant inductor L in the auxiliary branch of the main circuit a The voltage and current output terminals, and the resonant capacitor C a The output terminals of the voltage and current are connected to the input terminals of the ADC module in the digital signal processor DSP to output the voltage and current parameters of the resonant inductor and the resonant capacitor;

[0042] Then, by initializing the GPIO pin as the input of the ADC module and setting the sampling frequency and resolution of the ADC module (where the sampling frequency of the ADC module is set to 192kHz and the resolution is set to 12 bits), the voltage and current parameters of the resonant inductor and the resonant capacitor are converted by ADC.

[0043] Finally, the current data and voltage data of the data register in the ADC module are obtained, and the command current calculation is performed on the current data through the digital signal processing method to obtain the resonant capacitor C a The sampling current value I Ca The voltage data is processed by the soft start voltage regulator to obtain the resonant inductance L a The sampling voltage value V La .

[0044] Preferably, step (3) comprises the following sub-steps:

[0045] (3-1) The sampled voltage value V obtained in step (2) is La, and subtract it from the preset reference voltage value r(k) of the kth sampling to obtain the current error e(k) of the kth sampling, where k is an arbitrary natural number:

[0046] e(k)=r(k)-V La (4)

[0047] The preset k-th sampling reference voltage value r(k) has a value range of 0V to 600V, preferably 200V.

[0048] (3-2) Use a digital PI regulator to process the current error e(k) of the kth sampling obtained in step (3-1) to obtain the voltage control value u'(k) of the kth sampling:

[0049]

[0050] Where K p is the proportional gain, the current error e(k) of the kth sampling is the input of the digital PI regulator, and T is the sampling period;

[0051] (3-3) The k-th sampled voltage control quantity u'(k) obtained in step (3-2) is discretized by transfer function to obtain the differential equation of the k-th sampled voltage control quantity u(k):

[0052]

[0053] Where K i is the integral gain;

[0054] (3-4) The differential equation of the voltage control quantity u(k) obtained in step (3-3) is subjected to the k-1th sampling process to obtain the voltage control quantity u(k-1) of the k-1th sampling.

[0055] (3-5) Determine whether the voltage control value u(k-1) obtained in step (3-4) at the k-1th sampling is greater than the maximum input voltage u MAX If yes, go to step (3-6), otherwise go to step (3-7); where the maximum input voltage u MAX The value range is 0V to 800V, preferably 700V.

[0056] (3-6) Update the k-th sampled voltage control value u(k) obtained in step (3-3) to u MAX , then go to step (3-9);

[0057] (3-7) Determine whether the voltage control value u(k-1) sampled at the k-1th time is less than the minimum input voltage u MINIf yes, go to step (3-8), otherwise go to step (3-9); where the minimum input voltage u MIN The value range is -200V to 0V, preferably -200V.

[0058] (3-8) Update the k-th sampled voltage control value u(k) obtained in step (3-3) to u MIN , then go to step (3-9).

[0059] (3-9) The voltage control amount u(k) sampled at the kth time after the update is used as the voltage control amount V La '.

[0060] Preferably, step (4) is specifically,

[0061] First, according to the sampling current value I obtained in step (2), Ca and respectively obtain the resonant capacitance C a The size change of ΔC a and resonant inductor L a The size change ΔL a :

[0062]

[0063] Where Δt is the change in time, ΔV Ca is the lower resonant capacitor C a The voltage change, ΔI La is the resonant inductance L at Δt a The current changes.

[0064] Then, according to the obtained resonant capacitance C a The size change of ΔC a and resonant inductor L a The size change ΔL a Obtain the resonant period change T' of the auxiliary switch tube in the main circuit a The resonant cycle change T of the main switch tube in the main circuit s ':

[0065]

[0066] Finally, the resonant period of the auxiliary switch in the main circuit changes to T′ a The resonant period T of the auxiliary switch tube in the main circuit obtained by equation (3) in step (1) is a Subtract to obtain the real-time resonant period T of the auxiliary switch tube of the main circuit in the soft switching circuit after the LC parameters change. SYNC1 ; Change the resonant period of the main switch in the main circuit by T s'The resonant period T of the main switch tube in the main circuit obtained by equation (2) in step (1) S Subtract to obtain the real-time resonant period T of the main switch tube of the main circuit in the soft switching circuit after the LC parameters change. SYNC2 .

[0067] Preferably, step (5) is specifically,

[0068] First, the real-time resonant period T of the auxiliary switch tube obtained in step (4) SYNC1 Get the switching frequency f of the auxiliary switch tube PWM1 , and according to the real-time resonant period T of the main switch tube SYNC2 Get the switching frequency f of the main switch tube PWM2 :

[0069]

[0070] Then, according to the switching frequency f of the auxiliary switch tube obtained PWM1 Get the register value R1 of the auxiliary switch in the FPGA, and according to the switching frequency f of the main switch PWM2 Get the register value R2 of the main switch in FPGA:

[0071]

[0072] where f CLK The frequency of the clock signal generated by the clock module in the FPGA is preferably 50 MHz.

[0073] Finally, according to the register value R1 of the auxiliary switch tube in the main circuit in the FPGA, the synchronization signal of the auxiliary switch tube is generated by using the synchronization signal generating module in the FPGA; at the same time, according to the register value R2 of the main switch tube in the main circuit in the FPGA, the synchronization signal of the main switch tube is generated by using the synchronization signal generating module in the FPGA.

[0074] Preferably, step (6) is specifically,

[0075] First, the synchronization signal of the main switch tube obtained in step (5) is used to obtain the corresponding time period T2 from the register of the FPGA;

[0076] Then, the duty cycle D of the synchronization signal is obtained using the time period T2 corresponding to the synchronization signal of the main switch tube. PWM :

[0077]

[0078] Where T PWM Represents a preset output period, which ranges from 80 μs to 120 μs, preferably 100 μs.

[0079] Finally, the duty cycle D of the synchronization signal of the main switch tube is obtained. PWM The duty cycle of the FPGA is adjusted to obtain a main switch PWM signal output when the LC parameters change.

[0080] In this process, the duty cycle adjustment process of FPGA is as follows:

[0081] First, set the duty cycle adjustment step ΔD of the PWM signal of the main switch tube in the main circuit step , whose value range is 1% to 4%;

[0082] Then, use the set duty cycle to adjust the step size ΔD step Get the duty cycle adjustment amplitude ΔD PWM :

[0083]

[0084] Finally, the duty cycle adjustment amplitude ΔD is obtained. PWM When the LC parameters change and the resonance period of the main switch tube increases, the duty cycle D of the synchronization signal of the main switch tube is increased. PWM (i.e. increase ΔD PWM ); when the LC parameters change so that the resonance period of the main switch tube is reduced, the duty cycle D of the synchronization signal of the main switch tube is reduced PWM (i.e. reducing ΔD PWM ) to output the PWM signal of the main switch tube.

[0085] Preferably, step (7) is specifically,

[0086] First, the synchronization signal of the auxiliary switch tube obtained in step (5) is made to have a first leading resonance before the PWM signal of the main switch tube generated in step (6) changes from a low level to a high level, so as to obtain a duration T of the auxiliary switch tube leading the resonance of the main switch tube for the first time. on .

[0087] Then, the synchronization signal of the auxiliary switch tube obtained in step (5) is made to have a second leading resonance before the PWM signal of the main switch tube changes from a high level to a low level, so that the duration of the auxiliary switch tube leading the resonance of the main switch tube for the second time is also T on .

[0088] Then, according to the duration T on Get the number of clock cycles N during which the auxiliary switch tube undergoes advanced resonance:

[0089]

[0090] The duration of the two leading resonances is T on The value range of T is 1μs to 5μs, preferably 3μs; CLK The period of the clock signal generated by the clock module in the FPGA, the preferred value of which is 20ns;

[0091] Finally, before the PWM signal of the main switch tube generated in step (6) is turned on, the PWM signals of the N auxiliary switch tubes are generated, and after the PWM signal is turned off, the PWM signals of the N auxiliary switch tubes are generated.

[0092] In general, the control method of the present invention can produce the following beneficial effects compared with the prior art through the technical solution conceived by the present invention:

[0093] (1) The present invention adopts step (2) and step (3), and through the application of DSP sampling and digital PI regulator, it can maintain the efficient and stable working state of the soft switching circuit under dynamic conditions. Through accurate sampling and timely adjustment of the sampling time, it can timely detect and compensate for the changes in LC parameters to ensure the stability of the resonant frequency and the overall performance of the circuit. By adapting the LC parameters, the precise control of the resonant frequency is achieved, thereby achieving precise tuning control, thereby solving the technical problems of low PWM control accuracy and response speed in the quasi-resonant circuit, zero-switch PWM control, and zero-conversion PWM control methods of the existing soft switching circuits;

[0094] (2) The present invention adopts step (4), which accurately calculates the sampled data and the data adjusted by the digital PI, monitors and adjusts the resonant period in the soft switching circuit in real time to adapt to the change of the LC parameters, and can dynamically obtain the change of the resonant period of the auxiliary switch tube and the main switch tube. Therefore, it can solve the problem of inductance and capacitance value drift when the LC parameters change in the existing zero-switch PWM control and zero-conversion PWM control methods, as well as the technical problem that the long resonant period is limited to the change of the duty cycle;

[0095] (3) The present invention adopts step (5) and utilizes the design of generating synchronization signals of different frequencies to align the precise timing of each control module of the system. By precisely controlling the startup and operation time of each module, the stability of current and voltage and the coordination of the system are ensured, and the control accuracy is optimized; at the same time, by simplifying the timing design of the system, the complexity of timing matching between modules is avoided, and the anti-interference ability of the system is further enhanced. Therefore, it can solve the technical problem that the existing PWM control method of realizing soft switching circuit by digitalization causes errors due to inconsistent timing, which in turn leads to increased switching loss of the soft switching circuit and reduced overall efficiency;

[0096] (4) The present invention adopts step (6) and step (7), and the PWM signal duty cycle adjustment mechanism set in the FPGA automatically adjusts the step size and duty cycle, and dynamically adjusts the PWM signal output according to the sampled data, thereby improving the flexibility and automation of the system and enhancing the adaptability of the system in complex electrical environments. Furthermore, the DSP is responsible for data acquisition, processing and PI adjustment, and the FPGA is responsible for bus control, output PWM and other tasks. Therefore, the technical problems of the existing PWM control method for realizing soft switching circuits through digitalization, such as the low accuracy of DSP in controlling PWM waveform and the insufficient applicability of FPGA in optimizing the implementation method, can be solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0097] Figure 1 is a schematic block diagram of a soft switching circuit of the present invention;

[0098] Figure 2 It is a topological diagram of the main circuit in the soft switching circuit of the present invention;

[0099] Figure 3 It is the waveform and MATLAB simulation diagram of the main circuit;

[0100] Figure 4 It is the main circuit topology diagram with dual auxiliary switches;

[0101] Figure 5 It is the flow chart of sampling module;

[0102] Figure 6 This is the main program flow chart of the digital PI regulator;

[0103] Figure 7 It is a digital implementation method for synchronous signal generation;

[0104] Figure 8 This is the simulation waveform of the main switch tube PWM;

[0105] Fig. 9 This is the simulation waveform of the auxiliary switch tube PWM;

[0106] Fig.10 It is the PWM simulation waveform of the switch tube of the main circuit with dual auxiliary switches. DETAILED DESCRIPTION

[0107] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention. In addition, the technical features involved in the various embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0108] like Figure 1 As shown, the present invention provides a soft switching circuit, including a main circuit, a sampling module, a regulating module, a clock module, a synchronous signal generating module, and a PWM output module.

[0109] The sampling module is respectively connected to the output end of the main circuit and the input end of the regulating module, and the synchronization signal generating module is respectively connected to the output end of the regulating module and the input end of the PWM output module.

[0110] like Figure 2 As shown, the main circuit includes an input voltage source V in , filter inductor L f , resonant inductor L a , resonant capacitor C a , Main switch tube VT s , and auxiliary switch tube VT a . Input voltage V in The positive electrode of the main switch tube VT s The positive electrode and resonant capacitor C a The negative pole of the main switch VT s The negative pole of the resonant inductor L a The positive pole and filter inductor L f Auxiliary switch tube VT a The positive terminal of the resonant capacitor C a , the negative pole is connected to the input voltage V in The negative pole, resonant inductor L a , resonant capacitor C a Connect to the sampling module.

[0111] The adjustment module and the sampling module are integrated in a digital signal processor (DSP for short). The model of the DSP used is TMS320F28335.

[0112] The regulating module comprises a digital PI regulator, and the digital PI regulator is connected to the synchronization signal generating module.

[0113] The sampling module includes a general-purpose input / output (GPIO) pin, an analog digital conversion (ADC) module, and a soft-start voltage regulator. The GPIO pin is connected to the ADC module, the data register in the ADC module is connected to the soft-start voltage regulator, and the soft-start voltage regulator is connected to the digital PI regulator.

[0114] The clock module, the synchronization signal generation module and the PWM output module are all integrated in a Field Programmable Gate Array (FPGA). The model of the FPGA used is XC6SLX16.

[0115] The clock module is connected to the synchronization signal generation module and the PWM output module respectively, and the synchronization signal generation module is connected to the synchronization signal register in the PWM output module.

[0116] The present invention also provides a fully digital PWM control method for the above soft switching circuit, comprising the following steps:

[0117] (1) Obtaining circuit parameters of the soft switching circuit, and optimizing the obtained circuit parameters to obtain characteristic parameters of the main circuit in the soft switching circuit and a resonance period of the main switch in the main circuit.

[0118] The circuit diagram of the main circuit in the soft switching circuit is as follows Figure 2 As shown, based on the Buck converter circuit, a resonant inductor L is added. a , resonant capacitor C a , auxiliary switch tube VT a and auxiliary diode VD a The resonant branch formed.

[0119] The waveform of the main circuit topology diagram is as follows Figure 3 (a) shown. Figure 3 (b) is a MATLAB simulation diagram of the working process of the soft switching circuit. The red waveform is the voltage change of the main switch tube, and the red waveform is the current change curve.

[0120] Specifically, this step includes, first, obtaining the circuit parameters of the main circuit in the soft switching circuit, including: input voltage V in and filter inductor L f The current value I f .

[0121] Then, according to the input voltage V in and filter inductor L f The current value I f Obtain the resonant inductance L on the auxiliary branch that satisfies the following inequality (1): a and resonant capacitor C a .

[0122]

[0123] The resulting input voltage V in , resonant inductance L on auxiliary branch a The voltage V La and current ILa , resonant capacitor C a The voltage V Ca and current I Ca , resonant inductor L a , and the resonant capacitor C a Together they constitute the characteristic parameters of the main circuit of the soft switching circuit.

[0124] Then, according to the obtained resonant inductance L a and resonant capacitor C a , and the resonance period T of the auxiliary switch tube in the main circuit is obtained by the following formula (2): a :

[0125]

[0126] Finally, according to the obtained resonance period of the auxiliary switch tube in the main circuit, the resonance period T of the main switch tube in the main circuit is obtained by the following formula (3): s :

[0127]

[0128] The proportional coefficient α=0.1.

[0129] The advantage of this step is that the auxiliary switch tube VT is replaced by the main circuit in the soft switching circuit adopted. a And the diode VD of the auxiliary switch tube a The main switch tube VT in the main circuit is turned on under the condition of zero voltage switching (Zero voltage switching, referred to as ZVS) and turned off under the condition of zero current switching (Zero current switching, referred to as ZCS), which reduces the loss of the switch tube during the shutdown process. In addition, in addition to the soft switching circuit adopted in this embodiment, due to the adaptability of the present invention, it is also applicable to the circuit of multiple auxiliary switches. Figure 4 The circuit configuration shown, the auxiliary switch tube T B The auxiliary switch tube T A The resonant current is then resonated after the resonance of the main switch, further reducing the loss during shutdown. The switch is turned off when the current drops to zero across the main switch, thereby reducing the switch stress.

[0130] (2) Using a digital signal processing method, the characteristic parameters of the main circuit in the soft switching circuit obtained in step (1) are subjected to analog digital conversion (ADC) processing to obtain converted sampling current values ​​and sampling voltage values.

[0131] The specific steps of this step are as follows: first, the resonant inductor L in the auxiliary branch of the main circuit is aThe voltage and current output terminals, and the resonant capacitor C a The output terminals of the voltage and current are connected to the input terminals of the ADC module in the digital signal processor (DSP) to output the voltage and current parameters of the resonant inductor and the resonant capacitor;

[0132] Then, by initializing the GPIO pin as the input of the ADC module and setting the sampling frequency and resolution of the ADC module (where the sampling frequency of the ADC module is set to 192kHz and the resolution is set to 12 bits), the voltage and current parameters of the resonant inductor and the resonant capacitor are converted by ADC.

[0133] Finally, the current data and voltage data of the data register in the ADC module are obtained, and the command current calculation is performed on the current data through the digital signal processing method to obtain the resonant capacitor C a The sampling current value I Ca The voltage data is processed by the soft start voltage regulator to obtain the resonant inductance L a The sampling voltage value V La .

[0134] The sampling process of this step is as follows Figure 5 shown.

[0135] The advantage of this step is that the high sampling frequency and high resolution ensure the accurate capture of the fast-changing soft-switching circuit parameters, and also enhance the stability and reliability of the system.

[0136] (3) Using a digital PI regulator, an error adjustment operation is performed on the converted sampled voltage value obtained in step (2) to obtain a voltage control value.

[0137] This step includes the following sub-steps:

[0138] (3-1) The sampled voltage value V obtained in step (2) is La , and subtract it from the preset reference voltage value r(k) of the kth sampling to obtain the current error e(k) of the kth sampling, where k is an arbitrary natural number:

[0139] e(k)=r(k)-V La (4)

[0140] The preset k-th sampling reference voltage value r(k) has a value range of 0V to 600V, preferably 200V.

[0141] (3-2) Use a digital PI regulator to process the current error e(k) of the kth sampling obtained in step (3-1) to obtain the voltage control value u'(k) of the kth sampling:

[0142]

[0143] Where K p is the proportional gain, and its value range is 0 to 20, preferably 15. The current error e(k) of the kth sampling is the input of the digital PI regulator. T is the sampling period, and its value range is 0.1us to 12us, preferably 10us. The voltage control amount u'(k) of the kth sampling is the output of the digital PI regulator.

[0144] (3-3) The k-th sampled voltage control quantity u'(k) obtained in step (3-2) is discretized by transfer function to obtain the differential equation of the k-th sampled voltage control quantity u(k):

[0145]

[0146] Where K i is the integral gain, and its value range is 1 to 6, preferably 5.

[0147] (3-4) The differential equation of the voltage control quantity u(k) obtained in step (3-3) is subjected to the k-1th sampling process to obtain the voltage control quantity u(k-1) of the k-1th sampling.

[0148] (3-5) Determine whether the voltage control value u(k-1) obtained in step (3-4) at the k-1th sampling is greater than the maximum input voltage u MAX If yes, go to step (3-6), otherwise go to step (3-7).

[0149] Specifically, the maximum input voltage u MAX The value range is 0V to 800V, preferably 700V.

[0150] (3-6) Update the k-th sampled voltage control value u(k) obtained in step (3-3) to u MAX , then go to step (3-9);

[0151] (3-7) Determine whether the voltage control value u(k-1) sampled at the k-1th time is less than the minimum input voltage u MIN If yes, go to step (3-8), otherwise go to step (3-9).

[0152] Specifically, the minimum input voltage u MIN The value range is -200V to 0V, preferably -200V.

[0153] (3-8) Update the k-th sampled voltage control value u(k) obtained in step (3-3) to uMIN , then go to step (3-9).

[0154] (3-9) The voltage control amount u(k) sampled at the kth time after the update is used as the voltage control amount V La '.

[0155] The main program flow chart of the digital PI regulator is as follows Figure 6 shown.

[0156] The advantage of this step is that by accurately calculating the error and adjusting the control amount, the system output can be accurately controlled, thereby improving the steady-state accuracy of the system. It can respond quickly to deviations, reduce the response time of the system, and improve the dynamic performance of the system. By adjusting the control amount in real time, it can adapt to changes in system parameters and enhance the robustness of the system. This produces a greater beneficial effect in precise tuning control, eliminating steady-state errors, and making the system output more accurate and stable.

[0157] (4) According to the sampled current value and the sampled voltage value obtained in step (2) and the voltage control value obtained in step (3), the real-time resonance period of the auxiliary switch tube and the main switch tube of the main circuit in the soft switching circuit after the LC parameters change.

[0158] This step specifically includes, first, obtaining the sampled current value I according to step (2) Ca and respectively obtain the resonant capacitance C a The size change of ΔC a and resonant inductor L a The size change ΔL a :

[0159]

[0160] Where Δt is the change in time, ΔV Ca is the lower resonant capacitor C a The voltage change, ΔI La is the resonant inductance L at Δt a The current changes.

[0161] Then, according to the obtained resonant capacitance C a The size change of ΔC a and resonant inductor L a The size change ΔL a Obtain the resonant period change T' of the auxiliary switch tube in the main circuit a The resonant cycle change T of the main switch tube in the main circuit s ':

[0162]

[0163] Finally, the resonant period of the auxiliary switch in the main circuit changes to T′ a The resonant period T of the auxiliary switch tube in the main circuit obtained by equation (3) in step (1) is a Subtract to obtain the real-time resonant period T of the auxiliary switch tube of the main circuit in the soft switching circuit after the LC parameters change. SYNC1 ; Change the resonant period of the main switch in the main circuit by T s 'The resonant period T of the main switch tube in the main circuit obtained by equation (2) in step (1) S Subtract to obtain the real-time resonant period T of the main switch tube of the main circuit in the soft switching circuit after the LC parameters change. SYNC2 .

[0164] (5) Generate a synchronization signal of the auxiliary switch tube and a synchronization signal of the main switch tube according to the real-time resonance period of the auxiliary switch tube and the main switch tube after the LC parameters change obtained in step (4).

[0165] This step specifically includes: first, according to the real-time resonance period T of the auxiliary switch tube obtained in step (4), SYNC1 Get the switching frequency f of the auxiliary switch tube PWM1 , and according to the real-time resonant period T of the main switch tube SYNC2 Get the switching frequency f of the main switch tube PWM2 :

[0166]

[0167] Then, according to the switching frequency f of the auxiliary switch tube obtained PWM1 Get the register value R1 of the auxiliary switch in the FPGA, and according to the switching frequency f of the main switch PWM2 Get the register value R2 of the main switch in FPGA:

[0168]

[0169] where f CLK The frequency of the clock signal generated by the clock module in the FPGA is preferably 50 MHz.

[0170] Finally, according to the register value R1 of the auxiliary switch tube in the main circuit in the FPGA, the synchronization signal of the auxiliary switch tube is generated by using the synchronization signal generating module in the FPGA; at the same time, according to the register value R2 of the main switch tube in the main circuit in the FPGA, the synchronization signal of the main switch tube is generated by using the synchronization signal generating module in the FPGA.

[0171] The digital implementation method of synchronous signal generation is as follows Figure 7 shown.

[0172] The advantage of this step is that the synchronization signal generating module can generate synchronization signals with different clock cycles, and coordinate various parts of the system based on the synchronization signal to ensure the stability of current and voltage.

[0173] (6) Dynamically adjust the PWM duty cycle of the synchronization signal of the main switch tube obtained in step (5) to obtain the PWM signal of the main switch tube.

[0174] Specifically, this step includes, first, using the synchronization signal of the main switch tube obtained in step (5) to obtain the corresponding time period T2 from the register of the FPGA;

[0175] Then, the duty cycle D of the synchronization signal is obtained using the time period T2 corresponding to the synchronization signal of the main switch tube. PWM :

[0176]

[0177] Where T PWM Represents a preset output period, which ranges from 80 μs to 120 μs, preferably 100 μs.

[0178] Finally, the duty cycle D of the synchronization signal of the main switch tube is obtained. PWM The duty cycle of the FPGA is adjusted to obtain a main switch PWM signal output when the LC parameters change.

[0179] In this process, the duty cycle adjustment process of FPGA is as follows:

[0180] First, set the duty cycle adjustment step ΔD of the PWM signal of the main switch tube in the main circuit step , its value range is 1% to 4%, preferably 2%.

[0181] Then, use the set duty cycle to adjust the step size ΔD step Get the duty cycle adjustment amplitude ΔD PWM :

[0182]

[0183] Finally, the duty cycle adjustment amplitude ΔD is obtained. PWM When the LC parameters change and the resonance period of the main switch tube increases, the duty cycle D of the synchronization signal of the main switch tube is increased. PWM (i.e. increase ΔD PWM ); when the LC parameters change so that the resonance period of the main switch tube is reduced, the duty cycle D of the synchronization signal of the main switch tube is reduced PWM (i.e. reducing ΔD PWM ) to output the PWM signal of the main switch tube.

[0184] In this embodiment, the waveform of the main switch tube in the main circuit is as follows: Figure 8 As shown, Figure 8 (a) PWM waveforms of the main and auxiliary switches in the main circuit, for example, the initial resonant inductor L a is 15μH, the resonant capacitor C a is 6.75nF, and the duty cycle of the main switch in the output main circuit is D PWM When the LC parameters change, the FPGA performs duty cycle adjustment, such as the resonant inductor L a becomes 25μH, the resonant capacitor C a When it becomes 25.3pF, the duty cycle of the main switch in the output main circuit is D PWM is 50%, and the output waveform is always in a soft switching state.

[0185] (7) Generate a PWM signal for the auxiliary switch tube according to the synchronization signal of the auxiliary switch tube obtained in step (5) and the PWM signal of the main switch tube obtained in step (6).

[0186] Specifically, this step includes, first, making the synchronization signal of the auxiliary switch tube obtained in step (5) have a first leading resonance before the PWM signal of the main switch tube generated in step (6) changes from a low level to a high level, so as to obtain a duration T of the auxiliary switch tube leading the resonance of the main switch tube for the first time. on .

[0187] Then, the synchronization signal of the auxiliary switch tube obtained in step (5) is made to have a second leading resonance before the PWM signal of the main switch tube changes from a high level to a low level, so that the duration of the auxiliary switch tube leading the resonance of the main switch tube for the second time is also T on .

[0188] Then, according to the duration T on Get the number of clock cycles N during which the auxiliary switch tube undergoes advanced resonance:

[0189]

[0190] The duration of the two leading resonances is T on The value range of T is 1μs to 5μs, preferably 3μs; CLK The period of the clock signal generated by the clock module in the FPGA is preferably 20ns; the value T is set by the advanced resonance time on The preferred value of can be calculated that the number of clock cycles N during which the auxiliary switch tube undergoes advanced resonance is 150.

[0191] Finally, before the PWM signal of the main switch tube generated in step (6) is turned on, the PWM signals of the N auxiliary switch tubes are generated, and after the PWM signal is turned off, the PWM signals of the N auxiliary switch tubes are generated. The simulation diagram is as follows: Fig. 9 shown.

[0192] The advantage of this step is that no matter how the duty cycle of the main switch tube in the main circuit changes, the resonant action of the auxiliary switch tube will be accurately controlled, thereby improving the stability and adaptability of the system. And for the main circuit with dual auxiliary switch tubes, the following can also be achieved Fig.10 The PWM simulation waveforms of each switch tube in the main circuit are shown.

[0193] It will be easily understood by those skilled in the art that the above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A soft switching circuit, comprising a main circuit, a sampling module, a regulating module, a clock module, a synchronization signal generating module, and a PWM output module, characterized in that: The sampling module is respectively connected to the output end of the main circuit and the input end of the regulating module, and the synchronization signal generating module is respectively connected to the output end of the regulating module and the input end of the PWM output module. The adjustment module and the sampling module are integrated in the digital signal processor DSP; The regulating module comprises a digital PI regulator, and the digital PI regulator is connected to the synchronization signal generating module; The sampling module includes a general purpose input and output GPIO pin, an analog-to-digital conversion ADC module, and a soft-start voltage regulator; The GPIO pins are connected to the ADC module, the data register in the ADC module is connected to the soft-start voltage regulator, and the soft-start voltage regulator is connected to the digital PI regulator. The clock module, synchronization signal generation module and PWM output module are all integrated in the field programmable gate array FPGA; The clock module is connected to the synchronization signal generation module and the PWM output module respectively, and the synchronization signal generation module is connected to the synchronization signal register in the PWM output module.

2. The soft switching circuit according to claim 1, characterized in that: The main circuit includes an input voltage source, a filter inductor, a resonant inductor, a resonant capacitor, a main switch tube, and an auxiliary switch tube; The positive electrode of the input voltage is connected to the positive electrode of the main switch tube and the negative electrode of the resonant capacitor respectively; The negative electrode of the main switch tube is connected to the positive electrode of the resonant inductor and the positive electrode of the filter inductor respectively; The positive electrode of the auxiliary switch tube is connected to the resonant capacitor, and the negative electrode is connected to the negative electrode of the input voltage; The resonant inductor and the resonant capacitor are connected to the sampling module.

3. A fully digital PWM control method for a soft switching circuit according to claim 1 or 2, characterized in that: The following steps are involved: (1) Obtaining circuit parameters of the soft switching circuit, and optimizing the obtained circuit parameters to obtain characteristic parameters of the main circuit in the soft switching circuit and a resonance period of the main switch in the main circuit. (2) Using a digital signal processing method, the characteristic parameters of the main circuit in the soft switching circuit obtained in step (1) are subjected to analog-to-digital conversion (ADC) processing to obtain converted sampling current values ​​and sampling voltage values. (3) Using a digital PI regulator, an error adjustment operation is performed on the converted sampled voltage value obtained in step (2) to obtain a voltage control value. (4) According to the sampled current value and the sampled voltage value obtained in step (2) and the voltage control value obtained in step (3), the real-time resonance period of the auxiliary switch tube and the main switch tube of the main circuit in the soft switching circuit after the LC parameters change. (5) Generate a synchronization signal of the auxiliary switch tube and a synchronization signal of the main switch tube according to the real-time resonance period of the auxiliary switch tube and the main switch tube after the LC parameters change obtained in step (4). (6) Dynamically adjust the PWM duty cycle of the synchronization signal of the main switch tube obtained in step (5) to obtain the PWM signal of the main switch tube. (7) Generate a PWM signal for the auxiliary switch tube according to the synchronization signal of the auxiliary switch tube obtained in step (5) and the PWM signal of the main switch tube obtained in step (6).

4. The fully digital PWM control method of the soft switching circuit according to claim 3, characterized in that: Step (1) is specifically: First, obtain the circuit parameters of the main circuit in the soft switching circuit, including: input voltage V in and filter inductor L f The current value I f . Then, according to the input voltage V in and filter inductor L f The current value I f Obtain the resonant inductance L on the auxiliary branch that satisfies the following inequality (1): a and resonant capacitor C a . The resulting input voltage V in , resonant inductance L on auxiliary branch a The voltage V La and current I La , resonant capacitor C a The voltage V Ca and current I Ca , resonant inductor L a , and the resonant capacitor C a Together they constitute the characteristic parameters of the main circuit of the soft switching circuit. Then, according to the obtained resonant inductance L a and resonant capacitor C a , and the resonance period T of the auxiliary switch tube in the main circuit is obtained by the following formula (2): a : Finally, according to the obtained resonance period of the auxiliary switch tube in the main circuit, the resonance period T of the main switch tube in the main circuit is obtained by the following formula (3): s : The proportional coefficient α=0.

1.

5. The fully digital PWM control method of the soft switching circuit according to claim 3 or 4, characterized in that: Step (2) is specifically: First, the resonant inductor L in the auxiliary branch of the main circuit a The voltage and current output terminals, and the resonant capacitor C a The output terminals of the voltage and current are connected to the input terminals of the ADC module in the digital signal processor DSP to output the voltage and current parameters of the resonant inductor and the resonant capacitor; Then, by initializing the GPIO pin as the input of the ADC module and setting the sampling frequency and resolution of the ADC module (where the sampling frequency of the ADC module is set to 192kHz and the resolution is set to 12 bits), the voltage and current parameters of the resonant inductor and the resonant capacitor are converted by ADC. Finally, the current data and voltage data of the data register in the ADC module are obtained, and the command current calculation is performed on the current data through the digital signal processing method to obtain the resonant capacitor C a The sampling current value I Ca The voltage data is processed by the soft start voltage regulator to obtain the resonant inductance L a The sampling voltage value V La .

6. The fully digital PWM control method for a soft switching circuit according to any one of claims 3 to 5, characterized in that: Step (3) includes the following sub-steps: (3-1) The sampled voltage value V obtained in step (2) is La , and subtract it from the preset reference voltage value r(k) of the kth sampling to obtain the current error e(k) of the kth sampling, where k is an arbitrary natural number: e(k)=r(k)-V La (4) The preset k-th sampling reference voltage value r(k) has a value range of 0V to 600V, preferably 200V. (3-2) Use a digital PI regulator to process the current error e(k) of the kth sampling obtained in step (3-1) to obtain the voltage control value u'(k) of the kth sampling: Where K p is the proportional gain, the current error e(k) of the kth sampling is the input of the digital PI regulator, and T is the sampling period; (3-3) The k-th sampled voltage control quantity u'(k) obtained in step (3-2) is discretized by transfer function to obtain the differential equation of the k-th sampled voltage control quantity u(k): Where K i is the integral gain; (3-4) The differential equation of the voltage control quantity u(k) obtained in step (3-3) is subjected to the k-1th sampling process to obtain the voltage control quantity u(k-1) of the k-1th sampling. (3-5) Determine whether the voltage control value u(k-1) obtained in step (3-4) at the k-1th sampling is greater than the maximum input voltage u MAX If yes, go to step (3-6), otherwise go to step (3-7); where the maximum input voltage u MAX The value range is 0V to 800V, preferably 700V. (3-6) Update the k-th sampled voltage control value u(k) obtained in step (3-3) to u MAX , then go to step (3-9); (3-7) Determine whether the voltage control value u(k-1) sampled at the k-1th time is less than the minimum input voltage u MIN If yes, go to step (3-8), otherwise go to step (3-9); where the minimum input voltage u MIN The value range is -200V to 0V, preferably -200V. (3-8) Update the k-th sampled voltage control value u(k) obtained in step (3-3) to u MIN , then go to step (3-9). (3-9) The voltage control amount u(k) sampled at the kth time after the update is used as the voltage control amount V La '.

7. The fully digital PWM control method of the soft switching circuit according to claim 6, characterized in that: Step (4) is specifically: First, according to the sampling current value I obtained in step (2), Ca and respectively obtain the resonant capacitance C a The size change of ΔC a and resonant inductor L a The size change ΔL a : Where Δt is the change in time, ΔV Ca is the lower resonant capacitor C a The voltage change, ΔI La is the resonant inductance L at Δt a The current changes. Then, according to the obtained resonant capacitance C a The size change of ΔC a and resonant inductor L a The size change ΔL a Obtain the resonant period change T' of the auxiliary switch tube in the main circuit a The resonant cycle change T of the main switch tube in the main circuit s ': Finally, the resonant period of the auxiliary switch in the main circuit is changed by T a 'The resonant period T of the auxiliary switch tube in the main circuit obtained by equation (3) in step (1) a Subtract to obtain the real-time resonant period T of the auxiliary switch tube of the main circuit in the soft switching circuit after the LC parameters change. SYNC1 ; Change the resonant period of the main switch in the main circuit by T s 'The resonant period T of the main switch tube in the main circuit obtained by equation (2) in step (1) S Subtract to obtain the real-time resonant period T of the main switch tube of the main circuit in the soft switching circuit after the LC parameters change. SYNC2 .

8. The fully digital PWM control method of the soft switching circuit according to claim 7, characterized in that: Step (5) is specifically: First, the real-time resonant period T of the auxiliary switch tube obtained in step (4) SYNC1 Get the switching frequency f of the auxiliary switch tube PWM1 , and according to the real-time resonant period T of the main switch tube SYNC2 Get the switching frequency f of the main switch tube PWM2 : Then, according to the switching frequency f of the auxiliary switch tube obtained PWM1 Get the register value R1 of the auxiliary switch in the FPGA, and according to the switching frequency f of the main switch PWM2 Get the register value R2 of the main switch in FPGA: where f CLK The frequency of the clock signal generated by the clock module in the FPGA is preferably 50 MHz. Finally, according to the register value R1 of the auxiliary switch tube in the main circuit in the FPGA, the synchronization signal of the auxiliary switch tube is generated by using the synchronization signal generating module in the FPGA; at the same time, according to the register value R2 of the main switch tube in the main circuit in the FPGA, the synchronization signal of the main switch tube is generated by using the synchronization signal generating module in the FPGA.

9. The fully digital PWM control method of the soft switching circuit according to claim 8, characterized in that: Step (6) is specifically: First, the synchronization signal of the main switch tube obtained in step (5) is used to obtain the corresponding time period T2 from the register of the FPGA; Then, the duty cycle D of the synchronization signal is obtained using the time period T2 corresponding to the synchronization signal of the main switch tube. PWM : Where T PWM Represents a preset output period, which ranges from 80 μs to 120 μs, preferably 100 μs. Finally, the duty cycle D of the synchronization signal of the main switch tube is obtained. PWM The duty cycle of the FPGA is adjusted to obtain a main switch PWM signal output when the LC parameters change. In this process, the duty cycle adjustment process of FPGA is as follows: First, set the duty cycle adjustment step ΔD of the PWM signal of the main switch tube in the main circuit step , whose value range is 1% to 4%; Then, use the set duty cycle to adjust the step size ΔD step Get the duty cycle adjustment amplitude ΔD PWM : Finally, the duty cycle adjustment amplitude ΔD is obtained. PWM When the LC parameters change and the resonance period of the main switch tube increases, the duty cycle D of the synchronization signal of the main switch tube is increased. PWM (i.e. increase ΔD PWM ); when the LC parameters change so that the resonance period of the main switch tube is reduced, the duty cycle D of the synchronization signal of the main switch tube is reduced PWM (i.e. reducing ΔD PWM ) to output the PWM signal of the main switch tube.

10. The fully digital PWM control method of the soft switching circuit according to claim 9, characterized in that: Step (7) is specifically: First, the synchronization signal of the auxiliary switch tube obtained in step (5) is made to have a first leading resonance before the PWM signal of the main switch tube generated in step (6) changes from a low level to a high level, so as to obtain a duration T of the auxiliary switch tube leading the resonance of the main switch tube for the first time. on . Then, the synchronization signal of the auxiliary switch tube obtained in step (5) is made to have a second leading resonance before the PWM signal of the main switch tube changes from a high level to a low level, so that the duration of the auxiliary switch tube leading the resonance of the main switch tube for the second time is also T on . Then, according to the duration T on Get the number of clock cycles N during which the auxiliary switch tube undergoes advanced resonance: The duration of the two leading resonances is T on The value range of T is 1μs to 5μs, preferably 3μs; CLK The period of the clock signal generated by the clock module in the FPGA, the preferred value of which is 20ns; Finally, before the PWM signal of the main switch tube generated in step (6) is turned on, the PWM signals of the N auxiliary switch tubes are generated, and after the PWM signal is turned off, the PWM signals of the N auxiliary switch tubes are generated.

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