Programmable charge pump circuit based on CMOS technology

Abstract

The invention belongs to the field of integrated circuits, and particularly relates to a programmable charge pump circuit based on a CMOS process. The circuit comprises a charging current generation module, a discharging current generation module, a switching tube module, an output load module, a dummy module and an offset DAC module. The charging current generation module is used for providing charging current for the charge pump; the discharge current generation module is used for providing discharge current for the charge pump; the switching tube module and the output load module are used for converting a phase difference signal detected by the PFD into a current signal and controlling charging and discharging of the loop filter; the dummy module is used for suppressing the non-ideal effect of charge sharing and improving the switching speed of the charge pump; and the offset DAC module is used for improving integral noise and improving the linearity of the circuit. The matching performance of the charge pump is improved, the output voltage range during charging and discharging current matching is widened, the non-ideal effect of a CP circuit is weakened, and the charge pump has a good application prospect.

Description

Technical Field

[0001] The invention belongs to the field of integrated circuits, and in particular relates to a programmable charge pump circuit based on CMOS technology. Background Art

[0002] The single-ended charge pump has the advantages of simple circuit structure and low power consumption, and is currently a common charge pump structure. The existing single-ended charge pump has three single-ended charge pump structures with different constant current sources and switch positions.

[0003] In the drain switch charge pump, the instant of starting the switch will form a more obvious spike current because the switch is close to the output end, and further form a ripple voltage at the output end, which affects the jitter performance of the PLL circuit. At the same time, there will be multiple non-ideal effects, such as charge sharing and clock feedthrough. In the gate switch charge pump, the switch is transferred to the gate, which avoids the switch MOS tube working in the linear region being directly connected to the output end of the charge pump, eliminating charge injection and weakening the clock feedthrough effect. However, the gate capacitance of the current source MOS tube is large, and the time constant at the current source gate node will affect the speed of the switch tube. The current can be increased to compensate for the slow speed, but this will increase the power consumption of the circuit; the source switch charge pump avoids the non-ideal effects such as clock feedthrough and excessive charge injection caused by the switch of the drain switch charge pump being too close to the output end. However, due to the existence of the switch tube, the source potential at both ends of the current mirror will be different, which will reduce the matching performance of the charge pump, so an operational amplifier will be added to the circuit to improve it. Therefore, there is an urgent need for a programmable charge pump that meets the needs of different applications. Summary of the invention

[0004] In view of the shortcomings of the prior art, the present invention proposes a programmable charge pump circuit based on CMOS technology, which includes: a charging current generating module, a discharging current generating module, a switch tube module, an output load module, a dummy module and an offset DAC module; wherein:

[0005] The charging current generating module is used to provide charging current for the charge pump;

[0006] The discharge current generating module is used to provide a discharge current for the charge pump;

[0007] The switch tube module and the output load module are used to convert the phase difference signal detected by the PFD into a current signal to control the charging and discharging of the loop filter;

[0008] The dummy module is used to suppress the non-ideal effect of charge sharing and improve the switching speed of the charge pump;

[0009] The offset DAC module is used to improve the integrated noise and improve the linearity of the circuit.

[0010] Preferably, the charging current generating module includes a VrefP generating circuit, a first operational amplifier, an R CPP The output end of the VrefP generating circuit is connected to the positive input end of the first operational amplifier, and the negative input end of the first operational amplifier and the source of the PMOS tube M1 are connected to R CPP The output end of the generating circuit and the output end of the first operational amplifier are connected to the gate of the PMOS tube M1, and the drain of the PMOS tube M1 is connected to the switch tube module.

[0011] Further, the VrefP generating circuit includes four VrefP sub-circuits;

[0012] The first VrefP subcircuit includes a PMOS tube and a resistor; the source of the PMOS tube is connected to the power supply VDD, the drain of the PMOS tube is connected to one end of the resistor; the gate of the PMOS tube is connected to ResRefP <0> Control signal;

[0013] The second VrefP subcircuit includes two PMOS tubes and two resistors; the sources of the two PMOS tubes are connected to the power supply VDD, the drains of the two PMOS tubes are connected to one end of a resistor, and the gates of the two PMOS tubes are connected to ResRefP <1> Control signal;

[0014] The third VrefP subcircuit includes 4 PMOS tubes and 4 resistors; the sources of the 4 PMOS tubes are all connected to the power supply VDD, the drains of the 4 PMOS tubes are each connected to one end of a resistor, and the gates of the 4 PMOS tubes are all connected to ResRefP <2> Control signal;

[0015] The fourth VrefP subcircuit includes 8 PMOS tubes and 8 resistors; the sources of the 8 PMOS tubes are all connected to the power supply VDD, the drains of the 8 PMOS tubes are each connected to one end of a resistor, and the gates of the 8 PMOS tubes are all connected to ResRefP <3> Control signal;

[0016] The other ends of all the resistors of the four VrefP sub-circuits are connected to each other as the output of the VrefP generating circuit.

[0017] Furthermore, R CPP The generating circuit includes four R CPP Subcircuit;

[0018] First R CPPThe subcircuit includes three PMOS tubes, one NMOS tube and four resistors; the sources of the three PMOS tubes are all connected to the power supply VDD, the gate of one PMOS tube is connected to the drain of the PMOS tube and the gate of the NMOS tube, and the source of the NMOS tube is connected to the power supply VEE; the gate of another PMOS tube is connected to the drain of the NMOS tube, and the drain of the PMOS tube is connected to one end of two resistors; the drain of the last PMOS tube is connected to one end of the other two resistors, and the gate of the PMOS tube is connected to ResP <0> Control signal;

[0019] Second R CPP The subcircuit includes two PMOS tubes and four resistors; the sources of the two PMOS tubes are connected to the power supply VDD, the drains of the two PMOS tubes are connected to one end of the two resistors, and the gates of the two PMOS tubes are connected to ResP <1> Control signal;

[0020] The third R CPP The subcircuit includes 4 PMOS tubes and 8 resistors; the sources of the 4 PMOS tubes are connected to the power supply VDD, the drains of the 4 PMOS tubes are connected to one end of the two resistors, and the gates of the 4 PMOS tubes are connected to ResP <2> Control signal;

[0021] The Fourth R CPP The subcircuit includes 8 PMOS tubes and 16 resistors; the sources of the 8 PMOS tubes are connected to the power supply VDD, the drains of the 8 PMOS tubes are connected to one end of the two resistors, and the gates of the 8 PMOS tubes are connected to ResP <3> Control signal;

[0022] The Four Rs CPP The other ends of all resistors in the subcircuit are connected to each other as R CPP Generates the output of the circuit.

[0023] Preferably, the discharge current generating module includes a VrefN generating circuit, an operational amplifier, an R CPN The output end of the VrefN generating circuit is connected to the positive input end of the second operational amplifier, and the negative input end of the second operational amplifier and the source of the PMOS tube M6 are connected to R CPN The output end of the generating circuit and the output end of the second operational amplifier are connected to the gate of the PMOS tube M6, and the drain of the PMOS tube M6 is connected to the switch tube module.

[0024] Further, the VrefN generating circuit includes four VrefN sub-circuits;

[0025] The first VrefN subcircuit includes an NMOS tube and a resistor; the source of the NMOS tube is connected to the power supply VEE, the drain of the NMOS tube is connected to one end of the resistor; the gate of the NMOS tube is connected to ResRefN <0> Control signal;

[0026] The second VrefN subcircuit includes two NMOS tubes and two resistors; the sources of the two NMOS tubes are connected to the power supply VEE, the drains of the two NMOS tubes are connected to one end of a resistor, and the gates of the two NMOS tubes are connected to ResRefN. <1> Control signal;

[0027] The third VrefN subcircuit includes 4 NMOS tubes and 4 resistors; the sources of the 4 NMOS tubes are connected to the power supply VEE, the drains of the 4 NMOS tubes are connected to one end of a resistor, and the gates of the 4 NMOS tubes are connected to ResRefN. <2> Control signal;

[0028] The fourth VrefN subcircuit includes 8 NMOS tubes and 8 resistors; the sources of the 8 NMOS tubes are all connected to the power supply VEE, the drains of the 8 NMOS tubes are each connected to one end of a resistor, and the gates of the 8 NMOS tubes are all connected to ResRefN. <3> Control signal;

[0029] The other ends of all the resistors of the four VrefN sub-circuits are connected to each other as the output of the VrefN generating circuit.

[0030] Furthermore, R CPN The generating circuit includes four R CPN Subcircuit;

[0031] First R CPN The subcircuit includes three NMOS tubes, one PMOS tube and four resistors; the sources of the three NMOS tubes are all connected to the power supply VEE, the gate of one NMOS tube is connected to the drain of the NMOS tube and the gate of the PMOS tube, and the source of the PMOS tube is connected to the power supply VDD; the gate of another NMOS tube is connected to the drain of the PMOS tube, and the drain of the NMOS tube is connected to one end of two resistors; the drain of the last NMOS tube is connected to one end of the other two resistors, and the gate of the NMOS tube is connected to ResN. <0> Control signal;

[0032] Second R CPN The subcircuit includes two NMOS tubes and four resistors; the sources of the two NMOS tubes are connected to the power supply VEE, the drains of the two NMOS tubes are connected to one end of the two resistors, and the gates of the two NMOS tubes are connected to ResN. <1> Control signal;

[0033] The third R CPNThe subcircuit includes 4 NMOS tubes and 8 resistors; the sources of the 4 NMOS tubes are connected to the power supply VEE, the drains of the 4 NMOS tubes are connected to one end of the two resistors, and the gates of the 4 NMOS tubes are connected to ResN. <2> Control signal;

[0034] The Fourth R CPN The subcircuit includes 8 NMOS tubes and 16 resistors; the sources of the 8 NMOS tubes are connected to the power supply VEE, the drains of the 8 NMOS tubes are connected to one end of the two resistors, and the gates of the 8 NMOS tubes are connected to ResN. <3> Control signal;

[0035] The Four Rs CPN The other ends of all resistors in the subcircuit are connected to each other as R CPN Generates the output of the circuit.

[0036] Preferably, the switch tube module includes a buffer, a PMOS tube M2, a PMOS tube M3, an NMOS tube M4 and an NMOS tube M5; the sources of the PMOS tube M2 and the PMOS tube M3 are both connected to the output end of the charging current generating module, the drain of the PMOS tube M2 is connected to the drain of the NMOS tube M4, the negative input end of the buffer, the output end of the buffer and the dummy module; the drain of the PMOS tube M3 is connected to the drain of the NMOS tube M5, the positive input end of the buffer, the output load module and the offset DAC module; the sources of the NMOS tube M4 and the NMOS tube M5 are both connected to the output end of the discharge current generating module.

[0037] Preferably, the offset DAC module includes four offset sub-circuits;

[0038] The first offset subcircuit includes an NMOS tube and a resistor. The source of the NMOS tube is connected to the power supply VEE, the drain of the NMOS tube is connected to one end of the resistor, and the other end of the resistor is connected to the output end of the offset DAC module; the gate of the NMOS tube is connected to ResDacN <0> Control signal;

[0039] The second offset subcircuit includes two NMOS tubes and two resistors. The sources of the two NMOS tubes are connected to the power supply VEE, the drains of the two NMOS tubes are connected to one end of a resistor, and the other ends of the two resistors are connected to the output end of the offset DAC module; the gates of the two NMOS tubes are connected to ResDacN <1> Control signal;

[0040] The third offset subcircuit includes 4 NMOS tubes and 4 resistors. The sources of the 4 NMOS tubes are connected to the power supply VEE, the drains of the 4 NMOS tubes are connected to one end of a resistor, and the other ends of the 4 resistors are connected to the output end of the offset DAC module; the gates of the 4 NMOS tubes are connected to ResDacN <2> Control signal;

[0041] The third offset subcircuit includes 4 NMOS tubes and 4 resistors. The sources of the 4 NMOS tubes are connected to the power supply VEE, the drains of the 4 NMOS tubes are connected to one end of a resistor, and the other ends of the 4 resistors are connected to the output end of the offset DAC module; the gates of the 4 NMOS tubes are connected to ResDacN <2> Control signal;

[0042] The fourth offset subcircuit includes 8 NMOS tubes and 8 resistors. The sources of the 8 NMOS tubes are connected to the power supply VEE, the drains of the 8 NMOS tubes are connected to one end of a resistor, the other ends of the 8 resistors are connected to the output end of the offset DAC module, and the gates of the 8 NMOS tubes are connected to ResDacN. <3> Control signal.

[0043] Preferably, the output load module and the dummy module are each composed of four capacitors connected in parallel.

[0044] The beneficial effects of the present invention are as follows: the charge pump (CP) circuit with programmable output current designed by the present invention adopts a 4-bit output current programmable design, the output current size is 100uA to 5.1mA, and the output node voltage range can reach 0.3 to 1.5V when the power supply voltage is 1.8V. Under a 1.8V power supply, when the output voltage changes from 0.3V to 1.5V, the proposed CP can achieve a DC current mismatch of less than 0.01%. The circuit designed by the present invention meets the requirements of the charge pump phase-locked loop system, and is of great significance to the design of millimeter wave and terahertz frequency sources in the future. The source switch single-ended output CP circuit with an operational amplifier designed by the present invention further optimizes the performance of the CP, uses the high gain and "virtual short" principle of the operational amplifier for level clamping, improves the matching performance of the charge pump, improves the output voltage range when the charge and discharge currents are matched, and weakens the non-ideal effect of the CP circuit, and has good application prospects. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It is a schematic diagram of the structure of a programmable charge pump circuit based on CMOS technology in the present invention;

[0046] Figure 2 Schematic diagram of the VrefP generating circuit structure in the present invention;

[0047] Figure 3 R in the present invention CPP Generate a circuit structure schematic diagram;

[0048] Figure 4 is a schematic diagram of the structure of the first error amplifier in the present invention;

[0049] Figure 5 Schematic diagram of the structure of the VrefN generating circuit in the present invention;

[0050] Figure 6 R in the present invention CPN Generate a circuit structure schematic diagram;

[0051] Figure 7 is a schematic diagram of the structure of the second error amplifier in the present invention;

[0052] Figure 8 It is a schematic diagram of the structure of the switch tube module, the output load module and the dummy module in the present invention;

[0053] Fig. 9 It is a schematic diagram of the structure of the buffer in the present invention;

[0054] Fig.10 This is a schematic diagram of the structure of the offset DAC module in the present invention;

[0055] Fig.11 This is a simulation result diagram of VrefP in the charging branch of the present invention;

[0056] Fig.12 This is a diagram of the simulation results of RCPP in the charging branch of the present invention;

[0057] Fig.13 It is a simulation result diagram of VrefN in the discharge branch of the present invention;

[0058] Fig.14 This is a diagram of the simulation results of RCPN in the discharge branch of the present invention;

[0059] Fig.15 This is a diagram showing the functional verification result of the offset DAC in the present invention;

[0060] Fig.16 This is a simulation diagram before CP current mismatch in the present invention;

[0061] Fig.17 This is a simulation diagram before the CP current mismatch in the present invention;

[0062] Fig.18 This is a charging characteristic diagram of the charge pump in the present invention;

[0063] Fig.19 is a discharge characteristic diagram of the charge pump in the present invention;

[0064] Fig. 20 This is a diagram of the noise phase simulation results in the present invention. DETAILED DESCRIPTION

[0065] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0066] The present invention proposes a programmable charge pump circuit based on CMOS technology, such as Figure 1 As shown, the circuit includes: a charging current generating module, a discharging current generating module, a switch tube module, an output load module, a dummy module and an offset DAC module. The discharging current generating module, the output load module, the dummy module and the offset DAC module are all connected to the switch tube module.

[0067] The charge pump works mainly by programming the control signal to obtain the charge and discharge current, where the offset DAC pulls the PFD / charge pump operating point into the linear region to improve the noise in the fractional operation. The following is the specific structure and function description of each module:

[0068] Charging current generation module:

[0069] The charging current generating module is used to provide charging current for the charge pump. The module includes a VrefP generating circuit, a first operational amplifier, R CPP The output end of the VrefP generating circuit is connected to the positive input end of the first operational amplifier, and the negative input end of the first operational amplifier and the source of the PMOS tube M1 are connected to R CPP The output end of the generating circuit, the output end of the first operational amplifier is connected to the gate of the PMOS tube M1, and the drain of the PMOS tube M1 is connected to the switch tube module; the VrefP generating circuit generates a VrefP voltage, R CPP Generating circuit generates R CPP The voltage and current of the two are divided to obtain the charging current I CPP .

[0070] like Figure 2 As shown, the VrefP generating circuit includes four VrefP sub-circuits, specifically:

[0071] The first VrefP subcircuit includes a PMOS tube and a resistor; the source of the PMOS tube is connected to the power supply VDD, the drain of the PMOS tube is connected to one end of the resistor; the gate of the PMOS tube is connected to ResRefP <0> Control signal;

[0072] The second VrefP subcircuit includes two PMOS tubes and two resistors; the sources of the two PMOS tubes are connected to the power supply VDD, the drains of the two PMOS tubes are connected to one end of a resistor, and the gates of the two PMOS tubes are connected to ResRefP <1> Control signal;

[0073] The third VrefP subcircuit includes 4 PMOS tubes and 4 resistors; the sources of the 4 PMOS tubes are all connected to the power supply VDD, the drains of the 4 PMOS tubes are each connected to one end of a resistor, and the gates of the 4 PMOS tubes are all connected to ResRefP <2> Control signal;

[0074] The fourth VrefP subcircuit includes 8 PMOS tubes and 8 resistors; the sources of the 8 PMOS tubes are all connected to the power supply VDD, the drains of the 8 PMOS tubes are each connected to one end of a resistor, and the gates of the 8 PMOS tubes are all connected to ResRefP <3> Control signal;

[0075] The other ends of all the resistors of the four VrefP sub-circuits are connected to each other as the output of the VrefP generating circuit.

[0076] In the VrefP generation circuit, by changing the control bit of cpResRefP<3:0>, the on-off of the PMOS switch can be changed, thereby changing the total resistance of the parallel connected circuit; if the control bit code changes from 0000 to 1111, the number of parallel resistors will decrease step by step, the total resistance value will increase, and VrefP will decrease.

[0077] like Figure 3 As shown, R CPP The generating circuit includes four R CPP Subcircuit, specifically:

[0078] First R CPP The subcircuit includes three PMOS tubes, one NMOS tube and four resistors; the sources of the three PMOS tubes are all connected to the power supply VDD, the gate of one PMOS tube is connected to the drain of the PMOS tube and the gate of the NMOS tube, and the source of the NMOS tube is connected to the power supply VEE; the gate of another PMOS tube is connected to the drain of the NMOS tube, and the drain of the PMOS tube is connected to one end of two resistors; the drain of the last PMOS tube is connected to one end of the other two resistors, and the gate of the PMOS tube is connected to ResP <0> Control signal;

[0079] Second R CPP The subcircuit includes two PMOS tubes and four resistors; the sources of the two PMOS tubes are connected to the power supply VDD, the drains of the two PMOS tubes are connected to one end of the two resistors, and the gates of the two PMOS tubes are connected to ResP <1> Control signal;

[0080] The third RCPP The subcircuit includes 4 PMOS tubes and 8 resistors; the sources of the 4 PMOS tubes are connected to the power supply VDD, the drains of the 4 PMOS tubes are connected to one end of the two resistors, and the gates of the 4 PMOS tubes are connected to ResP <2> Control signal;

[0081] The Fourth R CPP The subcircuit includes 8 PMOS tubes and 16 resistors; the sources of the 8 PMOS tubes are connected to the power supply VDD, the drains of the 8 PMOS tubes are connected to one end of the two resistors, and the gates of the 8 PMOS tubes are connected to ResP <3> Control signal;

[0082] The Four Rs CPP The other ends of all resistors in the subcircuit are connected to each other as R CPP Generates the output of the circuit.

[0083] R CPP In the generation circuit, by changing the control bit of cpResP<3:0>, the on and off of the PMOS switch can be changed, thereby changing the total resistance of the parallel connected circuit; if the control bit changes from 0000 to 1111, the number of parallel resistors will decrease step by step, and the total resistance will increase, R CPP Increase.

[0084] After VrefP is generated, it needs to be output to the charging branch of the charge pump through the error amplifier. The purpose is to adjust the output of PMOS through the operational amplifier to stabilize the voltage. For example, when the voltage of the charging branch decreases, it is fed back to inn, causing the amplifier output voltage to increase, and the gate voltage of PMOS to increase, |V GS | decreases, so the current decreases, the resistance voltage decreases, and finally the charging branch voltage increases, forming a negative feedback. The feedback coefficient β=1, A is the open-loop gain, V REF Indicates the reference voltage.

[0085] The first error amplifier is Figure 4 As shown, the first stage is OTA, nmos differential pair input, pmos current mirror as load, forming an active current mirror, the second stage common source, Miller capacitor for frequency compensation, zeroing resistor to eliminate RHP zero, the amplifier as a whole is biased by NMOS current mirror copy current, PD signal controls whether the amplifier is working, when PD is high and PD2 is low, the circuit works.

[0086] Discharge current generation module:

[0087] The discharge current generation module is used to provide discharge current for the charge pump. The module includes a VrefN generation circuit, an operational amplifier, R CPNThe output end of the VrefN generating circuit is connected to the positive input end of the second operational amplifier, and the negative input end of the second operational amplifier and the source of the PMOS tube M6 are connected to R CPN The output end of the generating circuit and the output end of the second operational amplifier are connected to the gate of the PMOS tube M6, and the drain of the PMOS tube M6 is connected to the switch tube module.

[0088] like Figure 5 As shown, the VrefN generating circuit includes four VrefN sub-circuits, specifically:

[0089] The first VrefN subcircuit includes an NMOS tube and a resistor; the source of the NMOS tube is connected to the power supply VEE, the drain of the NMOS tube is connected to one end of the resistor; the gate of the NMOS tube is connected to ResRefN <0> Control signal;

[0090] The second VrefN subcircuit includes two NMOS tubes and two resistors; the sources of the two NMOS tubes are connected to the power supply VEE, the drains of the two NMOS tubes are connected to one end of a resistor, and the gates of the two NMOS tubes are connected to ResRefN. <1> Control signal;

[0091] The third VrefN subcircuit includes 4 NMOS tubes and 4 resistors; the sources of the 4 NMOS tubes are connected to the power supply VEE, the drains of the 4 NMOS tubes are connected to one end of a resistor, and the gates of the 4 NMOS tubes are connected to ResRefN. <2> Control signal;

[0092] The fourth VrefN subcircuit includes 8 NMOS tubes and 8 resistors; the sources of the 8 NMOS tubes are all connected to the power supply VEE, the drains of the 8 NMOS tubes are each connected to one end of a resistor, and the gates of the 8 NMOS tubes are all connected to ResRefN. <3> Control signal;

[0093] The other ends of all the resistors of the four VrefN sub-circuits are connected to each other as the output of the VrefN generating circuit.

[0094] like Figure 6 As shown, R CPN The generating circuit includes four R CPN Subcircuit, specifically:

[0095] First R CPNThe subcircuit includes three NMOS tubes, one PMOS tube and two resistors; the sources of the three NMOS tubes are all connected to the power supply VEE, the gate of one NMOS tube is connected to the drain of the NMOS tube and the gate of the PMOS tube, and the source of the PMOS tube is connected to the power supply VDD; the gate of another NMOS tube is connected to the drain of the PMOS tube, and the drain of the NMOS tube is connected to one end of the two resistors; the drain of the last NMOS tube is connected to one end of the other two resistors, and the gate of the NMOS tube is connected to ResN. <0> Control signal;

[0096] Second R CPN The subcircuit includes two NMOS tubes and four resistors; the sources of the two NMOS tubes are connected to the power supply VEE, the drains of the two NMOS tubes are connected to one end of the two resistors, and the gates of the two NMOS tubes are connected to ResN. <1> Control signal;

[0097] The third R CPN The subcircuit includes 4 NMOS tubes and 8 resistors; the sources of the 4 NMOS tubes are connected to the power supply VEE, the drains of the 4 NMOS tubes are connected to one end of the two resistors, and the gates of the 4 NMOS tubes are connected to ResN. <2> Control signal;

[0098] The Fourth R CPN The subcircuit includes 8 NMOS tubes and 16 resistors; the sources of the 8 NMOS tubes are connected to the power supply VEE, the drains of the 8 NMOS tubes are connected to one end of the two resistors, and the gates of the 8 NMOS tubes are connected to ResN. <3> Control signal;

[0099] The Four Rs CPN The other ends of all resistors in the subcircuit are connected to each other as R CPN Generates the output of the circuit.

[0100] After VrefN is generated, it needs to be output to the discharge branch of the charge pump through the error amplifier. The purpose is to adjust the output of NMOS through the operational amplifier to stabilize the voltage. For example, when the voltage of the discharge branch decreases, it is fed back to inn, causing the amplifier output voltage to increase, and the gate voltage of NMOS to increase, |V GS | increases, so the current increases, the resistance voltage increases, and finally the discharge branch voltage increases, forming a negative feedback. The feedback coefficient β=1,

[0101] The second error amplifier is Figure 7As shown, the first stage is OTA, pmos differential pair input, nmos current mirror as load, forming an active current mirror, the second stage common source, Miller capacitor for frequency compensation, zeroing resistor to eliminate RHP zero, the amplifier as a whole through the self-cascode PMOS current mirror copy current for bias, PD signal controls whether the amplifier is working, when PD is high, PD2 is low, the circuit works.

[0102] Switching tube module and output load module:

[0103] The switch tube module and the output load module are used to convert the phase difference signal detected by the PFD into a current signal to control the charging and discharging of the loop filter. The switch tube module includes a buffer, a PMOS tube M2, a PMOS tube M3, an NMOS tube M4 and an NMOS tube M5 (M3 and M5 are connected to a low level during charging, M2 and M4 are connected to a high level, and M3 and M5 are connected to a high level during discharging, and M2 and M4 are connected to a low level); the source electrodes of the PMOS tubes M2 and M3 are both connected to the output end of the charging current generating module, the drain electrode of the PMOS tube M2 is connected to the drain electrode of the NMOS tube M4, the negative input end of the buffer, the output end of the buffer and the dummy module; the drain electrode of the PMOS tube M3 is connected to the drain electrode of the NMOS tube M5, the positive input end of the buffer, the output load module and the offset DAC module; the source electrodes of the NMOS tubes M4 and M5 are both connected to the output end of the discharge current generating module.

[0104] The output load module and the dummy module are both composed of four capacitors connected in parallel. The dummy module is used to suppress the non-ideal effect of charge sharing and improve the switching speed of the charge pump.

[0105] like Figure 8 As shown in the figure, another switch controlled by the opposite signal is added at the output position of the original drain switch charge pump, and the outputs on both sides are connected to the same load capacitor. CpOut, as the output of the charge pump, converts the phase difference signal detected by the PFD into a current signal, thereby controlling the charging and discharging of the loop filter. CpDummy, as a dummy unit, is combined with a buffer circuit to suppress the non-ideal effect of charge sharing and improve the switching speed of the charge pump.

[0106] The purpose of introducing a buffer between the two outputs is to keep the voltage of the two outputs the same, avoid charge sharing of the charge pump, and improve the working speed. The circuit structure of the buffer is as follows Fig. 9As shown, the whole can be divided into the first-stage OTA, which uses PMOS differential pair input and NMOS current mirror as load to form an active current mirror; the second-stage source follower, as a voltage buffer, is convenient for driving resistive loads, and the output is connected back to the first-stage input; the compensation capacitor performs frequency compensation to make the operational amplifier stable; the self-cascode PMOS current mirror copy current is used for biasing; the PD signal controls whether the buffer works, and when PDB is high and PDB2 is low, the circuit works.

[0107] Offset DAC module:

[0108] The offset DAC module is used to improve the integrated noise and improve the linearity of the circuit. The module includes the offset DAC module and four offset sub-circuits. Specifically:

[0109] like Fig.10 As shown, the first offset subcircuit includes an NMOS tube and a resistor, the source of the NMOS tube is connected to the power supply VEE, the drain of the NMOS tube is connected to one end of the resistor, and the other end of the resistor is connected to the output end of the offset DAC module; the gate of the NMOS tube is connected to ResDacN <0> Control signal;

[0110] The second offset subcircuit includes two NMOS tubes and two resistors. The sources of the two NMOS tubes are connected to the power supply VEE, the drains of the two NMOS tubes are connected to one end of a resistor, and the other ends of the two resistors are connected to the output end of the offset DAC module; the gates of the two NMOS tubes are connected to ResDacN <1> Control signal;

[0111] The third offset subcircuit includes 4 NMOS tubes and 4 resistors. The sources of the 4 NMOS tubes are connected to the power supply VEE, the drains of the 4 NMOS tubes are connected to one end of a resistor, and the other ends of the 4 resistors are connected to the output end of the offset DAC module; the gates of the 4 NMOS tubes are connected to ResDacN <2> Control signal;

[0112] The third offset subcircuit includes 4 NMOS tubes and 4 resistors. The sources of the 4 NMOS tubes are connected to the power supply VEE, the drains of the 4 NMOS tubes are connected to one end of a resistor, and the other ends of the 4 resistors are connected to the output end of the offset DAC module; the gates of the 4 NMOS tubes are connected to ResDacN <2> Control signal;

[0113] The fourth offset subcircuit includes 8 NMOS tubes and 8 resistors. The sources of the 8 NMOS tubes are connected to the power supply VEE, the drains of the 8 NMOS tubes are connected to one end of a resistor, the other ends of the 8 resistors are connected to the output end of the offset DAC module, and the gates of the 8 NMOS tubes are connected to ResDacN. <3> Control signal.

[0114] In actual circuits, due to the existence of nonlinearity, the signal will undergo spectrum changes in the frequency domain, and may interact with the energy of other frequencies. After passing through the nonlinear system, the high-frequency noise energy of the DSM noise will be mixed to the low frequency, causing the DSM noise to reappear in the band and cannot be low-pass filtered by the phase-locked loop. The DSM itself is composed of pure digital circuits and is therefore ideally linear. The nonlinearity comes entirely from the analog modules of the phase-locked loop, among which the divider and the phase detector charge pump are particularly important. The linearity of the charge pump can be improved by changing the working conditions of the charge pump. When the phase-locked loop enters the locked steady state, if the input of the frequency detector and phase detector produces a static phase difference, the phase difference signal at the input of the phase-locked loop will only be on one side of the zero point, and the charge pump will only work on the positive phase or negative phase side, avoiding the zero point, and the linearity of the charge pump will be greatly improved. A static bias current is added to the output of the charge pump to introduce a static phase difference, and the static phase difference can be changed by adjusting the magnitude of the bias current. An offset DAC circuit is used to introduce a static bias current. By changing cpResDacN<3:0>, the on and off of the nmos switch can be changed, thereby changing the total resistance of the parallel connected circuit; if the control bit changes from 0000 to 1111, the number of parallel resistors will increase step by step, and the total resistance will decrease.

[0115] The present invention is simulated and verified:

[0116] The charging branch of CP is simulated and verified. VrefP is as follows: Fig.11 As shown, RCPP Fig.12 As shown;

[0117] The relationship between the charging current and the reference voltage is verified by simulating the charging process. The simulation results show that the charging branch can work stably according to the design requirements and can still maintain high accuracy and reliability under different input conditions.

[0118] The discharge branch of CP is simulated and verified. VrefN is as follows: Fig.13 As shown in Fig.14 As shown;

[0119] Through the simulation of the discharge process, we can see the response time and current change of the discharge branch. The simulation results show that the discharge branch can also effectively adjust the discharge current under given input voltage conditions to meet the design requirements of the circuit.

[0120] The offset DAC function verification results are as follows: Fig.15 As shown in the figure; by simulating the impact of the offset voltage on the DAC, we can confirm that the offset function of the circuit can be effectively adjusted within the predetermined range and the impact on the overall system performance is within an acceptable range.

[0121] The current mismatch of the pre-CP simulation is as follows: Fig.16 As shown (the left figure is CPResN: 0000; ResRefN: 0100~1111; the right figure is CPResN: 1111; ResRefN: 0100~1111), the mismatch size is as follows Fig.17 As shown, the mismatch size of the charge pump static current in the previous simulation case is: 0.35% ~ 0.96%, the mismatch ratio is mainly related to the matching output voltage range, the wider the range, the smaller the mismatch; the charge pump matching output voltage range is related to the size of the programming voltage, the programming bit is from 0000 → 1111, the smaller the programming voltage VrefN, the larger the VrefP, so the charge pump matching output voltage range is also larger.

[0122] The charge pump charging characteristics are as follows: Fig.18 As shown, the discharge characteristics are Fig.19 As shown; the simulation results show that the current response of the charging branch under different load conditions is stable, the charging characteristics are in line with the expected working curve, and the phase difference signal detected by the PFD can be effectively converted into a current signal, thereby controlling the charging and discharging of the loop filter.

[0123] The noise phase simulation results are as follows: Fig. 20 As shown; through the simulation analysis of noise, it is found that the charge pump system can effectively suppress the influence of noise, and the change of noise phase is within a controllable range, ensuring the overall performance and signal quality of the system.

[0124] The above simulation results show that the above simulation results verify the various design functions of the charge pump circuit in the present invention, including charging, discharging, offset DAC, static current mismatch and other characteristics. In the simulation verification of the charging branch and the discharging branch, good performance was shown, and the mismatch phenomenon was effectively controlled within the expected range. The simulation results of the noise phase also show that the system has good noise resistance. Overall, the charge pump design of the present invention meets the expected functional requirements, has good stability and reliability, and is suitable for scenarios with high requirements for current accuracy and stability in practical applications.

[0125] The above embodiments further illustrate the purpose, technical solutions and advantages of the present invention in detail. It should be understood that the above embodiments are only preferred implementation modes of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made to the present invention within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A programmable charge pump circuit based on CMOS technology, characterized in that: include: A charging current generating module, a discharging current generating module, a switch tube module, an output load module, a dummy module and an offset DAC module; wherein: The charging current generating module is used to provide charging current for the charge pump; The discharge current generating module is used to provide a discharge current for the charge pump; The switch tube module and the output load module are used to convert the phase difference signal detected by the PFD into a current signal to control the charging and discharging of the loop filter; The dummy module is used to suppress the non-ideal effect of charge sharing and improve the switching speed of the charge pump; The offset DAC module is used to improve the integrated noise and improve the linearity of the circuit.

2. A programmable charge pump circuit based on CMOS technology according to claim 1, characterized in that: The charging current generating module includes a VrefP generating circuit, a first operational amplifier, an R CPP The output end of the VrefP generating circuit is connected to the positive input end of the first operational amplifier, and the negative input end of the first operational amplifier and the source of the PMOS tube M1 are connected to R CPP The output end of the generating circuit and the output end of the first operational amplifier are connected to the gate of the PMOS tube M1, and the drain of the PMOS tube M1 is connected to the switch tube module.

3. A programmable charge pump circuit based on CMOS technology according to claim 2, characterized in that: The VrefP generating circuit includes four VrefP sub-circuits; The first VrefP subcircuit includes a PMOS tube and a resistor; the source of the PMOS tube is connected to the power supply VDD, the drain of the PMOS tube is connected to one end of the resistor; the gate of the PMOS tube is connected to ResRefP <0> Control signal; The second VrefP subcircuit includes two PMOS tubes and two resistors; the sources of the two PMOS tubes are connected to the power supply VDD, the drains of the two PMOS tubes are connected to one end of a resistor, and the gates of the two PMOS tubes are connected to ResRefP <1> Control signal; The third VrefP subcircuit includes 4 PMOS tubes and 4 resistors; the sources of the 4 PMOS tubes are all connected to the power supply VDD, the drains of the 4 PMOS tubes are each connected to one end of a resistor, and the gates of the 4 PMOS tubes are all connected to ResRefP <2> Control signal; The fourth VrefP subcircuit includes 8 PMOS tubes and 8 resistors; the sources of the 8 PMOS tubes are all connected to the power supply VDD, the drains of the 8 PMOS tubes are each connected to one end of a resistor, and the gates of the 8 PMOS tubes are all connected to ResRefP <3> Control signal; The other ends of all the resistors of the four VrefP sub-circuits are connected to each other as the output of the VrefP generating circuit.

4. A programmable charge pump circuit based on CMOS technology according to claim 2, characterized in that: R CPP The generating circuit includes four R CPP Subcircuit; First R CPP The subcircuit includes three PMOS tubes, one NMOS tube and four resistors; the sources of the three PMOS tubes are all connected to the power supply VDD, the gate of one PMOS tube is connected to the drain of the PMOS tube and the gate of the NMOS tube, and the source of the NMOS tube is connected to the power supply VEE; the gate of another PMOS tube is connected to the drain of the NMOS tube, and the drain of the PMOS tube is connected to one end of two resistors; the drain of the last PMOS tube is connected to one end of the other two resistors, and the gate of the PMOS tube is connected to ResP <0> Control signal; Second R CPP The subcircuit includes two PMOS tubes and four resistors; the sources of the two PMOS tubes are connected to the power supply VDD, the drains of the two PMOS tubes are connected to one end of the two resistors, and the gates of the two PMOS tubes are connected to ResP <1> Control signal; The third R CPP The subcircuit includes 4 PMOS tubes and 8 resistors; the sources of the 4 PMOS tubes are connected to the power supply VDD, the drains of the 4 PMOS tubes are connected to one end of the two resistors, and the gates of the 4 PMOS tubes are connected to ResP <2> Control signal; The Fourth R CPP The subcircuit includes 8 PMOS tubes and 16 resistors; the sources of the 8 PMOS tubes are connected to the power supply VDD, the drains of the 8 PMOS tubes are connected to one end of the two resistors, and the gates of the 8 PMOS tubes are connected to ResP <3> Control signal; The Four Rs CPP The other ends of all resistors in the subcircuit are connected to each other as R CPP Generates the output of the circuit.

5. The programmable charge pump circuit based on CMOS technology according to claim 1, characterized in that: The discharge current generating module includes a VrefN generating circuit, an operational amplifier, an R CPN The output end of the VrefN generating circuit is connected to the positive input end of the second operational amplifier, and the negative input end of the second operational amplifier and the source of the PMOS tube M6 are connected to R CPN The output end of the generating circuit and the output end of the second operational amplifier are connected to the gate of the PMOS tube M6, and the drain of the PMOS tube M6 is connected to the switch tube module.

6. A programmable charge pump circuit based on CMOS technology according to claim 5, characterized in that: The VrefN generating circuit includes four VrefN sub-circuits; The first VrefN subcircuit includes an NMOS tube and a resistor; the source of the NMOS tube is connected to the power supply VEE, the drain of the NMOS tube is connected to one end of the resistor; the gate of the NMOS tube is connected to ResRefN <0> Control signal; The second VrefN subcircuit includes two NMOS tubes and two resistors; the sources of the two NMOS tubes are connected to the power supply VEE, the drains of the two NMOS tubes are connected to one end of a resistor, and the gates of the two NMOS tubes are connected to ResRefN. <1> Control signal; The third VrefN subcircuit includes 4 NMOS tubes and 4 resistors; the sources of the 4 NMOS tubes are connected to the power supply VEE, the drains of the 4 NMOS tubes are connected to one end of a resistor, and the gates of the 4 NMOS tubes are connected to ResRefN. <2> Control signal; The fourth VrefN subcircuit includes 8 NMOS tubes and 8 resistors; the sources of the 8 NMOS tubes are all connected to the power supply VEE, the drains of the 8 NMOS tubes are each connected to one end of a resistor, and the gates of the 8 NMOS tubes are all connected to ResRefN. <3> Control signal; The other ends of all the resistors of the four VrefN sub-circuits are connected to each other as the output of the VrefN generating circuit.

7. The programmable charge pump circuit based on CMOS technology according to claim 5, characterized in that: R CPN The generating circuit includes four R CPN Subcircuit; First R CPN The subcircuit includes three NMOS tubes, one PMOS tube and four resistors; the sources of the three NMOS tubes are all connected to the power supply VEE, the gate of one NMOS tube is connected to the drain of the NMOS tube and the gate of the PMOS tube, and the source of the PMOS tube is connected to the power supply VDD; the gate of another NMOS tube is connected to the drain of the PMOS tube, and the drain of the NMOS tube is connected to one end of two resistors; the drain of the last NMOS tube is connected to one end of the other two resistors, and the gate of the NMOS tube is connected to ResN. <0> Control signal; Second R CPN The subcircuit includes two NMOS tubes and four resistors; the sources of the two NMOS tubes are connected to the power supply VEE, the drains of the two NMOS tubes are connected to one end of the two resistors, and the gates of the two NMOS tubes are connected to ResN. <1> Control signal; The third R CPN The subcircuit includes 4 NMOS tubes and 8 resistors; the sources of the 4 NMOS tubes are connected to the power supply VEE, the drains of the 4 NMOS tubes are connected to one end of the two resistors, and the gates of the 4 NMOS tubes are connected to ResN. <2> Control signal; The Fourth R CPN The subcircuit includes 8 NMOS tubes and 16 resistors; the sources of the 8 NMOS tubes are connected to the power supply VEE, the drains of the 8 NMOS tubes are connected to one end of the two resistors, and the gates of the 8 NMOS tubes are connected to ResN. <3> Control signal; The Four Rs CPN The other ends of all resistors in the subcircuit are connected to each other as R CPN Generates the output of the circuit.

8. The programmable charge pump circuit based on CMOS technology according to claim 1, characterized in that: The switch tube module includes a buffer, a PMOS tube M2, a PMOS tube M3, an NMOS tube M4 and an NMOS tube M5; the sources of the PMOS tube M2 and the PMOS tube M3 are both connected to the output end of the charging current generating module, the drain of the PMOS tube M2 is connected to the drain of the NMOS tube M4, the negative input end of the buffer, the output end of the buffer and the dummy module; the drain of the PMOS tube M3 is connected to the drain of the NMOS tube M5, the positive input end of the buffer, the output load module and the offset DAC module; the sources of the NMOS tube M4 and the NMOS tube M5 are both connected to the output end of the discharge current generating module.

9. The programmable charge pump circuit based on CMOS technology according to claim 1, characterized in that: The offset DAC module includes four offset sub-circuits; The first offset subcircuit includes an NMOS tube and a resistor. The source of the NMOS tube is connected to the power supply VEE, the drain of the NMOS tube is connected to one end of the resistor, and the other end of the resistor is connected to the output end of the offset DAC module; the gate of the NMOS tube is connected to ResDacN <0> Control signal; The second offset subcircuit includes two NMOS tubes and two resistors. The sources of the two NMOS tubes are connected to the power supply VEE, the drains of the two NMOS tubes are connected to one end of a resistor, and the other ends of the two resistors are connected to the output end of the offset DAC module; the gates of the two NMOS tubes are connected to ResDacN <1> Control signal; The third offset subcircuit includes 4 NMOS tubes and 4 resistors. The sources of the 4 NMOS tubes are connected to the power supply VEE, the drains of the 4 NMOS tubes are connected to one end of a resistor, and the other ends of the 4 resistors are connected to the output end of the offset DAC module; the gates of the 4 NMOS tubes are connected to ResDacN <2> Control signal; The third offset subcircuit includes 4 NMOS tubes and 4 resistors. The sources of the 4 NMOS tubes are connected to the power supply VEE, the drains of the 4 NMOS tubes are connected to one end of a resistor, and the other ends of the 4 resistors are connected to the output end of the offset DAC module; the gates of the 4 NMOS tubes are connected to ResDacN <2> Control signal; The fourth offset subcircuit includes 8 NMOS tubes and 8 resistors. The sources of the 8 NMOS tubes are connected to the power supply VEE, the drains of the 8 NMOS tubes are connected to one end of a resistor, the other ends of the 8 resistors are connected to the output end of the offset DAC module, and the gates of the 8 NMOS tubes are connected to ResDacN. <3> Control signal.

10. The programmable charge pump circuit based on CMOS technology according to claim 1, characterized in that: The output load module and the dummy module are both composed of four capacitors connected in parallel.

Images