Synchronous rectification circuit, circuit board and electronic equipment

Abstract

The invention relates to the field of electronic circuits, and discloses a synchronous rectification circuit, a circuit board and electronic equipment. The synchronous rectification circuit comprises a resonance circuit, a first bridge arm rectification circuit and a second bridge arm rectification circuit, the resonance circuit can provide a first secondary winding voltage and a second secondary winding voltage, the first bridge arm rectification circuit comprises a first rectification switch circuit and a first bridge arm driving circuit, and the first bridge arm driving circuit can respond to the two secondary winding voltages. The first bridge arm rectifying circuit comprises a first rectifying switching circuit and a first bridge arm driving circuit, the first rectifying switching circuit is driven to be in a first working state, the second bridge arm rectifying circuit comprises a second rectifying switching circuit and a second bridge arm driving circuit, the second bridge arm driving circuit can respond to two secondary winding voltages and drive the second rectifying switching circuit to be in a second working state, and the second working state and the first working state are mutually exclusive; therefore, the short circuit between the first rectification switch circuit and the second rectification switch circuit is prevented. Therefore, the rectifier switches of the two bridge arms can be prevented from being damaged due to short circuit, so that the circuit reliability is improved.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and in particular to a synchronous rectification circuit, a circuit board and an electronic device. Background Art

[0002] At present, in LLC topology applications, in order to improve efficiency, the secondary rectification part of the LLC topology usually uses MOS tube rectification instead of diode rectification. However, in the MOS tube rectification scheme, when the traditional driving method is used to drive the MOS tubes of different bridge arms, the driving waveforms of the two bridge arms usually cross, causing the MOS tubes of the two bridge arms to be turned on at the same time and short-circuited, which easily leads to damage to the MOS tubes of the two bridge arms. Summary of the invention

[0003] An object of the embodiments of the present invention is to provide a synchronous rectification circuit, a circuit board and an electronic device, which can solve the defects existing in the prior art.

[0004] In a first aspect, an embodiment of the present invention provides a synchronous rectification circuit, comprising:

[0005] A resonant circuit, used for providing a first secondary winding voltage and a second secondary winding voltage;

[0006] A first bridge arm rectifier circuit, comprising a first rectifier switch circuit and a first bridge arm drive circuit, wherein the first rectifier switch circuit is electrically connected to the resonant circuit and the first bridge arm drive circuit respectively, and the first bridge arm drive circuit is also electrically connected to the resonant circuit, and is used to respond to the first secondary winding voltage and the second secondary winding voltage to drive the first rectifier switch circuit to be in a first working state;

[0007] The second bridge arm rectifier circuit includes a second rectifier switch circuit and a second bridge arm drive circuit, wherein the first rectifier switch circuit is electrically connected to the resonant circuit and the second bridge arm drive circuit respectively, and the second bridge arm drive circuit is also electrically connected to the resonant circuit, and is used to respond to the first secondary winding voltage and the second secondary winding voltage to drive the second rectifier switch circuit to be in a second working state, wherein the second working state is mutually exclusive with the first working state to prevent the first rectifier switch circuit, the second rectifier switch circuit and the resonant circuit from forming a short circuit.

[0008] Optionally, when the first working state is a working state in which the first rectifier switch circuit is in a closed state, the second working state is a working state in which the second rectifier switch circuit is in an open state;

[0009] When the first working state is a working state in which the first rectifier switch circuit is in an open state, the second working state is a working state in which the second rectifier switch circuit is in a closed state.

[0010] Optionally, when the first secondary winding voltage is a first level type signal, the second secondary winding voltage is a second level type signal, and the first level type signal and the second level type signal are signals of different level types;

[0011] When the first secondary winding voltage is a second level type signal, the second secondary winding voltage is a first level type signal.

[0012] Optionally, the first bridge arm driving circuit includes:

[0013] a first driving circuit, electrically connected to the resonant circuit and the first rectifying switch circuit, respectively, the first driving circuit comprising a first node, for generating a first node voltage at the first node in response to the second secondary winding voltage, and driving the first rectifying switch circuit to be in a first working state according to the first node voltage;

[0014] A first interlock circuit is electrically connected to the resonant circuit and to the first drive circuit at the first node, and is used to control the first node voltage in response to the first secondary winding voltage.

[0015] Optionally, the first interlock circuit includes:

[0016] a first clamping circuit electrically connected to the resonant circuit, the first clamping circuit comprising a second node for clamping the first secondary winding voltage and controlling the second node to generate a clamped voltage;

[0017] The first switch control circuit is electrically connected to the first clamp circuit at the second node and to the first drive circuit at the first node, and is used to control the voltage of the first node in response to the voltage of the second node.

[0018] Optionally, the first driving circuit includes:

[0019] a first voltage conditioning circuit, electrically connected to the resonant circuit, the first voltage conditioning circuit comprising a third node, for conditioning the second secondary winding voltage and controlling the third node to generate a conditioned voltage;

[0020] A first push-pull driving circuit is electrically connected to the first voltage conditioning circuit at the third node and to the first interlocking circuit at the first node, and is used to generate a first node voltage at the first node according to the voltage of the third node;

[0021] The first push-pull circuit is electrically connected to the first rectifier switch circuit and is respectively electrically connected to the first push-pull drive circuit and the first interlock circuit at the first node, and is used for responding to the first node voltage to drive the first rectifier switch circuit to be in a first working state.

[0022] Optionally, the second bridge arm driving circuit includes:

[0023] a second driving circuit, electrically connected to the resonant circuit and the second rectifying switch circuit, respectively, the second driving circuit comprising a fourth node, for generating a fourth node voltage at the fourth node in response to the first secondary winding voltage, and driving the second rectifying switch circuit to be in a second working state according to the voltage of the fourth node;

[0024] The second interlock circuit is electrically connected to the resonant circuit and to the second drive circuit at the fourth node, and is used to control the fourth node voltage in response to the second secondary winding voltage.

[0025] Optionally, the second interlock circuit comprises:

[0026] a second clamping circuit electrically connected to the resonant circuit, the second clamping circuit comprising a fifth node for clamping the second secondary winding voltage and controlling the fifth node to generate a clamped voltage;

[0027] The second switch control circuit is electrically connected to the second clamping circuit at the fifth node and to the second driving circuit at the fourth node, and is used for controlling the voltage of the fourth node in response to the voltage of the fifth node.

[0028] Optionally, the second driving circuit includes:

[0029] a second voltage conditioning circuit, electrically connected to the resonant circuit, the second voltage conditioning circuit comprising a sixth node, for conditioning the first secondary winding voltage and controlling the sixth node to generate a conditioned voltage;

[0030] A second push-pull driving circuit is electrically connected to the second voltage conditioning circuit at the sixth node and to the second interlocking circuit at the fourth node, and is used to generate a fourth node voltage at the fourth node according to the voltage of the sixth node;

[0031] The second push-pull circuit is electrically connected to the second rectifier switch circuit, and is electrically connected to the second push-pull drive circuit and the second interlock circuit at the fourth node, respectively, and is used to respond to the fourth node voltage to drive the second rectifier switch circuit to a second working state.

[0032] Optionally, a power supply circuit is also included;

[0033] The power supply circuit is electrically connected to the resonant circuit, the first bridge arm drive circuit and the second bridge arm drive circuit respectively, and is used to generate a power supply voltage according to the first secondary winding voltage, and the power supply voltage is used to power the first bridge arm drive circuit and the second bridge arm drive circuit.

[0034] In a second aspect, an embodiment of the present invention provides a circuit board, comprising the synchronous rectification circuit as described above.

[0035] In a third aspect, an embodiment of the present invention provides an electronic device, comprising the circuit board as described above.

[0036] In the synchronous rectification circuit provided in the embodiment of the present invention, a resonance circuit, a first bridge arm rectification circuit and a second bridge arm rectification circuit are included, the resonance circuit is used to provide a first secondary winding voltage and a second secondary winding voltage, the first bridge arm rectification circuit includes a first rectification switch circuit and a first bridge arm driving circuit, the first bridge arm driving circuit is electrically connected to the first rectification switch circuit, and is used to respond to the first secondary winding voltage and the second secondary winding voltage, and drive the first rectification switch circuit to be in a first working state, the second bridge arm rectification circuit includes a second rectification switch circuit and a second bridge arm driving circuit, the second bridge arm driving circuit is electrically connected to the second rectification switch circuit, and is used to respond to the first secondary winding voltage and the second secondary winding voltage, and drive the second rectification switch circuit to be in a second working state, the second working state is mutually exclusive with the first working state, so as to prevent the first rectification switch circuit and the second rectification switch circuit from forming a short circuit. Therefore, this embodiment can ensure that the first rectification switch circuit and the second rectification switch circuit will not be closed at the same time to form a short circuit, thereby avoiding the first rectification switch circuit and the second rectification switch circuit from being damaged due to a short circuit, thereby improving the circuit reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] One or more embodiments are illustrated only as examples in the corresponding drawings, and these examples do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and unless otherwise stated, the figures in the drawings do not constitute proportional limitations.

[0038] Figure 1 is a structural schematic diagram of a synchronous rectification circuit provided by an embodiment of the present invention;

[0039] Figure 2 is a structural schematic diagram of a synchronous rectification circuit provided by another embodiment of the present invention;

[0040] Figure 3 is a structural schematic diagram of a synchronous rectification circuit provided by another embodiment of the present invention;

[0041] Figure 4 is a structural schematic diagram of a synchronous rectification circuit provided by another embodiment of the present invention;

[0042] Figure 5 is a structural schematic diagram of a synchronous rectification circuit provided by another embodiment of the present invention;

[0043] Figure 6 is a structural schematic diagram of a synchronous rectification circuit provided by another embodiment of the present invention;

[0044] Figure 7 1 is a schematic diagram of a circuit structure of a synchronous rectification circuit provided by an embodiment of the present invention;

[0045] Figure 8 Schematic diagram of the working principle of a synchronous rectification circuit provided by an embodiment of the present invention;

[0046] Fig. 9 This is a schematic diagram of the working principle of a synchronous rectification circuit provided by another embodiment of the present invention. DETAILED DESCRIPTION

[0047] In order to facilitate the understanding of the present application, the present application is described in more detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that when an element is described as "connected" to another element, it can be directly connected to the other element, or there can be one or more intermediate elements therebetween. In addition, the terms "first", "second", etc. are used only for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0048] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art of the present invention. The terms used in this specification and in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.

[0049] Please also read Figure 1 and Figure 2 , an embodiment of the present invention provides a synchronous rectification circuit. Figure 1 As shown, the synchronous rectification circuit 100 includes a resonant circuit 11 , a first bridge arm rectification circuit 12 and a second bridge arm rectification circuit 13 .

[0050] like Figure 2 As shown, the resonant circuit 11 includes a transformer 111 , a primary drive circuit 112 and a resonant adjustment circuit 113 .

[0051] The transformer 111 includes a primary winding and a secondary winding. The primary winding includes one or more windings, and the secondary winding includes one or more windings. For example, the primary winding is one winding and the secondary winding is two windings. For another example, the primary winding is two windings and the secondary winding is one winding.

[0052] In some embodiments, see Figure 3 The transformer 111 includes a primary winding Np1, a first secondary winding Ns1 and a second secondary winding Ns2.

[0053] The primary winding Np1 is electrically connected to the primary driving circuit 112 , the first secondary winding Ns1 is electrically connected to the first bridge arm rectifying circuit 12 and the second bridge arm rectifying circuit 13 , and the second secondary winding Ns2 is electrically connected to the first bridge arm rectifying circuit 12 and the second bridge arm rectifying circuit 13 .

[0054] The primary driving circuit 112 is used for driving the primary winding Np1 , the first secondary winding Ns1 , and the second secondary winding Ns2 to couple energy in response to an input control signal, thereby generating alternating current in the first secondary winding Ns1 and the second secondary winding Ns2 .

[0055] In some embodiments, Figure 3 As shown, the primary driving circuit 112 includes a first bridge arm switch circuit 1121 and a second bridge arm switch circuit 1122 .

[0056] The first bridge arm switch circuit 1121 is used to be applied with a DC input voltage and is electrically connected to the second bridge arm switch circuit 1122. The connection point between the first bridge arm switch circuit 1121 and the second bridge arm switch circuit 1122 is the center point 112A. The first bridge arm switch circuit 1121 and the second bridge arm switch circuit 1122 are electrically connected to the primary winding Np1 at the center point 112A.

[0057] See also Figure 7 The first bridge arm switch circuit 1121 includes a first MOS transistor M1, a first resistor R1, a second resistor R2, a third resistor R3, a first diode D1 and a first capacitor C1.

[0058] One end of the first resistor R1 is electrically connected to the cathode of the first diode D1 and is used for applying the first control signal. The other end of the first resistor R1 is electrically connected to the gate of the first MOS transistor M1, one end of the second resistor R2 and one end of the third resistor R3 respectively. The other end of the second resistor R2 is electrically connected to the anode of the first diode D1. The drain of the first MOS transistor M1 is electrically connected to one end of the first capacitor C1 and is used for applying the DC input voltage VIN. The source of the first MOS transistor M1, the other end of the third resistor R3 and the other end of the first capacitor C1 are commonly connected to the primary winding Np1 at the center point 112A.

[0059] The first control signal includes a first level type signal and a second level type signal, the first level type signal and the second level type signal are signals of different level types, for example, the first level type signal is a high level signal, the second level type signal is a low level signal, or the first level type signal is a low level signal, the second level type signal is a high level signal. In some embodiments, the first control signal is a PWM (Pulse Width Modulation) signal, which is a signal that modulates the bias of the transistor base or the MOS tube gate according to the change of the corresponding load to achieve a change in the conduction time of the transistor or the MOS tube, thereby changing the output of the switching power supply.

[0060] like Figure 7 As shown, when the first control signal PWM1 is a high-level signal, the high-level signal is applied to the gate of the first MOS tube M1 through the first resistor R1, and the first MOS tube M1 is in an on state. When the first control signal PWM1 is a low-level signal, the low-level signal is applied to the gate of the first MOS tube M1 through the first resistor R1, and the first MOS tube M1 is in an off state.

[0061] The first resistor R1 is a driving resistor, and is used to reliably drive the first MOS transistor M1.

[0062] The first diode D1 and the second resistor R2 can form a discharge circuit. When the first control signal PWM1 is a low level signal, the discharge circuit can quickly discharge the charge stored in the parasitic capacitor of the first MOS tube M1, thereby accelerating the turn-off speed of the first MOS tube M1.

[0063] The third resistor R3 is a pull-down resistor. On the one hand, the pull-down resistor can provide a discharge path for the charge stored in the parasitic capacitor of the first MOS tube M1, which can accelerate the turn-off speed of the first MOS tube M1 to a certain extent. On the other hand, it can discharge the electrostatic charge stored in the parasitic capacitor of the first MOS tube M1, which can prevent the first MOS tube M1 from being broken down by static electricity.

[0064] The first capacitor C1 is used to adjust the output capacitance Coss of the first MOS tube M1 to reduce switching loss and thus improve efficiency.

[0065] like Figure 7 As shown, the second bridge arm switch circuit 1122 includes a second MOS transistor M2, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a second diode D2 and a second capacitor C2.

[0066] One end of the fourth resistor R4 is electrically connected to the cathode of the second diode D2 and is used to be applied with the second control signal. The other end of the fourth resistor R4 is respectively electrically connected to the gate of the second MOS transistor M2, one end of the fifth resistor R5 and one end of the sixth resistor R6. The other end of the fifth resistor R5 is electrically connected to the anode of the second diode D2. The drain of the second MOS transistor M2 is respectively electrically connected to one end of the second capacitor C2 and the same-name end of the primary winding Np1 at the center point 112A. The source of the second MOS transistor M2, the other end of the sixth resistor R6 and the other end of the second capacitor C2 are grounded.

[0067] The functions of the fourth resistor R4, the fifth resistor R5, the sixth resistor R6, the second diode D2 and the second capacitor C2 may refer to the above embodiments, which will not be described in detail herein.

[0068] The second control signal includes a first level type signal and a second level type signal. As described above, when the first level type signal is a high level signal, the second level type signal can be a low level signal, and when the first level type signal is a low level signal, the second level type signal can be a high level signal. In some embodiments, the second control signal is a PWM signal.

[0069] like Figure 7 As shown, when the second control signal PWM2 is a high-level signal, the high-level signal is applied to the gate of the second MOS tube M2 through the fourth resistor R4, and the second MOS tube M2 is in an on state. When the second control signal PWM2 is a low-level signal, the low-level signal is applied to the gate of the second MOS tube M2 through the fourth resistor R4, and the second MOS tube M2 is in an off state.

[0070] In practical applications, it is necessary to control the first MOS tube M1 and the second MOS tube M2 to be alternately turned on through the first control signal PWM1 and the second control signal PWM2. For example, at a certain moment, the first control signal PWM1 is a high-level signal and the second control signal PWM2 is a low-level signal. At this time, the first MOS tube M1 is in a conducting state and the second MOS tube M2 is in a shut-off state. Then, at the next moment, the first control signal PWM1 changes from a high-level signal to a level signal and the second control signal PWM2 changes from a low-level signal to a high-level signal. At this time, the first MOS tube M1 is in a shut-off state and the second MOS tube M2 is in a conducting state.

[0071] The resonance adjustment circuit 113 is electrically connected to the transformer 111 and is used to form a resonance cavity with the transformer 111 to generate a resonance phenomenon, so as to adjust the performance of the resonance circuit 11 .

[0072] In some embodiments, Figure 7 As shown, the resonance adjustment circuit 113 includes a third capacitor C3.

[0073] One end of the third capacitor C3 is electrically connected to the primary winding Np1 , and the other end of the third capacitor C3 is grounded.

[0074] In some embodiments, at the same time, the voltage at the opposite-name end of the first secondary winding Ns1 is different from the voltage at the same-name end of the second secondary winding Ns2 .

[0075] See also Figure 8 When the first MOS tube M1 is in the on state and the second MOS tube M2 is in the off state, the DC input power supply VIN, the first MOS tube M1, the same-name end of the primary winding Np1, the opposite-name end of the primary winding Np1, and the third capacitor C3 form a loop, and the primary winding Np1 stores energy through the loop. At this time, the voltage of the same-name end of the primary winding Np1 is positive, and the voltage of the opposite-name end of the primary winding Np1 is negative. Therefore, after coupling, the voltage induced at the opposite-name end of the first secondary winding Ns1 is positive, and the voltage induced at the same-name end of the second secondary winding Ns2 is negative.

[0076] See also Fig. 9 When the first MOS tube M1 is in the off state and the second MOS tube M2 is in the on state, the opposite-name end of the primary winding Np1, the same-name end of the primary winding Np1, the second MOS tube M2 and the third capacitor C3 form a loop, and the primary winding Np1 releases the stored energy through the loop. At this time, the voltage of the opposite-name end of the primary winding Np1 is positive, and the voltage of the same-name end of the primary winding Np1 is negative. Therefore, after coupling, the voltage induced at the same-name end of the second secondary winding Ns2 is positive, and the voltage induced at the opposite-name end of the first secondary winding Ns1 is negative.

[0077] Therefore, the first secondary winding Ns1 and the second secondary winding Ns2 can generate alternating current after coupling the energy of the primary winding Np1.

[0078] The voltage of the opposite-name end of the first secondary winding Ns1 is used as the first secondary winding voltage, and the voltage of the same-name end of the second secondary winding Ns2 is used as the second secondary winding voltage. The first secondary winding voltage and the second secondary winding voltage are used to provide to the first bridge arm rectifier circuit 12 and the second bridge arm rectifier circuit 13, and the first bridge arm rectifier circuit 12 and the second bridge arm rectifier circuit 13 are used to rectify the alternating current generated by the first secondary winding Ns1 and the second secondary winding Ns2 according to the first secondary winding voltage and the second secondary winding voltage, respectively, to output the required direct current.

[0079] In some embodiments, when the first secondary winding voltage is a first level type signal, the second secondary winding voltage is a second level type signal, and when the first secondary winding voltage is a second level type signal, the second secondary winding voltage is a first level type signal.

[0080] First level type signal The first level type signal and the second level type signal are signals of different level types, for example, the first level type signal is a high level signal and the second level type signal is a low level signal, or the first level type signal is a low level signal and the second level type signal is a high level signal.

[0081] It can be understood that when the voltage at the opposite end of the first secondary winding Ns1 is positive and the voltage at the same end of the second secondary winding Ns2 is negative, the first secondary winding voltage is a high-level signal and the second secondary winding voltage is a low-level signal; when the voltage at the opposite end of the first secondary winding Ns1 is negative and the voltage at the same end of the second secondary winding Ns2 is positive, the first secondary winding voltage is a low-level signal and the second secondary winding voltage is a high-level signal.

[0082] See also Figure 4 The first bridge arm rectifier circuit 12 includes a first rectifier switch circuit 121 and a first bridge arm driving circuit 122 .

[0083] The first rectifying switch circuit 121 is electrically connected to the first secondary winding Ns1 .

[0084] The first bridge arm driving circuit 122 is electrically connected to the first rectifying switch circuit 121 , the first secondary winding Ns1 and the second secondary winding Ns2 , respectively, and can respond to the first secondary winding voltage and the second secondary winding voltage to drive the first rectifying switch circuit 121 to be in the first working state.

[0085] The first working state may be a working state when the first rectifying switch circuit 121 is in a closed state, or may be a working state when the first rectifying switch circuit 121 is in an open state.

[0086] When the first working state is the working state when the first rectifier switch circuit 121 is in a closed state, the current of the first secondary winding Ns1 can flow into the output load through the first rectifier switch circuit 121. When the first working state is the working state when the first rectifier switch circuit 121 is in an open state, the current of the first secondary winding Ns1 stops flowing into the output load.

[0087] like Figure 4 As shown, the second bridge arm rectifier circuit 13 includes a second rectifier switch circuit 131 and a second bridge arm driving circuit 132 .

[0088] The second rectifying switch circuit 131 is electrically connected to the second secondary winding Ns2 .

[0089] The second bridge arm driving circuit 132 is electrically connected to the second rectifying switch circuit 131 , the first secondary winding Ns1 and the second secondary winding Ns2 , respectively, and is used for responding to the first secondary winding voltage and the second secondary winding voltage to drive the second rectifying switch circuit 131 to be in the second working state.

[0090] The second working state may be a working state when the second rectifying switch circuit 131 is in a closed state, or may be a working state when the second rectifying switch circuit 131 is in an open state.

[0091] When the second working state is the working state when the second rectifier switch circuit 131 is in a closed state, the current of the second secondary winding Ns2 can flow into the output load through the second rectifier switch circuit 131. When the second working state is the working state when the second rectifier switch circuit 131 is in an open state, the current of the second secondary winding Ns2 stops flowing into the output load.

[0092] The second working state is mutually exclusive with the first working state. For example, when the first working state is the working state when the first rectifier switch circuit 121 is in a closed state, the second working state is the working state when the second rectifier switch circuit 131 is in an open state. For another example, when the first working state is the working state when the first rectifier switch circuit 121 is in an open state, the second working state is the working state when the second rectifier switch circuit 131 is in an on state.

[0093] Since the second working state is mutually exclusive with the first working state, the first rectifier switch circuit 121 and the second rectifier switch circuit 131 cannot be closed at the same time, thereby preventing the first rectifier switch circuit 121, the second rectifier switch circuit 131, the second secondary winding Ns2 and the first secondary winding Ns1 from forming a short circuit, avoiding the first rectifier switch circuit 121 and the second rectifier switch circuit 131 from being damaged by a large current when a short circuit occurs, thereby improving circuit reliability.

[0094] Please continue reading Figure 8 When the voltage at the same-name end of the primary winding Np1 is positive and the voltage at the opposite-name end of the primary winding Np1 is negative, the voltage of the first secondary winding is a high-level signal and the voltage of the second secondary winding is a low-level signal. At this time, the first bridge arm driving circuit 122 responds to the first secondary winding voltage and the second secondary winding voltage, and drives the first rectifier switch circuit 121 to be in an open state. At the same time, the second bridge arm driving circuit 132 responds to the first secondary winding voltage and the second secondary winding voltage, and drives the second rectifier switch circuit 131 to be in a closed state. Therefore, the opposite-name end of the second secondary winding Ns2, the output load RL, the second rectifier switch circuit 131 and the same-name end of the second secondary winding Ns2 form a loop, and the current passes through the loop to supply power to the output load RL.

[0095] Please continue reading Fig. 9 When the voltage at the opposite-name end of the primary winding Np1 is positive and the voltage at the same-name end of the primary winding Np1 is negative, the voltage of the first secondary winding is a low-level signal and the voltage of the second secondary winding is a high-level signal. At this time, the first bridge arm driving circuit 122 responds to the first secondary winding voltage and the second secondary winding voltage, and drives the first rectifier switch circuit 121 to be in a closed state. At the same time, the second bridge arm driving circuit 132 responds to the first secondary winding voltage and the second secondary winding voltage, and drives the second rectifier switch circuit 131 to be in an open state. Therefore, the same-name end of the first secondary winding Ns1, the output load RL, the first rectifier switch circuit 121 and the opposite-name end of the first secondary winding Ns1 form a loop, and the current passes through the loop to supply power to the output load RL.

[0096] In some embodiments, see Figure 5 The first bridge arm driving circuit 122 includes a first driving circuit 1221 and a first interlocking circuit 1222 .

[0097] The first driving circuit 1221 is electrically connected to the first rectifying switch circuit 121 and the second secondary winding Ns2 respectively. The first driving circuit 1221 includes a first node N1, which can respond to the second secondary winding voltage to generate a first node voltage at the first node N1, and drive the first rectifying switch circuit 121 to be in a first working state according to the first node voltage.

[0098] The first interlock circuit 1222 is electrically connected to the first secondary winding Ns1 and is electrically connected to the first driving circuit 1221 at the first node N1, and can control the first node voltage in response to the first secondary winding voltage.

[0099] For example, when the first secondary winding voltage is a high-level signal and the second secondary winding voltage is a low-level signal, the first interlock circuit 1222 can respond to the high-level signal and force the first node voltage to be lowered, so that the first drive circuit 1221 drives the first rectifier switch circuit 121 to be in an open state according to the first node voltage. When the first secondary winding voltage is a low-level signal and the second secondary winding voltage is a high-level signal, the first drive circuit 1221 can respond to the high-level signal, generate a first node voltage at the first node N1, and drive the first rectifier switch circuit 121 to be in a closed state according to the first node voltage.

[0100] Since the first interlock circuit 1222 is directly electrically connected to the first secondary winding Ns1 to respond to the first secondary winding voltage, it is beneficial to quickly pull down the first node voltage at the moment when the first secondary winding voltage changes from a low-level signal to a high-level signal, thereby reducing the driving delay of the first rectifier switch circuit 121, thereby facilitating the first rectifier switch circuit 121 to quickly enter the disconnected state at the moment when the second rectifier switch circuit 131 is in the closed state.

[0101] In some embodiments, see Figure 6 The first interlock circuit 1222 includes a first clamping circuit 12221 and a first switch control circuit 12222 .

[0102] The first clamping circuit 12221 is electrically connected to the first secondary winding Ns1 . The first clamping circuit 12221 includes a second node N2 , and can clamp the voltage of the first secondary winding and control the second node N2 to generate a clamped voltage.

[0103] In practical applications, since the peak value of the first secondary winding voltage is relatively high, the peak value of the first secondary winding voltage is clamped and limited by the first clamping circuit 12221 to obtain a suitable voltage at the second node N2.

[0104] In some embodiments, please refer to Figure 7 The first clamping circuit 12221 includes a seventh resistor R7 and a first zener diode ZD1.

[0105] One end of the seventh resistor R7 is electrically connected to the first secondary winding Ns1 , the other end of the seventh resistor R7 is electrically connected to the cathode of the first zener diode ZD1 and the first switch control circuit 12222 , respectively, and the anode of the first zener diode ZD1 is grounded.

[0106] When the first secondary winding voltage is higher than the voltage regulation value of the first Zener diode ZD1 , the first Zener diode ZD1 can limit the voltage of the second node N2 to the voltage regulation value of the first Zener diode ZD1 , ensuring that the voltage of the second node N2 is not higher than the voltage regulation value of the first Zener diode ZD1 .

[0107] It can be understood that when the first secondary winding voltage is a high level signal, the voltage of the second node N2 is also a high level signal, and when the first secondary winding voltage is a low level signal, the voltage of the second node N2 is also a low level signal.

[0108] In order to isolate the DC component of the first secondary winding voltage to obtain a more suitable voltage at the second node N2, in some embodiments, the first clamping circuit 12221 also includes a fourth capacitor (not shown), one end of the fourth capacitor is electrically connected to the first secondary winding, and one end of the fourth capacitor is electrically connected to one end of the seventh resistor R7.

[0109] The first switch control circuit 12222 is electrically connected to the first clamp circuit 12221 at the second node N2 and to the first driving circuit 1221 at the first node N1, and can control the voltage of the first node N1 in response to the voltage of the second node N2.

[0110] In some embodiments, Figure 7As shown, the first switch control circuit 12222 includes a third MOS tube M3 and an eighth resistor R8.

[0111] The gate of the third MOS transistor M3 is electrically connected to one end of the eighth resistor R8 and the first clamping circuit 12221 at the second node N2, the drain of the third MOS transistor M3 is electrically connected to the first driving circuit 1221 at the first node N1, and the source of the third MOS transistor M3 and the other end of the eighth resistor R8 are grounded.

[0112] When the voltage of the second node N2 is a high level signal, the third MOS tube M3 responds to the high level signal and is in a conducting state to pull the voltage of the first node N1 to the ground. When the voltage of the second node N2 is a low level signal, the third MOS tube M3 responds to the low level signal and is in a conducting state. At this time, the third MOS tube M3 loses control of the voltage of the first node N1.

[0113] The eighth resistor R8 is a pull-down resistor, which can accelerate the turn-off of the third MOS transistor M3 on the one hand, and prevent the third MOS transistor M3 from being broken down by static electricity stored in the parasitic capacitor on the other hand.

[0114] In some embodiments, please refer to Figure 6 The first driving circuit 1221 includes a first voltage conditioning circuit 12211, a first push-pull driving circuit 12212 and a first push-pull circuit 12213.

[0115] The first voltage conditioning circuit 12211 is electrically connected to the second secondary winding Ns2. The first voltage conditioning circuit 12211 includes a third node N3. The first voltage conditioning circuit 12211 can condition the second secondary winding voltage and control the third node N3 to generate a conditioned voltage.

[0116] In some embodiments, please refer to Figure 7 The first voltage conditioning circuit 12211 includes a fifth capacitor C5, a ninth resistor R9 and a second Zener diode ZD2.

[0117] The fifth capacitor C5 is electrically connected to the second secondary winding Ns2, and the other end of the fifth capacitor C5 is electrically connected to one end of the ninth resistor R9, and the other end of the ninth resistor R9 is electrically connected to the cathode of the second zener diode ZD2 and the first push-pull driving circuit 12212 respectively, and the anode of the second zener diode ZD2 is grounded.

[0118] The fifth capacitor C5 is used to isolate the DC signal of the second secondary winding voltage and allow the AC signal of the second secondary winding voltage to pass through. The ninth resistor R9 and the second zener diode ZD2 can, on the one hand, clamp and limit the peak value of the AC signal passing through the fifth capacitor C5 to ensure that the voltage of the third node N3 is not higher than the stabilization value of the second zener diode ZD2; on the other hand, they can raise the voltage amplitude of the AC signal passing through the fifth capacitor C5, so that the amplitude of the voltage at the third node N3 is close to the amplitude of the second secondary winding voltage, so as to improve the driving capability.

[0119] It can be understood that when the second secondary winding voltage is a high level signal, the voltage of the third node N3 is also a high level signal, and when the second secondary winding voltage is a low level signal, the voltage of the third node N3 is also a low level signal.

[0120] The first push-pull driving circuit 12212 is electrically connected to the first voltage conditioning circuit 12211 at the third node N3 and to the first interlocking circuit 1222 at the first node N1, and can generate a first node voltage at the first node N1 according to the voltage of the third node N3.

[0121] In some embodiments, Figure 7 As shown, the first push-pull driving circuit 12212 includes a tenth resistor R10.

[0122] One end of the tenth resistor R10 is electrically connected to the first voltage conditioning circuit 12211 at the third node N3, and the other end of the tenth resistor R10 is electrically connected to the first push-pull circuit 12213 and the first interlocking circuit 1222 at the first node N1.

[0123] As mentioned above, when the first secondary winding voltage is a high level signal and the second secondary winding voltage is a low level signal, the first interlock circuit 1222 responds to the high level signal and forcibly pulls down the voltage of the first node N1. At this time, the voltage of the first node N1 is a low level signal. When the first secondary winding voltage is a low level signal and the second secondary winding voltage is a high level signal, the first interlock circuit 1222 does not affect the voltage of the first node N1. At this time, the voltage of the third node N3 is a high level signal, and the voltage of the first node N1 is also a high level signal.

[0124] The first push-pull circuit 12213 is electrically connected to the first rectifier switch circuit 121 and is respectively electrically connected to the first push-pull driving circuit 12212 and the first interlocking circuit 1222 at the first node N1, and can respond to the first node voltage to drive the first rectifier switch circuit 121 to be in the first working state.

[0125] In some embodiments, Figure 7As shown, the first push-pull circuit 12213 includes a third diode D3, a first transistor Q1, a second transistor Q2, an eleventh resistor R11, a twelfth resistor R12 and a thirteenth resistor R13.

[0126] The base of the first transistor Q1, the base of the second transistor Q2, the anode of the third diode D3, and one end of the eleventh resistor R11 are electrically connected to the first push-pull drive circuit 12212 and the first interlocking circuit 1222 at the first node N1, respectively. The cathode of the third diode D3 is electrically connected to the first voltage conditioning circuit 12211 at the third node N3. The other end of the eleventh resistor R11 and the collector of the second transistor Q2 are grounded. The collector of the first transistor Q1 is electrically connected to one end of the twelfth resistor R12, and the other end of the twelfth resistor R12 can be applied with a supply voltage. The emitter of the first transistor Q1, the emitter of the second transistor Q2, and one end of the thirteenth resistor R13 are connected together, and the other end of the thirteenth resistor R13 is electrically connected to the first rectifier switch circuit 121.

[0127] As mentioned above, when the voltage of the first node N1 is a high-level signal, the first transistor Q1 is in an on state, the second transistor Q2 is in an off state, and the emitter voltage of the first transistor Q1 is a high-level signal. The high-level signal is applied to the first rectifier switch circuit 121 through the thirteenth resistor R13, so that the first rectifier switch circuit 121 is in a closed state.

[0128] When the voltage of the first node N1 is a low level signal, the first transistor Q1 is in the off state, the second transistor Q2 is in the on state, and the emitter voltage of the second transistor Q2 is a low level signal, so that the first rectifier switch circuit 121 is in the off state.

[0129] The third diode D3 is a feedback diode, and is used for accelerating the first transistor Q1 to enter a cut-off state when the voltage at the first node N1 changes from a high level signal to a low level signal.

[0130] The eleventh resistor R11 is a pull-down resistor, which can ground the base of the first transistor Q1 and the base of the second transistor Q2 reliably when an uncertain level signal appears at the voltage of the first node N1, thereby preventing the first transistor Q1 and the second transistor Q2 from malfunctioning due to the influence of noise signals.

[0131] The twelfth resistor R12 plays a role of pull-up and current limiting. On the one hand, the twelfth resistor R12 can pull the emitter voltage of the first transistor Q1 to a high level when the first transistor Q1 is in the on state. On the other hand, the twelfth resistor R12 can also limit the current flowing through the first transistor Q1 when the first transistor Q1 is in the on state.

[0132] The thirteenth resistor R13 is a driving resistor, and is used to reliably drive the first rectifying switch circuit 121 .

[0133] It is understandable that the number of the driving resistors may be one or more. Figure 8 Only one driving resistor is shown, and the specific number can be set according to the switch tube included in the first rectifier switch circuit 121. For example, when the first rectifier switch circuit 121 includes one switch tube, the number of driving resistors is set to 1, and the driving resistor is used to drive the switch tube. When the first rectifier switch circuit 121 includes two switch tubes, the number of driving resistors is set to 2, and each switch tube is driven using a corresponding driving resistor.

[0134] In some embodiments, Figure 7 As shown, the first rectifying switch circuit 121 includes a fourth MOS transistor M4 and a third zener diode ZD3.

[0135] The gate of the fourth MOS tube M4 is electrically connected to the first bridge arm driving circuit 122, the drain of the fourth MOS tube M4 and the cathode of the third zener diode ZD3 are electrically connected to the first secondary winding Ns1, and the source of the fourth MOS tube M4 and the anode of the third zener diode ZD3 are grounded.

[0136] When the voltage of the first node N1 is a high level signal, the fourth MOS transistor M4 is turned on in response to the high level signal. At this time, the current of the first secondary winding Ns1 flows into the output load RL through the fourth MOS transistor M4, thereby generating an output voltage Vout across the output load RL.

[0137] When the voltage of the first node N1 is a low level signal, the fourth MOS transistor M4 is in a turned-off state in response to the low level signal, and the current of the first secondary winding Ns1 stops flowing into the output load RL.

[0138] It is understandable that the first rectifier switch circuit 121 may include one switch tube or may include multiple switch tubes, such as Figure 7 Only one switch tube is shown, and the specific number can be set according to the actual rectification needs. For example, when a larger current needs to flow, the first rectification switch circuit 121 can be provided with multiple switch tubes, and the multiple switch tubes are connected in parallel. The multiple switch tubes are uniformly driven by the first bridge arm drive circuit 122. The first bridge arm drive circuit 122 can drive the multiple switch tubes to be turned on and off at the same time.

[0139] In some embodiments, please refer to Figure 4 The synchronous rectification circuit 100 also includes a power supply circuit 14 .

[0140] The power supply circuit 14 is electrically connected to the first bridge arm driving circuit 122 and the second bridge arm driving circuit 132 respectively, and can generate a power supply voltage for the first bridge arm driving circuit 122 and the second bridge arm driving circuit 132 according to the first secondary winding voltage or the second secondary winding voltage.

[0141] In some embodiments, please refer to Figure 7 The power supply circuit 14 includes a fourteenth resistor R14, a fourth diode D4, a fifth diode D5, a sixth capacitor C6, a seventh capacitor C7, an eighth capacitor C8 and a ninth capacitor C9.

[0142] One end of the fourteenth resistor R14 is electrically connected to the first secondary winding Ns1, the other end of the fourteenth resistor R14 is electrically connected to one end of the sixth capacitor C6, the other end of the sixth capacitor C6 is electrically connected to the cathode of the fourth diode D4 and the anode of the fifth diode D5, the anode of the fourth diode D4 is electrically connected to the voltage output end and one end of the seventh capacitor C7, the other end of the seventh capacitor C7 is electrically connected to the cathode of the fifth diode D5, one end of the eighth capacitor C8, one end of the ninth capacitor C9, the first bridge arm driving circuit 122 and the second bridge arm driving circuit 132, the other end of the eighth capacitor C8 and the other end of the ninth capacitor C9 are grounded.

[0143] In practical applications, the voltage of the first secondary winding is approximately twice the output voltage Vout. After rectification by the fourth diode D4 and the fifth diode D5, it is superimposed on the output voltage Vout through the seventh capacitor C7. At the same time, through the energy storage and filtering of the eighth capacitor C8 and the ninth capacitor C9, a supply voltage approximately three times the output voltage Vout can be stably output.

[0144] In some embodiments, please refer to Figure 5 The second bridge arm driving circuit 132 includes a second driving circuit 1321 and a second interlocking circuit 1322 .

[0145] The second driving circuit 1321 is electrically connected to the second rectifying switch circuit 131 and the first secondary winding Ns1 respectively. The second driving circuit 1321 includes a fourth node N4, which can respond to the first secondary winding voltage to generate a fourth node voltage at the fourth node N4, and drive the second rectifying switch circuit 131 to be in the second working state according to the fourth node voltage.

[0146] The second interlock circuit 1322 is electrically connected to the second secondary winding Ns2 and is electrically connected to the second driving circuit 1321 at the fourth node N4, and can control the fourth node voltage in response to the second secondary winding voltage.

[0147] For example, when the first secondary winding voltage is a high-level signal and the second secondary winding voltage is a low-level signal, the second drive circuit 1321 can respond to the high-level signal, generate a fourth node voltage at the fourth node N4, and drive the second rectifier switch circuit 131 to be in a closed state according to the fourth node voltage. When the first secondary winding voltage is a low-level signal and the second secondary winding voltage is a high-level signal, the second interlock circuit 1322 can respond to the high-level signal, force the fourth node voltage to be lowered, so that the second drive circuit 1321 drives the second rectifier switch circuit 131 to be in a disconnected state according to the fourth node voltage.

[0148] Since the second interlock circuit 1322 is directly electrically connected to the second secondary winding Ns2 to respond to the second secondary winding voltage, it is beneficial to quickly pull down the fourth node voltage at the moment when the second secondary winding voltage changes from a low-level signal to a high-level signal, thereby reducing the driving delay of the second rectifier switch circuit 131, thereby facilitating the second rectifier switch circuit 131 to quickly enter the disconnected state at the moment when the first rectifier switch circuit 121 is in the closed state.

[0149] In some embodiments, please refer to Figure 6 The second interlock circuit 1322 includes a second clamping circuit 13221 and a second switch control circuit 13222 .

[0150] The second clamping circuit 13221 is electrically connected to the second secondary winding Ns2. The second clamping circuit 13221 includes a fifth node N5, which can clamp the second secondary winding voltage and control the fifth node N5 to generate a clamped voltage.

[0151] In practical applications, since the peak value of the second secondary winding voltage is relatively high, the peak value of the second secondary winding voltage is clamped and limited by the second clamping circuit 13221 to obtain a suitable voltage at the fifth node N5.

[0152] In some embodiments, please refer to Figure 7 The second clamping circuit 13221 includes a fifteenth resistor R15 and a fourth zener diode ZD4.

[0153] One end of the fifteenth resistor R15 is electrically connected to the second secondary winding Ns2 , the other end of the fifteenth resistor R15 is electrically connected to the cathode of the fourth zener diode ZD4 and the second switch control circuit 13222 , respectively, and the anode of the fourth zener diode ZD4 is grounded.

[0154] When the second secondary winding voltage is higher than the voltage regulation value of the fourth Zener diode ZD4, the fourth Zener diode ZD4 can limit the voltage of the fifth node N5 to the voltage regulation value of the fourth Zener diode ZD4, ensuring that the voltage of the fifth node N5 is not higher than the voltage regulation value of the fourth Zener diode ZD4.

[0155] It can be understood that when the second secondary winding voltage is a high level signal, the voltage of the fifth node N5 is also a high level signal, and when the second secondary winding voltage is a low level signal, the voltage of the fifth node N5 is also a low level signal.

[0156] In order to isolate the DC component of the first secondary winding voltage to obtain a more suitable voltage at the fifth node N5, in some embodiments, the second clamping circuit 13221 also includes a tenth capacitor (not shown), one end of the tenth capacitor is electrically connected to the second secondary winding, and one end of the tenth capacitor is electrically connected to one end of the fifteenth resistor R15.

[0157] The second switch control circuit 13222 is electrically connected to the second clamp circuit 13221 at the fifth node N5 and to the second driving circuit 1321 at the fourth node N4, and can control the voltage of the fourth node N4 in response to the voltage of the fifth node N5.

[0158] In some embodiments, Figure 7 As shown, the second switch control circuit 13222 includes a fifth MOS transistor M5 and a sixteenth resistor R16.

[0159] The gate of the fifth MOS transistor M5 is electrically connected to one end of the sixteenth resistor R16 and the second clamping circuit 13221 at the fifth node N5, the drain of the fifth MOS transistor M5 is electrically connected to the second driving circuit 1321 at the fourth node N4, and the source of the fifth MOS transistor M5 and the other end of the sixteenth resistor R16 are grounded.

[0160] When the voltage of the fifth node N5 is a high level signal, the fifth MOS tube M5 responds to the high level signal and is in a conducting state to pull the voltage of the fourth node N4 to the ground. When the voltage of the fifth node N5 is a low level signal, the fifth MOS tube M5 responds to the low level signal and is in a conducting state. At this time, the fifth MOS tube M5 loses control of the voltage of the fourth node N4.

[0161] The sixteenth resistor R16 is a pull-down resistor, which can accelerate the turn-off of the fifth MOS transistor M5 on one hand, and prevent the fifth MOS transistor M5 from being broken down by static electricity stored in the parasitic capacitor on the other hand.

[0162] In some embodiments, please refer to Figure 6 The second driving circuit 1321 includes a second voltage conditioning circuit 13211 , a second push-pull driving circuit 13212 and a second push-pull circuit 13213 .

[0163] The second voltage conditioning circuit 13211 is electrically connected to the first secondary winding Ns1. The second voltage conditioning circuit 13211 includes a sixth node N6. The second voltage conditioning circuit 13211 can condition the voltage of the first secondary winding and control the sixth node N6 to generate a conditioned voltage.

[0164] In some embodiments, please refer to Figure 7 The second voltage conditioning circuit 13211 includes an eleventh capacitor C11, a seventeenth resistor R17 and a fifth zener diode ZD5.

[0165] The eleventh capacitor C11 is electrically connected to the first secondary winding Ns1, the other end of the eleventh capacitor C11 is electrically connected to one end of the seventeenth resistor R17, the other end of the seventeenth resistor R17 is electrically connected to the cathode of the fifth zener diode ZD5 and the second push-pull driving circuit 13212, and the anode of the fifth zener diode ZD5 is grounded.

[0166] The eleventh capacitor C11 is used to isolate the DC signal of the first secondary winding voltage and allow the AC signal of the first secondary winding voltage to pass through. The seventeenth resistor R17 and the fifth zener diode ZD5 can, on the one hand, clamp and limit the peak value of the AC signal passing through the eleventh capacitor C11 to ensure that the voltage of the sixth node N6 is not higher than the stabilization value of the fifth zener diode ZD5; ​​on the other hand, they can raise the voltage amplitude of the AC signal passing through the eleventh capacitor C11 so that the amplitude of the voltage at the sixth node N6 is close to the amplitude of the first secondary winding voltage, so as to improve the driving capability.

[0167] It can be understood that when the first secondary winding voltage is a high level signal, the voltage of the sixth node N6 is also a high level signal, and when the first secondary winding voltage is a low level signal, the voltage of the sixth node N6 is also a low level signal.

[0168] The second push-pull driving circuit 13212 is electrically connected to the second voltage conditioning circuit 13211 at the sixth node N6 and to the second interlocking circuit 1322 at the fourth node N4, and can generate a fourth node voltage at the fourth node N4 according to the voltage of the sixth node N6.

[0169] In some embodiments, Figure 7 As shown, the second push-pull driving circuit 13212 includes an eighteenth resistor R18.

[0170] One end of the eighteenth resistor R18 is electrically connected to the second voltage conditioning circuit 13211 at the sixth node N6, and the other end of the eighteenth resistor R18 is electrically connected to the second push-pull circuit 13213 and the second interlocking circuit 1322 at the fourth node N4.

[0171] As mentioned above, when the first secondary winding voltage is a high level signal and the second secondary winding voltage is a low level signal, the second interlock circuit 1322 does not affect the voltage of the fourth node N4. At this time, the voltage of the sixth node N6 is a high level signal, and the voltage of the fourth node N4 is also a high level signal. When the first secondary winding voltage is a low level signal and the second secondary winding voltage is a high level signal, the second interlock circuit 1322 responds to the high level signal and forcibly pulls down the voltage of the fourth node N4. At this time, the voltage of the fourth node N4 is a low level signal.

[0172] The second push-pull circuit 13213 is electrically connected to the second rectifier switch circuit 131, and is respectively electrically connected to the second push-pull drive circuit 13212 and the second interlock circuit 1322 at the fourth node N4, and can respond to the fourth node voltage to drive the second rectifier switch circuit 131 to be in the second working state.

[0173] In some embodiments, Figure 7 As shown, the second push-pull circuit 13213 includes a sixth diode D6, a third transistor Q3, a fourth transistor Q4, a nineteenth resistor R19, a twentieth resistor R20 and a twenty-first resistor R21.

[0174] The base of the third transistor Q3, the base of the fourth transistor Q4, the anode of the sixth diode D6, and one end of the nineteenth resistor R19 are electrically connected to the second push-pull drive circuit 13212 and the second interlocking circuit 1322 at the fourth node N4, respectively. The cathode of the sixth diode D6 is electrically connected to the second voltage conditioning circuit 13211 at the sixth node N6. The other end of the nineteenth resistor R19 and the collector of the fourth transistor Q4 are grounded. The collector of the third transistor Q3 is electrically connected to one end of the twentieth resistor R20, and the other end of the twentieth resistor R20 is applied with a supply voltage. The emitter of the third transistor Q3, the emitter of the fourth transistor Q4, and one end of the twenty-first resistor R21 are connected together, and the other end of the twenty-first resistor R21 is electrically connected to the second rectifier switch circuit 131.

[0175] As mentioned above, when the voltage of the fourth node N4 is a high-level signal, the third transistor Q3 is in an on state, the fourth transistor Q4 is in an off state, and the emitter voltage of the third transistor Q3 is a high-level signal. The high-level signal is applied to the second rectifier switch circuit 131 through the twenty-first resistor R21, so that the second rectifier switch circuit 131 is in a closed state.

[0176] When the voltage of the fourth node N4 is a low level signal, the third transistor Q3 is in the off state, the fourth transistor Q4 is in the on state, and the emitter voltage of the fourth transistor Q4 is a low level signal, so that the second rectifier switch circuit 131 is in the off state.

[0177] The sixth diode D6 is a feedback diode, and is used for accelerating the third transistor Q3 to enter a cut-off state when the voltage of the fourth node N4 changes from a high level signal to a low level signal.

[0178] The nineteenth resistor R19 is a pull-down resistor, which can reliably ground the base of the third transistor Q3 and the base of the fourth transistor Q4 when an uncertain level signal appears at the voltage of the fourth node N4, thereby preventing the third transistor Q3 and the fourth transistor Q4 from malfunctioning due to the influence of noise signals.

[0179] The twentieth resistor R20 plays a role of pull-up and current limiting. On the one hand, the twentieth resistor R20 can pull the emitter voltage of the third transistor Q3 to a high level when the third transistor Q3 is in the on state. On the other hand, the twentieth resistor R20 can also limit the current flowing through the third transistor Q3 when the third transistor Q3 is in the on state.

[0180] The twenty-first resistor R21 is a driving resistor, and is used to reliably drive the second rectifying switch circuit 131 .

[0181] It is understandable that the number of the driving resistors may be one or more. Figure 7 Only one driving resistor is shown, and the specific number can be set according to the switch tube included in the second rectifier switch circuit 131. For example, when the second rectifier switch circuit 131 includes one switch tube, the number of driving resistors is set to 1, and the driving resistor is used to drive the switch tube. When the second rectifier switch circuit 131 includes two switch tubes, the number of driving resistors is set to 2, and each switch tube is driven using a corresponding driving resistor.

[0182] In some embodiments, please refer to Figure 7 The second rectifying switch circuit 131 includes a sixth MOS transistor M6 and a sixth voltage stabilizing diode ZD6.

[0183] The gate of the sixth MOS tube M6 is electrically connected to the second bridge arm driving circuit 132, the drain of the sixth MOS tube M6 and the cathode of the sixth zener diode ZD6 are electrically connected to the second secondary winding Ns2, and the source of the sixth MOS tube M6 and the anode of the sixth zener diode ZD6 are grounded.

[0184] When the voltage of the fourth node N4 is a high level signal, the sixth MOS transistor M6 is in a conducting state in response to the high level signal. At this time, the current of the second secondary winding Ns2 can flow into the output load RL through the sixth MOS transistor M6, thereby generating an output voltage Vout across the output load RL.

[0185] When the voltage of the fourth node N4 is a low level signal, the fifth MOS transistor M5 is in a turned-off state in response to the low level signal, and the current of the second secondary winding Ns2 stops flowing into the output load RL.

[0186] It is understandable that the second rectifier switch circuit 131 may include one switch tube or may include multiple switch tubes, such as Figure 7 Only one switch tube is shown, and the specific number can be set according to the actual rectification needs. For example, when a larger current needs to flow, the second rectification switch circuit 131 can be provided with multiple switch tubes, and the multiple switch tubes are connected in parallel. The multiple switch tubes are uniformly driven by the first bridge arm drive circuit 122, and the second bridge arm drive circuit 132 can drive the multiple switch tubes to be turned on and off at the same time.

[0187] In order to further explain the working principle of a synchronous rectification circuit 100 provided by an embodiment of the present invention, Figure 8 and Fig. 9 Elaborate in detail.

[0188] like Figure 8 As shown, when the first control signal PWM1 is a high-level signal and the second control signal PWM2 is a low-level signal, the first MOS tube M1 is in an on state, and the second MOS tube M2 is in an off state. The DC input power supply VIN, the first MOS tube M1, the same-name end of the primary winding Np1, the opposite-name end of the primary winding Np1, and the third capacitor C3 form a loop, and the primary winding Np1 stores energy through the loop. At this time, the same-name end voltage of the primary winding Np1 is positive, and the opposite-name end voltage of the primary winding Np1 is negative. After energy coupling, the opposite-name end voltage of the first secondary winding Ns1 is positive, and the same-name end voltage of the second secondary winding Ns2 is negative, that is, the first secondary winding voltage is a high-level signal, and the second secondary winding voltage is a low-level signal.

[0189] Since the first secondary winding voltage is a high level signal, the voltage of the fourth node N4 is also a high level signal, so the third transistor Q3 is in the on state, the fourth transistor Q4 is in the off state, so that the sixth MOS transistor M6 is in the on state, and the third MOS transistor M3 is in the on state in response to the high level signal, forcibly pulling down the voltage of the first node N1, so that the first transistor Q1 is in the off state, the second transistor Q2 is in the on state, so that the fourth MOS transistor M4 quickly enters the off state.

[0190] Since the second secondary winding voltage is a low level signal, the fifth MOS transistor M5 responds to the low level signal and is in a turned-off state, thereby not affecting the voltage of the fourth node N4 and ensuring that the sixth MOS transistor M6 is in a turned-on state.

[0191] Therefore, at this time, the opposite-name end of the second secondary winding Ns2, the output load RL / output capacitor Cout, the sixth MOS transistor M6 and the same-name end of the second secondary winding Ns2 form a loop, and the current passes through the loop to charge the output capacitor Cout and supply power to the output load RL.

[0192] like Fig. 9 As shown, when the first control signal PWM1 is a low-level signal and the second control signal PWM2 is a high-level signal, the first MOS tube M1 is in an off state, and the second MOS tube M2 is in an on state. The opposite-name end of the primary winding Np1, the same-name end of the primary winding Np1, the second MOS tube M2 and the third capacitor C3 form a loop, and the primary winding Np1 releases the stored energy through the loop. At this time, the opposite-name end voltage of the primary winding Np1 is positive, and the same-name end voltage of the primary winding Np1 is negative. After energy coupling, the same-name end voltage of the second secondary winding Ns2 is positive, and the opposite-name end voltage of the first secondary winding Ns1 is negative, that is, the second secondary winding voltage is a high-level signal, and the first secondary winding voltage is a low-level signal.

[0193] Since the second secondary winding voltage is a high level signal, the voltage of the first node N1 is also a high level signal, so the first transistor Q1 is in the on state, the second transistor Q2 is in the off state, so that the fourth MOS transistor M4 is in the on state, and the fifth MOS transistor M5 is in the on state in response to the high level signal, and the voltage of the fourth node N4 is forced to be lowered, so that the third transistor Q3 is in the off state, the fourth transistor Q4 is in the on state, so that the sixth MOS transistor M6 quickly enters the off state.

[0194] Since the first secondary winding voltage is a low level signal, the third MOS transistor M3 is in a turned-off state in response to the low level signal, thereby not affecting the voltage of the first node N1 and ensuring that the fourth MOS transistor M4 is in a turned-on state.

[0195] Therefore, at this time, the same-name end of the first secondary winding Ns1, the output load RL / output capacitor Cout, the fourth MOS transistor M4 and the opposite-name end of the first secondary winding Ns1 form a loop, and the current passes through the loop to supply power to the output load RL.

[0196] As another embodiment of the present invention, the present invention provides a circuit board, which includes the synchronous rectification circuit as described above, wherein the circuit board can be an independent circuit board or a circuit board formed by splicing multiple circuit boards.

[0197] As another embodiment of the present invention, an electronic device is provided in the embodiment of the present invention. The electronic device includes the circuit board as described above.

[0198] Finally, it should be noted that the present invention can be implemented in many different forms and is not limited to the embodiments described in this specification. These embodiments are not intended to be additional limitations on the content of the present invention. The purpose of providing these implementations is to make the understanding of the disclosure of the present invention more thorough and comprehensive. In addition, under the idea of ​​the present invention, the above-mentioned technical features continue to be combined with each other, and there are many other changes in different aspects of the present invention as described above, which are all considered to be within the scope of the present invention specification; further, for ordinary technicians in this field, they can be improved or transformed according to the above description, and all these improvements and transformations should belong to the scope of protection of the claims attached to the present invention.

Claims

1. A synchronous rectification circuit, characterized in that: include: A resonant circuit, used for providing a first secondary winding voltage and a second secondary winding voltage; A first bridge arm rectifier circuit, comprising a first rectifier switch circuit and a first bridge arm drive circuit, wherein the first rectifier switch circuit is electrically connected to the resonant circuit and the first bridge arm drive circuit respectively, and the first bridge arm drive circuit is also electrically connected to the resonant circuit, and is used to respond to the first secondary winding voltage and the second secondary winding voltage to drive the first rectifier switch circuit to be in a first working state; The second bridge arm rectifier circuit includes a second rectifier switch circuit and a second bridge arm drive circuit, wherein the first rectifier switch circuit is electrically connected to the resonant circuit and the second bridge arm drive circuit respectively, and the second bridge arm drive circuit is also electrically connected to the resonant circuit, and is used to respond to the first secondary winding voltage and the second secondary winding voltage to drive the second rectifier switch circuit to be in a second working state, wherein the second working state is mutually exclusive with the first working state to prevent the first rectifier switch circuit, the second rectifier switch circuit and the resonant circuit from forming a short circuit.

2. The synchronous rectification circuit according to claim 1, characterized in that: When the first working state is a working state in which the first rectifier switch circuit is in a closed state, the second working state is a working state in which the second rectifier switch circuit is in a disconnected state; When the first working state is a working state in which the first rectifier switch circuit is in an open state, the second working state is a working state in which the second rectifier switch circuit is in a closed state.

3. The synchronous rectification circuit according to claim 1, characterized in that: When the first secondary winding voltage is a first level type signal, the second secondary winding voltage is a second level type signal, and the first level type signal and the second level type signal are signals of different level types; When the first secondary winding voltage is a second level type signal, the second secondary winding voltage is a first level type signal.

4. The synchronous rectification circuit according to claim 1, characterized in that: The first bridge arm driving circuit comprises: a first driving circuit, electrically connected to the resonant circuit and the first rectifying switch circuit, respectively, the first driving circuit comprising a first node, for generating a first node voltage at the first node in response to the second secondary winding voltage, and driving the first rectifying switch circuit to be in a first working state according to the first node voltage; A first interlock circuit is electrically connected to the resonant circuit and to the first drive circuit at the first node, and is used to control the first node voltage in response to the first secondary winding voltage.

5. The synchronous rectification circuit according to claim 4, characterized in that: The first interlock circuit comprises: a first clamping circuit electrically connected to the resonant circuit, the first clamping circuit comprising a second node for clamping the first secondary winding voltage and controlling the second node to generate a clamped voltage; The first switch control circuit is electrically connected to the first clamp circuit at the second node and to the first drive circuit at the first node, and is used to control the voltage of the first node in response to the voltage of the second node.

6. The synchronous rectification circuit according to claim 4, characterized in that: The first driving circuit comprises: a first voltage conditioning circuit, electrically connected to the resonant circuit, the first voltage conditioning circuit comprising a third node, for conditioning the second secondary winding voltage and controlling the third node to generate a conditioned voltage; A first push-pull driving circuit is electrically connected to the first voltage conditioning circuit at the third node and to the first interlocking circuit at the first node, and is used to generate a first node voltage at the first node according to the voltage of the third node; The first push-pull circuit is electrically connected to the first rectifier switch circuit and is respectively electrically connected to the first push-pull drive circuit and the first interlock circuit at the first node, and is used for responding to the first node voltage to drive the first rectifier switch circuit to be in a first working state.

7. The synchronous rectification circuit according to claim 1, characterized in that: The second bridge arm driving circuit comprises: a second driving circuit, electrically connected to the resonant circuit and the second rectifying switch circuit, respectively, the second driving circuit comprising a fourth node, for generating a fourth node voltage at the fourth node in response to the first secondary winding voltage, and driving the second rectifying switch circuit to be in a second working state according to the voltage of the fourth node; The second interlock circuit is electrically connected to the resonant circuit and to the second drive circuit at the fourth node, and is used to control the fourth node voltage in response to the second secondary winding voltage.

8. The synchronous rectification circuit according to claim 7, characterized in that: The second interlock circuit comprises: a second clamping circuit electrically connected to the resonant circuit, the second clamping circuit comprising a fifth node for clamping the second secondary winding voltage and controlling the fifth node to generate a clamped voltage; The second switch control circuit is electrically connected to the second clamping circuit at the fifth node and to the second driving circuit at the fourth node, and is used for controlling the voltage of the fourth node in response to the voltage of the fifth node.

9. The synchronous rectification circuit according to claim 7, characterized in that: The second driving circuit comprises: a second voltage conditioning circuit, electrically connected to the resonant circuit, the second voltage conditioning circuit comprising a sixth node, for conditioning the first secondary winding voltage and controlling the sixth node to generate a conditioned voltage; A second push-pull driving circuit is electrically connected to the second voltage conditioning circuit at the sixth node and to the second interlocking circuit at the fourth node, and is used to generate a fourth node voltage at the fourth node according to the voltage of the sixth node; The second push-pull circuit is electrically connected to the second rectifier switch circuit, and is electrically connected to the second push-pull drive circuit and the second interlock circuit at the fourth node, respectively, and is used to respond to the fourth node voltage to drive the second rectifier switch circuit to a second working state.

10. The synchronous rectification circuit according to any one of claims 1 to 9, characterized in that: Also includes a power supply circuit; The power supply circuit is electrically connected to the resonant circuit, the first bridge arm drive circuit and the second bridge arm drive circuit respectively, and is used to generate a power supply voltage according to the first secondary winding voltage, and the power supply voltage is used to power the first bridge arm drive circuit and the second bridge arm drive circuit.

11. A circuit board, characterized in that: Comprising the synchronous rectification circuit as claimed in any one of claims 1 to 10.

12. An electronic device, characterized in that: Comprising the circuit board as claimed in claim 11.

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