Monitoring signal generation circuit and method of intelligent output stage

Abstract

The invention discloses a monitoring signal generation circuit of an intelligent output stage and a method thereof. The intelligent output stage provides an output current. The monitoring signal generating circuit provides a current monitoring signal related to the output current. The monitoring signal generating circuit comprises an analog current circuit and a control circuit. The analog current circuit receives a reference voltage and provides an analog current signal or the reference voltage as a current monitoring signal. The control circuit is coupled to the analog current circuit and receives the reference voltage, the current monitoring signal and the indication signal. The control circuit controls the analog current circuit to provide the analog current signal or the reference voltage as the current monitoring signal according to the current monitoring signal and the reference voltage when the indication signal indicates that the plurality of power switches of the intelligent output stage are all turned off. According to the monitoring signal generation circuit and method of the intelligent output stage, the current monitoring signal reflecting the waveform of the output current can still be provided when the pulse width modulation signal received by the intelligent output stage is a tri-state signal, so that an overcurrent protection mechanism can still operate normally.

Description

Technical Field

[0001] The present invention relates to a smart power stage (SPS), and in particular to a monitoring signal generating circuit and method of the smart power stage. Background Art

[0002] Generally speaking, when a traditional SPS receives a pulse width modulation (PWM) signal from an external controller, the driver inside the SPS will convert the pulse width modulation signal into an on-time signal to the drive circuit to control the upper bridge switch / lower bridge switch of the output stage to alternately turn on / off, so as to achieve the function of adjusting the output voltage / current. In light load or special circumstances (such as during the protection mechanism), since there is no need to shut down the switch temporarily, the controller will switch the pulse width modulation signal to the third state (Tri-state) to shut down the upper bridge switch / lower bridge switch at the same time, so that the switching frequency can be greatly reduced to reduce switching losses.

[0003] For an SPS capable of providing an analog current signal as a monitoring signal (I MON) to a controller, since the analog current signal is generated according to a PWM signal, when the PWM signal is in a third state, the monitoring signal will be reset to a fixed reference voltage (REF IN).

[0004] However, since the SPS itself cannot judge whether the load is light or heavy, if it enters this state during the over-current protection (OCP) period of heavy load, the monitoring signal is reset to the reference voltage, causing the SPS to be unable to obtain the correct output current information during this period. When the SPS resumes switching, the over-current protection (OCP) mechanism cannot be triggered, which will cause the switch to burn out. This situation needs to be further resolved. Summary of the invention

[0005] In view of this, the present invention proposes a monitoring signal generating circuit and method of an intelligent output stage to effectively solve the above problems encountered in the prior art.

[0006] According to one embodiment of the present invention, a monitoring signal generating circuit of an intelligent output stage is provided. In this embodiment, the intelligent output stage provides an output current. The monitoring signal generating circuit provides a current monitoring signal related to the output current. The monitoring signal generating circuit includes an analog current circuit and a control circuit. The analog current circuit receives a reference voltage and provides an analog current signal or a reference voltage as a current monitoring signal. The control circuit is coupled to the analog current circuit and receives the reference voltage, the current monitoring signal and the indication signal respectively. During the period when the indication signal indicates that multiple power switches of the intelligent output stage are all turned off, the control circuit controls the analog current circuit to provide an analog current signal or a reference voltage as a current monitoring signal according to the current monitoring signal and the reference voltage.

[0007] In one embodiment, if the current monitoring signal is equal to the reference voltage, the control circuit controls the analog current circuit to provide the reference voltage as the current monitoring signal.

[0008] In one embodiment, the analog current circuit includes a ramp signal generating circuit and a switching switch. The ramp signal generating circuit is coupled to the output node of the analog current circuit to provide a ramp signal as the analog current signal during the period when the intelligent output stage provides the output current. One end of the switching switch is coupled to the output node and the other end receives a reference voltage. During the period when the indication signal indicates that the multiple power switches of the intelligent output stage are all turned off, when the current monitoring signal is not equal to the reference voltage, the switching switch is turned off so that the ramp signal generating circuit continues to provide the ramp signal. When the current monitoring signal is equal to the reference voltage, the switching switch is turned on so that the analog current circuit provides the reference voltage as the current monitoring signal.

[0009] In one embodiment, when the current monitoring signal is greater than the reference voltage, the ramp signal has a negative slope.

[0010] In one embodiment, when the current monitoring signal is less than the reference voltage, the ramp signal has a positive slope.

[0011] In one embodiment, the monitoring signal generating circuit further includes a sensing signal generating circuit and a selector. The sensing signal generating circuit generates a current sensing signal according to the output current or the switch voltage received from the intelligent output stage. The selector is respectively coupled to the sensing signal generating circuit, the output node of the analog current circuit and the output end of the monitoring signal generating circuit, and is used to selectively connect the output end of the monitoring signal generating circuit to the output node of the sensing signal generating circuit or the analog current circuit according to the pulse width modulation signal.

[0012] In one embodiment, the intelligent output stage includes a driver, a monitoring signal generating circuit and an output stage. The driver is respectively coupled to an external controller and the output stage, and is used to receive a pulse width modulation signal from the controller to control the output stage to provide an output current. The output stage includes a plurality of power switches, and is used to provide an output current. The monitoring signal generating circuit is respectively coupled to the driving circuit, the output stage and the controller, and provides a current monitoring signal to the controller according to the pulse width modulation signal. The pulse width modulation signal has a first state, a second state and a third state between the first state and the second state, and the indication signal is synchronized with the third state of the pulse width modulation signal.

[0013] In one embodiment, the control circuit includes a comparison circuit and a logic circuit. The comparison circuit compares the current monitoring signal with a reference voltage to generate a comparison result. The logic circuit is coupled to the comparison circuit and the analog current circuit respectively to generate a switching signal according to the indication signal and the comparison result to control the analog current circuit to provide a reference voltage as the current monitoring signal.

[0014] In one embodiment, during a period when the indication signal indicates that the multiple power switches of the intelligent output stage are all turned off, when the comparison result changes state, the switching signal controls the analog current circuit to output a reference voltage as the current monitoring signal.

[0015] According to another embodiment of the present invention, a monitoring signal generating method for an intelligent output stage is provided. In this embodiment, the monitoring signal generating method for an intelligent output stage is used to generate a current monitoring signal related to an output current provided by the intelligent output stage. The monitoring signal generating method includes the following steps: (a) determining whether the indication signal indicates that multiple power switches of the intelligent output stage are all turned off; and (b) if the determination result of step (a) is yes, then selectively providing an analog current signal or a reference voltage as the current monitoring signal according to the current monitoring signal and the reference voltage.

[0016] In one embodiment, if the current monitoring signal is equal to the reference voltage, step (b) provides the reference voltage as the current monitoring signal.

[0017] In one embodiment, if the current monitoring signal is not equal to the reference voltage, step (b) continues to provide the ramp signal as the current monitoring signal.

[0018] In one embodiment, step (b) includes: if the current monitoring signal is greater than the reference voltage, the ramp signal has a negative slope.

[0019] In one embodiment, step (b) includes: if the current monitoring signal is less than the reference voltage, the ramp signal has a positive slope.

[0020] In one embodiment, step (b) includes: (b1) comparing the current monitoring signal with a reference voltage to generate a comparison result; and (b2) providing the reference voltage as the current monitoring signal according to the indication signal and the comparison result.

[0021] In one embodiment, when the comparison result changes state, step (b2) provides a reference voltage as a current monitoring signal.

[0022] Compared to the prior art, even when the pulse width modulation signal received by the intelligent output stage is a tri-state signal, the monitoring signal generating circuit and method of the intelligent output stage of the present invention can still provide a current monitoring signal (IMON) reflecting the output current waveform without directly switching the current monitoring signal to a reference voltage, so that the over-current protection (OCP) mechanism can still operate normally.

[0023] The advantages and spirit of the present invention may be further understood through the following specific embodiments and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings of the present invention are described as follows:

[0025] Figure 1 FIG. 4 is a schematic diagram of a smart output stage (SPS) integrated circuit according to an embodiment of the present invention.

[0026] Figure 2 FIG. 4 is a schematic diagram of a monitoring signal generating circuit of an intelligent output stage in an embodiment of the present invention.

[0027] Figure 3 is a schematic diagram of a simulation current circuit in an embodiment of the present invention.

[0028] Figure 4 is a schematic diagram of a logic circuit in an embodiment of the present invention.

[0029] Figure 5A They are waveform timing diagrams of the pulse width modulation signal PWM, the output current IL, the current monitoring signal IMON, the switching signal S1, and the comparison result CMP.

[0030] Figure 5B FIG. 4 is a waveform timing diagram of the current monitoring signal IMON when it is close to the reference voltage REFIN.

[0031] Figure 6 FIG. 4 is a schematic diagram of a monitoring signal generating circuit of an intelligent output stage according to another embodiment of the present invention.

[0032] Figure 7 FIG. 4 is a flow chart of a monitoring signal generating method of an intelligent output stage according to another embodiment of the present invention.

[0033] Description of main component symbols:

[0034] CON…Controller

[0035] 1…Intelligent output stage

[0036] DR…Driver

[0037] OS…Output stage

[0038] P1~P4…pins

[0039] IMG…Monitoring signal generation circuit

[0040] PWM…Pulse Width Modulation Signal

[0041] HS…First control signal

[0042] LS...Second control signal

[0043] M1, M2…power switch

[0044] TS…Indicator signal

[0045] IL…output current

[0046] VSW…Switching voltage

[0047] 10…Simulation current circuit

[0048] 12…Control circuit

[0049] 120…Comparator

[0050] 122…Logic circuit

[0051] SW…Switch

[0052] N…output nodes

[0053] IMON…current monitoring signal

[0054] IMON_EMU…Analog current signal

[0055] TS…Indicator signal

[0056] REFIN…reference voltage

[0057] S1…Switching signal

[0058] CMP…Comparison results

[0059] IS1…First current source

[0060] IS2…Second current source

[0061] SW1…First switch

[0062] SW2…Second switch

[0063] SW3…The third switch

[0064] NOT...Reverse lock

[0065] C…Capacitance

[0066] GND…ground terminal

[0067] DFF1…The first D-type flip-flop

[0068] DFF2…The second D-type flip-flop

[0069] NOR1~NOR3…NOR gate

[0070] t1~t11…time

[0071] COM…Comparison Circuit

[0072] RG...Ramp signal generating circuit

[0073] VIN…Input voltage

[0074] VOUT…output voltage

[0075] LG…Logic Circuit

[0076] 20…Sensing signal generating circuit

[0077] 22…Simulation current circuit

[0078] 24…Control circuit

[0079] 26…Selector

[0080] 240…Comparator

[0081] 242…Logic circuit

[0082] CS…Current sensing signal

[0083] P…Output

[0084] S10~S16…Steps DETAILED DESCRIPTION

[0085] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Elements / components using the same or similar reference numerals in the drawings and embodiments are intended to represent the same or similar parts.

[0086] According to one embodiment of the present invention, a monitoring signal generating circuit of an intelligent output stage is provided. In this embodiment, an SPS receives a pulse width modulation (PWM) signal and provides an output current (IL). The monitoring signal generating circuit provides a current monitoring signal (IMON) related to the output current. When the pulse width modulation signal is a tri-state signal, the current monitoring signal output by the monitoring signal generating circuit can still normally reflect the output current, so that the over-current protection (OCP) mechanism of the intelligent output stage can still operate normally.

[0087] Please refer to Figure 1 , Figure 1 This is a schematic diagram of the intelligent output stage in this embodiment. Figure 1 As shown, the intelligent output stage 1 is coupled to an external controller CON. The intelligent output stage 1 includes a driver DR, a monitoring signal generating circuit IMG and an output stage OS. The driver DR is coupled to the monitoring signal generating circuit IMG and the output stage OS respectively and is coupled to the controller CON through a pin P1. The output stage OS is coupled to the monitoring signal generating circuit IMG.

[0088] The controller CON provides a pulse width modulation signal PWM to the driver DR. The driver DR receives the pulse width modulation signal PWM and generates a first control signal HS and a second control signal LS to the output stage OS to control the upper bridge switch M1 and the lower bridge switch M2 (i.e., a plurality of power switches in the intelligent output stage) therein. The driver DR also generates an indication signal TS to the monitoring signal generating circuit IMG according to the pulse width modulation signal PWM.

[0089] The output stage OS receives the first control signal HS and the second control signal LS respectively and controls the multiple power switches in the output stage to generate an output current (inductor current) IL to the pin P3. The output stage OS also generates a switch voltage VSW to the monitoring signal generating circuit IMG. The monitoring signal generating circuit IMG receives the first control signal HS, the second control signal LS, the indication signal TS and the switch voltage VSW from the output stage OS from the driver DR respectively and receives the reference voltage REFIN from the intelligent output stage 1 through the pin P2 to generate a current monitoring signal IMON to the pin P4 and output it to the controller CON for feedback control.

[0090] It should be noted that the pulse width modulation signal PWM provided by the controller CON has a first state of a high level (H), a second state of a low level (L), and a third state (Tri-state) between the high level and the low level. The first control signal HS, the second control signal LS, and the indication signal TS provided by the driver DR only have a first state of a high level (H) and a second state of a low level (L), but are not limited thereto.

[0091] For example, in a normal operation state, when the pulse width modulation signal PWM is in a first state of a high level (H), the first control signal HS is in a first state of a high level (H), and the second control signal LS and the indication signal TS are in a second state of a low level (L); when the pulse width modulation signal PWM is in a second state of a low level (L), the first control signal HS and the indication signal TS are in a second state of a low level (L), and the second control signal LS is in a first state of a high level (H). When the pulse width modulation signal PWM is in a third state, the first control signal HS and the second control signal LS are both in a second state of a low level (L), and the indication signal TS is in a first state of a high level (H). In other words, the indication signal TS is synchronized with the third state of the pulse width modulation signal PWM, and when the indication signal TS is in a first state of a high level (H), the upper bridge switch M1 and the lower bridge switch M2 of the indication output stage OS are both turned off.

[0092] Please refer to Figure 2 , Figure 2 This is a schematic diagram of the monitoring signal generating circuit IMG of the intelligent output stage 1 in this embodiment. Figure 2As shown, the monitoring signal generating circuit IMG includes an analog current circuit 10, a control circuit 12 and an output terminal P. The control circuit 12 is coupled to the analog current circuit 10. An output node N of the analog current circuit 10 is coupled to the output terminal P of the monitoring signal generating circuit IMG.

[0093] The analog current circuit 10 receives the reference voltage REFIN and provides an analog current signal IMON_EMU or the reference voltage REFIN as a current monitoring signal IMON. The control circuit 12 receives the reference voltage REFIN, the current monitoring signal IMON and the indication signal TS respectively. During the period when the indication signal TS indicates that the multiple power switches of the intelligent output stage 1 (i.e., the upper bridge switch M1 and the lower bridge switch M2 of the output stage OS) are all turned off, the control circuit 12 controls the analog current circuit 10 to provide the analog current signal IMON_EMU or the reference voltage REFIN as the current monitoring signal IMON according to the current monitoring signal IMON and the reference voltage REFIN.

[0094] In this embodiment, the analog current circuit 10 includes a ramp signal generating circuit RG and a switch SW. The ramp signal generating circuit is coupled to the output node N of the analog current circuit 10 and provides a ramp signal as the analog current signal IMON_EMU. One end of the switch SW is coupled to the output node N and the other end receives the reference voltage REFIN. When the current monitoring signal IMON is not equal to the reference voltage REFIN, the switch SW is turned off so that the ramp signal generating circuit RG continues to provide the ramp signal. When the current monitoring signal IMON is equal to the reference voltage REFIN, the switch SW is turned on so that the analog current circuit 10 provides the reference voltage REFIN as the current monitoring signal IMON.

[0095] In this embodiment, the control circuit 12 includes a comparator 120 and a logic circuit 122. A first input terminal + of the comparator 120 is coupled to the output node N to receive the current monitoring signal IMON. A second input terminal - of the comparator 120 receives a reference voltage REFIN. The comparator 120 compares the current monitoring signal IMON with the reference voltage REFIN to generate a comparison result CMP and provides it to the logic circuit 122. The logic circuit 122 receives the indication signal TS and the comparison result CMP respectively, and generates a switching signal S1 according to the indication signal TS and the comparison result CMP to control the on or off of the switching switch SW in the analog current circuit 10.

[0096] The analog current circuit 10 receives the comparison result CMP from the comparator 120 and the switching signal S1 from the logic circuit 122, and determines the ramp waveform of the analog current signal IMON_EMU, whether to continue to provide the analog current signal IMON_EMU with the ramp waveform or to provide the reference voltage REFIN as the current monitoring signal IMON according to the comparison result CMP and the switching signal S1.

[0097] For example, if the comparison result CMP indicates that the current monitoring signal IMON is not equal to the reference voltage REFIN, the control circuit 12 controls the analog current circuit 10 to continuously provide the analog current signal IMON_EMU (i.e., continuously provide the ramp signal) as the current monitoring signal IMON output by the monitoring signal generating circuit IMG; if the comparison result CMP indicates that the analog current signal IMON_EMU is equal to the reference voltage REFIN, the control circuit 12 controls the analog current circuit 10 to provide the reference voltage REFIN as the current monitoring signal IMON output by the monitoring signal generating circuit IMG.

[0098] Please refer to Figure 3 , Figure 3 FIG. 1 is a schematic diagram of a ramp signal generating circuit RG in an analog current circuit 10 according to an embodiment of the present invention. Figure 3 As shown, the ramp signal generating circuit RG includes a first current source IS1, a second current source IS2, a first switch SW1, a second switch SW2, a third switch SW3, a gate NOT and a capacitor C. The first switch SW1, the second switch SW2 and the second current source IS2 are connected in series between the first current source IS1 and the ground terminal GND. One end of the third switch SW3 is coupled between the first switch SW1 and the second switch SW2 and the other end of the third switch SW3 is coupled to one end of the capacitor C. The other end of the capacitor C is coupled to the ground terminal GND.

[0099] The first switch SW1 and the second switch SW2 are turned on or off according to the comparison result CMP. When the first switch SW1 is turned on according to the comparison result CMP, the second switch SW2 is turned off according to the comparison result CMP; when the first switch SW1 is turned off according to the comparison result CMP, the second switch SW2 is turned on according to the comparison result CMP. The third switch SW3 is turned on or off according to the switching signal S1 after the NOT gate is turned on.

[0100] Therefore, the ramp signal generator RG can control the third switch SW3 to generate the ramp signal according to the switching signal S1 from the logic circuit 122, and control the first current source IS1 to charge the capacitor C or the second current source IS2 to discharge the capacitor C according to the comparison result CMP from the comparator 120, so as to determine whether the current analog current signal IMON_EMU is a ramp signal waveform with a positive slope or a ramp signal waveform with a negative slope.

[0101] Please refer to Figure 4 , Figure 4 1 is a schematic diagram of a logic circuit 122 according to an embodiment of the present invention. It should be noted that when the pulse width modulation signal PWM enters the third state (Tri-state), the indication signal TS is at a high level. During this period, the logic circuit 122 will continue to confirm whether the comparison result CMP of the current monitoring signal IMON and the reference voltage REFIN has a state transition. Once the comparison result CMP has a state transition, the logic circuit 122 will output a switching signal S1 to stop the capacitor C inside the analog current circuit 10 from being charged / discharged, and control the switching switch SW to turn on the output node N to the reference voltage REFIN.

[0102] In one embodiment, a truth table of the comparison result CMP and the indication signal TS corresponding to different level changes of the switching signal S1 is shown in Table 1 below.

[0103] Table 1

[0104]

[0105] Please refer to Figure 5A and Figure 5B , Figure 5A It is a waveform timing diagram of the pulse width modulation signal PWM, the output current IL, the current monitoring signal IMON, the switching signal S1, and the comparison result CMP. Figure 5B FIG. 4 is a waveform timing diagram of the current monitoring signal IMON when it is close to the reference voltage REFIN.

[0106] like Figure 5A As shown, at time t1, the indication signal TS is converted to a high level (H), indicating that the pulse width modulation signal PWM enters the third state. At this time, the current monitoring signal IMON is greater than the reference voltage REFIN, and the comparison result CMP of the comparator 120 is a high level (H). The logic circuit 122 issues a switching signal S1=0 to maintain the switch SW disconnected and the switch SW3 turned on according to the indication signal TS being a high level (H) and the comparison result CMP being a high level (H). At the same time, the analog current circuit 10 generates an analog current signal IMON_EMU in response to the comparison result CMP being a high level (H) as a ramp signal with a falling waveform as the current monitoring signal IMON output.

[0107] During the period from time t1 to time t2, since the comparison result CMP has not changed state, the switching signal S1 issued by the logic circuit 122 is still maintained at 0, so that the current monitoring signal IMON continues to be a falling ramp signal. It should be noted that during the period from time t1 to time t2, the slope of the ramp signal is the same as the slope of the current monitoring signal IMON before time t1. In contrast, the prior art without tri-state emulation directly pulls the current monitoring signal IMON to the level of the reference voltage REFIN (e.g., 1.2V) at time t1 in response to the indication signal TS being at a high level (H).

[0108] At time t2, the indication signal TS is at a low level (L), and the logic circuit 122 responds to the indication signal TS being at a low level (L) and issues a switching signal S1=0 to keep the switch SW disconnected and the switch SW3 turned on. At the same time, the analog current circuit 10 generates a falling ramp signal as the current monitoring signal IMON output according to the pulse width modulation signal PWM being at a low level (L) in a normal operation mechanism. In contrast, the prior art without three-state simulation also responds to the indication signal TS being at a low level (L) and generates a falling ramp signal as the current monitoring signal IMON output according to the pulse width modulation signal PWM being at a low level (L) in a normal operation mechanism.

[0109] At time t3 , the pulse width modulation signal PWM is at a high level (H), and the analog current signal IMON_EMU generated by the analog current circuit 10 in the normal operation mode starts to rise.

[0110] At time t4, the current monitoring signal IMON of the present invention reaches the threshold value (e.g., 1.9V) of the over-current protection (OCP), triggering the current-limit mechanism of the controller CON and turning the pulse width modulation signal PWM to a low level (L), and the actual output current IL also begins to decrease due to the current-limit mechanism. The waveform of the current monitoring signal IMON also begins to decrease in response to the pulse width modulation signal PWM turning to a low level (L). In contrast, the prior art without three-state simulation does not trigger the over-current protection (OCP) at time t4, so the current monitoring signal IMON and the output current IL continue to rise.

[0111] At time t5 , the output current IL of the prior art without three-state simulation has exceeded the threshold of over-current protection (OCP), which may easily cause the circuit to burn out.

[0112] During the period from time t6 to time t8 and from time t9 to time t11, the current monitoring signal IMON is substantially equal to the reference voltage REFIN (e.g., 1.2V). During the third state of the pulse width modulation signal PWM, the logic circuit 122 triggers the switching signal S1=1 according to the transition of the comparison result CMP to turn on the switching switch SW, so that the analog current circuit 10 outputs the reference voltage REFIN as the current monitoring signal IMON.

[0113] Please refer to Figure 5B Specifically, during the period from time t6 to time t8, the indication signal TS is at a high level (H) in response to the third state of the pulse width modulation signal PWM. At time t6, the comparator 120 obtains a comparison result CMP with a low level (L) according to the current monitoring signal IMON being less than the reference voltage REFIN. The logic circuit 122 sends a switching signal S1=0 according to the comparison result CMP to disconnect the switching switch SW, so that the monitoring signal generating circuit selects the analog current signal IMON_EMU as the current monitoring signal IMON output. At this time, the analog current circuit 122 responds to the comparison result CMP as a low level (L), and the ramp signal generating circuit generates a ramp signal with a positive slope.

[0114] At time t7, the comparison result CMP of the comparator 120 changes from a low level (L) to a high level (H) in response to the current monitoring signal IMON being greater than the reference voltage REFIN, thereby triggering the logic circuit 122 to issue a switching signal S1=1 to turn on the switch SW and turn off the switch SW3. The monitoring signal generating circuit selects the reference voltage REFIN as the current monitoring signal IMON output, and at the same time causes the analog current circuit 122 to stop outputting the ramp signal.

[0115] At time t8 , the indication signal TS is at a low level (L), and the original current monitoring signal IMON generation mechanism is restored.

[0116] During the period from time t9 to time t11 , the indication signal TS is at a high level (H) in response to the third-state period of the pulse width modulation signal PWM.

[0117] At time t9, the comparator 120 generates a comparison result CMP with a high level (H) according to the current monitoring signal IMON being greater than the reference voltage REFIN, so that the logic circuit 122 issues a switching signal S1=0 to turn off the switch SW, so that the monitoring signal generating circuit selects the analog current signal IMON_EMU as the current monitoring signal IMON output. At this time, the analog current circuit 10 responds to the comparison result CMP as a high level (H), and the ramp signal generated by the ramp signal generating circuit has a negative slope.

[0118] At time t10, the comparison result CMP of the comparator 120 changes from a high level (H) to a low level (L) in response to the current monitoring signal IMON being less than the reference voltage REFIN, thereby triggering the logic circuit 122 to issue a switching signal S1=1 to turn on the switch SW and turn off the switch SW3. The monitoring signal generating circuit selects the reference voltage REFIN as the current monitoring signal IMON output, and at the same time causes the analog current circuit 122 to stop outputting the ramp signal.

[0119] At time t11 , the indication signal TS is at a low level (L), and the original current monitoring signal IMON generation mechanism is restored.

[0120] In summary, it can be seen that when the monitoring signal generating circuit IMG receives the indication signal TS, it will first determine whether the current monitoring signal IMON is equal to the reference voltage REFIN. If the current monitoring signal IMON is not equal to the reference voltage REFIN, the analog current circuit 10 continues to provide the analog current signal IMON_EMU as the current monitoring signal IMON output. If the current monitoring signal IMON is equal to the reference voltage REFIN, the reference voltage REFIN is used as the current monitoring signal IMON output.

[0121] It should be noted that the principle of this method is to design using the continuity of the output current (IL). When the pulse width modulation signal PWM enters the third state, the upper bridge switch and the lower bridge switch of the output stage OS are both turned off, and the actual output current IL will maintain the slope of the original normal operation state and return to zero current. That is, if the output current IL enters the third state when it is greater than zero, the output current IL will maintain the original slope and linearly decrease, otherwise the slope of the output current IL will maintain the original slope and linearly increase.

[0122] Please refer to Figure 6 , Figure 6 FIG. 1 is a schematic diagram of a monitoring signal generating circuit of an intelligent output stage according to another embodiment of the present invention. Figure 2 The difference between the embodiments is that the monitoring signal generating circuit IMG further includes a sensing signal generating circuit 20 and a selector 26. The sensing signal generating circuit 20 senses the output current IL or receives the switch voltage VSW to generate a current sensing signal CS. The selector 26 is coupled to the sensing signal generating circuit 20, the output node N of the analog current circuit 22, and the output terminal P of the monitoring signal generating circuit IMG, respectively.

[0123] In this embodiment, the selector 26 selectively connects the output terminal P of the monitoring signal generating circuit IMG to the output node N of the sensing signal generating circuit 20 or the analog current circuit 22 according to the second control signal LS.

[0124] When the pulse width modulation signal PWM is at a low level (L), the second control signal LS is at a high level (H), and the selector 26 selects the current sensing signal CS provided by the sensing signal generating circuit 20 as the current monitoring signal IMON output; when the pulse width modulation signal PWM is at a high level (H) or the third state, the second control signal LS is at a low level (L), and the selector 26 selects the analog current signal IMON_EMU provided by the analog current circuit 22 as the current monitoring signal IMON output.

[0125] Another embodiment of the present invention is a method for generating a monitoring signal of an intelligent output stage. In this embodiment, the method for generating a monitoring signal of an intelligent output stage is used to provide a current monitoring signal related to an output current provided by the intelligent output stage.

[0126] Please refer to Figure 7 . Figure 7 This is a flow chart of the monitoring signal generation method of the intelligent output stage in this embodiment. Figure 7 As shown, the monitoring signal generation method of the intelligent output stage includes the following steps:

[0127] Step S10: determining whether the indication signal indicates that multiple power switches of the intelligent output stage are all turned off;

[0128] Step S12: If the determination result of step S10 is yes, determine whether the analog current signal is equal to the reference voltage;

[0129] If the judgment result of step S10 is no, re-execute step S10;

[0130] Step S14: if the determination result of step S12 is yes, that is, the analog current signal is equal to the reference voltage, then providing the reference voltage as the current monitoring signal; and

[0131] Step S16: If the determination result of step S12 is no, that is, the analog current signal is greater than or less than the reference voltage, then the analog current signal is continuously provided as the current monitoring signal.

[0132] In practical applications, the method may first compare the current monitoring signal with the reference voltage to generate a comparison result, and then provide the reference voltage as the current monitoring signal according to the indication signal and the comparison result, but is not limited thereto.

[0133] In one embodiment, the intelligent output stage receives a pulse width modulation signal to provide an output current. The pulse width modulation signal has a first state, a second state, and a third state between the first state and the second state, and the indication signal is synchronized with the third state of the pulse width modulation signal. In the third state of the pulse width modulation signal, when the comparison result indicates that the current monitoring signal is greater than the reference voltage, the ramp signal has a negative slope; when the comparison result indicates that the current monitoring signal is less than the reference voltage, the ramp signal has a positive slope; when the comparison result changes state, a DC reference voltage is provided as an analog signal.

[0134] Compared to the prior art, even when the pulse width modulation signal received by the intelligent output stage is a tri-state signal, the monitoring signal generating circuit and method of the intelligent output stage of the present invention can still provide a current monitoring signal (I MON) reflecting the slope of the output current without directly switching the current monitoring signal to a reference voltage, so that the over-current protection (OCP) mechanism can still operate normally.

Claims

1. A monitoring signal generating circuit of an intelligent output stage, characterized in that: The intelligent output stage provides an output current, the monitoring signal generating circuit provides a current monitoring signal related to the output current, and the monitoring signal generating circuit includes: an analog current circuit, receiving a reference voltage and providing an analog current signal or the reference voltage as the current monitoring signal; and A control circuit is coupled to the analog current circuit and receives the reference voltage, the current monitoring signal and the indication signal respectively. Wherein, during the period when the indication signal indicates that multiple power switches of the intelligent output stage are all turned off, the control circuit controls the analog current circuit to provide the analog current signal or the reference voltage as the current monitoring signal according to the current monitoring signal and the reference voltage.

2. The monitoring signal generating circuit according to claim 1, characterized in that: If the current monitoring signal is equal to the reference voltage, the control circuit controls the analog current circuit to provide the reference voltage as the current monitoring signal.

3. The monitoring signal generating circuit according to claim 1, characterized in that: The analog current circuit comprises: a ramp signal generating circuit coupled to an output node of the analog current circuit, for providing a ramp signal as the analog current signal during a period in which the intelligent output stage provides the output current; and A switch, one end of which is coupled to the output node and the other end of which receives the reference voltage; Wherein, during the period when the indication signal indicates that the multiple power switches of the intelligent output stage are all turned off, when the current monitoring signal is not equal to the reference voltage, the switching switch is turned off so that the ramp signal generating circuit continues to provide the ramp signal; when the current monitoring signal is equal to the reference voltage, the switching switch is turned on so that the analog current circuit provides the reference voltage as the current monitoring signal.

4. The monitoring signal generating circuit as claimed in claim 3, characterized in that: When the current monitoring signal is greater than the reference voltage, the ramp signal has a negative slope.

5. The monitoring signal generating circuit as claimed in claim 3, characterized in that: When the current monitoring signal is less than the reference voltage, the ramp signal has a positive slope.

6. The monitoring signal generating circuit according to claim 1, characterized in that: The monitoring signal generating circuit also includes: A sensing signal generating circuit, configured to generate a current sensing signal according to the output current or a switch voltage received from the intelligent output stage; and The selector is respectively coupled to the sensing signal generating circuit, the output node of the analog current circuit and the output end of the monitoring signal generating circuit, and is used to selectively connect the output end of the monitoring signal generating circuit to the sensing signal generating circuit or the output node of the analog current circuit according to the pulse width modulation signal.

7. The monitoring signal generating circuit according to claim 1, characterized in that: The intelligent output stage includes a driver, a monitoring signal generating circuit and an output stage. The driver is respectively coupled to an external controller and the output stage to receive a pulse width modulation signal from the controller to control the output stage. The output stage includes the plurality of power switches to provide the output current. The monitoring signal generating circuit is respectively coupled to the driving circuit, the output stage and the controller, and provides the current monitoring signal to the controller according to the pulse width modulation signal. The pulse width modulation signal has a first state, a second state and a third state between the first state and the second state, and the indication signal is synchronized with the third state of the pulse width modulation signal.

8. The monitoring signal generating circuit according to claim 1, characterized in that: The control circuit comprises: a comparison circuit, used for comparing the current monitoring signal with the reference voltage to generate a comparison result; and The logic circuit is respectively coupled to the comparison circuit and the analog current circuit, and is used for generating a switching signal according to the indication signal and the comparison result to control the analog current circuit to provide the reference voltage as the current monitoring signal.

9. The monitoring signal generating circuit according to claim 8, characterized in that: During the period when the indication signal indicates that the multiple power switches of the intelligent output stage are all turned off, when the comparison result changes state, the switching signal controls the analog current circuit to output the reference voltage as the current monitoring signal.

10. A method for generating a monitoring signal of an intelligent output stage, for generating a current monitoring signal related to an output current provided by the intelligent output stage, characterized in that: The monitoring signal generating method comprises the following steps: (a) determining whether the indication signal indicates that the plurality of power switches of the intelligent output stage are all turned off; and (b) If the determination result of step (a) is yes, then selectively providing an analog current signal or the reference voltage as the current monitoring signal according to the current monitoring signal and the reference voltage.

11. The method for generating a monitoring signal of an intelligent output stage according to claim 10, characterized in that: If the current monitoring signal is equal to the reference voltage, step (b) provides the reference voltage as the current monitoring signal.

12. The monitoring signal generating method according to claim 10, characterized in that: If the current monitoring signal is not equal to the reference voltage, step (b) continues to provide a ramp signal as the current monitoring signal.

13. The monitoring signal generating method according to claim 12, characterized in that: Step (b) includes: if the current monitoring signal is greater than the reference voltage, the ramp signal has a negative slope.

14. The monitoring signal generating method according to claim 12, characterized in that: Step (b) includes: if the current monitoring signal is less than the reference voltage, the ramp signal has a positive slope.

15. The monitoring signal generating method according to claim 10, characterized in that: Step (b) comprises: (b1) comparing the current monitoring signal with the reference voltage to generate a comparison result; and (b2) Providing the reference voltage as the current monitoring signal according to the indication signal and the comparison result.

16. The monitoring signal generating method according to claim 15, characterized in that: When the comparison result changes state, step (b2) provides the reference voltage as the current monitoring signal.

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