Semiconductor device and forming method thereof

Abstract

The embodiment of the invention provides a semiconductor device and a forming method, and the semiconductor device comprises a substrate; the semiconductor units are located on the substrate and arranged in the first direction, and each semiconductor unit comprises a first transistor and a second transistor which are sequentially arranged in the second direction; the first transistor at least comprises a first gate structure, an L-shaped first channel and a first source drain electrode; the second transistor at least comprises a second gate structure; the second gate structure is connected with the first source-drain electrode; the first channel is in contact with two adjacent side walls of the first gate structure; the first direction and the second direction intersect and are located in the plane where the substrate is located.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to a semiconductor device and a method for forming the same. Background Art

[0002] Since Indium Gallium Zinc Oxide-Thin Film Transistor (IGZO-TFT) has a very low cut-off current compared to silicon transistors, using Indium Gallium Zinc Oxide-Thin Film Transistor to form a semiconductor device can improve the data retention capability of a storage unit (eg, a dynamic random access memory unit).

[0003] However, in the related art, the capacitor-free dynamic random access memory composed of IGZO transistors has serious gate-induced drain leakage (GIDL), which causes the performance of the dynamic random access memory to gradually degrade. Summary of the invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor device and a method for forming the same.

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor device,

[0006] substrate;

[0007] A semiconductor unit located on the substrate and arranged along a first direction, the semiconductor unit comprising a first transistor and a second transistor arranged in sequence along a second direction; the first transistor at least comprises a first gate structure, an L-shaped first channel and a first source and drain; the second transistor at least comprises a second gate structure; the second gate structure is connected to the first source and drain; the first channel is in contact with two adjacent side walls of the first gate structure;

[0008] The first direction intersects with the second direction and is located in a plane where the substrate is located.

[0009] In some embodiments, the first channel includes a first horizontal channel extending along the first direction and a second horizontal channel extending along the second direction;

[0010] The first source and drain are arranged at one end of the first horizontal channel away from the second horizontal channel; the first transistor also includes a second source and drain arranged at one end of the second horizontal channel away from the first horizontal channel; the semiconductor device also includes a first conductive line; the second source and drain are connected to the first conductive line.

[0011] In some embodiments, the first source and drain extend along the first direction, and the second source and drain extend along the second direction; or,

[0012] The first source and drain include a portion extending along the second direction toward the first horizontal channel, and the second source and drain include a portion extending along the first direction toward the second horizontal channel.

[0013] In some embodiments, the second gate structure includes a second gate conductive layer and a second gate dielectric layer; wherein the second gate conductive layer includes a first portion extending along the first direction and a second portion extending along the second direction; and the second gate dielectric layer is in contact with the first portion;

[0014] The second transistor also includes a second channel in contact with the second gate dielectric layer.

[0015] In some embodiments, the second transistor further includes: a third source-drain electrode and a fourth source-drain electrode located at two ends of the second channel; the semiconductor device further includes a second conductive line and a third conductive line;

[0016] The second conductive line is connected to the third source and drain;

[0017] The third conductive line is connected to the fourth source and drain.

[0018] In some embodiments, the third source and drain are in a straight line or an L-shape; the fourth source and drain are in a straight line.

[0019] In some embodiments, the semiconductor device includes a plurality of semiconductor units, and the plurality of semiconductor units are arranged in an array along the first direction and the third direction;

[0020] The first gate structures of the semiconductor units sequentially arranged along the third direction are connected to each other, and the third conductive lines of the semiconductor units sequentially arranged along the third direction are connected to each other;

[0021] The third direction intersects with the plane where the substrate is located.

[0022] In some embodiments, the first conductive line and the second conductive line both extend along the first direction;

[0023] The first conductive lines of the semiconductor units sequentially arranged along the first direction are connected to each other;

[0024] The second conductive lines of the semiconductor units sequentially arranged along the first direction are connected to each other;

[0025] A first step structure is formed between the plurality of first conductive lines arranged along the third direction;

[0026] A second step structure is formed between the plurality of second conductive lines arranged along the third direction.

[0027] In some embodiments, the first channel and the second channel material include an oxide semiconductor.

[0028] In some embodiments, further comprising: an isolation structure;

[0029] The isolation structure is located between the first transistor and the second transistor in each of the semiconductor units.

[0030] In a second aspect, the present disclosure provides a method for forming a semiconductor device.

[0031] providing a substrate;

[0032] A semiconductor unit arranged along a first direction is formed on the surface of the substrate; the semiconductor unit includes a first transistor and a second transistor arranged in sequence along a second direction; the first transistor includes at least a first gate structure, an L-shaped first channel and a first source and drain; the second transistor includes at least a second gate structure; the second gate structure is connected to the first source and drain; the first channel is in contact with two adjacent side walls of the first gate structure;

[0033] The first direction intersects with the second direction and is located in a plane where the substrate is located.

[0034] In some embodiments, there are a plurality of semiconductor units, and the plurality of semiconductor units are arranged in an array along the first direction and the third direction; the plurality of semiconductor units are formed by the following steps:

[0035] forming a stacking structure on the surface of the substrate;

[0036] Patterning the stacked structure to form a plurality of active regions arranged at intervals; the active regions include a first region, a second region, a third region and a fourth region arranged in sequence along the second direction;

[0037] The first transistor is formed in the second region; the first transistor further includes a second source and drain;

[0038] The second transistor is formed in the second region and the third region; the second transistor further includes a second channel, a third source and drain, and a fourth source and drain;

[0039] A first conductive line is formed in the first region, and a second conductive line is formed in the fourth region; the first conductive line is connected to the second source and drain; the second conductive line extends into the third region and is connected to the third source and drain;

[0040] A third conductive line is formed in the third region; the third conductive line is connected to the fourth source and drain.

[0041] In some embodiments, the second region includes a first sub-region and a second sub-region sequentially arranged along the second direction; wherein the first sub-region is connected to the first region; and forming the first transistor in the second region includes:

[0042] Etching the first sub-region to form a first groove penetrating the stacked structure and extending along the third direction;

[0043] forming a first semiconductor layer on an inner wall of the first trench; the material of the first semiconductor layer includes an oxide semiconductor;

[0044] forming a first gate structure on a surface of a portion of the first semiconductor layer;

[0045] Among them, the L-shaped part of the first gate structure connected to the first semiconductor layer constitutes the first channel; the first channel includes a first horizontal channel extending along the first direction and a second horizontal channel extending along the second direction; the part of the remaining first semiconductor layer connected to the first horizontal channel constitutes the first source and drain, and the part connected to the second horizontal channel constitutes the second source and drain.

[0046] In some embodiments, forming the second transistor in the second region and the third region includes:

[0047] Etching the second region to expose the first source and drain, and the sidewall of the third region, to form an L-shaped second trench extending along the third direction;

[0048] forming a second gate conductive layer in the second trench; the second gate conductive layer comprising a first portion extending along the first direction and a second portion extending along the second direction;

[0049] Etching the third region to expose the first portion and form a third groove extending along the third direction;

[0050] Forming a second gate dielectric layer on the surface of the first portion; wherein the second gate dielectric layer and the second gate conductive layer form a second gate structure;

[0051] A second semiconductor layer is formed on the sidewall of the third trench having the second gate dielectric layer; a portion of the second semiconductor layer in contact with the second gate dielectric layer constitutes the second channel, and the remaining second semiconductor layer located at both ends of the second channel along the first direction respectively constitutes the third source and drain and the fourth source and drain; a material of the second semiconductor layer includes an oxide semiconductor.

[0052] In some embodiments, the stack structure includes a first sacrificial layer and a second sacrificial layer that are cyclically and alternately stacked;

[0053] After forming the first gate structure, the method further includes: removing the first channel located on the sidewall of the first sacrificial layer in the second region;

[0054] After forming the second gate conductive layer, the method further includes: removing the second gate conductive layer located on the side wall of the first sacrificial layer in the second region.

[0055] In some embodiments, the method further comprises:

[0056] Etching the second sub-region to form a fourth trench extending along a third direction;

[0057] Through the fourth trench, removing the exposed first sacrificial layer and the second trench in contact with the sidewall of the first sacrificial layer, to form a fifth trench including the fourth trench;

[0058] An isolation structure is formed in the fifth trench.

[0059] In some embodiments, the method further comprises:

[0060] Laterally etching and removing the first sacrificial layer, the second source and drain electrode contacting the first sacrificial layer, and the third source and drain electrode contacting the first sacrificial layer in the first region and the fourth region to form a sixth trench;

[0061] A spacer layer is formed in the sixth trench.

[0062] In some embodiments, forming a third conductive line in the third region includes:

[0063] Etching the third region to at least expose the fourth source and drain to form a seventh trench extending along the third direction;

[0064] The third conductive line is formed in the seventh trench.

[0065] In some embodiments, forming the first conductive line in the first region, and forming the second conductive line in the fourth region, comprises:

[0066] removing the second sacrificial layer in the first region and the fourth region to form an eighth trench and a ninth trench respectively;

[0067] The first conductive line and the second conductive line are formed in the eighth trench and the ninth trench, respectively.

[0068] The embodiment of the present disclosure provides a semiconductor device and a method for forming the same, wherein the semiconductor device comprises: a substrate; a semiconductor unit located on the substrate and arranged along a first direction; the semiconductor unit comprises a first transistor and a second transistor arranged in sequence along a second direction; the first transistor comprises at least a first gate structure, an L-shaped first channel and a first source and drain; the second transistor comprises at least a second gate structure; the second gate structure is connected to the first source and drain; the first channel contacts two adjacent side walls of the first gate structure. Since the first channel of the first transistor in the embodiment of the present disclosure is L-shaped, an isolation structure can be provided between the first gate structure of the first transistor and the second gate structure of the second transistor, thereby reducing the GIDL of the semiconductor device and improving the performance of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0069] In the accompanying drawings (which are not necessarily drawn to scale), like reference numerals may describe similar components in different views. Like reference numerals with different letter suffixes may represent different examples of similar components. The accompanying drawings generally illustrate various embodiments discussed herein by way of example and not limitation.

[0070] Figure 1 To Figure 8 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present disclosure;

[0071] Fig. 9 A schematic diagram of the structure of another semiconductor device provided by an embodiment of the present disclosure;

[0072] Fig.10 A schematic flow chart of a method for forming a semiconductor device provided in an embodiment of the present disclosure;

[0073] Figures 11 to 45 Schematic diagram of various structures in the process of forming a semiconductor device provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0074] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0075] In the following description, a large number of details are given to provide a more thorough understanding of the present disclosure. However, it is obvious to those skilled in the art that the present disclosure can be implemented without one or more of these details. In other examples, in order to avoid confusion with the present disclosure, some technical features known in the art are not described; that is, all features of actual embodiments are not described here, and well-known functions and structures are not described in detail.

[0076] In the drawings, the sizes of layers, regions, elements and their relative sizes may be exaggerated for clarity. Like reference numerals denote like elements throughout.

[0077] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "directly adjacent to ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Therefore, without departing from the teachings of the present disclosure, the first element, component, region, layer or part discussed below can be represented as the second element, component, region, layer or part. And when the second element, component, region, layer or part is discussed, it does not indicate that the present disclosure necessarily has the first element, component, region, layer or part.

[0078] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be a limitation of the present disclosure. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0079] At present, 3D DRAM is mostly formed based on the super lattice process of silicon channel epitaxy (EPI). However, during the epitaxial stacking process, defects such as cracks will be generated due to lattice mismatch and stress of the film itself. Due to the excellent anti-leakage characteristics of IGZO material, as well as low cost and relatively simple process, IGZO as a channel material of dynamic random access memory has become the current research focus. IGZO-based dynamic random access memory can avoid defects such as cracks caused by lattice mismatch and stress of the film itself during the epitaxial stacking process.

[0080] However, the gate-induced drain leakage current in the dynamic random access memory using IGZO as the channel material is serious, resulting in performance degradation of the dynamic random access memory.

[0081] Based on this, the embodiment of the present disclosure provides a semiconductor device and a method for forming the same, the semiconductor device comprising: a substrate; a semiconductor unit located on the substrate and arranged along a first direction; the semiconductor unit comprises a first transistor and a second transistor arranged in sequence along a second direction; the first transistor comprises at least a first gate structure, an L-shaped first channel and a first source and drain; the second transistor comprises at least a second gate structure; the second gate structure is connected to the first source and drain; the first channel is in contact with two adjacent side walls of the first gate structure. Since the first channel of the first transistor in the embodiment of the present disclosure is L-shaped, an isolation structure can be provided between the first gate structure of the first transistor and the second gate structure of the second transistor, thereby reducing the GIDL of the semiconductor device and improving the performance of the semiconductor device.

[0082] Hereinafter, the semiconductor device and the method for forming the same in the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0083] Before introducing the embodiments of the present disclosure, the three directions that may be used in the following embodiments to describe the three-dimensional structure are defined. Taking the Cartesian coordinate system as an example, the three directions may include the X-axis, Y-axis and Z-axis directions. The substrate may include a top surface on the front side and a bottom surface on the back side opposite to the front side; ignoring the flatness of the top surface and the bottom surface, the direction intersecting (e.g., perpendicular) with the top surface and the bottom surface of the substrate is defined as the third direction. In the directions of the top surface and the bottom surface of the substrate (i.e., the plane where the substrate is located), two directions intersecting (e.g., perpendicular to each other) are defined. For example, the arrangement direction of the first transistor and the second transistor may be defined as the second direction, and the plane direction of the substrate may be determined based on the first direction and the second direction. In the embodiments of the present disclosure, the first direction, the second direction and the third direction may be perpendicular to each other in pairs. In other embodiments, the first direction, the second direction and the third direction may not be perpendicular. In the embodiments of the present disclosure, the first direction is defined as the X-axis direction, the second direction is defined as the Y-axis direction, and the third direction is defined as the Z-axis direction.

[0084] The present disclosure provides a semiconductor device 100. Figures 1 to 8 A schematic diagram of the structure of a semiconductor device 100 provided in an embodiment of the present disclosure is shown in FIG. Figures 1 to 8 As shown, the semiconductor device 100 includes:

[0085] a substrate (not shown);

[0086] A semiconductor unit located on a substrate and arranged along the X-axis direction; the semiconductor unit includes a first transistor and a second transistor arranged in sequence along the Y-axis direction; the first transistor at least includes a first gate structure 21, an L-shaped first channel 22 and a first source and drain 23; the second transistor at least includes a second gate structure 31; the second gate structure 31 is connected to the first source and drain 23; the first channel 22 is in contact with two adjacent side walls of the first gate structure 21.

[0087] In the embodiments of the present disclosure, the substrate may be a silicon substrate, and the substrate may also include other semiconductor elements, such as germanium (Ge), or include semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or include other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and / or gallium indium arsenide phosphide (GaInAsP) or a combination thereof.

[0088] It should be noted that, since the semiconductor unit includes two transistors, the semiconductor unit in the embodiment of the present disclosure may be a 2T0C DRAM unit.

[0089] It should also be noted that the first transistor in the embodiment of the present disclosure can be an IGZO thin-film transistor, or an ordinary silicon-based transistor or other types of transistors; the second transistor can be an IGZO thin-film transistor, or an ordinary silicon-based transistor or other types of transistors.

[0090] It should be noted that Figure 1 is a schematic diagram of a three-dimensional structure of a semiconductor device 100, Figures 2 to 8 is a top view of the semiconductor device 100, wherein: Figure 2 for Figure 1 Top view of the corresponding structure.

[0091] In some embodiments, please see Figures 1 to 8 The material of the first channel 22 includes an oxide semiconductor, such as indium gallium zinc oxide, indium tin oxide (ITO), tungsten tin oxide (IWO), zinc oxide, indium oxide, titanium oxide, tin oxide, etc. Due to the inherent characteristics of oxide semiconductors (low electron mobility), when the first channel uses an oxide semiconductor, the leakage current of the first transistor can be reduced, thereby reducing the speed of charge loss on the semiconductor unit, extending the data retention time of the semiconductor device, and reducing the power consumption of the semiconductor device.

[0092] In some embodiments, please see Figures 1 to 8 The first gate structure 21 includes a first gate dielectric layer 211 and a first gate conductive layer 212 located on the surface of the first gate dielectric layer 211. The material of the first gate dielectric layer 211 may be silicon oxide or other suitable materials; the material of the first gate conductive layer 212 may be any material with good conductivity, such as titanium (Ti), titanium nitride (TiN), tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), copper (Cu) or any combination thereof.

[0093] It should be noted that the first gate conductive layer 212 can be used as a write word line (WWL) of a DRAM memory cell.

[0094] In some embodiments, please see Figures 1 to 8 The second gate structure 31 includes a second gate conductive layer 311 and a second gate dielectric layer 312 , and the materials of the second gate dielectric layer 312 and the second gate conductive layer 311 are similar to those of the first gate dielectric layer 211 and the first gate conductive layer 212 , respectively.

[0095] It should be noted that the second gate structure 31 is connected to the first source and drain 23 means that the second gate conductive layer 311 in the second gate structure 31 is connected to the first source and drain 23 .

[0096] In some embodiments, see Figures 1 to 8 The first channel 22 contacts two adjacent side walls of the first gate structure 21, that is, the first channel 22 is L-shaped. In this way, an isolation structure can be provided between the first gate structure of the first transistor and the second gate structure of the second transistor, thereby reducing the GIDL of the semiconductor device and improving the performance of the semiconductor device.

[0097] In some embodiments, see Figures 1 to 8 The first channel 22 includes a first horizontal channel 221 extending along the X-axis direction and a second horizontal channel 222 extending along the Y-axis direction; the first source and drain 23 are arranged at one end of the first horizontal channel 221 away from the second horizontal channel 222; the first transistor also includes a second source and drain 24 arranged at one end of the second horizontal channel 222 away from the first horizontal channel 221.

[0098] In some embodiments, see Figures 1 to 8 The semiconductor device 100 further includes a first conductive line 41 ; the second source and drain 24 are connected to the first conductive line 41 .

[0099] It should be noted that the first conductive line 41 may be a write bit line (WBL). The material of the first conductive line 41 may include any one of tungsten, cobalt, copper, titanium, platinum, palladium, ruthenium, titanium nitride, and tungsten nitride, or a combination thereof.

[0100] In some embodiments, see Figures 1 to 6 , the first source-drain electrode 23 includes a portion extending along the Y-axis direction toward the first horizontal channel 221, and the second source-drain electrode 24 includes a portion extending along the X-axis direction toward the second horizontal channel 222. In other words, the extension direction of a portion of the first source-drain electrode 23 is consistent with the extension direction of the second horizontal channel 222, and the extension direction of a portion of the second source-drain electrode 24 is consistent with the extension direction of the first horizontal channel 221.

[0101] In some embodiments, the first source and drain 23 may further include a portion extending along the X axis, and the second source and drain 24 may further include a portion extending along the Y axis. That is, the first source and drain 23 and the second source and drain 24 may both be L-shaped. The first source and drain 23, the first channel 22, and the second source and drain 24 are sequentially connected to form an unsealed ring structure.

[0102] In other embodiments, please continue to refer to Figure 7 and Figure 8, the first source and drain 23 extends along the X-axis direction, and the second source and drain 24 extends along the Y-axis direction. In other words, the extension direction of the first source and drain 23 is consistent with the extension direction of the first horizontal channel 221, and the extension direction of the second source and drain 24 is consistent with the extension direction of the second horizontal channel 222. The first source and drain 23, the first channel 22, and the second source and drain 24 are connected in sequence to form an L-shaped structure.

[0103] In some embodiments, see Figures 1 to 8 The second gate conductive layer 311 includes a first portion b extending along the X-axis direction and a second portion a extending along the Y-axis direction; the second gate dielectric layer 312 is in contact with the first portion b.

[0104] It should be noted that the second part a can be used as a storage node (Storage Node, SN) of a DRAM storage unit.

[0105] In some embodiments, see Figures 1 to 8 The second transistor further includes a second channel 32 in contact with the second gate dielectric layer 312. The material of the second channel 32 includes an oxide semiconductor, such as IGZO.

[0106] In some embodiments, see Figures 1 to 8 The second transistor also includes: a third source-drain 33 and a fourth source-drain 34 located at both ends of the second channel 32; the semiconductor device 100 also includes a second conductive line 42 and a third conductive line 43; the second conductive line 42 is connected to the third source-drain 33; the third conductive line 43 is connected to the fourth source-drain 34.

[0107] It should be noted that the second conductive line 42 can be used as a read bit line (Read BitLine, RBL) of the DRAM storage unit, and the third conductive line 43 can be used as a read word line (Read Word Line, RWL) of the DRAM storage unit.

[0108] In some embodiments, see Figures 1 to 3 , Figure 8 The third source and drain electrode 33 is L-shaped, that is, the third source and drain electrode 33 includes a portion extending along the X axis and a portion extending along the Y axis. The third source and drain electrode 33, the second channel 32 and the fourth source and drain electrode 34 are connected in sequence to form an unsealed ring structure.

[0109] In some embodiments, see Figures 4 to 7 , the third source and drain electrode 33 is linear; that is, the extension direction of the third source and drain electrode 33 is consistent with the extension direction of the second channel 32 (such as Figure 6 and Figure 7Alternatively, the extension direction of the third source and drain 33 is perpendicular to the extension direction of the second channel 32 (as shown in Figure 4 and Figure 5 (shown)

[0110] In some embodiments, see Figures 1 to 8 , the fourth source-drain electrode 34 is linear; that is, the extension direction of the fourth source-drain electrode 34 is consistent with the extension direction of the second channel 32 (eg Figure 3 , Figures 5 to 7 Alternatively, the extension direction of the fourth source and drain 34 is perpendicular to the extension direction of the second channel 32 (as shown in Figure 1 , Figure 2 , Figure 4 and Figure 8 shown).

[0111] Fig. 9 A schematic diagram of the structure of another semiconductor device provided in an embodiment of the present disclosure is shown in FIG. Fig. 9 As shown, the semiconductor device 100 includes a plurality of semiconductor units, and the plurality of semiconductor units are arranged in an array along the X-axis direction and the Z-axis direction.

[0112] In some embodiments, see Fig. 9 , the first gate structures 21 of the semiconductor units sequentially arranged along the Z-axis direction are connected to each other; specifically, the first gate conductive layers 212 in the first gate structures 21 of the semiconductor units sequentially arranged along the Z-axis direction are connected to each other.

[0113] In some embodiments, see Fig. 9 The third conductive lines 43 of the semiconductor units arranged in sequence along the Z-axis direction are connected to each other.

[0114] In some embodiments, see Fig. 9 , the first conductive lines 41 and the second conductive lines 42 both extend along the X-axis direction; the first conductive lines 41 of the semiconductor units arranged in sequence along the X-axis direction are connected to each other; the second conductive lines 42 of the semiconductor units arranged in sequence along the X-axis direction are connected to each other.

[0115] In some embodiments, a first step structure (not shown) is formed between the plurality of first conductive lines 41 arranged along the Z-axis direction; a second step structure (not shown) is formed between the plurality of second conductive lines 42 arranged along the Z-axis direction. In this way, the electrical signal of each layer of semiconductor units can be led out through the first step structure and the second step structure.

[0116] In some embodiments, see Fig. 9 The semiconductor device 100 further includes an isolation structure 80 , wherein the isolation structure 80 is located between the first transistor and the second transistor in each semiconductor unit.

[0117] It should be noted that the material of the isolation structure 80 may be a low-K material, which can reduce the coupling effect between the first transistor and the second transistor, that is, reduce the parasitic capacitance between the first gate structure and the second gate structure, thereby improving the performance of the semiconductor device. Low dielectric constant materials include but are not limited to silicon oxide, silicon nitride, silicon carbide, silicon carbide nitride or silicon oxynitride.

[0118] In another embodiment of the present disclosure, Fig.10 A schematic diagram of a process for forming a semiconductor device according to an embodiment of the present disclosure. Figures 11 to 45 The schematic diagrams of various structures in the process of forming the semiconductor device provided in the embodiment of the present disclosure are as follows. Figure 10 to Figure 45 The formation process of the semiconductor device is described in detail.

[0119] like Fig.10 As shown, the method for forming a semiconductor device includes the following steps S11 and S12.

[0120] First, refer to Fig.10 and Fig.11 , perform step S11 to provide a substrate 50.

[0121] Here, the substrate 50 may be a silicon substrate, or may include other semiconductor elements, such as germanium, or semiconductor compounds, such as silicon carbide, gallium arsenide, or other semiconductor alloys, such as silicon germanium, gallium arsenic phosphide.

[0122] Next, please refer to Figure 10 to Figure 45 , execute step S12 to form a semiconductor unit arranged along the first direction on the surface of the substrate 50; the semiconductor unit includes a first transistor and a second transistor arranged in sequence along the second direction; the first transistor at least includes a first gate structure 21, an L-shaped first channel 22 and a first source and drain 23; the second transistor at least includes a second gate structure 31; the second gate structure 31 is connected to the first source and drain 23; the first channel 22 is in contact with two adjacent side walls of the first gate structure 21.

[0123] It should be noted that the semiconductor unit in the embodiment of the present disclosure may be one or more. When there are more than one semiconductor unit, the more than one semiconductor unit may form a two-dimensional structure or a three-dimensional structure. For example, the more than one semiconductor unit may be arranged in sequence along the X-axis direction, or the more than one semiconductor unit may be arranged in an array along the X-axis direction and the Z-axis direction. Figure 1 and Figure 2 Taking the specific structure of the semiconductor unit shown as an example, the specific formation process of the semiconductor device composed of multiple semiconductor units is explained.

[0124] In some embodiments, a plurality of semiconductor units may be formed by following steps S121 to S126:

[0125] Step S121, forming a stacking structure 40 on the surface of the substrate 50;

[0126] In some embodiments, the stacked structure 40 includes a first sacrificial layer 401 and a second sacrificial layer 402 that are cyclically and alternately stacked. During implementation, the first sacrificial material and the second sacrificial material are sequentially deposited on the surface of the substrate 50 to form the first sacrificial layer 401 and the second sacrificial layer 402. Under the same etching conditions, the first sacrificial material is easier to remove than the second sacrificial material. The first sacrificial material may be, for example, silicon oxide, and the second sacrificial material may be, for example, polysilicon.

[0127] The first sacrificial layer 401 and the second sacrificial layer 402 may be formed by any of the following deposition processes: a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process or other suitable processes.

[0128] Step S122, patterning the stacked structure 40 to form a plurality of active regions arranged at intervals; the active regions include a first region 501, a second region 502, a third region 503 and a fourth region 504 arranged in sequence along the second direction;

[0129] During implementation, for example, a mask layer 51 and a photoresist layer (not shown) having a preset pattern may be formed on the surface of the stacked structure 40, and the mask layer 51 and the stacked structure 40 may be etched through the photoresist layer until the surface of the substrate 50 is exposed, thereby forming a plurality of active regions arranged at intervals, and a first isolation trench 61 and a second isolation trench 62 (such as the first isolation trench 61 and the second isolation trench 62) located at both ends of the active region along the X-axis direction. Fig.12 The active region includes a first region 501, a second region 502, a third region 503 and a fourth region 504 arranged in sequence along the Y-axis direction (as shown in FIG. Fig.12 shown).

[0130] Next, an isolation material is deposited in the first isolation trench 61 and the second isolation trench 62 to form the following structures: Fig.13 The first spacer structure 63 and the second spacer structure 64 are shown. Here, the isolation material may be a low-K material or silicon oxide.

[0131] In some embodiments, the second region 502 includes a first sub-region 5021 and a second sub-region 5022 which are sequentially arranged along the Y-axis direction.

[0132] Step S123, forming a first transistor in the second region 502; the first transistor further includes a second source and drain 24;

[0133] In some embodiments, step S123 may be formed by the following steps:

[0134] Step S1231, etching the first sub-region 5021 to form a first trench 65 penetrating the stacked structure 40 and extending along the Z-axis direction;

[0135] During implementation, for example, a dry etching process (such as a plasma etching process) may be used to etch a portion of the first sub-region 5021 to form a Fig.14 The first trench 65 shown extends along the Z-axis direction. The first trench 65 exposes the surface of the substrate 50.

[0136] Step S1232, forming a first initial semiconductor layer 66a on the inner wall of the first trench 65; the material of the first initial semiconductor layer 66a includes an oxide semiconductor;

[0137] During implementation, first, an oxide semiconductor material may be deposited on the inner wall of the first trench 65 to form a Fig.15 The first initial semiconductor layer 66a shown in FIG. 1; the oxide semiconductor material may be, for example, IGZO. Next, the isolation material is continuously deposited in the remaining first trench 65 to form a Fig.16 Finally, etching a portion of the initial first semiconductor layer 66a, a portion of the third spacer structure 67, and a portion of the stacked structure 40 adjacent to the etched portion of the first initial semiconductor layer 66a to form a Fig.16 The tenth trench 68 and the first semiconductor layer 66 are shown.

[0138] Step S1233, forming a first gate structure 21 on a surface of a portion of the first semiconductor layer 66;

[0139] During implementation, first, the isolation material is continuously deposited in the tenth trench 68 to form a Fig.17 Secondly, the third spacing structure 67 located inside the first semiconductor layer 66 is etched to form a third spacing structure 67 as shown in FIG. Fig.18 Finally, a first gate dielectric material and a first gate conductive material are sequentially deposited on the sidewalls of the eleventh trench 69 to form a first gate dielectric layer 211 and a first gate conductive layer 212; the first gate dielectric layer 211 and the first gate conductive layer 212 constitute a first gate structure 21. The first gate dielectric material may be silicon oxide or other suitable materials, and the first gate conductive material may be any material with good conductive properties, such as any one of titanium, titanium nitride, tungsten nitride, tungsten, cobalt, platinum, palladium, ruthenium, and copper, or a combination thereof.

[0140] It should be noted that the L-shaped portion of the first gate structure 21 connected to the first semiconductor layer 66 constitutes the first channel 22 of the first transistor. The first channel 22 is in contact with two adjacent side walls of the first gate structure 21, that is, the first channel 22 is L-shaped. In this way, an isolation structure can be provided between the first gate structure of the first transistor and the second gate structure of the second transistor, thereby reducing the GIDL of the semiconductor device and improving the performance of the semiconductor device.

[0141] In some embodiments, please see Fig.19 The first channel 22 includes a first horizontal channel 221 extending along the X-axis direction and a second horizontal channel 222 extending along the Y-axis direction. The remaining portion of the first semiconductor layer 66 connected to the first horizontal channel 221 constitutes the first source and drain 23, and the portion connected to the second horizontal channel 222 constitutes the second source and drain 24.

[0142] In the embodiment of the present disclosure, the first source drain 23 and the second source drain 24 are L-shaped, that is, the first source drain 23 includes a portion extending along the Y-axis direction toward the first horizontal channel 221 and a portion extending along the first horizontal channel 221, and the second source drain 24 includes a portion extending along the X-axis direction toward the second horizontal channel 222 and a portion extending along the second horizontal channel 222.

[0143] In some embodiments, after forming the first gate structure 21 , the method further includes: removing the first channel 22 located on the sidewall of the first sacrificial layer 401 in the second region 502 .

[0144] During implementation, first, the mask layer 51 between the second region 502 and the second spacing structure 64 and the stacked structure 40 thereunder are etched to form a Fig. 20 and Fig.21 The twelfth groove 70 shown in FIG. 1 exposes the surface of the substrate 50 and a portion of the first sacrificial layer 401 and the sidewalls of the second sacrificial layer 402; next, the exposed first sacrificial layer 401 and a portion of the first channel 22 in contact with the first sacrificial layer 401 are removed through the twelfth groove 70 to form a substrate 50 as shown in FIG. Fig. 22 Finally, the thirteenth trench 70a and the twelfth trench 70 are filled with an isolation material to form a Fig.23 and Fig.24 The structure shown.

[0145] It should be noted that Fig.21 and Fig. 22 for Fig. 20 Cross-sectional view along a-a', Fig.24 for Fig.23Cross-sectional view along aa'. By etching away a portion of the first channel 22 and filling with isolation material, each layer of first transistors arranged along the Z-axis direction can be isolated.

[0146] Step S124, forming a second transistor in the second region 502 and the third region 503; the second transistor further includes a second channel 32, a third source and drain 33 and a fourth source and drain 34;

[0147] In some embodiments, step S124 may be formed by the following steps:

[0148] Step S1241, etching the second region 502 to expose the first source and drain 23 and the sidewall of the third region 503, forming an L-shaped second trench 71 extending along the Z-axis direction (eg, Fig.25 shown);

[0149] Step S1242, forming a second gate conductive layer 311 in the second trench 71; the second gate conductive layer 311 includes a first portion b extending along the X-axis direction and a second portion a extending along the Y-axis direction;

[0150] During implementation, a second gate conductive material is deposited in the second trench 71 to form a Fig.26 As shown in the second gate conductive layer 311 , the second gate conductive material and the first gate conductive material may be the same.

[0151] In some embodiments, after forming the second gate conductive layer 311, the method further includes:

[0152] The second gate conductive layer 311 located on the sidewall of the first sacrificial layer 401 in the second region 502 is removed.

[0153] During implementation, the first spacing structure 63 is etched to form a Fig. 27 The fourteenth trench 72 is shown, and the fourteenth trench 72 exposes the surface of the substrate 50 and a portion of the first sacrificial layer 401 and the sidewalls of the second sacrificial layer 402; next, the exposed first sacrificial layer 401, the portion of the second gate conductive layer 311 in contact with the first sacrificial layer 401 and the portion of the first source and drain 23 connected thereto are removed through the fourteenth trench 72 to form a Fig.28 Finally, please refer to the fifteenth trench 73 shown in FIG. 1 , and fill the fifteenth trench 73 with an isolation material to form a Fig.29 and Fig.30 The structure shown.

[0154] It should be noted that Fig.28 for Fig. 27 Cross-sectional view along a-a', Fig.30 for Fig.29Cross-sectional view along aa'. By etching away a portion of the first source and drain electrodes 23 and filling with isolation materials, each layer of first transistors arranged along the Z-axis direction can be isolated.

[0155] Step S1243, etching the third region 503 to expose the first portion b, forming a third trench 74 extending along the Z-axis direction;

[0156] During implementation, for example, a plasma etching process may be used to etch the third region 503 along the Z-axis direction to form a Fig.31 The third trench 74 is shown, and the third trench exposes the surface of the substrate 50 and the sidewall of the first portion b.

[0157] Step S1244, forming a second gate dielectric layer 312 on the surface of the first portion b; wherein the second gate dielectric layer 312 and the second gate conductive layer 311 form a second gate structure 31;

[0158] During implementation, a second gate dielectric material is deposited on the surface of the first portion b to form a gate dielectric material as shown in FIG. Fig.32 The second gate dielectric layer 312 is shown. The second gate dielectric material may be silicon oxide.

[0159] Step S1245, forming a second semiconductor layer 75 on the sidewall of the third trench 74 having the second gate dielectric layer 312;

[0160] During implementation, first, an oxide semiconductor material is deposited on the sidewall of the third trench 74 having the second gate dielectric layer 312 to form a Fig.32 The second initial semiconductor layer 75a shown in FIG. 1 may be made of an oxide semiconductor material such as IGZO. Next, an isolation material is deposited in the remaining third trench 74 to form a Fig.32 Finally, etching a portion of the initial second initial semiconductor layer 75a, a portion of the fourth spacer layer 76, and a portion of the stacked structure 40 adjacent to the etched portion of the second initial semiconductor layer 75a to form a Fig.38 Finally, the isolation material is continuously deposited in the sixteenth trench 77 to form a Fig.39 The structure shown.

[0161] It should be noted that the portion of the second semiconductor layer 75 in contact with the second gate dielectric layer 312 constitutes the second channel 32 , and the remaining second semiconductor layer 75 located at both ends of the second channel 32 along the first direction constitutes the third source and drain 33 and the fourth source and drain 34 , respectively.

[0162] In some embodiments, after forming the fourth spacer layer 76 and before etching the second initial semiconductor layer 75a to form the second semiconductor layer 75, the method further includes:

[0163] The second sub-region 5022 is etched to form Fig.33 and Fig.34 The fourth groove 78 extending along the Z-axis direction is shown; through the fourth groove 78, the exposed first sacrificial layer 401 and the second channel 32 in contact with the sidewall of the first sacrificial layer 401 are removed to form a Fig.35 The fifth trench 79 shown includes the fourth trench 78; an isolation material is deposited in the fifth trench 79 to form a Fig.36 and Fig.37 An isolation structure 80 is shown.

[0164] It should be noted that Fig.34 and Fig.35 for Fig.33 Cross-sectional view along b-b', Fig.37 for Fig.36 Cross-sectional view along line bb'. By etching away a portion of the second channel 32 and filling with isolation material, each layer of second transistors arranged along the Z-axis direction can be isolated.

[0165] It should also be noted that the material of the isolation structure 80 can be a low-K material. The isolation structure 80 is located between the first gate structure of the first transistor and the second gate structure of the second transistor, which can reduce the parasitic capacitance between the first gate structure and the second gate structure, thereby reducing the coupling effect between the first transistor and the second transistor, and improving the performance of the semiconductor device.

[0166] In some embodiments, the method for forming a semiconductor device further includes:

[0167] The first sacrificial layer 401, the second source / drain electrode 24 in contact with the first sacrificial layer 401, and the third source / drain electrode 33 in contact with the first sacrificial layer 401 in the first region 501 and the fourth region 504 are removed by lateral etching to form Fig.39 and Fig.40 The sixth groove 81 shown in FIG. 81 is formed as follows: Fig.41 The spacer layer 403 is shown. The material of the spacer layer 403 may be silicon oxide.

[0168] During implementation, wet etching technology can be used to laterally etch and remove the first sacrificial layer 401 in the first region 501 and the fourth region 504, as well as part of the second source and drain 24 and part of the third source and drain 33, and form a spacer layer 403 between adjacent first transistors along the Z-axis direction.

[0169] It should be noted that Fig.40 for Fig.39Cross-sectional view along b-b'. By etching away part of the second source and drain 24 and filling with isolation material, each layer of first transistors arranged along the Z-axis direction can be isolated; by etching away part of the third source and drain 33 and filling with isolation material, each layer of second transistors arranged along the Z-axis direction can be isolated.

[0170] Step S125 , forming a first conductive line 41 in the first region 501 and a second conductive line 42 in the fourth region 504 ; the first conductive line 41 is connected to the second source and drain 24 ; the second conductive line 42 extends into the third region 503 ; the second conductive line 42 is connected to the third source and drain 33 .

[0171] In some embodiments, step S125 includes:

[0172] The second sacrificial layer 402 in the first region 501 and the fourth region 504 is removed to form Fig.42 The eighth groove 82 and the ninth groove 83 are shown; the eighth groove 82 and the ninth groove 83 are respectively formed as follows Fig.43 A first conductive line 41 and a second conductive line 43 are shown.

[0173] During implementation, for example, the second sacrificial layer 402 in the first region 501 and the fourth region 504 can be laterally etched away by wet etching technology to form the eighth trench 82 and the ninth trench 83; then a conductive material is deposited in the eighth trench 82 and the ninth trench 83 to form the first conductive line 41 and the second conductive line 43. Here, the conductive material can be any one of tungsten, cobalt, copper, titanium, platinum, palladium, ruthenium, titanium nitride, and tungsten nitride, or a combination thereof.

[0174] Step S126 , forming a third conductive line 43 in the third region 503 ; the third conductive line 43 is connected to the fourth source and drain 34 .

[0175] During implementation, the third region 503 is etched to expose at least the fourth source and drain 34, forming Fig.44 Next, a conductive material is deposited in the seventh groove 84 to form a seventh groove 84 extending in the Z-axis direction. Fig.45 The third conductive line 43 is shown. The material of the third conductive line 43 is similar to that of the first conductive line 41 .

[0176] It should be noted that the semiconductor device formed by the method for forming a semiconductor device provided in the embodiment of the present disclosure is similar to the semiconductor device in the above-mentioned embodiment. For the technical features not fully disclosed in the embodiment of the present disclosure, please refer to the above-mentioned embodiment for understanding, and no further details will be given here.

[0177] In the method for forming a semiconductor device provided by an embodiment of the present disclosure, since the first channel of the first transistor in the formed semiconductor device is L-shaped, an isolation structure can be set between the first gate structure of the first transistor and the second gate structure of the second transistor, thereby reducing the GIDL of the semiconductor device and improving the performance of the semiconductor device.

[0178] It should also be noted that the above method embodiment only describes Figure 1 and Figure 2 The specific process of forming a semiconductor device by a semiconductor unit shown in FIG. Figures 3 to 8 The formation process of the semiconductor unit and the semiconductor device is basically similar to that of the above embodiment, and will not be described one by one here.

[0179] In the several embodiments provided in the present disclosure, it should be understood that the disclosed structures and methods can be implemented in a non-targeted manner. The structural embodiments described above are only schematic. For example, the division of units is only a logical function division. There may be other division methods in actual implementation, such as: multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. In addition, the components shown or discussed are coupled or directly coupled to each other.

[0180] The features disclosed in several method or structural embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or structural embodiments.

[0181] The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that: include: substrate; A semiconductor unit located on the substrate and arranged along a first direction, the semiconductor unit comprising a first transistor and a second transistor arranged in sequence along a second direction; the first transistor at least comprises a first gate structure, an L-shaped first channel and a first source and drain; the second transistor at least comprises a second gate structure; the second gate structure is connected to the first source and drain; the first channel is in contact with two adjacent side walls of the first gate structure; The first direction intersects with the second direction and is located in a plane where the substrate is located.

2. The semiconductor device according to claim 1, wherein: The first channel includes a first horizontal channel extending along the first direction and a second horizontal channel extending along the second direction; The first source and drain are arranged at one end of the first horizontal channel away from the second horizontal channel; the first transistor also includes a second source and drain arranged at one end of the second horizontal channel away from the first horizontal channel; the semiconductor device also includes a first conductive line; the second source and drain are connected to the first conductive line.

3. The semiconductor device according to claim 2, characterized in that The first source and drain extend along the first direction, and the second source and drain extend along the second direction; or, The first source and drain include a portion extending along the second direction toward the first horizontal channel, and the second source and drain include a portion extending along the first direction toward the second horizontal channel.

4. The semiconductor device according to claim 3, characterized in that The second gate structure comprises a second gate conductive layer and a second gate dielectric layer; wherein the second gate conductive layer comprises a first portion extending along the first direction and a second portion extending along the second direction; the second gate dielectric layer contacts the first portion; The second transistor also includes a second channel in contact with the second gate dielectric layer.

5. The semiconductor device according to claim 4, characterized in that The second transistor further includes: a third source-drain electrode and a fourth source-drain electrode located at two ends of the second channel; the semiconductor device further includes a second conductive line and a third conductive line; The second conductive line is connected to the third source and drain; The third conductive line is connected to the fourth source and drain.

6. The semiconductor device according to claim 5, characterized in that The third source and drain are in a straight line or L-shape; the fourth source and drain are in a straight line.

7. The semiconductor device according to claim 5, characterized in that The semiconductor device comprises a plurality of semiconductor units, and the plurality of semiconductor units are arranged in an array along the first direction and the third direction; The first gate structures of the semiconductor units sequentially arranged along the third direction are connected to each other, and the third conductive lines of the semiconductor units sequentially arranged along the third direction are connected to each other; The third direction intersects with the plane where the substrate is located.

8. The semiconductor device according to claim 7, characterized in that The first conductive line and the second conductive line both extend along the first direction; The first conductive lines of the semiconductor units sequentially arranged along the first direction are connected to each other; The second conductive lines of the semiconductor units sequentially arranged along the first direction are connected to each other; A first step structure is formed between the plurality of first conductive lines arranged along the third direction; A second step structure is formed between the plurality of second conductive lines arranged along the third direction.

9. The semiconductor device according to claim 8, characterized in that The first channel and the second channel material include an oxide semiconductor.

10. The semiconductor device according to claim 7, wherein: Also included: isolation structure; The isolation structure is located between the first transistor and the second transistor in each of the semiconductor units.

11. A method for forming a semiconductor device, characterized in that: The method comprises: providing a substrate; A semiconductor unit arranged along a first direction is formed on the surface of the substrate; the semiconductor unit includes a first transistor and a second transistor arranged in sequence along a second direction; the first transistor includes at least a first gate structure, an L-shaped first channel and a first source and drain; the second transistor includes at least a second gate structure; the second gate structure is connected to the first source and drain; the first channel is in contact with two adjacent side walls of the first gate structure; The first direction intersects with the second direction and is located in a plane where the substrate is located.

12. The method according to claim 11, characterized in that There are a plurality of semiconductor units, and the plurality of semiconductor units are arranged in an array along the first direction and the third direction; the plurality of semiconductor units are formed by the following steps: forming a stacking structure on the surface of the substrate; Patterning the stacked structure to form a plurality of active regions arranged at intervals; the active regions include a first region, a second region, a third region and a fourth region arranged in sequence along the second direction; The first transistor is formed in the second region; the first transistor further includes a second source and drain; The second transistor is formed in the second region and the third region; the second transistor further includes a second channel, a third source and drain, and a fourth source and drain; A first conductive line is formed in the first region, and a second conductive line is formed in the fourth region; the first conductive line is connected to the second source and drain; the second conductive line extends into the third region and is connected to the third source and drain; A third conductive line is formed in the third region; the third conductive line is connected to the fourth source and drain.

13. The method according to claim 12, characterized in that The second region includes a first sub-region and a second sub-region sequentially arranged along the second direction; wherein the first sub-region is connected to the first region; and forming the first transistor in the second region includes: Etching the first sub-region to form a first groove penetrating the stacked structure and extending along the third direction; forming a first semiconductor layer on an inner wall of the first trench; the material of the first semiconductor layer includes an oxide semiconductor; forming a first gate structure on a surface of a portion of the first semiconductor layer; Among them, the L-shaped part of the first gate structure connected to the first semiconductor layer constitutes the first channel; the first channel includes a first horizontal channel extending along the first direction and a second horizontal channel extending along the second direction; the part of the remaining first semiconductor layer connected to the first horizontal channel constitutes the first source and drain, and the part connected to the second horizontal channel constitutes the second source and drain.

14. The method according to claim 13, characterized in that The second transistor is formed in the second region and the third region, comprising: Etching the second region to expose the first source and drain, and the sidewall of the third region, to form an L-shaped second trench extending along the third direction; forming a second gate conductive layer in the second trench; the second gate conductive layer comprising a first portion extending along the first direction and a second portion extending along the second direction; Etching the third region to expose the first portion and form a third groove extending along the third direction; Forming a second gate dielectric layer on the surface of the first portion; wherein the second gate dielectric layer and the second gate conductive layer form a second gate structure; A second semiconductor layer is formed on the sidewall of the third trench having the second gate dielectric layer; a portion of the second semiconductor layer in contact with the second gate dielectric layer constitutes the second channel, and the remaining second semiconductor layer located at both ends of the second channel along the first direction respectively constitutes the third source and drain and the fourth source and drain; a material of the second semiconductor layer includes an oxide semiconductor.

15. The method according to claim 14, characterized in that The stacked structure includes a first sacrificial layer and a second sacrificial layer that are cyclically and alternately stacked; After forming the first gate structure, the method further includes: removing the first channel located on the sidewall of the first sacrificial layer in the second region; After forming the second gate conductive layer, the method further includes: removing the second gate conductive layer located on the side wall of the first sacrificial layer in the second region.

16. The method according to claim 15, characterized in that The method further comprises: Etching the second sub-region to form a fourth trench extending along a third direction; Through the fourth trench, removing the exposed first sacrificial layer and the second trench in contact with the sidewall of the first sacrificial layer, to form a fifth trench including the fourth trench; An isolation structure is formed in the fifth trench.

17. The method according to claim 16, characterized in that The method further comprises: Laterally etching and removing the first sacrificial layer, the second source and drain electrode contacting the first sacrificial layer, and the third source and drain electrode contacting the first sacrificial layer in the first region and the fourth region to form a sixth trench; A spacer layer is formed in the sixth trench.

18. The method according to any one of claims 14 to 17, characterized in that Forming a third conductive line in the third region includes: Etching the third region to at least expose the fourth source and drain to form a seventh trench extending along the third direction; The third conductive line is formed in the seventh trench.

19. The method according to any one of claims 15 to 17, characterized in that The method comprises forming the first conductive line in the first region and forming the second conductive line in the fourth region, comprising: removing the second sacrificial layer in the first region and the fourth region to form an eighth trench and a ninth trench respectively; The first conductive line and the second conductive line are formed in the eighth trench and the ninth trench, respectively.

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