Semiconductor device, manufacturing method thereof, and memory system

Abstract

The invention provides a semiconductor device, a manufacturing method thereof and a storage system, and the method comprises the steps: forming a plurality of channel lines which extend in a first direction and a second direction in a semiconductor layer, and enabling the first direction to intersect with the second direction; a plurality of first grooves and a plurality of second grooves which extend in the first direction and are arranged in the second direction are formed in the semiconductor layer, the first grooves and the second grooves intersect with the channel lines to form a plurality of channel structures, and the size of the first grooves in the second direction is smaller than that of the second grooves in the second direction; conducting layers are formed in the first grooves and the second grooves, part of the conducting layers are removed, the remaining conducting layers in the first grooves form a plurality of conducting shielding structures, and the remaining conducting layers in the second grooves form a plurality of gate lines. The method can simplify the manufacturing process of the semiconductor device.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and a storage system. Background Art

[0002] Dynamic random access memory is an important memory. The storage unit of dynamic random access memory mainly includes a storage capacitor and a transistor connected in series with the storage capacitor. The storage capacitor is used to store data, and the transistor is used to control the storage of data in the storage capacitor.

[0003] Currently, the manufacturing process of dynamic random access memory is complicated, and how to simplify the manufacturing process of dynamic random access memory is a technical problem that needs to be solved. Summary of the invention

[0004] The purpose of the present application is to provide a semiconductor device and a manufacturing method thereof, and a storage system to simplify the manufacturing method of the semiconductor device.

[0005] In a first aspect, the present application provides a method for manufacturing a semiconductor device, the method comprising:

[0006] forming a plurality of channel lines extending along a first direction and a second direction in the semiconductor layer, wherein the first direction intersects with the second direction;

[0007] forming a plurality of first grooves and a plurality of second grooves extending along the first direction and arranged along the second direction in the semiconductor layer, wherein the plurality of first grooves and the plurality of second grooves intersect with the plurality of channel lines to form a plurality of channel structures, and a size of the first groove along the second direction is smaller than a size of the second groove along the second direction; and

[0008] A conductive layer is formed in the first grooves and the second grooves, and a portion of the conductive layer is removed. The remaining conductive layers in the first grooves form a plurality of conductive shielding structures, and the remaining conductive layers in the second grooves form a plurality of gate lines.

[0009] In the method for manufacturing a semiconductor device in some embodiments, forming a plurality of first grooves and a plurality of second grooves extending along the first direction and arranged along the second direction in the semiconductor layer comprises:

[0010] Forming a plurality of first initial grooves and a plurality of second initial grooves in the semiconductor layer, extending along the first direction and a third direction and alternately arranged along the second direction, wherein the size of the first initial grooves in the third direction is smaller than the size of the second initial grooves, and the third direction intersects the first direction and the second direction;

[0011] Filling a sacrificial layer in the plurality of first initial grooves and the plurality of second initial grooves;

[0012] removing the sacrificial layer in the plurality of second initial grooves, and enlarging the dimensions of the second initial grooves along the first direction and the second direction to form a plurality of second grooves; and

[0013] The sacrificial layer in the plurality of first initial grooves is removed to form a plurality of first grooves.

[0014] In the method for manufacturing a semiconductor device in some embodiments, before removing the sacrificial layer in the plurality of second initial grooves, the method further includes:

[0015] removing a portion of the sacrificial layer in the plurality of first initial grooves; and

[0016] A covering layer is formed on the remaining sacrificial layer in the plurality of first initial grooves.

[0017] In the method for manufacturing a semiconductor device in some embodiments, before removing the portion of the sacrificial layer in the plurality of first initial grooves, the method further includes:

[0018] A protection layer covering the sacrificial layer in the plurality of second initial grooves is formed on one side of the semiconductor layer in the first direction.

[0019] In the method for manufacturing a semiconductor device in some embodiments, before forming a conductive layer in the plurality of first grooves and the plurality of second grooves, the method further includes:

[0020] An isolation layer is formed on the sidewall of the channel structure in the first groove, and a gate insulation layer is formed on the sidewall of the channel structure in the second groove.

[0021] In the method for manufacturing a semiconductor device in some embodiments, forming a conductive layer in the plurality of first grooves and the plurality of second grooves includes:

[0022] A first conductive layer is formed to cover the isolation layer, fill the first groove, and cover the gate insulating layer in the second groove.

[0023] In the method for manufacturing a semiconductor device in some embodiments, forming a conductive layer in the plurality of first grooves and the plurality of second grooves includes:

[0024] forming a first conductive layer covering the isolation layer and filling the first groove, and covering the gate insulating layer in the second groove; and

[0025] A second conductive layer is formed in the second groove and covers the first conductive layer in the second groove, wherein a material of the second conductive layer is different from a material of the first conductive layer.

[0026] In the method for manufacturing a semiconductor device in some embodiments, forming a conductive layer in the plurality of first grooves and the plurality of second grooves includes:

[0027] forming a first conductive layer covering the isolation layer in the first groove and the gate insulating layer in the second groove; and

[0028] A second conductive layer is formed to cover the first conductive layer in the first groove and fill the first groove and to cover the first conductive layer in the second groove, wherein a material of the second conductive layer is different from a material of the first conductive layer.

[0029] In the method for manufacturing a semiconductor device in some embodiments, after forming the plurality of second grooves and before forming the plurality of first grooves, the method further includes:

[0030] An insulating raised portion is formed at the bottom of the second groove, and the insulating raised portion includes an insulating top surface away from the bottom surface of the second groove. In the first direction, the insulating top surface is located on the side of the bottom surface of the first initial groove close to the groove opening of the first initial groove.

[0031] In the method for manufacturing a semiconductor device in some embodiments, the method further includes: forming a lead-out conductive structure connected to the plurality of conductive shielding structures.

[0032] In a second aspect, the present application further provides a semiconductor device, comprising:

[0033] a plurality of channel structures extending along a first direction;

[0034] a plurality of gate lines extending along the first direction, wherein one of the gate lines is located between adjacent channel structures in a second direction, and the second direction intersects the first direction; and

[0035] a plurality of conductive shielding structures extending along the first direction, wherein the plurality of conductive shielding structures and the plurality of gate lines are arranged at intervals along the second direction, and one of the conductive shielding structures is located between adjacent channel structures in the second direction;

[0036] Wherein, a size of the conductive shielding structure along the second direction is less than twice a size of one of the gate lines along the second direction.

[0037] In some embodiments of the semiconductor device, the semiconductor device further includes: an insulating spacer, located at one side of the gate line in the first direction and in contact with the gate line;

[0038] Among them, in the first direction, the conductive shielding structure includes a relatively conductive shielding bottom end surface and a conductive shielding top end surface, and the conductive shielding bottom end surface is arranged close to the insulating pad; the gate line includes a gate line bottom end surface in contact with the insulating pad, and the conductive shielding bottom end surface is located on the side of the gate line bottom end surface away from the conductive shielding top end surface.

[0039] In some embodiments of the semiconductor device, the semiconductor device further includes: a gate insulating layer, the gate insulating layer being located between the gate line and a sidewall of the channel structure; and

[0040] An isolation layer, wherein the isolation layer is located between the conductive shielding structure and the side wall of the channel structure, the thickness of the isolation layer is the same as the thickness of the gate insulating layer, and the material of the isolation layer is the same as the material of the gate insulating layer.

[0041] In the semiconductor device of some embodiments, the conductive shielding structure includes a first conductive shielding layer, and the isolation layer is located between the first conductive shielding layer and the sidewall of the channel structure;

[0042] The gate line includes a first gate layer. The gate insulating layer is located between the first gate layer and the sidewall of the channel structure. The material of the first gate layer is the same as that of the first conductive shielding layer.

[0043] In the semiconductor device of some embodiments, the conductive shielding structure includes a first conductive shielding layer, and the isolation layer is located between the first conductive shielding layer and the sidewall of the channel structure;

[0044] The gate line includes a first gate layer and a second gate layer of different materials, the first gate layer is located between the second gate layer and the side wall of the channel structure, the gate insulating layer is located between the first gate layer and the side wall of the channel structure, and the material of the first gate layer is the same as that of the first conductive shielding layer.

[0045] In the semiconductor device of some embodiments, the conductive shielding structure includes a first conductive shielding layer and a second conductive shielding layer made of different materials, the first conductive shielding layer is located between the second conductive shielding layer and the sidewall of the channel structure, and the isolation layer is located between the first conductive shielding layer and the sidewall of the channel structure;

[0046] The gate line includes a first gate layer and a second gate layer of different materials, the first gate layer is located between the second gate layer and the side wall of the channel structure, the gate insulating layer is located between the first gate layer and the side wall of the channel structure, the material of the first gate layer is the same as the material of the first conductive shielding layer, and the material of the second gate layer is the same as the material of the second conductive shielding layer.

[0047] In some embodiments of the semiconductor device, the semiconductor device further includes: a lead-out conductive structure connected to the conductive shielding structure.

[0048] In a third aspect, the present application further provides a storage system, including:

[0049] A memory, comprising the semiconductor device of any of the above embodiments; and

[0050] The controller is connected to the memory and is used to control the memory.

[0051] The beneficial effects of some embodiments of the present application include: first, a plurality of first grooves and second grooves intersecting with a plurality of channel lines are formed, and the size of the first groove along the second direction is smaller than the size of the second groove along the second direction. Then, a conductive layer is formed in the plurality of first grooves and the plurality of second grooves. Finally, a portion of the conductive layer is removed, and the remaining conductive layers in the plurality of first grooves respectively form a plurality of conductive shielding structures, and the remaining conductive layers in the plurality of second grooves respectively form a plurality of gate lines. Through this manufacturing method, the size difference between the first groove and the second groove is utilized to simultaneously manufacture the conductive shielding structure and the gate line, which can simplify the manufacturing process of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0052] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device according to some embodiments of the present application;

[0053] Figure 2A A schematic diagram of a planar structure of a semiconductor layer, a first insulating layer located on the semiconductor layer, and a mask layer located on the first insulating layer in some embodiments of the present application;

[0054] Figure 2B For along Figure 2A Schematic diagram of the cross-sectional structure taken by the AA tangent line in FIG.

[0055] Figure 3A It is a schematic diagram of a planar structure in which a plurality of channel lines and a first dielectric layer are formed in a semiconductor layer in some embodiments of the present application;

[0056] Figure 3B For along Figure 3A Schematic diagram of the cross-sectional structure taken by the BB tangent line;

[0057] Figure 4A A schematic plan view of forming a first initial groove and a second initial groove intersecting a plurality of channel lines in some embodiments of the present application;

[0058] Figure 4B For along Figure 4A Schematic diagram of the cross-sectional structure taken by the CC tangent line in FIG.

[0059] Figure 4C It is a schematic plan view of forming a second insulating layer and a sacrificial layer in the first initial groove and the second initial groove in some embodiments of the present application;

[0060] Figure 4D For along Figure 4C Schematic diagram of the cross-sectional structure taken by the DD tangent line;

[0061] Figure 4E A schematic diagram of a planar structure in which a protective layer is formed on the sacrificial layer in the second initial groove and a covering layer is formed on the remaining sacrificial layer in the first initial groove in some embodiments of the present application;

[0062] Figure 4F For along Figure 4E Schematic diagram of the cross-sectional structure taken by the EE tangent line in FIG.

[0063] Figure 4G It is a schematic cross-sectional structure diagram of forming a second groove and an insulating pad portion in the second groove in some embodiments of the present application;

[0064] Figure 4H A schematic plan view of a structure in which a sacrificial layer in a plurality of first initial grooves is removed to form a plurality of first grooves in some embodiments of the present application;

[0065] Fig. 4I For along Figure 4H Schematic diagram of the cross-sectional structure taken by the FF tangent line;

[0066] Figure 5A It is a schematic diagram of a planar structure in which a conductive layer is formed in a first groove and a second groove in some embodiments of the present application;

[0067] Figure 5B For along Figure 5A Schematic diagram of the cross-sectional structure taken by the GG tangent line;

[0068] Figure 5C This is a schematic plan view of removing part of the conductive layer in some embodiments of the present application;

[0069] Figure 5D For along Figure 5C Schematic diagram of the cross-sectional structure taken by the HH tangent line;

[0070] Fig. 6A It is a schematic cross-sectional structure diagram of forming a conductive layer in the first groove and the second groove in some other embodiments of the present application;

[0071] Figure 6B It is a schematic cross-sectional structure diagram of removing part of the conductive layer in other embodiments of the present application;

[0072] Fig. 7A Schematic diagram of a cross-sectional structure of forming a conductive layer in a first groove and a second groove in some other embodiments of the present application;

[0073] Figure 7B Schematic diagram of a cross-sectional structure in which a portion of a conductive layer is removed in some other embodiments of the present application;

[0074] Fig. 8A A schematic diagram of a planar structure in which a capacitor is formed and the second surface of the semiconductor layer is thinned in some embodiments of the present application;

[0075] Figure 8B For along Fig. 8A Schematic diagram of the cross-sectional structure taken along the JJ tangent line;

[0076] Figure 8C For along Fig. 8A Schematic diagram of the cross-sectional structure taken by the KK tangent line;

[0077] Fig.9A A schematic diagram of a planar structure of a semiconductor device according to some embodiments of the present application;

[0078] Fig. 9B It is a schematic diagram of the cross-sectional structure taken along the LL tangent line in FIG9 ;

[0079] Fig.10 A block diagram of a storage system according to some embodiments of the present application;

[0080] Fig.11 A block diagram of a storage system according to some other embodiments of the present application;

[0081] Fig.12 A block diagram of an electronic device according to some embodiments of the present application.

[0082] The reference numerals are as follows:

[0083] z, first direction; y, second direction; x, third direction;

[0084] 11, semiconductor layer; 11a, first surface; 11b, second surface; 11c, recessed portion; 11d, third surface; 112, channel line; 113, columnar semiconductor structure; 114, channel structure;

[0085] 121, first insulating layer; 122, first dielectric layer; 123, second insulating layer; 124, sacrificial layer; 125, protective layer; 126, covering layer; 127, isolation layer; 128, gate insulating layer; 129, second dielectric layer; 130, third dielectric layer;

[0086] 131, mask layer; 132, mask pattern;

[0087] 141, first initial groove; 141a, first groove bottom surface; 142, second initial groove; 143, first groove; 143a, second groove bottom surface; 144, second groove;

[0088] 15, gate line; 151, first gate layer; 152, second gate layer; 15a, bottom end surface of gate line; 15b, top end surface of gate line;

[0089] 16, conductive shielding structure; 161, first conductive shielding layer; 16a, conductive shielding bottom end surface; 16b, conductive shielding top end surface;

[0090] 17, insulating pad portion; 17a, insulating top surface; 171, insulating outer covering layer; 172, insulating core portion;

[0091] 18, conductive layer; 181, first conductive layer; 182, second conductive layer; 18a, notch;

[0092] 191, a first insulating filling portion; 192, a second insulating filling portion;

[0093] 201, first electrode; 202, second electrode; 203, connection contact; 204, capacitor; 205, lead-out conductive structure; 206, isolation part;

[0094] 100, semiconductor device; 200, memory; 300, controller; 400, storage system; 500, electronic device; 600, host. DETAILED DESCRIPTION

[0095] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0096] See also Figure 1 As shown, it is a schematic flow chart of a method for manufacturing a semiconductor device in some embodiments of the present application. The method for manufacturing a semiconductor device comprises the following steps:

[0097] Step S101: forming a plurality of channel lines extending along a first direction and a second direction in a semiconductor layer, wherein the first direction intersects the second direction.

[0098] Step S102: forming a plurality of first grooves and a plurality of second grooves extending along the first direction and arranged along the second direction in the semiconductor layer, wherein the plurality of first grooves and the plurality of second grooves intersect with a plurality of channel lines to form a plurality of channel structures, and a size of the first groove along the second direction is smaller than a size of the second groove along the second direction.

[0099] Step S103: forming a conductive layer in the first grooves and the second grooves, removing part of the conductive layer, and forming a plurality of conductive shielding structures with the remaining conductive layer in the first grooves, and forming a plurality of gate lines with the remaining conductive layer in the second grooves.

[0100] In some embodiments of the present application, after forming the first groove and the second groove of different sizes, a conductive layer is formed in the first groove and the second groove, and then a portion of the conductive layer is removed to form a conductive shielding structure in the first groove while forming a gate line in the second groove. This manufacturing method, i.e., utilizing the size difference between the first groove and the second groove in the second direction and forming the gate line and the conductive shielding structure in one step, can simplify the manufacturing method of the semiconductor device.

[0101] In some related technologies, air gaps are provided between adjacent channel structures to improve the coupling effect between adjacent channel structures. However, since the size of the air gaps is difficult to control, the uniformity of the sizes of multiple air gaps is difficult to control, and some air gaps may not meet the requirements of electrical isolation. In some embodiments of the present application, the size of the conductive shielding structure obtained by the above method is easier to control, which can better improve the coupling effect between adjacent channel structures.

[0102] The following is a detailed description of the manufacturing methods of semiconductor devices according to some embodiments of the present application.

[0103] In some embodiments, see Figure 2A and Figure 2B As shown, before performing the above step S101, the method for manufacturing a semiconductor device further includes:

[0104] providing a semiconductor layer 11; and

[0105] A first insulating layer 121 is formed on the semiconductor layer 11 .

[0106] The semiconductor layer 11 includes a first surface 11a and a second surface 11b opposite to each other in a first direction z. The material of the semiconductor layer 11 includes but is not limited to single-element semiconductor materials such as single crystal silicon. Specifically, the semiconductor layer 11 includes a silicon wafer.

[0107] The first insulating layer 121 is disposed on the first surface 11a of the semiconductor layer 11. During the processing of the semiconductor layer 11, the first insulating layer 121 protects the semiconductor layer 11. The material of the first insulating layer 121 includes, but is not limited to, insulating materials such as silicon oxide, silicon nitride, or silicon oxynitride. Specifically, the material of the first insulating layer 121 includes silicon oxide to ensure that it can better adhere to the semiconductor layer 11.

[0108] In some embodiments, please refer to Figure 2A and Figure 2B As shown, after forming the first insulating layer 121 on the semiconductor layer 11 , the method for manufacturing a semiconductor device further includes: forming a mask layer 131 on a surface of the first insulating layer 121 away from the semiconductor layer 11 .

[0109] The material of the mask layer 131 may include at least one of an inorganic insulating material and an organic insulating material. The inorganic insulating material includes but is not limited to silicon nitride. The organic insulating material includes but is not limited to photoresist.

[0110] Next, see Figure 3A and Figure 3B As shown, the above step S101 is performed to form a plurality of channel lines 112 extending along a first direction z and a second direction y in the semiconductor layer 11 , wherein the first direction z intersects the second direction y.

[0111] In some embodiments, forming a plurality of channel lines 112 extending along the first direction z and the second direction y in the semiconductor layer 11 includes: forming a plurality of recessed portions 11 c in the semiconductor layer 11 , and the remaining semiconductor layer 11 includes the plurality of channel lines 112 .

[0112] The plurality of recessed portions 11c are sunken from the first surface 11a to the second surface 11b. The plurality of recessed portions 11c also extend along the second direction y and are arranged at intervals along the third direction x, and the third direction x intersects the second direction y. The depth of the recessed portions 11c in the semiconductor layer 11 is less than the thickness of the semiconductor layer 11. The cross-section of the plurality of recessed portions 11c parallel to the first direction z and the third direction x may be a rectangle or an inverted trapezoid.

[0113] A plurality of channel lines 112 are arranged at intervals along the third direction x. One channel line 112 is located between two adjacent recessed portions 11c. The shape of the cross section of the channel line 112 parallel to the first direction z and the third direction x may be a rectangle or a trapezoid.

[0114] The first direction z is the thickness direction of the semiconductor layer 11, but is not limited thereto. The angle between the first direction z and the thickness direction of the semiconductor layer 11 may be an acute angle. The first direction z is perpendicular to both the second direction y and the third direction x, but is not limited thereto. The second direction y is perpendicular to the third direction x, but is not limited thereto. The angle between the second direction y and the third direction x may be an obtuse angle or an acute angle.

[0115] In some embodiments, forming a plurality of recessed portions 11 c in the semiconductor layer 11 includes: patterning the mask layer 131 to obtain a mask pattern 132 ; and

[0116] Using the mask pattern 132 as a mask, a portion of the first insulating layer 121 and a portion of the semiconductor layer 11 are removed to form a plurality of recessed portions 11 c , which penetrate the first insulating layer 121 along the first direction z and extend into the semiconductor layer 11 .

[0117] In some embodiments, please refer to Figure 3A and Figure 3B As shown, after forming a plurality of recessed portions 11 c in the semiconductor layer 11 , the method for manufacturing a semiconductor device further includes: forming a first dielectric layer 122 in the plurality of recessed portions 11 c.

[0118] Specifically, forming the first dielectric layer in the plurality of recessed portions 11 c includes: forming a first initial dielectric layer filling the plurality of recessed portions 11 c and covering the mask pattern 132 ; and

[0119] The first initial dielectric layer on the mask pattern 132 is removed, and the remaining first initial dielectric layer constitutes the first dielectric layer 122 .

[0120] Exemplarily, chemical mechanical polishing is used to remove the first initial dielectric layer on the mask pattern 132 , but is not limited thereto.

[0121] In some embodiments, the material of the first dielectric layer 122 includes but is not limited to insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.

[0122] Next, see FIG. 4A to FIG. 4I As shown, the above step S102 is performed to form a plurality of first grooves 143 and a plurality of second grooves 144 extending along the first direction z and arranged along the second direction y in the semiconductor layer 11, and the plurality of first grooves 143 and the plurality of second grooves 144 intersect with the plurality of channel lines 112 to form a plurality of channel structures 114, and the size of the first groove 143 along the second direction y is smaller than the size of the second groove 144 along the second direction y.

[0123] In some embodiments, see FIG. 4A to FIG. 4IAs shown, forming a plurality of first grooves 143 and a plurality of second grooves 144 extending along the first direction z and arranged along the second direction y in the semiconductor layer 11 includes:

[0124] A plurality of first initial grooves 141 and a plurality of second initial grooves 142 are formed in the semiconductor layer 11, extending along the first direction z and the third direction x and alternately arranged along the second direction y, wherein the size of the first initial grooves 141 in the third direction x is smaller than the size of the second initial grooves 142;

[0125] Filling the plurality of first preliminary grooves 141 and the plurality of second preliminary grooves 142 with a sacrificial layer 124 ;

[0126] removing the sacrificial layer 124 in the plurality of second preliminary grooves 142 and enlarging the dimensions of the second preliminary grooves 142 along the first direction z and the second direction y to form a plurality of second grooves 144; and

[0127] The sacrificial layer 124 in the plurality of first preliminary grooves 141 is removed to form a plurality of first grooves 143 .

[0128] In some embodiments, see Figure 4A and Figure 4B As shown, a plurality of first initial grooves 141 and a plurality of second initial grooves 142 extending along the first direction z and the third direction x and alternately arranged along the second direction y are formed in the semiconductor layer 11, including: removing part of the first dielectric layer 122 and part of the channel line 112 to form a plurality of first initial grooves 141 and a plurality of second initial grooves 142 extending along the first direction z and the third direction x and alternately arranged along the second direction x, the remaining channel line 112 includes a plurality of columnar semiconductor structures 113, and the first initial grooves 141 and the second initial grooves 142 are both sunken from the first surface 11a to the second surface 11b.

[0129] The first initial groove 141 and the second initial groove 142 both intersect the channel line 112 , and a plurality of first initial grooves 141 and a plurality of second initial grooves 142 are alternately arranged in a one-to-one manner along the second direction y.

[0130] In the third direction x, the size of the first initial groove 141 is smaller than the size of the second initial groove 142, and the opposite ends of the second initial groove 142 in the third direction x protrude from the first initial groove 141. With this design, when the first initial groove 141 is processed to obtain the first groove 143 described below, and the second initial groove 142 is processed to obtain the second groove 144 described below, the size of the first groove 143 along the third direction x is smaller than the size of the second groove 144 along the third direction x. Correspondingly, the size of the gate line 15 formed in the second groove 144 described below along the third direction x is larger than the size of the conductive shielding structure 16 formed in the first groove 143 described below along the third direction x.

[0131] The first initial groove 141 and the second initial groove 142 have the same size along the second direction y and the same depth along the first direction x, so as to manufacture the first initial groove 141 and the second initial groove 142 simultaneously, thereby simplifying the manufacturing process of the semiconductor device.

[0132] In some embodiments, see Figure 4C and Figure 4D As shown, a second insulating layer 123 is formed on the sidewall of the columnar semiconductor structure 113. The second insulating layer 123 repairs the sidewall of the columnar semiconductor structure 113. The material of the second insulating layer 123 includes insulating materials such as silicon oxide, silicon nitride or silicon oxynitride.

[0133] Exemplarily, in an oxygen atmosphere and under heating conditions, silicon on the sidewalls of the columnar semiconductor structure 113 is oxidized to form a second insulating layer 123; alternatively, a thin film deposition process is used to form the second insulating layer 123 in the sidewalls of the first initial groove 141 and the sidewalls of the second initial groove 142.

[0134] In some embodiments, please refer to Figure 4C and Figure 4D As shown, the method for manufacturing a semiconductor device further includes: filling a sacrificial layer 124 in the plurality of first initial grooves 141 and the plurality of second initial grooves 142. The material of the sacrificial layer 124 includes but is not limited to spin on carbon (SOC).

[0135] In some embodiments, see Figure 4E and Figure 4F As shown, after the sacrificial layer 124 is filled in the multiple first initial grooves 141 and the multiple second initial grooves 142, the manufacturing method of the semiconductor device also includes: forming a protective layer 125 covering the sacrificial layer 124 in the multiple second initial grooves 142 on one side of the semiconductor layer 11 in the first direction z.

[0136] The protective layer 125 protects the sacrificial layer 124 in the second initial groove 142. The material of the protective layer 125 includes but is not limited to organic insulating materials and inorganic insulating materials. The organic insulating materials include but are not limited to photoresists. The inorganic insulating materials include but are not limited to silicon nitride.

[0137] In some embodiments, please refer to Figure 4E and Figure 4F As shown, after forming the protection layer 125 , the method for manufacturing a semiconductor device further includes: removing a portion of the sacrificial layer 124 in the plurality of first initial grooves 141 ; and forming a covering layer 126 on the remaining sacrificial layer 124 in the plurality of first initial grooves 141 .

[0138] In some embodiments, the material of the capping layer 126 is the same as that of the mask layer 131. In other embodiments, the material of the capping layer 126 may also be different from that of the mask layer 131. In some embodiments, the material of the capping layer 126 includes but is not limited to silicon nitride, silicon oxide, or silicon oxynitride.

[0139] It should be noted that, since the protective layer 125 protects the sacrificial layer 124 in the second initial groove 142, the sacrificial layer 124 in the second initial groove 142 will not be affected during the process of removing part of the sacrificial layer 124 in the plurality of first initial grooves 141. In addition, when removing the sacrificial layer 124 in the second initial groove 142, the covering layer 126 protects the remaining sacrificial layer 124 in the first initial groove 141, and the remaining sacrificial layer 124 in the first initial groove 141 will not be affected.

[0140] In some embodiments, see Figure 4G As shown, the sacrificial layer 124 in the plurality of second initial grooves 142 is removed, and the dimensions of the second initial grooves 142 along the first direction z and the second direction y are enlarged to form a plurality of second grooves 144 , and the remaining semiconductor layer 11 includes a plurality of channel structures 114 .

[0141] Specifically, the protective layer 125 is removed, and then the sacrificial layer 124 in the second initial grooves 142 is removed. Then, a portion of the first dielectric layer 122 and the columnar semiconductor structure 113 is removed to form a plurality of second grooves 144 , and the remaining columnar semiconductor structure 113 forms a channel structure 114 .

[0142] In some other embodiments, while the size of the second initial groove 142 along the first direction z and the second direction y is enlarged, the size of the second initial groove 142 along the third direction x may also be enlarged at the same time to form a plurality of second grooves 144 .

[0143] In some embodiments, the plurality of channel structures 114 extend along the first direction z, and are arranged in an array along the second direction y and the third direction x.

[0144] In some embodiments, please refer to Figure 4G As shown, after forming a plurality of second grooves 144 and before removing the sacrificial layer 124 in the plurality of first initial grooves 141, the method for manufacturing a semiconductor device further includes: forming an insulating pad 17 at the bottom of the plurality of second grooves 144, the insulating pad 17 including an insulating top surface 17a away from the bottom surface of the second groove 144, and in the first direction z, the insulating top surface 17a is located on the side of the first bottom surface 141a of the first initial groove 141 close to the groove opening of the first initial groove 141.

[0145] The insulating raised portion 17 can isolate the semiconductor layer 11 from the gate line 15. Moreover, by adjusting the height of the insulating raised portion 17, the size of the gate line 15 in the first direction z can be controlled. In addition, by controlling the insulating top surface 17a to include a plane, it can be ensured that the gate line 15 is formed on a plane, thereby ensuring that the size of the gate line 15 in the first direction z is controllable.

[0146] In some embodiments of the present application, the insulating top surface 17a is located on the side of the groove bottom surface 141a of the first initial groove 141 close to the groove opening of the first initial groove 141 in the first direction z. With this design, the size of the gate line 15 formed on the insulating pad 17 along the first direction z is smaller than the size of the conductive shielding structure 16 along the first direction z, further ensuring the improvement effect of the conductive shielding structure 16 on the coupling effect between adjacent channel structures.

[0147] In some embodiments, the insulating pad portion 17 includes an insulating outer coating 171 and an insulating core 172, and the insulating outer coating 171 covers the sidewalls and bottom surface of the insulating core 172. The insulating outer coating 172 is located at the bottom of the second groove 144 and on the sidewalls of the second groove 144. The material of the insulating outer coating 172 is different from the material of the insulating core 172. Exemplarily, the material of the insulating outer coating 172 includes silicon oxide, and the material of the insulating core 172 includes silicon nitride, but is not limited thereto. In other embodiments, the insulating pad portion 17 may also include only the insulating core 172.

[0148] In some embodiments, see Figure 4H and Fig. 4I As shown, after the insulating pads 17 are formed, the sacrificial layer 124 in the plurality of first initial grooves 141 is removed to form a plurality of first grooves 143 .

[0149] Specifically, the cover layer 126 and the remaining sacrificial layer 124 in the plurality of first preliminary grooves 141 are removed to form a plurality of first grooves 143 .

[0150] In some embodiments of the present application, the second initial groove 142 is expanded to form a second groove 144. The sacrificial layer 124 in the plurality of first initial grooves 141 is removed to form a plurality of first grooves 143. In this way, a plurality of second grooves 144 and a plurality of first grooves 143 arranged alternately along the second direction y are obtained. The size of the second groove 144 along the first direction z is greater than the size of the first groove 143 along the first direction z, the size of the second groove 144 along the second direction y is greater than the size of the first groove 143 along the first direction z, and the size of the second groove 144 along the third direction x is also greater than the size of the first groove 143 along the third direction x.

[0151] In some embodiments, see Fig. 4I As shown, in the first direction z, the distance d between the insulating top surface 17a of the insulating pad portion 17 and the second groove bottom surface 143a of the first groove 143 is greater than or equal to 70 nanometers and less than or equal to 100 nanometers. With this design, the gate line bottom end surface 15a where the gate line 15 contacts the insulating pad portion 17 is located above the conductive shielding bottom end surface 16a of the conductive shielding structure 16. When the gate voltage loaded by the gate line 15 acts on the channel structure 114, the conductive shielding structure 16 can better shield the coupling effect between adjacent channel structures 114 in the second direction y.

[0152] In some embodiments, see Figure 5A and Figure 5B As shown, before forming a conductive layer in multiple first grooves 143 and multiple second grooves 144, the manufacturing method of the semiconductor device also includes: forming an isolation layer 127 located on the side wall of the channel structure 114 in the first groove 143, and forming a gate insulation layer 128 located on the side wall of the channel structure 114 in the second groove 144.

[0153] The isolation layer 127 serves to isolate the channel structure 114 from the conductive shielding structure 16 , and the gate insulating layer 128 serves to isolate the channel structure 114 from the gate line 15 .

[0154] In some embodiments, the material of the isolation layer 127 is the same as that of the gate insulating layer 128, and the thickness of the isolation layer 127 is the same as that of the gate insulating layer 128. With this design, the isolation layer 127 and the gate insulating layer 128 can be formed in one step, further simplifying the manufacturing process of the semiconductor device.

[0155] In some embodiments, the sidewalls of the channel structure 114 may be oxidized to form an isolation layer 127 and a gate insulating layer 128. In other embodiments, an insulating layer may be deposited on the sidewalls of the first groove 143 and the sidewalls of the second groove 144 by a thin film deposition process to form an isolation layer 127 and a gate insulating layer 128.

[0156] Finally, see FIG. 5A to FIG. 5D , Fig. 6A and Figure 6B as well as Fig. 7A and Figure 7B As shown, the above step S103 is performed to form a conductive layer 18 in multiple first grooves 143 and multiple second grooves 144, and a portion of the conductive layer 18 is removed. The remaining conductive layer 18 in the multiple first grooves 143 respectively forms multiple conductive shielding structures 16, and the remaining conductive layer 18 in the multiple second grooves 144 respectively forms multiple gate lines 15.

[0157] In some embodiments, see Figure 5A and Figure 5B As shown, forming a conductive layer in the plurality of first grooves 143 and the plurality of second grooves 144 includes: forming a first conductive layer 181 covering the isolation layer 127 and filling the first grooves 143 , and covering the gate insulating layer 128 in the second grooves 144 and the sidewalls of the second grooves 144 ; and

[0158] A second conductive layer 182 is formed in the second groove 144 and covers the first conductive layer 181 in the second groove 144 . The material of the second conductive layer 182 is different from that of the first conductive layer 181 .

[0159] In some embodiments of the present application, the size of the first groove 143 along the second direction y is smaller than the size of the second groove 144 along the second direction y. Therefore, in the process of forming the first conductive layer 181, while the first conductive layer 181 fills the first groove 143, there is still a gap in the second groove 144 formed with the first conductive layer 181, that is, the second groove 144 is not filled.

[0160] In some embodiments, the materials of the first conductive layer 181 and the second conductive layer 182 include metal and non-metal conductive materials, and the metal includes but is not limited to tungsten, cobalt, copper, nickel and alloys thereof. The non-metal conductive materials include but are not limited to titanium nitride.

[0161] Exemplarily, the material of the first conductive layer 181 includes titanium nitride, and the material of the second conductive layer 182 includes tungsten. With this design, both the second conductive layer 182 and the first conductive layer 181 have conductivity, so as to ensure the conductivity of the gate line 15 and the conductive shielding structure 16, while the first conductive layer 181 prevents the second conductive layer 182 from diffusing into the channel structure 114.

[0162] In some embodiments, see Figure 5C and Figure 5D As shown, removing part of the conductive layer 18 includes: removing the conductive layer 18 outside the first groove 143 and the second groove 144, and removing part of the conductive layer 18 in the first groove 143 and the second groove 144, the remaining conductive layer 18 in the first groove 143 constitutes a conductive shielding structure 16; and forming a notch 18a on the remaining conductive layer 18 in the second groove 144, and forming two gate lines 15 in the second groove 144.

[0163] In some embodiments, please refer to Figure 5C and Figure 5D As shown, the gate line 15 includes a first gate layer 151 and a second gate layer 152 of different materials, and the conductive shielding structure 16 includes a first conductive shielding layer 161. The first gate layer 151 is located between the second gate layer 152 and the sidewall of the channel structure 114. The gate insulating layer 128 is located between the first gate layer 151 and the sidewall of the channel structure 114. The isolation layer 127 is located between the first conductive shielding layer 161 and the sidewall of the channel structure 114. The material of the first gate layer 151 is the same as that of the first conductive shielding layer 161. The size of the first conductive shielding layer 161 along the second direction y is less than or equal to twice the size of the first gate layer 151 along the second direction y.

[0164] In other embodiments, see Fig. 6A As shown, forming the conductive layer 18 in the plurality of first grooves 143 and the plurality of second grooves 144 includes: forming a first conductive layer 181 covering the isolation layer 127 and filling the first grooves 143 , and covering the gate insulating layer 128 in the second grooves 144 .

[0165] In other embodiments, see Figure 6B As shown, the gate line 15 includes a first gate layer 151, and the conductive shielding structure 16 includes a first conductive shielding layer 161. The gate insulating layer 128 is located between the first gate layer 151 and the sidewall of the channel structure 114. The isolation layer 127 is located between the first conductive shielding layer 161 and the sidewall of the channel structure 114. The material of the first gate layer 151 is the same as that of the first conductive shielding layer 161. The size of the first conductive shielding layer 161 along the second direction y is less than twice the size of the first gate layer 151 along the second direction y.

[0166] In some other embodiments, see Fig. 7AAs shown, forming the conductive layer 18 in the plurality of first grooves 143 and the plurality of second grooves 144 includes: forming a first conductive layer 181 covering the isolation layer 127 and the sidewalls of the first grooves 143 in the first grooves 143, and the gate insulating layer 128 and the sidewalls of the second grooves 144 in the second grooves 144; and

[0167] A second conductive layer 182 is formed to cover the first conductive layer 181 in the first groove 143 and fill the first groove 143 and to cover the first conductive layer 181 in the second groove 144 . The material of the second conductive layer 182 is different from that of the first conductive layer 181 .

[0168] In some other embodiments, see Figure 7B As shown, the gate line 15 includes a first gate layer 151 and a second gate layer 152 of different materials, and the conductive shielding structure 16 includes a first conductive shielding layer 161 and a second conductive shielding layer 162 of different materials. The first gate layer 151 is located between the second gate layer 152 and the sidewall of the channel structure 114. The gate insulating layer 128 is located between the first gate layer 151 and the sidewall of the channel structure 114. The first conductive shielding layer 161 is located between the second conductive shielding layer 162 and the sidewall of the channel structure 114. The isolation layer 127 is located between the first conductive shielding layer 161 and the sidewall of the channel structure 114. The material of the first gate layer 151 is the same as that of the first conductive shielding layer 161. The material of the second gate layer 152 is the same as that of the second conductive shielding layer 162. The size of the first conductive shielding layer 161 along the second direction y is equal to twice the size of the first gate layer 151 along the second direction y, and the size of the second conductive shielding layer 162 along the second direction y is less than twice the size of the second gate layer 152 along the second direction y.

[0169] In some other embodiments of the present application, when the first conductive layer 181 cannot fill the first groove 143 , the second conductive layer 182 may be used to continue filling the first groove 143 .

[0170] In some embodiments of the present application, Figure 5D , Figure 6B as well as Figure 7B It can be seen that the size of the conductive shielding structure 16 along the second direction y is less than twice the size of one gate line 15 along the second direction y.

[0171] See also Figure 5D , Figure 6B as well as Figure 7BAs shown, the gate line 15 includes a gate line bottom end surface 15a and a gate line top end surface 15b opposite to each other in the first direction z. The gate line bottom end surface 15a and the gate line top end surface 15b include planes, so that the size of the gate line 15 in the first direction z is more controllable. The gate line bottom end surface 15a contacts the insulating pad 17. The conductive shielding structure 16 includes a conductive shielding bottom end surface 16a and a conductive shielding top end surface 16b opposite to each other in the first direction z, and the conductive shielding bottom end surface 16a is arranged close to the insulating pad 17. The conductive shielding bottom end surface 16a includes a curved surface, and the conductive shielding top end surface 16b includes a plane.

[0172] In some embodiments, the gate line top surface 15b and the conductive shield top surface 16b are flush in the second direction y, so that after removing part of the conductive layer in one step, the gate line 15 and the conductive shield structure 16 are formed simultaneously, simplifying the manufacturing process of the semiconductor device.

[0173] It should be noted that, in the present application, the top surface 15 b of the gate line is flush with the top surface 16 b of the conductive shielding, which is flush within a certain error range.

[0174] In some embodiments, in the first direction z, the gate line bottom end surface 15a is located between the conductive shield bottom end surface 16a and the conductive shield top end surface 16b. With this design, when the gate voltage output by the gate line 15 acts on the channel structure 114, the action area of ​​the gate voltage on the channel structure 114 can be covered by the conductive shield structure 16, ensuring that the conductive shield structure 16 can better improve the coupling effect between adjacent channel structures 114 in the second direction.

[0175] In some embodiments, a dimension of the gate line 15 in the first direction z is greater than or equal to 100 nanometers and less than or equal to 200 nanometers.

[0176] In some embodiments, please refer to Figure 5D , Figure 6B as well as Figure 7B As shown, after forming the gate line 15 and the conductive shielding structure 16, the manufacturing method of the semiconductor device also includes: forming a first insulating filling part 191 covering the gate line 15 and filling the second groove 144, and forming a second insulating filling part 192 covering the conductive shielding structure 16 and filling the first groove 143.

[0177] In some embodiments of the present application, the first insulating filling part 191 and the second insulating filling part 192 are formed in one step, which further simplifies the manufacturing process of the semiconductor device.

[0178] In some embodiments, the material of the first insulating filling part 191 and the second insulating filling part 192 includes silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof.

[0179] In some embodiments, see Fig. 8A and Figure 8B As shown, after forming the first insulating filling part 191 and the second insulating filling part 192 , the method for manufacturing a semiconductor device further includes: performing ion implantation on an end of the channel structure 114 away from the bottom end surface 15 a of the gate line to form a first electrode 201 .

[0180] In some embodiments, please refer to Fig. 8A and Figure 8B As shown, the method for manufacturing a semiconductor device further includes: forming a connection contact 203 connected to the first electrode 201 ; forming a capacitor 204 connected to the first electrode 201 ; and filling a second dielectric layer 129 between the plurality of capacitors 204 .

[0181] In some embodiments, see FIG. 8A to FIG. 8C As shown, the method for manufacturing the semiconductor device also includes: thinning the second surface 11b of the semiconductor layer 11 to expose the first dielectric layer 122 and form a third surface 11d; and performing ion implantation on an end of the channel structure 114 away from the first electrode 201 to form a second electrode 202.

[0182] It should be noted that one of the first electrode 201 and the second electrode 202 is a source electrode, and the other of the first electrode 201 and the second electrode 202 is a drain electrode.

[0183] In some embodiments, see Fig.9A and Fig. 9B As shown, the method for manufacturing a semiconductor device further includes: forming a lead-out conductive structure 205 connected to the plurality of conductive shielding structures 16 ; and forming an isolation portion 206 between the lead-out conductive structure 205 and the channel structure 114 .

[0184] In some embodiments of the present application, the lead-out conductive structure 205 is grounded, or a negative potential is loaded on the lead-out conductive structure 205, so that the conductive shielding structure 16 connected to the lead-out conductive structure 205 is also grounded or loaded with a negative potential, and the conductive shielding structure 16 shields the coupling effect between adjacent channel structures 114 in the second direction.

[0185] The isolation portion 206 serves to isolate the lead-out conductive structure 205 from the second electrode 202 .

[0186] In some embodiments, please refer to Fig.9A and Fig. 9B As shown, a third dielectric layer 130 is formed to cover the lead-out conductive structure 205 .

[0187] Based on the same inventive concept, the present application also provides a semiconductor device 100 manufactured by the above method. Fig.9A and Fig. 9B As shown, the semiconductor device 100 includes a plurality of channel structures 114 , a plurality of gate lines 15 , a plurality of conductive shielding structures 16 , a capacitor 204 , an isolation layer 127 , a gate insulating layer 128 , and a lead-out conductive structure 205 .

[0188] The plurality of channel structures 114 extend along the first direction z and are arranged in an array along the second direction y and the third direction x. Any two of the first direction z, the second direction y and the third direction x intersect. Specifically, the first direction z is perpendicular to the second direction y and the third direction x, and the second direction y is perpendicular to the third direction x, but is not limited thereto.

[0189] Each channel structure 114 is provided with a first electrode 201 and a second electrode 202 at two opposite ends in the first direction z. One of the first electrode 201 and the second electrode 202 is a source, and the other of the first electrode 201 and the second electrode 202 is a drain.

[0190] The plurality of gate lines 15 extend along the first direction z and the third direction x and are spaced apart along the second direction y. Each gate line 15 includes a gate line bottom end surface 15a and a gate line top end surface 15b opposite to each other in the first direction z. The gate insulating layer 128 is located between the gate line 15 and the sidewall of the channel structure 114.

[0191] In some embodiments, two gate lines 15 are disposed between two adjacent rows of channel structures 114 in the second direction y. In other embodiments, only one gate line 15 may be disposed between two adjacent rows of channel structures 114 in the second direction y.

[0192] A plurality of conductive shielding structures 16 extend along the first direction z and the third direction x, and are spaced apart along the second direction y. A plurality of conductive shielding structures 16 are spaced apart from a plurality of gate lines 15 along the second direction y. In the second direction y, one conductive shielding structure 16 is located between two adjacent rows of channel structures 114, and one conductive shielding structure 16 is located on the side of the adjacent channel structure 114 away from the gate line 115. In the first direction z, the conductive shielding structure 16 includes opposite conductive shielding bottom end surfaces 16a and conductive shielding top end surfaces 16b. An isolation layer 127 is located between the conductive shielding structure 16 and the sidewalls of the channel structure 114.

[0193] In some embodiments, the size of the conductive shielding structure 16 along the second direction y is less than twice the size of a gate line 15 along the second direction y, that is, the thickness of the conductive shielding structure 16 along the second direction is less than twice the thickness of a gate line 15 along the second direction y. Through this design, on the basis of forming the above-mentioned differentiated first groove and second groove, the conductive shielding structure 16 and the gate line 15 can be formed simultaneously in one step, simplifying the manufacturing process of the semiconductor device 100.

[0194] In some embodiments, the thickness of the isolation layer 127 is the same as that of the gate insulating layer 128, and the material of the isolation layer 127 is the same as that of the gate insulating layer 128. With this design, it is convenient to form the isolation layer 127 and the gate insulating layer 128 simultaneously in one step, further simplifying the manufacturing process of the semiconductor device 100.

[0195] In some embodiments, the semiconductor device 100 further includes an insulating spacer 17, which is located at one side of the gate line 15 in the first direction z and contacts the gate line 15. The conductive shielding bottom end surface 16a is disposed close to the insulating spacer 17. The gate line bottom end surface 15a contacts the insulating spacer 17.

[0196] In some embodiments, in the first direction z, the gate line top surface 15b is flush with the conductive shield top surface 16b, so that the gate line top surface 15b and the conductive shield top surface 16b are formed in one step, further simplifying the manufacturing process of the semiconductor device.

[0197] In some embodiments, in the first direction z, the conductive shielding bottom end surface 16a is located on the side of the gate line bottom end surface 15a away from the conductive shielding top end surface 16b, that is, the gate line bottom end surface 15a is located between the conductive shielding bottom end surface 16a and the conductive shielding top end surface 16b. Through this design, the area where the gate voltage transmitted by the gate line 15 acts on the channel structure 114 is covered by the conductive shielding structure 16, thereby better improving the coupling effect between adjacent channel structures 114 in the second direction under the action of the gate voltage.

[0198] In some embodiments, Fig. 9BAs shown, the gate line 15 includes a first gate layer 151 and a second gate layer 152 of different materials, and the conductive shielding structure 16 includes a first conductive shielding layer 161. The first gate layer 151 is located between the second gate layer 152 and the sidewall of the channel structure 114. The gate insulating layer 128 is located between the first gate layer 151 and the sidewall of the channel structure 114. The isolation layer 127 is located between the first conductive shielding layer 161 and the sidewall of the channel structure 114. The material of the first gate layer 151 is the same as that of the first conductive shielding layer 161. The size of the first conductive shielding layer 161 along the second direction y is less than or equal to twice the size of the first gate layer 151 along the second direction y, so that the size of the conductive shielding structure 16 along the second direction y is less than twice the size of one gate line 15 along the second direction y.

[0199] In some other embodiments, the gate line 15 includes a first gate layer 151, and the conductive shielding structure 16 includes a first conductive shielding layer 161. The gate insulating layer 128 is located between the first gate layer 151 and the sidewall of the channel structure 114. The isolation layer 127 is located between the first conductive shielding layer 161 and the sidewall of the channel structure 114. The material of the first gate layer 151 is the same as that of the first conductive shielding layer 161. Therefore, the size of the first conductive shielding layer 161 along the second direction y is less than twice the size of the first gate layer 151 along the second direction y, so that the size of the conductive shielding structure 16 along the second direction y is less than twice the size of one gate line 15 along the second direction y.

[0200] In some other embodiments, the gate line 15 includes a first gate layer 151 and a second gate layer 152 of different materials, and the conductive shielding structure 16 includes a first conductive shielding layer 161 and a second conductive shielding layer 162 of different materials. The first gate layer 151 is located between the second gate layer 152 and the sidewall of the channel structure 114. The gate insulating layer 128 is located between the first gate layer 151 and the sidewall of the channel structure 114. The first conductive shielding layer 161 is located between the second conductive shielding layer 162 and the sidewall of the channel structure 114. The isolation layer 127 is located between the first conductive shielding layer 161 and the sidewall of the channel structure 114. The material of the first gate layer 151 is the same as the material of the first conductive shielding layer 161. The material of the second gate layer 152 is the same as the material of the second conductive shielding layer 162. The material of the second gate layer 152 is the same as the material of the second conductive shielding layer 162. The size of the first conductive shielding layer 161 along the second direction y is equal to twice the size of the first gate layer 151 along the second direction y, and the size of the second conductive shielding layer 162 along the second direction y is smaller than twice the size of the second gate layer 152 along the second direction y, so that the size of the conductive shielding structure 16 along the second direction y is smaller than twice the size of a gate line 15 along the second direction y.

[0201] It should be noted that, due to differences in processes, when the gate line 15 and the conductive shielding structure 16 are formed in one step, the composition of the conductive layer of the gate line 15 and the conductive layer of the conductive shielding structure 16 may be the same or different.

[0202] In addition, see Fig.10 and Fig.11 As shown, based on the same inventive concept, the present application further provides a storage system 400, which includes a memory 200 and a controller 300. The controller 300 is connected to the memory 200 and is used to control the memory 200. The memory 200 includes the semiconductor device 100 of any of the above embodiments.

[0203] Among them, the storage system 400 can be applied to and packaged into different types of electronic products, such as mobile phones (such as mobile phones), desktop computers, tablet computers, laptops, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.

[0204] In some embodiments, reference Fig.10 As shown, the memory system 400 includes a memory 200 and a controller 300. The memory system 400 may be integrated into a three-dimensional memory card.

[0205] Among them, the three-dimensional memory card includes any one of PC card (PCMCIA, Personal Computer Three-Dimensional Memory Card International Association), Compact Flash (CF) card, Smart Media (SM) card, three-dimensional memory, Multimedia Card (MMC), Secure Digital (SD) card, and UFS.

[0206] In other embodiments, reference Fig.11 As shown, the storage system 400 includes a plurality of memories 200 and a controller 300. The storage system 400 is integrated into a solid state drive (SSD).

[0207] In some embodiments, in the storage system 400, the controller 300 is configured to operate in a low duty cycle environment, such as an SD card, a CF card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile phones, etc.

[0208] In other embodiments, in the storage system 400, the controller 300 is configured to operate in a high duty cycle environment SSD or eMMC, which is used for data storage in mobile devices such as smart phones, tablets, laptops, and enterprise storage arrays.

[0209] In some embodiments, the controller 300 may be configured to manage data stored in the memory 200 and communicate with an external device (e.g., a host). In some embodiments, the controller 300 may also be configured to control operations of the memory 200, such as read, erase, and program operations. In some embodiments, the controller 300 may also be configured to manage various functions regarding data stored or to be stored in the memory 200, including at least one of bad block management, garbage collection, logical to physical address conversion, and wear leveling. In some embodiments, the controller 300 is also configured to process error correction codes for data read from or written to the memory 200.

[0210] Of course, the controller 300 may also perform any other suitable functions, such as formatting the memory 200; for example, the controller 300 may communicate with an external device (eg, a host) via at least one of various interface protocols.

[0211] It should be noted that the interface protocol includes at least one of the USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer interface (SCSI) protocol, enhanced minidisk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, and Firewire protocol.

[0212] Please refer to Fig.12 Some embodiments of the present application further provide an electronic device 500. The electronic device 500 may be any one of a mobile phone, a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, etc.

[0213] The electronic device 500 may include the above-mentioned storage system 400 and a host 600 , and the host 600 includes at least one of a central processing unit (CPU) and a cache.

[0214] The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technical personnel in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents. However, these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for manufacturing a semiconductor device, characterized in that: The method comprises: forming a plurality of channel lines extending along a first direction and a second direction in the semiconductor layer, wherein the first direction intersects with the second direction; forming a plurality of first grooves and a plurality of second grooves extending along the first direction and arranged along the second direction in the semiconductor layer, wherein the plurality of first grooves and the plurality of second grooves intersect with the plurality of channel lines to form a plurality of channel structures, and a size of the first groove along the second direction is smaller than a size of the second groove along the second direction; and A conductive layer is formed in the first grooves and the second grooves, and a portion of the conductive layer is removed. The remaining conductive layers in the first grooves form a plurality of conductive shielding structures, and the remaining conductive layers in the second grooves form a plurality of gate lines.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The forming of a plurality of first grooves and a plurality of second grooves extending along the first direction and arranged along the second direction in the semiconductor layer comprises: Forming a plurality of first initial grooves and a plurality of second initial grooves in the semiconductor layer, extending along the first direction and a third direction and alternately arranged along the second direction, wherein the size of the first initial grooves in the third direction is smaller than the size of the second initial grooves, and the third direction intersects the first direction and the second direction; Filling a sacrificial layer in the plurality of first initial grooves and the plurality of second initial grooves; removing the sacrificial layer in the plurality of second initial grooves, and enlarging the dimensions of the second initial grooves along the first direction and the second direction to form a plurality of second grooves; and The sacrificial layer in the plurality of first initial grooves is removed to form a plurality of first grooves.

3. The method for manufacturing a semiconductor device according to claim 2, wherein: Before removing the sacrificial layer in the plurality of second initial grooves, the method further comprises: removing a portion of the sacrificial layer in the plurality of first initial grooves; and A covering layer is formed on the remaining sacrificial layer in the plurality of first initial grooves.

4. The method for manufacturing a semiconductor device according to claim 3, characterized in that: Before removing the portion of the sacrificial layer in the plurality of first initial grooves, the method further includes: A protection layer covering the sacrificial layer in the plurality of second initial grooves is formed on one side of the semiconductor layer in the first direction.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: Before forming a conductive layer in the plurality of first grooves and the plurality of second grooves, the method further includes: An isolation layer is formed on the sidewall of the channel structure in the first groove, and a gate insulation layer is formed on the sidewall of the channel structure in the second groove.

6. The method for manufacturing a semiconductor device according to claim 5, characterized in that: The forming of a conductive layer in the plurality of first grooves and the plurality of second grooves comprises: A first conductive layer is formed to cover the isolation layer, fill the first groove, and cover the gate insulating layer in the second groove.

7. The method for manufacturing a semiconductor device according to claim 5, characterized in that: The forming of a conductive layer in the plurality of first grooves and the plurality of second grooves comprises: forming a first conductive layer covering the isolation layer and filling the first groove, and covering the gate insulating layer in the second groove; and A second conductive layer is formed in the second groove and covers the first conductive layer in the second groove, wherein a material of the second conductive layer is different from a material of the first conductive layer.

8. The method for manufacturing a semiconductor device according to claim 5, characterized in that: The forming of a conductive layer in the plurality of first grooves and the plurality of second grooves comprises: forming a first conductive layer covering the isolation layer in the first groove and the gate insulating layer in the second groove; and A second conductive layer is formed to cover the first conductive layer in the first groove and fill the first groove and to cover the first conductive layer in the second groove, wherein a material of the second conductive layer is different from a material of the first conductive layer.

9. The method for manufacturing a semiconductor device according to claim 2, wherein: After forming the plurality of second grooves and before forming the plurality of first grooves, the method further includes: An insulating raised portion is formed at the bottom of the second groove, and the insulating raised portion includes an insulating top surface away from the bottom surface of the second groove. In the first direction, the insulating top surface is located on the side of the bottom surface of the first initial groove close to the groove opening of the first initial groove.

10. The method for manufacturing a semiconductor device according to claim 1, wherein: The method further includes forming a lead-out conductive structure connected to the plurality of conductive shielding structures.

11. A semiconductor device, characterized in that: include: a plurality of channel structures extending along a first direction; A plurality of gate lines extending along the first direction, wherein one of the gate lines is located between adjacent channel structures in a second direction, and the second direction intersects the first direction; as well as a plurality of conductive shielding structures extending along the first direction, wherein the plurality of conductive shielding structures and the plurality of gate lines are arranged at intervals along the second direction, and one of the conductive shielding structures is located between adjacent channel structures in the second direction; Wherein, a size of the conductive shielding structure along the second direction is less than twice a size of one of the gate lines along the second direction.

12. The semiconductor device according to claim 11, characterized in that The semiconductor device further comprises: an insulating pad located at one side of the gate line in the first direction and in contact with the gate line; Wherein, in the first direction, the conductive shielding structure comprises a conductive shielding bottom end surface and a conductive shielding top end surface opposite to each other, and the conductive shielding bottom end surface is arranged close to the insulating pad portion; The gate line comprises a gate line bottom end surface contacting the insulating pad portion, and the conductive shield bottom end surface is located on a side of the gate line bottom end surface away from the conductive shield top end surface.

13. The semiconductor device according to claim 11, characterized in that The semiconductor device further includes: a gate insulating layer, the gate insulating layer being located between the gate line and a sidewall of the channel structure; and An isolation layer, wherein the isolation layer is located between the conductive shielding structure and the side wall of the channel structure, the thickness of the isolation layer is the same as the thickness of the gate insulating layer, and the material of the isolation layer is the same as the material of the gate insulating layer.

14. The semiconductor device according to claim 13, characterized in that The conductive shielding structure comprises a first conductive shielding layer, and the isolation layer is located between the first conductive shielding layer and the sidewall of the channel structure; The gate line includes a first gate layer. The gate insulating layer is located between the first gate layer and the sidewall of the channel structure. The material of the first gate layer is the same as that of the first conductive shielding layer.

15. The semiconductor device according to claim 13, wherein: The conductive shielding structure comprises a first conductive shielding layer, and the isolation layer is located between the first conductive shielding layer and the sidewall of the channel structure; The gate line includes a first gate layer and a second gate layer of different materials, the first gate layer is located between the second gate layer and the side wall of the channel structure, the gate insulating layer is located between the first gate layer and the side wall of the channel structure, and the material of the first gate layer is the same as that of the first conductive shielding layer.

16. The semiconductor device according to claim 13, characterized in that The conductive shielding structure comprises a first conductive shielding layer and a second conductive shielding layer made of different materials, the first conductive shielding layer is located between the second conductive shielding layer and the side wall of the channel structure, and the isolation layer is located between the first conductive shielding layer and the side wall of the channel structure; The gate line includes a first gate layer and a second gate layer of different materials, the first gate layer is located between the second gate layer and the side wall of the channel structure, the gate insulating layer is located between the first gate layer and the side wall of the channel structure, the material of the first gate layer is the same as the material of the first conductive shielding layer, and the material of the second gate layer is the same as the material of the second conductive shielding layer.

17. The semiconductor device according to claim 11, characterized in that The semiconductor device further comprises: a lead-out conductive structure connected to the conductive shielding structure.

18. A storage system, characterized in that: include: A memory, comprising a semiconductor device as claimed in any one of claims 11 to 17; as well as The controller is connected to the memory and is used to control the memory.

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