Semiconductor device and method of manufacturing the same

Abstract

The present invention relates to a semiconductor device having highly integrated memory cells and a method for manufacturing the same. The method for manufacturing a semiconductor device according to the present technology comprises the steps of: forming a cell mold in which a plurality of mold layers are laminated on an upper portion of a lower structure; a step of removing a portion of the unit mold to form a linear vertical opening vertically oriented along a stacking direction of the unit mold; a step of forming a storage opening extending horizontally from the linear vertical opening; and a step of forming a data storage element in the storage opening.

Description

Technical Field

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device including a three-dimensional memory cell and a method for manufacturing the same. Background Art

[0002] Recently, in order to cope with the increase in capacity and the reduction in size of memory devices, a technology for providing a three-dimensional memory device in which a plurality of memory cells are stacked has been proposed. Summary of the invention

[0003] (Problems to be solved by the invention)

[0004] Embodiments of the present invention provide a semiconductor device having a highly integrated memory cell and a method for manufacturing the same.

[0005] (Measures taken to solve the problem)

[0006] The manufacturing method of the semiconductor device involved in an embodiment of the present invention includes: a step of forming a unit mold with multiple mold layers stacked on the upper part of a lower structure; a step of removing a portion of the unit mold to form a linear vertical opening vertically oriented along the stacking direction of the unit mold; a step of forming a storage opening extending horizontally from the linear vertical opening; and a step of forming a data storage element in the storage opening.

[0007] The manufacturing method of the semiconductor device involved in an embodiment of the present invention includes: a step of forming a unit mold on the upper part of a lower structure, in which a first sacrificial layer, a semiconductor layer, and a second sacrificial layer are stacked in sequence; a step of removing the first part of the unit mold to form a linear vertical opening oriented vertically along the stacking direction of the unit mold; a step of removing the second part of the unit mold to form a hole-type vertical opening oriented vertically along the stacking direction of the unit mold; a step of forming a switching element horizontally oriented from the hole-type vertical opening; a step of forming a vertical conductive line connected to the switching element in the hole-type vertical opening; a step of forming a storage opening extending horizontally from the linear vertical opening; and a step of forming a data storage element in the storage opening.

[0008] The manufacturing method of the three-dimensional capacitor involved in the embodiment of the present invention includes: the step of forming a mold on the upper part of the lower structure, in which a first silicon nitride, a semiconductor layer, and a second silicon nitride are stacked in sequence; the step of forming a unit separation layer vertically oriented along the stacking direction of the mold on the mold; the step of removing a part of the mold and a part of the unit separation layer to form a linear vertical opening vertically oriented along the stacking direction of the mold; the step of making the first silicon nitride, the semiconductor layer, and the second silicon nitride horizontally recessed from the linear vertical opening to form a storage opening; the step of forming a first electrode in the storage opening; the step of forming a dielectric layer on the first electrode; and the step of forming a second electrode on the dielectric layer.

[0009] The manufacturing method of the semiconductor device involved in an embodiment of the present invention includes: a step of forming a unit mold including a horizontal layer on the upper part of a lower structure; a step of forming a first unit separation layer and a second unit separation layer in the unit mold; a step of etching a first portion of the unit mold to form a first linear vertical opening between the second unit separation layers; a step of forming a horizontal conductive line horizontally spaced apart from the first linear vertical opening and overlapping the horizontal layer; a step of cutting a portion of the horizontal layer from the first linear vertical opening to form a vertical expansion portion; and a step of forming a vertical conductive line in the vertical expansion portion, wherein the vertical conductive line is connected to a side surface of the horizontal layer and self-aligned with a side surface of the second unit separation layer.

[0010] The semiconductor device involved in an embodiment of the present invention includes: a horizontal layer, which is arranged on the upper part of a lower structure and has a first edge and a second edge; a first unit separation layer, which is located around the second edge of the horizontal layer and extends vertically from the lower structure; a second unit separation layer, which is located around the first edge of the horizontal layer and extends vertically from the lower structure; a vertical conductive line, which is connected to the first edge of the horizontal layer and self-aligned with a side surface of the second unit separation layer; and a data storage element, which is connected to the second edge of the horizontal layer and is located between the first unit separation layers.

[0011] (Effects of the Invention)

[0012] This technology applies a lines patterning method to form a three-dimensional data storage element, thereby improving the yield rate. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1A FIG. 1 is a simplified three-dimensional diagram of a memory cell according to an embodiment.

[0014] Figure 1B for Figure 1AA simplified cross-sectional view of a memory cell in FIG.

[0015] Figure 1C for Figure 1A Top view of the switching element in FIG.

[0016] Figure 1D FIG. 4 is a schematic cross-sectional view of a memory cell according to another embodiment.

[0017] Figure 2 FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention.

[0018] Figure 3A for Figure 2 A simplified three-dimensional diagram of the memory cell array MCA1 in FIG.

[0019] Figure 3B for Figure 2 A simplified cross-sectional view of the memory cell array MCA1 in FIG.

[0020] FIG. 4A to FIG. 26B A diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment.

[0021] Fig.27A and Fig.27B It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to another embodiment.

[0022] Fig.28A FIG. 1 is a schematic top view of a semiconductor device according to another embodiment.

[0023] Fig.28B For along Fig.28A A-A' cross-sectional view.

[0024] FIG. 28C to FIG. 28E FIG. 4 is a diagram for explaining electrical connection between a first vertical conductive line and a second vertical conductive line.

[0025] Fig.28F FIG. 1 is a diagram for explaining a separation structure of a first vertical conductive line and a second vertical conductive line.

[0026] FIG. 29A to FIG. 46B A diagram for explaining an example of a method for manufacturing a semiconductor device according to another embodiment.

[0027] FIG. 47A to FIG. 47C A diagram for explaining an example of a method for manufacturing a semiconductor device according to another embodiment.

[0028] Fig.48 FIG. 1 is a schematic top view of a semiconductor device according to another embodiment.

[0029] Fig.49A and Fig.49BA diagram for explaining an example of a method for manufacturing a semiconductor device according to another embodiment.

[0030] Fig.50A FIG. 1 is a schematic top view of a semiconductor device according to another embodiment.

[0031] Fig.50B For along Fig.50A A-A' cross-sectional view.

[0032] Fig.50C for Fig.50A A simplified three-dimensional diagram of a semiconductor device.

[0033] Fig.51A FIG. 1 is a schematic top view of a semiconductor device according to another embodiment.

[0034] Fig.51B For along Fig.51A A-A' cross-sectional view.

[0035] Fig.51C for Fig.51A A simplified three-dimensional diagram of a semiconductor device.

[0036] Fig.52A FIG. 1 is a schematic top view of a semiconductor device according to another embodiment.

[0037] Fig.52B For along Fig.52A A-A' cross-sectional view. DETAILED DESCRIPTION

[0038] The embodiments described in this specification are described with reference to the cross-sectional views, top views and block diagrams which are ideal schematic diagrams of the present invention. Therefore, the form of the example diagram may be deformed due to manufacturing technology and / or tolerances. Therefore, the embodiments of the present invention are not limited to the specific forms shown in the figure, but include changes in form caused by the manufacturing process. Therefore, the areas illustrated in the figure have schematic properties, and the shapes of the areas illustrated in the figure are used to illustrate the specific forms of the areas of the device, and are not intended to limit the scope of the present invention.

[0039] The following embodiments relate to three-dimensional memory cells, which are vertically stacked to increase memory cell density and reduce parasitic capacitance.

[0040] Figure 1A FIG. 1 is a simplified three-dimensional diagram of a memory cell according to an embodiment. Figure 1B for Figure 1A A simplified cross-sectional view of a memory cell in FIG. Figure 1C for Figure 1ATop view of the switching element in FIG.

[0041] Reference Figures 1A to 1C , the memory cell MC includes: a first conductive line BL, a switching element TR and a data storage element CAP.

[0042] The first conductive line BL is vertically oriented along the first direction D1. The first conductive line BL includes a bit line. The first conductive line BL may be referred to as a vertical conductive line, a vertically-oriented bit line, a vertically-extended bit line, or a pillar-shape bit line. The first conductive line BL may include a conductive material. The first conductive line BL may include a silicon-base material, a metal-base material, or a combination thereof. The first conductive line BL may include polysilicon, a metal, a metal nitride, a metal silicide, or a combination thereof. The first conductive line BL may include polysilicon, titanium nitride, tungsten, or a combination thereof. For example, the first conductive line BL may include polysilicon or titanium nitride (TiN) doped with N-type impurities. The first conductive line BL may include a stack of titanium nitride and tungsten (TiN / W).

[0043] In the data writing action and data reading action of the data storage element CAP, the switching element TR has the function of controlling the voltage (or current) supplied to the data storage element CAP. The switching element TR includes: a horizontal layer HL, an interlevel dielectric layer GD, and a second conductive line DWL. The second conductive line DWL includes a horizontal conductive line or a word line, and the horizontal layer HL includes an active layer. The switching element TR includes a transistor, in which case the second conductive line DWL performs the function of a gate. The switching element TR can also be referred to as an access element or a selection element. The second conductive line DWL can be referred to as a horizontal gate or a horizontal word line.

[0044] The horizontal layer HL extends along a second direction D2 intersecting the first direction D1. The second conductive line DWL extends along a third direction D3 intersecting the first direction D1 and the second direction D2. The first direction D1 is a vertical direction, the second direction D2 is a first horizontal direction, and the third direction D3 is a second horizontal direction. The horizontal layer HL extends along the first horizontal direction (i.e., D2), and the second conductive line DWL extends along the second horizontal direction (i.e., D3).

[0045] The horizontal layer HL is horizontally oriented along the second direction D2 from the first conductive line BL. The second conductive line DWL is a double structure. For example, the second conductive line DWL includes an upper horizontal line G1 and a lower horizontal line G2 that face each other with the horizontal layer HL in between. An interlayer insulating layer GD is formed on the upper surface and the lower surface of the horizontal layer HL. The upper horizontal line G1 is located at the upper part of the horizontal layer HL, and the lower horizontal line G2 is located at the lower part of the horizontal layer HL. The second conductive line DWL includes a pair of upper horizontal lines G1 and lower horizontal lines G2. In the second conductive line DWL, the same driving voltage can be applied to the upper horizontal line G1 and the lower horizontal line G2. For example, the upper horizontal line G1 and the lower horizontal line G2 are connected to the memory cell MC in pairs. In another embodiment, different driving voltages are applied to the upper horizontal line G1 and the lower horizontal line G2. In this case, one of the upper horizontal line G1 and the lower horizontal line G2 performs the role of a back gate or a shield gate.

[0046] Refer again Figure 1C , the width of each of the upper horizontal line G1 and the lower horizontal line G2 in the second direction D2, for example, the width of the overlapping portion overlapping with the horizontal layer HL is greater than the width of the portion not overlapping with the horizontal layer HL. Due to the above-mentioned width difference, the second conductive line DWL may have two notch-shaped sidewalls. The notch-shaped sidewalls of the second conductive line DWL may be symmetrical to each other.

[0047] The second conductive line DWL includes a channel overlapping portion WLP. The channel overlapping portion WLP is in a cross shape or a diamond shape.

[0048] When viewed from a top view, the horizontal layer HL is in a cross shape or a diamond shape. In another embodiment, the side surface of the horizontal layer HL may be in a bent shape or a rounded shape.

[0049] The horizontal layer HL may include a semiconductor material. For example, the horizontal layer HL may include polycrystalline silicon, single crystal silicon, germanium, or silicon-germanium. In another embodiment, the horizontal layer HL may include an oxide semiconductor material. For example, the oxide semiconductor material may include indium gallium zinc oxide (IGZO). In another embodiment, the horizontal layer HL may include a conductive metal oxide. In another embodiment, the horizontal layer HL may include a two-dimensional material, such as MoS2, WS2, or MoSe2.

[0050] The upper surface and the lower surface of the horizontal layer HL have flat surfaces, that is, the upper surface and the lower surface of the horizontal layer HL are parallel to each other along the second direction D2.

[0051] The horizontal layer HL includes a channel CH, a first doped region SR between the channel CH and the first conductive line BL, and a second doped region DR between the channel CH and the data storage element CAP. In the case where the horizontal layer HL is an oxide semiconductor material, the channel CH may be formed of an oxide semiconductor material, and the first doped region SR and the second doped region DR may be omitted. The horizontal layer HL may also be referred to as an active layer or a thin-body. The channel CH and the channel overlap portion WLP of the second conductive line DWL may overlap each other. The channel CH may be in a cross shape or a diamond shape. The size of the channel overlap portion WLP of the second conductive line DWL is larger than the channel CH. The channel overlap portion WLP of the second conductive line DWL may fully overlap with the channel CH.

[0052] The first doping region SR and the second doping region DR may be doped with impurities of the same conductivity type. The first doping region SR and the second doping region DR may be doped with N-type conductivity type impurities or P-type conductivity type impurities. The first doping region SR and the second doping region DR may contain at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and a combination thereof. The first doping region SR is connected to the first conductive line BL, and the second doping region DR is connected to the data storage element CAP. The first doping region SR and the second doping region DR may be referred to as the first and second source / drain regions.

[0053] The interlayer insulating layer GD is located between the horizontal layer HL and the second conductive line DWL. The interlayer insulating layer GD may be referred to as a gate dielectric layer. The interlayer insulating layer GD may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, anti-ferroelectric material, or a combination thereof. The interlayer insulating layer GD may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, HfZrO, or a combination thereof. The interlayer insulating layer GD may be formed by thermal oxidation of a semiconductor material.

[0054] The second conductive line DWL may include a metal-base material, a semiconductor material, or a combination thereof. The second conductive line DWL may include titanium nitride, tungsten, polysilicon, molybdenum, molybdenum nitride, or a combination thereof. For example, the second conductive line DWL may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The second conductive line DWL may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function (Low work function) of less than 4.5 eV, and the P-type work function material may have a high work function (High work function) of more than 4.5 eV. The second conductive line DWL may include a stack of a low work function material and a high work function material.

[0055] The data storage element CAP includes a memory element such as a capacitor. The data storage element CAP is horizontally arranged along the second direction D2 from the switch element TR. The data storage element CAP includes a first electrode SN extending horizontally from the horizontal layer HL along the second direction D2. The data storage element CAP also includes a second electrode PN on the first electrode SN and a dielectric layer DE between the first electrode SN and the second electrode PN. The first electrode SN, the dielectric layer DE and the second electrode PN are horizontally arranged along the second direction D2. The first electrode SN includes an inner space and a plurality of outer surfaces, and the inner space of the first electrode SN includes a plurality of inner surfaces. The outer surface of the first electrode SN includes a vertical outer surface and a plurality of horizontal outer surfaces. The vertical outer surface of the first electrode SN extends vertically along the first direction D1, and the horizontal outer surface of the first electrode SN may extend horizontally along the second direction D2 or the third direction D3. The inner space of the first electrode SN may be a three-dimensional space. The dielectric layer DE conformally covers the inner and outer surfaces of the first electrode SN. The second electrode PN is arranged in the inner space of the first electrode SN on the dielectric layer DE. A portion of the outer side surfaces of the first electrode SN is electrically connected to the second doping region DR of the horizontal layer HL.

[0056] The data storage element CAP is a three-dimensional structure. The first electrode SN has a three-dimensional structure, and the first electrode SN of the three-dimensional structure is a horizontal three-dimensional structure oriented along the second direction D2. As an example of a three-dimensional structure, the first electrode SN is a cylinder shape. The cylinder shape of the first electrode SN includes a cylinder inner surface and a cylinder outer surface. A portion of the outer surface of the cylinder outer surface of the first electrode SN is electrically connected to the second doping region DR of the horizontal layer HL. The dielectric layer DE and the second electrode PN are arranged on the cylinder inner surface of the first electrode SN.

[0057] In another embodiment, the first electrode SN has a pillar shape or a pylinder shape. The pylinder shape refers to a structure in which a pillar shape and a pylinder shape are merged.

[0058] The first electrode SN and the second electrode PN may include a metal, a noble metal, a metal nitride, a conductive metal oxide, a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, titanium silicon nitride / titanium nitride (TiSiN / TiN) stack, or a combination thereof. The second electrode PN may also include a combination of a metal-based material and a silicon-based material. For example, the second electrode PN may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium may be a gap filling material filling the inside of the first electrode SN, titanium nitride (TiN) may perform the role of the second electrode PN of the data storage element CAP, and tungsten nitride may be a low resistance material.

[0059] The dielectric layer DE may be referred to as a capacitor dielectric layer or a memory layer. The dielectric layer DE may include silicon oxide, silicon nitride, a high dielectric constant material, a perovskite material, or a combination thereof. The high dielectric constant material may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). In another embodiment, the dielectric layer DE may also be formed by a composite layer including two or more layers of the aforementioned high dielectric constant materials.

[0060] The dielectric layer DE may be formed of a zirconium-based oxide (Zr-base oxide). The dielectric layer DE may be a stacked structure including zirconium oxide (ZrO2). The dielectric layer DE may include a ZA (ZrO2 / Al2O3) stack or a ZAZ (ZrO2 / Al2O3 / ZrO2) stack. The ZA stack may be a structure in which aluminum oxide (Al2O3) is stacked on zirconium oxide (ZrO2). The ZAZ stack may be a structure in which zirconium oxide (ZrO2), aluminum oxide (Al2O3) and zirconium oxide (ZrO2) are stacked in sequence. The ZA stack and the ZAZ stack may be referred to as a zirconium oxide-based layer (ZrO2-base layer). In another embodiment, the dielectric layer DE may be formed of a hafnium-based oxide (Hf-base oxide). The dielectric layer DE may be a stack including hafnium oxide (HfO2). The dielectric layer DE may include a HA (HfO2 / Al2O3) stack or a HAH (HfO2 / Al2O3 / HfO2) stack. The HA stack may be a structure in which aluminum oxide (Al2O3) is stacked on hafnium oxide (HfO2). The HAH stack may be a structure in which hafnium oxide (HfO2), aluminum oxide (Al2O3) and hafnium oxide (HfO2) are stacked in sequence. The HA stack and the HAH stack may be referred to as a hafnium oxide-based layer (HfO2-base layer). The band gap energy (Band gap Energy) of aluminum oxide (Al2O3) in the ZA stack, the ZAZ stack, the HA stack and the HAH stack may be greater than the band gap energy (Band gap Energy) of zirconium oxide (ZrO2) and hafnium oxide (HfO2). The dielectric constant of aluminum oxide (Al2O3) may be lower than the dielectric constant of zirconium oxide (ZrO2) and hafnium oxide (HfO2). Therefore, the dielectric layer DE may include a stack of a high band gap material having a band gap energy higher than a high dielectric constant material and a high dielectric constant material. In addition to aluminum oxide (Al2O3), the dielectric layer DE may also include silicon oxide (SiO2) as another high band gap material. The dielectric layer DE includes the high band gap material, so leakage current can be suppressed. The high band gap material can be thinner than the high dielectric constant material. In another embodiment, the dielectric layer DE may include a stacked structure in which the high dielectric constant material and the high band gap material are alternately stacked. For example, the dielectric layer DE may include a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack.In the above stacked structure, aluminum oxide (Al 2 O 3 ) may be thinner than zirconium oxide (ZrO 2 ) and hafnium oxide (HfO 2 ).

[0061] In another embodiment, the dielectric layer DE includes a high dielectric constant material and a high bandgap material, and may include a laminated structure of a plurality of high dielectric constant materials and a plurality of high bandgap materials or a mixed structure of a high dielectric constant material and a high bandgap material intermixing.

[0062] In another embodiment, the dielectric layer DE may include a ferroelectric material, an antiferroelectric material, or a combination thereof. For example, the dielectric layer DE may include HfZrO.

[0063] In another embodiment, the dielectric layer DE may include a combination of a high dielectric constant material and a ferroelectric material, a combination of a high dielectric constant material and an antiferroelectric material, or a combination of a high dielectric constant material or a ferroelectric material and an antiferroelectric material.

[0064] In another embodiment, an interface control layer for improving leakage current may be formed between the first electrode SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode PN and the dielectric layer DE.

[0065] The data storage element CAP may include a three-dimensional capacitor. The data storage element CAP includes a MIM (Metal-Insulator-Metal) capacitor. The data storage element CAP may also be replaced by other data storage materials. For example, the data storage material is a thyristor, a phase change material, an MTJ (Magnetic Tunnel Junction) or a variable resistance material.

[0066] For example, the memory cell MC includes a thyristor, the first conductive line BL is a cathode line, and the data storage element CAP can be replaced by an anode line. Thus, the horizontal layer HL includes four semiconductor layers stacked along the second direction D2. The thyristor includes a first diode and a second diode connected in series. When a forward bias of the same voltage is applied to the thyristor, the thyristor has a high conductance state in which a large current flows or a low conductance state in which a small current flows or does not flow. The memory cell MC of this embodiment utilizes the high conductance state and the low conductance state of the thyristor to have a "1" state and a "0" state, respectively.

[0067] Refer again Figure 1A and Figure 1B , the memory cell MC also includes a first contact node BLC and a second contact node SNC. The first contact node BLC surrounds the outer wall of the first conductive line BL. The second contact node SNC is arranged between the horizontal layer HL and the first electrode SN. The first contact node BLC may include a metal-based material or a semiconductor material. The second contact node SNC may include a metal-based material or a semiconductor material. For example, the first contact node BLC and the second contact node SNC may include titanium, titanium nitride, tungsten or a combination thereof. Moreover, the first contact node BLC and the second contact node SNC may include doped polysilicon, and the first doping region SR and the second doping region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0068] Figure 1D FIG. 4 is a schematic cross-sectional view of a memory cell according to another embodiment. Figure 1D The memory cell MC1 can be connected with Figures 1A to 1C Hereinafter, detailed description of the repeated structural elements will be omitted.

[0069] The memory cell MC1 includes a first conductive line BL, a switching element TR and a data storage element CAP. The switching element TR includes a horizontal layer HL, an interlayer insulating layer GD and a second conductive line DWL. The horizontal layer HL includes a first doped region SR, a second doped region DR and a channel CH. The data storage element CAP includes a first electrode SN, a second electrode PN and a dielectric layer DE.

[0070] The memory cell MC1 also includes a first contact node BLC between the first conductive line BL and the horizontal layer HL and a second contact node SNC between the horizontal layer HL and the data storage element CAP. The first contact node BLC and the second contact node SNC may include doped polysilicon. The first doped region SR and the second doped region DR may include impurities diffused from the first contact node BLC and the second contact node SNC, respectively.

[0071] The second conductive line DWL includes an upper horizontal line G1 and a lower horizontal line G2. The upper horizontal line G1 and the lower horizontal line G2 include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13, respectively. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 are horizontally arranged along the second direction D2. The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 are in direct contact with each other. The second work function electrode G12 is adjacent to the first conductive line BL, and the third work function electrode G13 is adjacent to the data storage element CAP. The horizontal layer HL has a thickness thinner than the first work function electrode G11, the second work function electrode G12, and the third work function electrode G13.

[0072] The first work function electrode G11, the second work function electrode G12, and the third work function electrode G13 are formed of different work function materials. The work function of the first work function electrode G11 is higher than the work function of the second work function electrode G12 and the third work function electrode G13. The first work function electrode G11 may include a high work function material. The first work function electrode G11 may have a work function higher than the mid-gap work function of silicon. The second work function electrode G12 and the third work function electrode G13 may include a low work function material. The second work function electrode G12 and the third work function electrode G13 may have a work function lower than the mid-gap work function of silicon. Specifically, the high work function material may have a work function higher than 4.5 eV, and the low work function material may have a work function lower than 4.5 eV. The first work function electrode G11 may include a metal-based material, and the second work function electrode G12 and the third work function electrode G13 may include a semiconductor material.

[0073] The second work function electrode G12 and the third work function electrode G13 may include N-type dopant doped polysilicon. The first work function electrode G11 may include metal, metal nitride, or a combination thereof. The first work function electrode G11 may include tungsten, titanium nitride, or a combination thereof. A barrier material may also be formed between the second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11.

[0074] In the present embodiment, the upper horizontal line G1 and the lower horizontal line G2 of the second conductive line DWL are respectively arranged horizontally along the second direction D2 in the order of the second work function electrode G12-the first work function electrode G11-the third work function electrode G13. The first work function electrode G11 may include metal, and the second work function electrode G12 and the third work function electrode G13 may include polysilicon.

[0075] The upper horizontal line G1 and the lower horizontal line G2 of the second conductive line DWL are respectively PMP (Poly Si-Metal-Poly Si) structures horizontally arranged along the second direction D2. In the PMP structure, the first work function electrode G11 can be a metal-based material, and the second work function electrode G12 and the third work function electrode G13 can be doped polysilicon doped with an N-type dopant. The N-type dopant can include phosphorus or arsenic.

[0076] The first barrier layer G12L is located between the first work function electrode G11 and the second work function electrode G12. The second barrier layer G13L is located between the first work function electrode G11 and the third work function electrode G13. The first barrier layer G12L and the second barrier layer G13L may include titanium nitride, tantalum nitride, tungsten nitride or molybdenum nitride. The second barrier layer G13L may cover the upper surface, the lower surface and a side surface of the first work function electrode G11.

[0077] The volume of the first work function electrode G11 may be greater than the volume of the second work function electrode G12 and the third work function electrode G13, so the second conductive line DWL has a low impedance. The first work function electrode G11 of the upper horizontal line G1 and the lower horizontal line G2 is separated by a horizontal layer HL and vertically overlaps along the first direction D1. The second work function electrode G12 and the third work function electrode G13 of the upper horizontal line G1 and the lower horizontal line G2 are separated by a horizontal layer HL and vertically overlap along the first direction D1. The overlapping area of ​​the first work function electrode G11 and the horizontal layer HL is greater than the overlapping area of ​​the second work function electrode G12 and the third work function electrode G13 and the horizontal layer HL. The second work function electrode G12 and the third work function electrode G13 and the first work function electrode G11 extend along the third direction D3, and the second work function electrode G12 and the third work function electrode G13 can directly contact the first work function electrode G11.

[0078] As described above, the upper horizontal line G1 and the lower horizontal line G2 are triple work function electrode structures including a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13. The second conductive line DWL includes a pair of first work function electrodes G11, a pair of second work function electrodes G12, and a pair of third work function electrodes G13 extending along a third direction D3 across the horizontal layer HL with the horizontal layer HL in between. The first work function electrode G11, the plurality of second work function electrodes G12, and the plurality of third work function electrodes G13 overlap vertically with the channel CH.

[0079] The second conductive line DWL includes Figure 1C The channel overlap portion WLP is shown. The channel overlap portion WLP is a cross-shape or a diamond shape. The channel overlap portion WLP fully overlaps with the channel CH. Due to the channel overlap portion WLP, the second conductive line DWL may have notch-shape sidewalls. The channel overlap portion WLP includes a plurality of first work function electrodes G11, a plurality of second work function electrodes G12, and a plurality of third work function electrodes G13, and the plurality of first work function electrodes G11, the plurality of second work function electrodes G12, and the plurality of third work function electrodes G13 vertically overlap with the channel CH.

[0080] Along the second direction D2, a first work function electrode G11 with a high work function is arranged at the center of the second conductive line DWL, and a second work function electrode G12 and a third work function electrode G13 with a low work function are arranged at both ends of the second conductive line DWL, thereby improving leakage current such as GIDL (Gate Induced Drain leakage).

[0081] A first work function electrode G11 with a high work function is disposed at the center of the second conductive line DWL, thereby increasing the threshold voltage of the switch element TR. The second work function electrode G12 of the second conductive line DWL has a low work function, thereby forming a low electric field between the first conductive line BL and the second conductive line DWL. The third work function electrode G13 of the second conductive line DWL has a low work function, thereby forming a low electric field between the data storage element CAP and the second conductive line DWL.

[0082] As described above, the memory cell MC1 includes a second conductive line DWL having a triple work function electrode structure. The upper horizontal line G1 and the lower horizontal line G2 of the second conductive line DWL include a first work function electrode G11, a second work function electrode G12, and a third work function electrode G13, respectively. The first work function electrode G11 overlaps with the channel CH, the second work function electrode G12 is adjacent to the first conductive line BL and the first doping region SR, and the third work function electrode G13 is adjacent to the data storage element CAP and the second doping region DR. Due to the low work function of the second work function electrode G12, a low electric field is formed between the second conductive line DWL and the first conductive line BL, which can improve the leakage current. Due to the low work function of the third work function electrode G13, a low electric field is formed between the second conductive line DWL and the data storage element CAP, which can improve the leakage current. Due to the high work function of the first work function electrode G11, not only a high threshold voltage of the switching element TR is formed, but also the height of the memory cell MC1 can be reduced due to the formation of a low electric field, so it is also advantageous in terms of integration.

[0083] Figure 2 FIG. 1 is a schematic top view of a semiconductor device according to an embodiment of the present invention. Figure 3A for Figure 2 A simplified three-dimensional diagram of the memory cell array MCA1 in FIG. Figure 3B for Figure 2 A simplified cross-sectional view of the memory cell array MCA1 in FIG.

[0084] Reference Figure 2 , Figure 3A and Figure 3B , the semiconductor device 100 includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory cells MC. Each memory cell MC can refer to Figures 1A to 1C Each memory cell MC includes a first conductive line BL, a switching element TR, and a data storage element CAP.

[0085] The memory cell array MCA includes a three-dimensional array of a plurality of memory cells MC. The three-dimensional array of a plurality of memory cells MC includes a column array of a plurality of memory cells MC and a row array of a plurality of memory cells MC. In the column array of a plurality of memory cells MC, a plurality of memory cells MC are stacked along a first direction D1, and in the row array of a plurality of memory cells MC, a plurality of memory cells MC are horizontally arranged along a second direction D2 and a third direction D3. The memory cell array MCA includes a plurality of sub-memory cell arrays MCA1 adjacent to each other along the second direction D2. The sub-memory cell array MCA1 is a mirror-type structure in which two memory cells MC share a first conductive line BL. In another embodiment, the semiconductor device 100 further includes a plurality of sub-memory cell arrays of a mirror-type structure in which two memory cells MC share a second electrode PN of a data storage element CAP. The memory cell array MCA includes a plurality of sub-memory cell arrays MCA1 in which a plurality of memory cells MC are vertically stacked along the first direction D1. The memory cell array MCA includes a plurality of sub-memory cell arrays MCA1 horizontally arranged along a third direction D3.

[0086] An inter-cell dielectric layer IL is disposed between a plurality of memory cells MC stacked along the first direction D1. The inter-cell dielectric layer IL may include silicon oxide.

[0087] A plurality of cell separation layers ISOA and ISOB are disposed between a plurality of memory cells MC adjacent to each other along a third direction D3. The plurality of cell separation layers ISOA and ISOB may include silicon oxide, silicon carbide oxide (SiCO), silicon nitride, or a combination thereof. The plurality of cell separation layers ISOA and ISOB include a plurality of first cell separation layers ISOA and a plurality of second cell separation layers ISOB. The plurality of first cell separation layers ISOA and the plurality of second cell separation layers ISOB extend vertically along the first direction D1. The plurality of first cell separation layers ISOA and the plurality of second cell separation layers ISOB are pillar structures extending vertically along the first direction D1. The plurality of first cell separation layers ISOA and the plurality of second cell separation layers ISOB are alternately and repeatedly disposed along the second direction D2. The plurality of first cell separation layers ISOA are disposed between the plurality of data storage elements CAP along the third direction D3. The plurality of second cell separation layers ISOB are disposed between the plurality of first conductive lines BL along the third direction D3. The second conductive line DWL is disposed between the plurality of first cell separation layers ISOA and the plurality of second cell separation layers ISOB along the second direction D2.

[0088] The memory cell array MCA may be located on the upper portion of the lower structure LS.

[0089] The memory cell array MCA includes a plurality of second conductive lines DWL vertically stacked along a first direction D1. The memory cell array MCA includes a plurality of horizontal layers HL vertically stacked along the first direction D1. The memory cell array MCA includes a plurality of data storage elements CAP vertically stacked along the first direction D1. The memory cell array MCA includes a plurality of first conductive lines BL spaced apart along a third direction D3.

[0090] The second conductive lines DWL include Figure 1C The channel overlapping portion WLP shown. The channel overlapping portion WLP is a cross-shape or a diamond shape. The channel overlapping portion WLP completely overlaps with the channel CH. The second conductive line DWL extending along the third direction D3 includes a plurality of channel overlapping portions WLP. A plurality of channel overlapping portions WLP and a plurality of channel non-overlapping portions (with reference numerals omitted) are alternately repeated along the third direction D3, so that the second conductive line DWL has a notch-shaped sidewall.

[0091] A plurality of first protection layers BF1 are provided between the bottom second conductive line DWL among the plurality of second conductive lines DWL and the lower structure LS. A second protection layer BF2 is provided between the first conductive line BL and the lower structure LS. A plurality of third protection layers BF3 are provided between the data storage element CAP and the lower structure LS. The first protection layer BF1, the second protection layer BF2 and the third protection layer BF3 include insulating materials. The first protection layer BF1, the second protection layer BF2 and the third protection layer BF3 may include silicon oxide. Under the action of the first protection layer BF1, the second protection layer BF2 and the third protection layer BF3, the first conductive line BL, the second conductive line DWL and the plurality of data storage elements CAP are electrically separated from the lower structure LS. The first protection layer BF1, the second protection layer BF2 and the third protection layer BF3 may be referred to as a bottom dielectric layer or a bottom passivation layer. A bottom interlayer insulating layer LIL is provided between the plurality of first protection layers BF1 and the data storage element CAP.

[0092] The plurality of first conductive lines BL extend vertically from the upper portion of the lower structure LS along the first direction D1. The plurality of horizontal layers HL extend along the second direction D2 intersecting the first direction D1. The second conductive lines DWL extend along the third direction D3 intersecting the first direction D1 and the second direction D2.

[0093] When viewed from a top view, the horizontal layer HL is in a cross shape or a diamond shape. In another embodiment, the side of the horizontal layer HL may be in a curved shape or a circular shape. Figure 1B As shown, the horizontal layer HL includes a channel CH, a first doping region SR between the channel CH and the first conductive line BL, and a second doping region DR between the channel CH and the data storage element CAP.

[0094] The first cover layer BC is located between the second conductive line DWL and the first conductive line BL. The second cover layer CC is located between the second conductive line DWL and the first electrode SN of the data storage element. The first cover layer BC is arranged between the upper horizontal line G1 and the first conductive line BL, and the first cover layer BC is arranged between the lower horizontal line G2 and the first conductive line BL. The second cover layer CC is arranged between the upper horizontal line G1 and the first electrode SN of the data storage element CAP, and the second cover layer CC is arranged between the lower horizontal line G2 and the first electrode SN of the data storage element CAP. One memory cell MC includes a pair of first cover layers BC and a pair of second cover layers CC.

[0095] The first capping layer BC and the second capping layer CC may include insulating materials. The first capping layer BC and the second capping layer CC may include silicon oxide, silicon nitride, silicon oxycarbide, air gaps, or combinations thereof. The first capping layer BC may include silicon oxide, and the second capping layer CC may include a stack of silicon oxide and silicon nitride.

[0096] Multiple horizontal layers HL of multiple switching elements TR horizontally arranged along the third direction D3 share one second conductive line DWL. Multiple horizontal layers HL of multiple switching elements TR horizontally arranged along the third direction D3 are connected to mutually different first conductive lines BL. Multiple switching elements TR stacked along the first direction D1 share one first conductive line BL. Multiple switching elements TR horizontally arranged along the third direction D3 share one second conductive line DWL.

[0097] The plurality of first cell separation layers ISOA are disposed between the plurality of first electrodes SN of the plurality of data storage elements CAP along the third direction D3. The plurality of first electrodes SN are separated from each other by the plurality of first cell separation layers ISOA. The plurality of second electrodes PN of the plurality of data storage elements CAP are connected to a common plate PL.

[0098] Refer again Figure 2, a part of the plurality of second electrodes PN divides the first unit separation layer ISOA. The plurality of second electrodes PN of the plurality of data storage elements CAP are merged into a common plate PL. The plurality of second electrodes PN of the plurality of data storage elements CAP arranged horizontally along the third direction D3 are merged with each other. The plurality of second electrodes PN of the plurality of data storage elements CAP arranged vertically along the first direction D1 are merged with each other. The common plate PL extends horizontally along the third direction D3 while extending horizontally along the first direction D1. The common plate PL includes a shared portion PL_S that shares the memory cells MC adjacent along the second direction D2 and a merge portion PL_M arranged between the plurality of first unit separation layers ISOA. The common plate PL becomes a cross-shape extending along the third direction D3 by a combination of the plurality of shared portions PL_S and the plurality of merge portions PL_M. The plurality of first unit separation layers ISOA are divided into a plurality of first unit separation segments ISOA1, ISOA2 by the merge portion PL_M of the common plate PL. The size of the plurality of first unit separation segments ISOA1, ISOA2 is less than or equal to the plurality of second unit separation layers ISOB. The plurality of first electrodes SN of the data storage element CAP are disposed between the plurality of first cell separation sections ISOA1 along the third direction D3. The plurality of first electrodes SN of the data storage element CAP are disposed between the plurality of first cell separation sections ISOA2 along the third direction D3.

[0099] A plurality of first cell separation layers ISOA are disposed between a plurality of data storage elements CAP along a third direction D3. A plurality of second cell separation layers ISOB are disposed between a plurality of first conductive lines BL along a third direction D3. A second conductive line DWL is disposed between a plurality of first cell separation layers ISOA and a plurality of second cell separation layers ISOB along a second direction D2. A size of the plurality of first cell separation layers ISOA is greater than that of the plurality of second cell separation layers ISOB.

[0100] The lower structure LS includes a semiconductor substrate, a metal wiring structure, an insulating structure, a conductive structure, a pad structure, and other memory or peripheral circuit parts.

[0101] For example, the lower structure LS includes a structure in which a peripheral circuit portion, a metal wiring structure, and a pad structure are stacked in this order. The memory cell array MCA and the peripheral circuit portion of the lower structure LS are bonded by wafer bonding.

[0102] The peripheral circuit portion of the lower structure LS is arranged at a lower position than the memory cell array MCA. This is called a COP (Cell over PERI, cell over periphery under) structure. The peripheral circuit portion includes at least one control circuit for driving the memory cell array MCA. At least one control circuit of the peripheral circuit portion includes an N-channel transistor, a P-channel transistor, a CMOS circuit or a combination thereof. At least one control circuit of the peripheral circuit portion includes an address decoder circuit, a read circuit, a write circuit, etc. At least one control circuit of the peripheral circuit portion includes a planar channel transistor, a recessed channel transistor, a buried gate transistor, a fin channel transistor (Fin channel transistor, FinFET), etc.

[0103] For example, the peripheral circuit unit includes a plurality of sub-word line drivers and a sense amplifier. The second conductive line DWL is connected to the plurality of sub-word line drivers. The first conductive line BL is connected to the sense amplifier.

[0104] In another embodiment, the peripheral circuit part is located higher than the memory cell array MCA, which is called a POC (PERI over Cell) structure.

[0105] In another embodiment, the memory cell array MCA includes DRAM, embedded DRAM, NAND, FeRAM, STTRAM, PCRAM, or ReRAM.

[0106] In another embodiment, each memory cell MC may be used Figure 1D The memory cell MC1 is replaced.

[0107] FIG. 4A to FIG. 26B A diagram for explaining an example of a method for manufacturing a semiconductor device according to an embodiment.

[0108] Figure 4A is a top view of the fourth layer 14 for explaining the method of forming the stacked body, Figure 4B For along Figure 4A A-A' cross-sectional view.

[0109] like FIG. 4A to FIG. 4BAs shown, the stack SB is formed on the upper part of the lower structure 11. The lower structure 11 is a material suitable for semiconductor processing. The lower structure 11 may include at least one of a conductive material, an insulating material, and a semiconductor material. Various materials are formed on the upper part of the lower structure 11. The lower structure 11 includes a semiconductor substrate. The lower structure 11 may be formed of a material containing silicon. The lower structure 11 may include silicon, single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanium, single crystal silicon germanium, polycrystalline silicon germanium, carbon-doped silicon, a combination thereof, or a multilayer thereof. The lower structure 11 may also include other semiconductor materials such as germanium. The lower structure 11 may also include a III / V semiconductor substrate, such as a compound semiconductor substrate such as GaAs. The lower structure 11 may also include an SOI (Silicon On Insulator) substrate.

[0110] The stack SB is formed by alternately stacking a plurality of sub-stacks. Each sub-stack is stacked in the order of a first layer 12A, a second layer 13, a third layer 12B, and a fourth layer 14. The plurality of first layers 12A and the plurality of third layers 12B are formed of the same material, such as silicon germanium. The plurality of second layers 13 may include single crystal silicon. The fourth layer 14 may include single crystal silicon. The first layer 12A, the second layer 13, the third layer 12B, and the fourth layer 14 are formed by an epitaxial growth process. The first layer 12A is thinner than the second layer 13, and the fourth layer 14 is thicker than the second layer 13.

[0111] The stack SB includes a plurality of fourth layers 14, a first sacrificial layer stack SB1, a second sacrificial layer stack SB2, and a third sacrificial layer stack SB3. The stack SB is stacked in the order of the first sacrificial layer stack SB1, the fourth layer 14, the second sacrificial layer stack SB2, the fourth layer 14, and the third sacrificial layer stack SB3. The top layer of the stack SB is provided with a second layer 13. The first sacrificial layer stack SB1, the second sacrificial layer stack SB2, and the third sacrificial layer stack SB3 are three-layer stacks of the first layer 12A / the second layer 13 / the third layer 12B, respectively. For example, in the case where the first layer 12A and the third layer 12B include a silicon germanium layer and the second layer 13 includes a single crystal silicon layer, the first sacrificial layer stack SB1, the second sacrificial layer stack SB2, and the third sacrificial layer stack SB3 include a first silicon germanium layer / single crystal silicon layer / a second silicon germanium layer (SiGe / Si / SiGe) stack.

[0112] The second layer 13 includes a first single crystal silicon layer, and the fourth layer 14 includes a second single crystal silicon layer. The second single crystal silicon layer is thicker than the first single crystal silicon layer. Thus, in the stack SB, the first sacrificial layer stack SB1 is arranged at the lower part of the second single crystal silicon layer, and the second sacrificial layer stack SB2 is arranged at the upper part of the second single crystal silicon layer. The first sacrificial layer stack SB1 and the second sacrificial layer stack SB2 respectively include a first silicon germanium layer / a first single crystal silicon layer / a second silicon germanium layer stack. The second single crystal silicon layer is thicker than the first single crystal silicon layer.

[0113] The first layer 12A, the second layer 13, and the third layer 12B may be referred to as “sacrificial layers”, and the fourth layer 14 may be referred to as a recess target layer.

[0114] As mentioned above Figures 2 to 3B As shown, in the case of stacking a plurality of memory cells MC, the first sacrificial layer stack SB1 , the fourth layer 14 , the second sacrificial layer stack SB2 , the fourth layer 14 , and the third sacrificial layer stack SB3 are alternately stacked multiple times.

[0115] In another embodiment, the plurality of second layers 13 may include an oxide semiconductor material or a two-dimensional material.

[0116] Figure 5A FIG. 1 is a top view of the fourth layer 14 for explaining a method of forming the sacrificial separation openings 15A and 15B. Figure 5B For along Figure 5A Cross-sectional view along the line B-B'. Figure 5C For along Figure 5A A1-A1' cross-sectional view.

[0117] Reference FIG. 5A to FIG. 5C , a portion of the stacked body SB is etched to form a plurality of sacrificial separation openings 15A, 15B. The plurality of sacrificial separation openings 15A, 15B include a plurality of large openings 15A and a plurality of small openings 15B as initial openings for device separation. The size of the large opening 15A is larger than the small opening 15B. When viewed from a top view, the large opening 15A and the small opening 15B are rectangular in shape. In another embodiment, the large opening 15A and the small opening 15B may be circular or elliptical in shape. In another embodiment, the plurality of sacrificial separation openings 15A, 15B may be referred to as sacrificial separation grooves. The large openings 15A and the small openings 15B are alternately arranged along the second direction D2. The plurality of large openings 15A are arranged along the third direction D3. The plurality of small openings 15B are arranged along the third direction D3.

[0118] After etching the stacked body SB, a portion of the lower structure 11 is etched. As a result, the bottom surfaces of the plurality of sacrificial separation openings 15A and 15B extend toward the inside of the lower structure 11. The bottom surfaces of the plurality of sacrificial separation openings 15A and 15B include a U-shaped profile. The plurality of fourth layers 14 form a mesh-shaped pattern through the plurality of sacrificial separation openings 15A and 15B.

[0119] Fig. 6A 1 is a top view of the fourth layer 14 for explaining the method of forming the sacrificial unit separation layers 16A′ and 16B. Figure 6B For along Fig. 6A Cross-sectional view along the line B-B'. Figure 6C It is a cross-sectional view along A1 - A1 ' in FIG. 6a.

[0120] like FIG. 6A to FIG. 6C As shown, a plurality of sacrificial unit separation layers 16A', 16B are formed to fill a plurality of sacrificial separation openings 15A, 15B. The plurality of sacrificial unit separation layers 16A', 16B include a plurality of preliminary first sacrificial unit separation layers 16A' and a plurality of second sacrificial unit separation layers 16B. The plurality of preliminary first sacrificial unit separation layers 16A' fill the large openings 15A, and the plurality of second sacrificial unit separation layers 16B fill the small openings 15B.

[0121] The plurality of prepared first sacrificial unit separation layers 16A' and the plurality of second sacrificial unit separation layers 16B may include the same material. The plurality of prepared first sacrificial unit separation layers 16A' and the plurality of second sacrificial unit separation layers 16B may be formed of insulating materials. For example, the plurality of prepared first sacrificial unit separation layers 16A' and the plurality of second sacrificial unit separation layers 16B may include silicon oxide, silicon nitride, silicon carbide oxide, silicon carbon nitride or a combination thereof. The steps of forming the plurality of prepared first sacrificial unit separation layers 16A' and the plurality of second sacrificial unit separation layers 16B include: the steps of forming an insulating material in the stack SB to fill the plurality of sacrificial separation openings 15A, 15B and the step of flattening the insulating material to expose the top layer of the stack SB. The plurality of prepared first sacrificial unit separation layers 16A' and the plurality of second sacrificial unit separation layers 16B may be of different sizes or different volumes. For example, the size (or volume) of the plurality of prepared first sacrificial unit separation layers 16A' is larger than the plurality of second sacrificial unit separation layers 16B.

[0122] The plurality of preliminary first sacrificial unit separation layers 16A' and the plurality of second sacrificial unit separation layers 16B are alternately disposed along the second direction D2. The plurality of preliminary first sacrificial unit separation layers 16A' are disposed along the third direction D3. The plurality of second sacrificial unit separation layers 16B are disposed along the third direction D3.

[0123] Fig. 7A1 is a top view of the fourth layer 14 for explaining a method of forming a plurality of sacrificial openings V1 ′ and V2 ′. Figure 7B For along Fig. 7A A-A' cross-sectional view. Figure 7C For along Fig. 7A A1-A1' cross-sectional view.

[0124] like 7A to 7C As shown, a first hard mask layer HM1 is formed on the stacked body SB, the plurality of preliminary first sacrificial cell separation layers 16A' and the plurality of second sacrificial cell separation layers 16B. The first hard mask layer HM1 may include silicon nitride.

[0125] Next, a mask layer MK is formed on the first hard mask layer HM1. The mask layer MK includes a hard mask material, a photoresist, or a combination thereof as an etching mask layer. The mask layer MK includes a plurality of hole-type opening patterns MH and line-type opening patterns ML. The plurality of line-type opening patterns ML extend along the third direction D3 and intersect with the plurality of preliminary first sacrificial unit separation layers 16A'.

[0126] Next, the mask layer MK is used as an etch barrier to etch the first hard mask layer HM1, the stacked body SB and the plurality of prepared first sacrificial unit separation layers 16A'. As a result, a plurality of sacrificial openings V1', V2' are formed on the stacked body SB. The plurality of sacrificial openings V1', V2' include a plurality of first sacrificial openings V1' and a plurality of second sacrificial openings V2'. When viewed from a top view, the plurality of first sacrificial openings V1' are a plurality of linear sacrificial openings, and the plurality of second sacrificial openings V2' are a plurality of hole-type sacrificial openings. The plurality of first sacrificial openings V1' are formed by etching the stacked body SB and the plurality of prepared first sacrificial unit separation layers 16A'. The plurality of second sacrificial openings V2' are formed by etching the stacked body SB between the plurality of second sacrificial unit separation layers 16B.

[0127] The plurality of first sacrificial openings V1' divide the plurality of preliminary first sacrificial unit separation layers 16A'. The plurality of preliminary first sacrificial unit separation layers 16A' are respectively divided into a plurality of first sacrificial unit separation layers 16A by the plurality of first sacrificial openings V1'. The two second sacrificial openings V2' are located between the plurality of second sacrificial unit separation layers 16B adjacent to each other along the third direction D3.

[0128] As described above, in order to form the plurality of sacrificial openings V1 ′, V2 ′, line patterning and hole patterning are performed simultaneously.

[0129] Fig. 8A 1 is a top view for explaining a method for forming the preliminary horizontal layer 14A. Figure 8B For along Fig. 8A A-A' cross-sectional view. Figure 8C For along Fig. 8A A1-A1' cross-sectional view.

[0130] like FIG. 8A to FIG. 8C As shown, a portion of the first hard mask layer HM1 is trimmed.

[0131] Next, the first layer 12A and the third layer 12B are selectively removed through the plurality of sacrificial openings V1 ′, V2 ′.

[0132] In order to selectively remove the first layer 12A and the third layer 12B, the difference in etching selectivity between the second layer 13 and the fourth layer 14 and the first layer 12A and the third layer 12B is utilized. The first layer 12A and the third layer 12B are removed by wet etching or dry etching. For example, when the first layer 12A and the third layer 12B include a silicon germanium layer and the second layer 13 and the fourth layer 14 include a silicon layer, the silicon germanium layer is etched using an etching solution or etching gas that is selective to the silicon layer.

[0133] Next, the plurality of second layers 13 and the plurality of fourth layers 14 are recessed. In order to recess the plurality of second layers 13 and the plurality of fourth layers 14, wet etching or dry etching is used. In the present embodiment, the plurality of fourth layers 14 are partially etched during the removal of the plurality of second layers 13. As a result, the plurality of second layers 13 are removed, and the fourth layer 14 is thinned as shown by the reference numeral "14A". The recessing process for forming the thinned fourth layer 14A (i.e., the preliminary horizontal layer 14A) may be referred to as a thinning process or a trimming process of the fourth layer 14. The plurality of preliminary horizontal layers 14A may be referred to as a thin-body active layer. The plurality of preliminary horizontal layers 14A include a single crystal silicon layer. During the formation of the preliminary horizontal layer 14A, the surface of the lower structure 11 may also be recessed to a predetermined depth (refer to the reference numeral "11A"). The recessing process for forming the preliminary horizontal layer 14A may use HSC1 (Hot SC-1). The HSC1 may include a solution in which ammonium hydroxide (NH4OH), hydrogen peroxide (H2O2), and water (H2O) are mixed at a ratio of 1:4:20. The second layer 13 and the fourth layer 14 are selectively etched using the HSC1.

[0134] The plurality of preliminary horizontal layers 14A are formed by the recessing process of the plurality of fourth layers 14 as described above, and a plurality of horizontal type recessed parts 18 are formed between the plurality of preliminary horizontal layers 14A. The upper and lower surfaces of the plurality of preliminary horizontal layers 14A include planes, respectively.

[0135] After forming the plurality of preliminary horizontal layers 14A, the sacrificial openings are expanded as indicated by reference numerals V1, V2. The plurality of preliminary horizontal layers 14A are spaced apart from each other in the second direction D2 by the plurality of sacrificial openings V1, V2.

[0136] When viewed from a top view, the plurality of preliminary horizontal layers 14A are in a cross shape. The sides of the plurality of preliminary horizontal layers 14A may be curved or circular. The plurality of preliminary horizontal layers 14A are separated from each other by a plurality of sacrificial openings V1 and V2. The plurality of preliminary horizontal layers 14A are in a shape where a plurality of cross shapes merge along a third direction D3.

[0137] As described above, during the formation of the plurality of preliminary horizontal layers 14A, the surface of the lower structure 11 may be recessed by a predetermined depth, thereby increasing the depth of the plurality of sacrificial openings V1 and V2.

[0138] A plurality of linear sacrificial openings V1 and a plurality of hole-type sacrificial openings V2 are alternately arranged between a plurality of preliminary horizontal layers 14A along the second direction D2. A plurality of linear sacrificial openings V1 are arranged between a plurality of first sacrificial unit separation layers 16A along the second direction D2, and a plurality of hole-type sacrificial openings V2 are arranged between a plurality of second sacrificial unit separation layers 16B along the third direction D3.

[0139] Fig.9A 1 is a top view for explaining a method of forming the first insulating layer 19 and the second insulating layer 20. Fig. 9B For along Fig.9A A-A' cross-sectional view. Fig. 9C For along Fig.9A A1-A1' cross-sectional view.

[0140] like 9A to 9C As shown, a first insulating layer 19 is formed to cover the plurality of preliminary horizontal layers 14A. The plurality of first insulating layers 19 may include silicon nitride. The plurality of first insulating layers 19 completely cover the upper surface, the lower surface and the side surfaces of the plurality of preliminary horizontal layers 14A.

[0141] During the formation of the plurality of first insulating layers 19, a dummy insulating layer 19D is formed on the surface of the lower structure 11. Parts of the plurality of first insulating layers 19 completely cover the upper surface, the lower surface, and the side surfaces of the first hard mask layer HM1.

[0142] Next, a second insulating layer 20 is formed on the plurality of first insulating layers 19. The second insulating layer 20 is filled between the plurality of vertically adjacent first insulating layers 19. The second insulating layer 20 may include silicon oxide. A portion of the second insulating layer 20 is conformally formed on the surface of the sacrificial openings V1 and V2. A plurality of horizontal recesses 18 are filled with the first insulating layer 19 and the second insulating layer 20.

[0143] Next, a sacrificial column 21 is formed on the second insulating layer 20 located at the plurality of sacrificial openings V1 and V2. As a sacrificial material, the sacrificial column 21 may include amorphous carbon. In another embodiment, a column cover layer may be formed on the upper portion of the sacrificial column 21. The column cover layer may include a metal-based material. The column cover layer may include titanium nitride. The step of forming the sacrificial column 21 includes a step of depositing the sacrificial material and a step of planarizing the sacrificial material. The planarizing step for forming the sacrificial column 21 is performed until the plurality of first insulating layers 19 on the uppermost layer are exposed.

[0144] The second insulating layer 20 and the sacrificial column 21 form a first sacrificial column structure SV1 and a second sacrificial column structure SV2 for filling the sacrificial openings V1 and V2. The first sacrificial column structure SV1 fills the linear sacrificial opening V1, and the second sacrificial column structure SV2 fills the hole-type sacrificial opening V2. No sacrificial column 21 is formed between the vertically stacked multiple first insulating layers 19. In another embodiment, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include an insulating material, a carbon-containing material, a metal-based material, or a combination thereof. In another embodiment, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. When viewed from a top view, the first sacrificial column structure SV1 is a linear sacrificial column extending along the third direction D3, and the second sacrificial column structure SV2 is a hole-type sacrificial column.

[0145] Refer again Fig. 9C A first insulating layer 19 is formed between the plurality of preliminary horizontal layers 14A, and a second insulating layer 20 is disposed inside the first insulating layer 19. The first insulating layer 19 surrounds the second insulating layer 20.

[0146] As described above, a cell mold structure is formed by forming a plurality of preliminary horizontal layers 14A, a plurality of first insulating layers 19, and a plurality of second insulating layers 20. The cell mold structure includes a plurality of cell molds CM. Each cell mold CM includes a plurality of mold layers. The plurality of mold layers are a plurality of preliminary horizontal layers 14A, a plurality of first insulating layers 19, and a plurality of second insulating layers 20. In each cell mold CM, a first sacrificial layer, a semiconductor layer, and a second sacrificial layer are stacked in order. Among them, the first sacrificial layer and the second sacrificial layer are the first insulating layer 19, and the semiconductor layer is the preliminary horizontal layer 14A.

[0147] In another embodiment, each unit mold CM includes an ONSNO (Oxide-Nitride-Silicon-Nitride-Oxide, oxide-nitride-silicon-nitride-oxide) stack. The ONSNO stack is a structure in which a first silicon oxide, a first silicon nitride, a single crystal silicon layer, a second silicon nitride, and a second silicon oxide are stacked in sequence. The first silicon oxide and the second silicon oxide correspond to a plurality of second insulating layers 20, the first silicon nitride and the second silicon nitride may correspond to a plurality of first insulating layers 19, and the single crystal silicon layer corresponds to a plurality of preliminary horizontal layers 14A.

[0148] pass 4A to 9C In a series of processes, the sub-stacks SB1, SB2, and SB3 of the stack SB are replaced by the unit mold MC. The first layer 12A, the second layer 13, and the third layer 12B are replaced by a plurality of first insulating layers 19 and a plurality of second insulating layers 20. The fourth layer 14 is formed into a preliminary horizontal layer 14A. The plurality of first insulating layers 19 may be referred to as trimming target layers.

[0149] Fig. 10A 2 is a top view for explaining a method for forming a plurality of device separation openings 22A and 22B. Fig. 10B For along Fig. 10A Cross-sectional view along the line B-B'. Fig. 10C For along Fig. 10A A1-A1' cross-sectional view.

[0150] like FIG. 10A to FIG. 10C As shown, in order to form a plurality of device separation openings 22A, 22B, a plurality of first sacrificial unit separation layers 16A and a plurality of second sacrificial unit separation layers 16B are removed. During the removal of the first sacrificial unit separation layers 16A and the second sacrificial unit separation layers 16B, the first sacrificial column structure SV1 and the second sacrificial column structure SV2 are covered by a mask layer (not shown). The side surfaces of the plurality of preliminary horizontal layers 14A and the plurality of first insulating layers 19 are exposed in the BB' direction due to the device separation openings 22A, 22B.

[0151] Fig.11A 14B is a top view for explaining a method for forming a plurality of horizontal layers 14B. Fig. 11B For along Fig.11A Cross-sectional view along the line B-B'. Fig. 11C For along Fig.11A A1-A1' cross-sectional view.

[0152] like FIG. 11A to FIG. 11CAs shown, the side surfaces of the plurality of preliminary horizontal layers 14A are trimmed by the plurality of device separation openings 22A and 22B. Thus, a plurality of horizontal layers 14B are formed. Horizontal layer level gaps 14R are formed on both sides of the plurality of horizontal layers 14B. The horizontal layer level gaps 14R and the plurality of horizontal layers 14B are disposed between the plurality of first insulating layers 19. The plurality of horizontal layers 14B may be referred to as a "trimmed horizontal layer pattern".

[0153] During the formation of the plurality of horizontal layers 14B, the surface of the lower structure 11 (eg, the bottom surface of the device separation openings 22A and 22B) may be recessed to a predetermined depth.

[0154] A plurality of horizontal layers 14B are arranged between a plurality of sacrificial column structures SV1 and SV2 along the second direction D2. When viewed from a top view, the plurality of horizontal layers 14B are in a cross-shape. The horizontal layer 14B is a cross-shape smaller in size than the preliminary horizontal layer 14A. The preliminary horizontal layer 14A is a shape in which a plurality of cross shapes are merged, and the horizontal layer 14B is a shape in which a plurality of cross shapes are separated separately along the third direction D3. A horizontal level gap 14R is formed between the plurality of horizontal layers 14B arranged along the third direction D3. A plurality of first sacrificial column structures SV1 and a plurality of second sacrificial column structures SV2 are arranged between the plurality of horizontal layers 14B along the second direction D2.

[0155] Fig. 12A 2 is a top view for explaining a method for forming a horizontal level spacer 23. Fig. 12B For along Fig. 12A Cross-sectional view along the line B-B'. Fig. 12C For along Fig. 12A A1-A1' cross-sectional view.

[0156] like FIG. 12A to FIG. 12C As shown, a horizontal level spacer 23 is formed on the sidewall of the horizontal layer 14B. The horizontal level spacer 23 may include an insulating material, such as silicon oxide. The horizontal level spacer 23 fills the horizontal level gap 14R. The plurality of horizontal layers 14B arranged along the third direction D3 are separated from each other by the horizontal level spacer 23.

[0157] Fig.13A 1 is a top view for explaining a method for trimming the plurality of first insulating layers 19A. Fig. 13B For along Fig.13A Cross-sectional view along the line B-B'. Fig. 13C For along Fig.13A A1-A1' cross-sectional view.

[0158] like FIG. 13A to FIG. 13C As shown, a portion of the plurality of first insulating layers 19 is horizontally trimmed through the device separation openings 22A, 22B. After the trimming, the plurality of first insulating layers 19 remain as shown by reference numeral 19A. Therefore, when viewed from BB', the second insulating layer 20 is provided between the plurality of first insulating layers 19A.

[0159] according to FIG. 11A to FIG. 13C , the width of the first insulating layer 19A in the third direction D3 is greater than the width of the horizontal layer 14B. Specifically, the trimming depth of the first insulating layer 19A in the third direction D3 is less than the trimming depth of the preliminary horizontal layer 14A.

[0160] A pair of first insulating layers 19A are vertically overlapped in one horizontal layer 14B. The trimmed first insulating layer 19A may be referred to as a "trimmed first insulating layer".

[0161] Fig.14A 2 is a top view for explaining a method of forming a plurality of unit separation layers 24A and 24B. Fig. 14B For along Fig.14A Cross-sectional view along the line B-B'. Fig. 14C For along Fig.14A A1-A1' cross-sectional view. Fig.14A It can be a top view of the first insulating layer 19A level for explaining the method of forming the plurality of cell separation layers 24A and 24B.

[0162] like FIG. 14A to FIG. 14C As shown, a plurality of unit separation layers 24A, 24B are formed to fill a plurality of device separation openings 22A, 22B. The plurality of unit separation layers 24A, 24B include a plurality of first unit separation layers 24A and a plurality of second unit separation layers 24B. The plurality of first unit separation layers 24A and the plurality of second unit separation layers 24B may contain the same substance. The plurality of first unit separation layers 24A and the plurality of second unit separation layers 24B may be formed of an insulating material. For example, the plurality of first unit separation layers 24A and the plurality of second unit separation layers 24B may contain silicon oxide, silicon nitride, silicon carbide oxide, silicon carbon nitride, or a combination thereof. When viewed from a top view, the outermost material of the plurality of first unit separation layers 24A and the plurality of second unit separation layers 24B may contain silicon carbide oxide.

[0163] The step of forming a plurality of first unit separation layers 24A and a plurality of second unit separation layers 24B includes the step of forming an insulating material for filling a plurality of device separation openings 22A, 22B and the step of flattening the insulating material to expose the surface of the uppermost first insulating layer 19. The plurality of first unit separation layers 24A and the plurality of second unit separation layers 24B may have different sizes or different volumes. The plurality of first unit separation layers 24A and the plurality of second unit separation layers 24B are a dual structure of silicon oxide and silicon carbide oxide. For example, silicon carbide oxide is deposited after silicon oxide is deposited. In another embodiment, the plurality of first unit separation layers 24A and the plurality of second unit separation layers 24B include embedded air gaps. A linear first sacrificial column structure SV1 is provided between the plurality of first unit separation layers 24A, and a hole-type first sacrificial column structure SV2 is provided between the plurality of second unit separation layers 24B.

[0164] Fig.15 FIG. 2 is a top view for explaining a method for forming a plurality of linear vertical sacrificial structures 29. FIG. 16A to FIG. 16D For along Fig.15 A-A' cross-sectional view.

[0165] First, if Fig.16A As shown, in order to form the hard mask level recess 25 , the first hard mask layer HM1 and the uppermost first insulating layer 19A are removed.

[0166] like Fig. 16B As shown, a top dielectric layer (26) is formed to fill the hard mask level recess 25. The top dielectric layer 26 may include silicon oxide.

[0167] like Fig. 16C As shown, the first sacrificial pillar structure SV1 is removed to form a plurality of initial line-shape vertical openings 27. The first insulating layer 19A and the dummy insulating layer 19D are exposed through the initial line-shape vertical openings 27.

[0168] Next, the plurality of second insulating layers 20 are horizontally recessed.

[0169] Next, the plurality of first insulating layers 19A and the dummy insulating layers 19D are selectively recessed horizontally, thereby forming a plurality of first insulating layer patterns 19B and a plurality of insulating layer-level recesses 28 . A portion of the horizontal layer 14B is exposed through the insulating layer-level recesses 28 .

[0170] like Fig.16DAs shown, a plurality of line-type vertical sacrificial structures 29 are formed to fill the plurality of insulating level recesses 28 and the plurality of initial line-type vertical openings 27. The plurality of line-type vertical sacrificial structures 29 may include insulating materials. The plurality of line-type vertical sacrificial structures 29 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof.

[0171] Fig.17A 2 is a top view for explaining a method for forming a vertical channel 30. Fig. 17B For along Fig.17A A-A' cross-sectional view.

[0172] like Fig.17A and Fig. 17B As shown, in order to form the vertical channel 30 , the sacrificial post 21 of the first sacrificial post structure SV2 is removed.

[0173] Next, in order to form the lower-level gap 19D′, the dummy insulating layer 19D below the vertical channel 30 is removed.

[0174] Fig.18A 3 is a top view for explaining a method for forming a hole-shaped vertical opening 32. Fig.18B For along Fig.18A A-A' cross-sectional view.

[0175] like Fig.18A and Fig.18B As shown, the second insulating layer 20 is cut 31 through the vertical channel 30 in order to form a hole-shaped vertical opening 32 .

[0176] Next, a first protective layer BF1 is formed to fill the lower level gap 19D'. The first protective layer BF1 may include silicon oxide. The step of forming the first protective layer BF1 may include a step of depositing silicon oxide to fill the lower level gap 19D' and a silicon oxide etching step. Next, in order to form a second protective layer BF2, the surface of the lower structure 11 is oxidized.

[0177] Fig.19A 2 is a top view for explaining a method for forming a plurality of horizontal recesses 33. Fig.19B For along Fig.19A A-A' cross-sectional view.

[0178] like Fig.19A and Fig.19B As shown, the plurality of first insulation layer patterns 19B are removed to form the plurality of horizontal level recesses 33. A portion of the horizontal layer 14B is exposed through the horizontal level recesses 33.

[0179] Fig. 20A 2 is a top view for explaining a method for forming a plurality of horizontal conductive lines 35. Fig. 20B For along Fig. 20AA-A' cross-sectional view.

[0180] like Fig. 20A and Fig. 20B As shown, an interlayer insulating layer 34 is formed on the exposed portion of the horizontal layer 14B. The interlayer insulating layer 34 may include a gate insulating layer. The interlayer insulating layer 34 is formed by oxidizing the surface of the horizontal layer 14B. In another embodiment, the interlayer insulating layer 34 is formed by a deposition process of silicon oxide.

[0181] The interlayer insulating layer 34 may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, anti-ferroelectric material, or a combination thereof. The interlayer insulating layer 34 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof.

[0182] Next, a horizontal conductive line 35 for filling the horizontal recess 33 is formed on the interlayer insulating layer 34. The step of forming the horizontal conductive line 35 includes: a step of depositing a conductive material for filling the horizontal recess 33 on the interlayer insulating layer 34 and a step of etching back the conductive material. The horizontal conductive line 35 includes a first horizontal conductive line 35A and a second horizontal conductive line 35B in pairs facing each other with the horizontal layer 14B in between. The first horizontal conductive line 35A and the second horizontal conductive line 35B may include a metal-base material, a semiconductor material, or a combination thereof. The first horizontal conductive line 35A and the second horizontal conductive line 35B may include titanium nitride, tungsten, polysilicon, molybdenum, molybdenum nitride, or a combination thereof. For example, the first horizontal conductive line 35A and the second horizontal conductive line 35B may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The first horizontal conductive line 35A and the second horizontal conductive line 35B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function (Low work function) of 4.5 eV or less, and the P-type work function material may have a high work function (High work function) of 4.5 eV or more.

[0183] The horizontal conductive lines 35 correspond to Figures 1A to 1D The second conductive line DWL shown, the first horizontal conductive line 35A and the second horizontal conductive line 35B correspond to the upper horizontal line G1 and the lower horizontal line G2. Figures 1A to 1DAs shown, the first horizontal conductive line 35A and the second horizontal conductive line 35B are each in a cross shape and include a channel overlapping portion WLP.

[0184] Fig.21A 2 is a top view for explaining a method for forming a plurality of vertical conductive lines 39. Fig.21B For along Fig.21A A-A' cross-sectional view.

[0185] like Fig.21A and Fig.21B As shown, a first capping layer 36 is formed on one side of the horizontal conductive line 35. The first capping layer 36 may include silicon oxide, silicon nitride, or a combination thereof. In order to form the first capping layer 36, deposition and etching back of the capping material are performed. During or after the formation of the first capping layer 36, a portion of the interlayer insulating layer 34 is removed to expose the first edge portion of each horizontal layer 14B.

[0186] Next, a vertical conductive line 39 connected to the first edge portion of each horizontal layer 14B is formed. The vertical conductive line 39 fills the hole-type vertical opening 32. The vertical conductive line 39 is commonly connected to the plurality of horizontal layers 14B. The vertical conductive line 39 may include titanium nitride, tungsten, or a combination thereof. The vertical conductive line 39 includes a bit line.

[0187] Before forming the vertical conductive line 39, the first doped region 37 and the first contact node 38 are formed. The first doped region 37 is formed in the first edge portion of the horizontal layer 14B. The step of forming the first doped region 37 includes: a deposition step of polysilicon doped with N-type impurities, a heat treatment step, and a doped polysilicon removal step. The first doped region 37 may include impurities diffused from the doped polysilicon. In another embodiment, the first doped region 37 may be formed by a doping process of impurities.

[0188] The first contact node 38 may include doped polysilicon. The first doped region 37 includes impurities diffused from the first contact node 38.

[0189] The vertical conductive lines 39 correspond to Figures 1A to 1D The first conductive line BL is shown.

[0190] Fig.22A 4 is a top view for explaining a method of forming a plurality of linear vertical openings 40 and a plurality of storage openings 41. Fig. 22B For along Fig.22A A-A' cross-sectional view.

[0191] like Fig.22A and Fig. 22BAs shown, in order to form a linear vertical opening 40 for exposing the second edge portion of the horizontal layer 14B, a portion of the linear vertical sacrificial structure 29 is removed. One side of the horizontal layer 14B is exposed through the linear vertical opening 40. The linear vertical opening 40 has the same shape as the linear vertical sacrificial structure 29. That is, the linear vertical opening 40 extends horizontally along the third direction D3.

[0192] Finally, the line-type vertical opening 40 is a structure formed by line patterning of the stacked body.

[0193] Next, a third protective layer BF3 is formed on the surface of the lower structure 11. The third protective layer BF3 may include silicon oxide.

[0194] Next, the second edge portion of the horizontal layer 14B is horizontally recessed along the second direction D2. The horizontal layer remains as indicated by reference symbol "HL".

[0195] Next, in order to form the second cover layer 29C, the remaining linear vertical sacrificial structure 29 is selectively recessed. As a result, the linear vertical opening 40 is horizontally expanded. The second cover layer 29C may include silicon oxide, silicon nitride, or a combination thereof. By forming the second cover layer 29C, a storage opening 41 is formed. The storage opening 41 may be referred to as a capacitor opening.

[0196] The horizontal layer HL includes a first edge and a second edge. The first edge is a portion connected to the first contact node 38 and the vertical conductive line 39, and the second edge is a portion exposed through the storage opening 41.

[0197] The storage opening 41 is located between the second insulating layers 20. The second cover layer 29C is disposed at the lower portion and the upper portion of the horizontal layer HL, respectively.

[0198] As described above, the step of forming the horizontal layer HL and the storage opening 41 includes the step of forming the line-type vertical opening 40 , the step of recessing the horizontal layer 14B, and the step of forming the second cover layer 29C.

[0199] Fig.23A 4 is a top view for explaining a method of forming a plurality of second contact nodes 42. Fig. 23B For along Fig.23A A-A' cross-sectional view.

[0200] like Fig.23A and Fig. 23BAs shown, a second doped region 43 is formed in the second edge of the horizontal layer HL. The step of forming the second doped region 43 includes a step of depositing polysilicon doped with N-type impurities, a step of thermal treatment, and a step of removing the doped polysilicon. The second doped region 43 may include impurities diffused from the doped polysilicon. In another embodiment, after the thermal treatment step, the doped polysilicon may remain.

[0201] Next, a second contact node 42 is formed at a second edge of the horizontal layer HL. The second contact node 42 may include doped polysilicon. The second doping region 43 may include impurities diffused from the second contact node 42.

[0202] The horizontal layer HL includes a first doping region 37, a second doping region 43 and a channel 44 which are horizontally arranged along the second direction D2. The channel 44 is defined between the first doping region 37 and the second doping region 43. The channel 44 vertically overlaps the horizontal conductive line 35. Figures 1A to 1C As shown, the horizontal layer HL may be in a cross shape, and the channel 44 may also be in a cross shape.

[0203] Fig.24A 4 is a top view for explaining a method of forming a plurality of first electrodes 45. Fig. 24B For along Fig.24A A-A' cross-sectional view.

[0204] like Fig.24A and Fig. 24B As shown, a first electrode 45 of the data storage element is formed at the second contact node 42. The first electrode 45 is in the shape of a horizontally oriented cylinder.

[0205] Fig.25A 4 is a top view for explaining a method of exposing the outer wall of the first electrode 45. Fig.25B For along Fig.25A A-A' cross-sectional view.

[0206] like Fig.25A and Fig.25B As shown in FIG. 4 , the second insulating layer 20 is horizontally recessed (reference numeral 46 ). Thus, the outer wall of the first electrode 45 is exposed.

[0207] Fig.26A 4 is a top view for explaining a method of forming a dielectric layer 47 and a second electrode 48. Fig.26B For along Fig.26A A-A' cross-sectional view.

[0208] like Fig.26A and Fig.26B As shown, a dielectric layer 47 and a second electrode 48 are sequentially formed on the first electrode 45. The first electrode 45, the dielectric layer 47 and the second electrode 48 form a data storage element CAP.

[0209] The first electrode 45 includes an inner space and a plurality of outer sides, and the inner space of the first electrode 45 includes a plurality of inner sides. The outer side of the first electrode 45 includes a vertical outer side and a plurality of horizontal outer sides. The vertical outer side of the first electrode 45 extends vertically along the first direction D1, and the horizontal outer side of the first electrode 45 extends horizontally along the second direction D2 or the third direction D3. The inner space of the first electrode 45 is a three-dimensional space. The dielectric layer 47 conformally covers the inner side and the outer side of the first electrode 45. The second electrode 48 is disposed in the inner space of the first electrode 45 on the dielectric layer 47. A portion of the outer side of the outer side of the first electrode 45 is electrically connected to the second doping region 43 of the horizontal layer HL.

[0210] The first electrode 45 is in a cylindrical shape. The cylindrical shape of the first electrode 45 includes a cylindrical inner side surface and a cylindrical outer side surface. A portion of the outer side surface of the cylindrical outer side surface of the first electrode 45 is electrically connected to the second doping region 43 of the horizontal layer HL. The dielectric layer 47 and the second electrode 48 are disposed on the cylindrical inner side surface of the first electrode 45.

[0211] The second electrode 48 extends vertically along the first direction D1 and horizontally along the third direction D3 .

[0212] The first electrode 45 and the second electrode 48 may include a metal, a noble metal, a metal nitride, a conductive metal oxide or a conductive noble metal oxide, a metal carbide, a metal silicide, or a combination thereof. For example, the first electrode SN and the second electrode PN may include titanium (Ti), titanium nitride (TiN), titanium silicon nitride (TiSiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO2), iridium (Ir), iridium oxide (IrO2), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten (TiN / W) stack, tungsten nitride / tungsten (WN / W) stack, titanium silicon nitride / titanium nitride (TiSiN / TiN) stack, or a combination thereof. The second electrode 48 may also include a combination of a metal-based material and a silicon-based material. For example, the second electrode 48 may be a stack of titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN). In the titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium is a gap filling material filling the inner space of the first electrode 45, titanium nitride (TiN) can serve as the second electrode 48 of the data storage element CAP, and tungsten nitride can be a low resistance material.

[0213] The dielectric layer 47 may be referred to as a capacitor dielectric layer or a memory layer. The dielectric layer 47 may include silicon oxide, silicon nitride, a high dielectric constant material, a ferroelectric material, an antiferroelectric material, a perovskite material, or a combination thereof. For example, the dielectric layer 47 may include hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), or strontium titanium oxide (SrTiO3). For example, the dielectric layer 47 may include a ZA (ZrO2 / Al2O3) stack, a ZAZ (ZrO2 / Al2O3 / ZrO2) stack, a ZAZA (ZrO2 / Al2O3 / ZrO2 / Al2O3) stack, a ZAZAZ (ZrO2 / Al2O3 / ZrO2 / Al2O3 / ZrO2) stack, a HA (HfO2 / Al2O3) stack, a HAH (HfO2 / Al2O3 / HfO2) stack, a HAHA (HfO2 / Al2O3 / HfO2 / Al2O3) stack, or a HAHAH (HfO2 / Al2O3 / HfO2 / Al2O3 / HfO2) stack.

[0214] In another embodiment, an interface control layer for improving leakage current may be formed between the first electrode 45 and the dielectric layer 47. The interface control layer may include titanium oxide (TiO2), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), niobium nitride (NbN), or a combination thereof. The interface control layer may also be formed between the second electrode 48 and the dielectric layer 47.

[0215] In this embodiment, in order to form the storage opening 41 for forming the first electrode 45, the linear vertical opening 40 is formed in advance. In order to form the linear vertical opening 40, line patterning is adopted. Since the line patterning is adopted, the cleaning process loading and the deposition process loading for forming the first electrode 45 can be reduced, thereby improving the finished product rate (yield).

[0216] In another embodiment, the first sacrificial opening V1' and the second sacrificial opening V2' may be formed by line patterning. Since the first sacrificial opening V1' and the second sacrificial opening V2' are formed by line patterning, the vertical conductive line 39 is formed into a double structure spaced apart horizontally. That is, one memory cell includes one vertical conductive line 39, and the vertical conductive lines 39 of horizontally adjacent memory cells are spaced apart from each other.

[0217] Fig.27A and Fig.27B It is a cross-sectional view for explaining a method for manufacturing a semiconductor device according to another embodiment.

[0218] like Fig.27AAs shown, a stack SB10 is formed on the upper part of the lower structure 11. The stack SB10 includes an alternating stack of a first semiconductor layer and a second semiconductor layer. For example, in the alternating stack, a plurality of silicon germanium layers 12 and a plurality of single crystal silicon layers 14' are alternately stacked by an epitaxial growth process. The silicon germanium layer 12 is a sacrificial layer, and the single crystal silicon layer 14' is a recessed target layer. That is, the silicon germanium layer 12 corresponds to Figure 4A and Figure 4B The single crystal silicon layer 14' corresponds to the fourth layer 14 of FIG. 4a and FIG. 4b. Figure 4B Different from the stacked body SB of FIG. 1 , the stacked body SB10 is formed by alternately stacking silicon germanium layers 12 and single crystal silicon layers 14 ′.

[0219] Next, you can execute FIG. 5A to FIG. 6C The series of steps shown in the figure form sacrificial separation openings 15A, 15B and sacrificial unit separation layers 16A', 16B in the stacked body SB10.

[0220] like Fig. 7A , Figure 7B , Figure 7C and Fig.27B As shown, a first hard mask layer HM1 is formed on the stack SB10. Then, a mask layer MK is formed on the first hard mask layer HM1. The mask layer MK may include a hard mask material, a photoresist, or a combination thereof as an etching mask layer. Fig. 7A , Figure 7B and Figure 7C As shown, the mask layer MK includes a plurality of hole-type opening patterns MH and line-type opening patterns ML. The line-type opening patterns ML extend along the third direction D3 and cross the plurality of preliminary first sacrificial unit separation layers 16A'.

[0221] Next, the mask layer MK is used as an etching barrier layer to etch the stacked body SB and the multiple prepared first sacrificial unit separation layers 16A'. As a result, multiple sacrificial openings V1', V2' are formed on the stacked body SB. The multiple sacrificial openings V1', V2' include multiple first sacrificial openings V1' and multiple second sacrificial openings V2'. When observed from a top view, the first sacrificial opening V1' is a linear opening, and the second sacrificial opening V2' is a hole-type opening. The first sacrificial opening V1' divides the prepared first sacrificial unit separation layer 16A'. The multiple prepared first sacrificial unit separation layers 16A' are respectively divided into multiple first sacrificial unit separation layers 16A by the multiple first sacrificial openings V1'. Two multiple second sacrificial openings V2' are arranged between multiple second sacrificial unit separation layers 16B adjacent to each other along the third direction D3.

[0222] As described above, in order to form the sacrificial openings V1 ′, V2 ′, line patterning and hole patterning are performed simultaneously.

[0223] Following Figure 27, execute FIG. 8A to FIG. 8B The preliminary horizontal layer 14A is formed by a series of processes shown in FIG. The preliminary horizontal layer 14A is formed by a recessing process of the single crystal silicon layer 14'. After the silicon germanium layer 12 is removed, the recessing process of the single crystal silicon layer 14' is performed.

[0224] Then, execute FIG. 9A to FIG. 26B A series of steps shown.

[0225] Fig.28A FIG. 1 is a schematic top view of a semiconductor device according to another embodiment. Fig.28B For along Fig.28A A-A' cross-sectional view.

[0226] Reference Fig.28A and Fig.28B , the semiconductor device 200 and Figure 2 , Figure 3 and Figure 3A The semiconductor device 100 shown in FIG. 1 is similar to the semiconductor device 100 shown in FIG. 1 . Figure 2 , Figure 3 and Figure 3A .

[0227] The semiconductor device 200 includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory cells MC21 and MC22. The memory cells MC21 and MC22 are connected to Figures 1A to 1C The memory cells MC shown are identical.

[0228] The memory cell array MCA includes a three-dimensional array of memory cells MC21 and MC22. The three-dimensional array of multiple memory cells MC21 and MC22 includes a column array of multiple memory cells MC21 and MC22 and a row array of memory cells MC21 and MC22. In the column array of multiple memory cells MC21 and MC22, multiple memory cells MC21 and MC22 are stacked along a first direction D1, and in the row array of multiple memory cells MC21 and MC22, multiple memory cells MC21 and MC22 are horizontally arranged along a second direction D2 and a third direction D3. The memory cell array MCA includes multiple sub-memory cell arrays MCA2 adjacent to each other along the second direction D2. The sub-memory cell array MCA2 includes a three-dimensional array of first memory cells MC21 and a three-dimensional array of second memory cells MC22.

[0229] Each first memory cell MC21 includes a first vertical conductive line BL1, a horizontal layer HL, a second conductive line DWL, and a data storage element CAP. The horizontal layer HL includes a first doped region SR, a channel CH, and a second doped region DR. An interlayer insulating layer GD is located between the horizontal layer HL and the second conductive line DWL. The data storage element CAP includes a first electrode SN, a dielectric layer DE, and a second electrode PN. Each memory cell MC21 also includes a second contact node SNC between the horizontal layer HL and the data storage element CAP. Although not shown in the figure, as shown in FIG. Figure 1B As shown, each memory cell MC21 further includes a first contact node BLC between the horizontal layer HL and the first vertical conductive line BL1. A plurality of second electrodes PN of adjacent first memory cells MC21 along the second direction D2 are merged to form a common plate PL.

[0230] The common plate PL includes a shared portion PL_S that shares the first memory cells MC21 adjacent along the second direction D2 and a merged portion PL_M disposed between the plurality of first cell separation layers ISOA. The common plate PL is a cross-shape extending along the third direction D3 by a combination of the plurality of shared portions PL_S and the plurality of merged portions PL_M. The plurality of first cell separation layers ISOA are disposed between the plurality of data storage elements CAP along the third direction D3. The plurality of second cell separation layers ISOB are disposed between the plurality of first vertical conductive lines BL1 along the third direction D3. The second conductive line DWL is disposed between the plurality of first cell separation layers ISOA and the plurality of second cell separation layers ISOB along the second direction D2. The plurality of first cell separation layers ISOA are larger in size than the plurality of second cell separation layers ISOB.

[0231] A plurality of first cell separation layers ISOA and a plurality of second cell separation layers ISOB are located between a plurality of first memory cells MC21 adjacent to each other along a third direction D3. A plurality of first cell separation layers ISOA are located between a plurality of data storage elements CAP, and a plurality of second cell separation layers ISOB are located between a plurality of first vertical conductive lines BL1. A plurality of first cell separation layers ISOA include a plurality of first cell separation segments ISOA1 and ISOA2, respectively. A plurality of second cell separation layers ISOB include a plurality of second cell separation segments ISOB1 and ISOB2, respectively. A first electrode SN of a plurality of data storage elements CAP is located between a plurality of first cell separation segments ISOA2. A plurality of first vertical conductive lines BL1 are located between a plurality of second cell separation segments ISOB1.

[0232] Each second memory cell MC22 includes a second vertical conductive line BL2, a horizontal layer HL, a second conductive line DWL, and a data storage element CAP. The horizontal layer HL includes a first doped region SR, a channel CH, and a second doped region DR. An interlayer insulating layer GD is located between the horizontal layer HL and the second conductive line DWL. The data storage element CAP includes a first electrode SN, a dielectric layer DE, and a second electrode PN. Each memory cell MC22 also includes a second contact node SNC between the horizontal layer HL and the data storage element CAP. Although not shown in the figure, as shown in FIG. Figure 1B As shown, each memory cell MC22 further includes a first contact node BLC between the horizontal layer HL and the second vertical conductive line BL2. The second electrodes PN of the second memory cells MC22 adjacent to each other along the second direction D2 are merged to form a common plate PL.

[0233] The common plate PL includes a shared portion PL_S that shares the second memory cells MC22 adjacent along the second direction D2 and a merged portion PL_M disposed between the plurality of first cell separation layers ISOA. The common plate PL is a cross-shape extending along the third direction D3 by a combination of the plurality of shared portions PL_S and the plurality of merged portions PL_M. The plurality of first cell separation layers ISOA are disposed between the plurality of data storage elements CAP along the third direction D3. The plurality of second cell separation layers ISOB are disposed between the plurality of second vertical conductive lines BL2 along the third direction D3. The second conductive line DWL is disposed between the plurality of first cell separation layers ISOA and the plurality of second cell separation layers ISOB along the second direction D2. The size of the plurality of first cell separation layers ISOA is larger than the plurality of second cell separation layers ISOB.

[0234] A plurality of first cell separation layers ISOA and a plurality of second cell separation layers ISOB are located between a plurality of second memory cells MC22 adjacent to each other along a third direction D3. A plurality of first cell separation layers ISOA are located between a plurality of data storage elements CAP, and a plurality of second cell separation layers ISOB are located between a plurality of second vertical conductive lines BL2. A plurality of first cell separation layers ISOA include a plurality of first cell separation segments ISOA1 and ISOA2, respectively. A plurality of second cell separation layers ISOB include a plurality of second cell separation segments ISOB1 and ISOB2, respectively. A first electrode SN of a plurality of data storage elements CAP is located between a plurality of first cell separation segments ISOA2. A plurality of second vertical conductive lines BL2 are located between a plurality of second cell separation segments ISOB1.

[0235] The three-dimensional array of the plurality of first memory cells MC21 shares the first vertical conductive line BL1, and the three-dimensional array of the plurality of second memory cells MC22 shares the second vertical conductive line BL2. For reference, Figure 2 , Figure 3A and Figure 3B The semiconductor device 100 shown includes a first conductive line BL, and a plurality of memory cells MC adjacent to each other along a second direction D2 share one first conductive line BL. That is, the first conductive line BL may be referred to as a common first conductive line BL. Fig.28A and Fig.28B The plurality of first vertical conductive lines BL1 and the second vertical conductive lines BL2 may be respectively referred to as individual first conductive lines.

[0236] The vertical separation layer BLF is located between the first vertical conductive line BL1 and the second vertical conductive line BL2. The second bottom protection layer BF2 and the additional second bottom protection layer BF21 are located below the first vertical conductive line BL1 and the second vertical conductive line BL2.

[0237] A third bottom protection layer BF3 is connected between the bottoms of the plurality of data storage elements CAP and the lower structure LS.

[0238] FIG. 28C to FIG. 28E 2 is a diagram for explaining electrical connection between the first vertical conductive line BL1 and the second vertical conductive line BL2 .

[0239] like Fig.28C As shown, the first vertical conductive line BL1 and the second vertical conductive line BL2 are connected to each other through an interconnection ML.

[0240] like Fig.28D As shown, the first vertical conductive line BL1 and the second vertical conductive line BL2 are connected to each other through a plurality of vias VA and interconnections ML.

[0241] like Fig.28E As shown, the first vertical conductive line BL1 is connected to the via VA and the interconnection ML1, and the second vertical conductive line BL2 is connected to the via VA and the interconnection ML2. As described above, the first vertical conductive line BL1 and the second vertical conductive line BL2 are respectively connected to different interconnections ML1 and ML2, and therefore, can be respectively connected to different sense amplifiers.

[0242] Fig.28F 1 is a diagram for explaining a separation structure of a first vertical conductive line BL1 and a second vertical conductive line BL2 .

[0243] like Fig.28FAs shown, the first vertical conductive line BL1 and the second vertical conductive line BL2 are separated by the linear groove BLS. The plurality of second cell separation layers ISOB are divided into a plurality of second cell separation segments ISOB1 and ISOB2 by the linear groove BLS. The plurality of second cell separation segments ISOB1 of the second cell separation layer ISOB are located between the plurality of first vertical conductive lines BL1 along the third direction D3. The plurality of first cell separation segments ISOB2 of the plurality of second cell separation layers ISOB are located between the plurality of second vertical conductive lines BL2 along the third direction D3.

[0244] The plurality of second cell separation segments ISOB1 of the plurality of second cell separation layers ISOB and the plurality of first vertical conductive lines BL1 are self-aligned in the fourth direction D31. The plurality of second cell separation segments ISOB2 of the plurality of second cell separation layers ISOB and the plurality of second vertical conductive lines BL2 are self-aligned in the fifth direction D32. In this way, the plurality of first vertical conductive lines BL1 and the second vertical conductive lines BL2 are self-aligned on one side of the plurality of second cell separation segments ISOB1 and ISOB2.

[0245] As described above, the semiconductor device 200 includes: a horizontal layer HL disposed on an upper portion of a lower structure LS and having a first edge and a second edge, a plurality of first unit separation layers ISOA located around the second edge of the horizontal layer HL and vertically extending from the lower structure LS, a plurality of second unit separation layers ISOB located around the first edge of the horizontal layer HL and vertically extending from the lower structure LS, vertical conductive lines BL1 and BL2 connected to the first edge of the horizontal layer and self-aligned on one side of the plurality of second unit separation layers ISOB, and a data storage element CAP connected to the second edge of the horizontal layer HL and located between the plurality of first unit separation layers ISOA.

[0246] FIG. 29A to FIG. 46B FIG. 1 is a diagram for explaining an example of a method for manufacturing a semiconductor device according to another embodiment. FIG. 4A to FIG. 27B The manufacturing method shown is similar.

[0247] Fig.29A FIG. 1 is a top view of the fourth layer 14 for explaining a method of forming a plurality of sacrificial separation openings 15A′ and 15B′. Fig.29B For along Fig.29A A1-A1' cross-sectional view.

[0248] Reference Fig.29A and Fig.29B, the stack SB is formed on the upper part of the lower structure 11. The stack SB is formed by alternately stacking a plurality of sub-stacks. Each sub-stack is stacked in the order of a first layer 12A, a second layer 13, a third layer 12B, and a fourth layer 14. The plurality of first layers 12A and the plurality of third layers 12B are formed of the same material, such as silicon germanium. The plurality of second layers 13 may include single crystal silicon. The fourth layer 14 may include single crystal silicon. The first layer 12A, the second layer 13, the third layer 12B, and the fourth layer 14 are formed by an epitaxial growth process.

[0249] A portion of the stacked body SB is etched to form a plurality of sacrificial separation openings 15A', 15B'. The plurality of sacrificial separation openings 15A', 15B' include a plurality of large openings 15A' and a plurality of small openings 15B' as initial openings for device separation. The size of the plurality of large openings 15A' is larger than the plurality of small openings 15B'. When viewed from a top view, the plurality of large openings 15A' and the plurality of small openings 15B' are rectangular in shape. In another embodiment, the plurality of large openings 15A' and the plurality of small openings 15B' may be circular or elliptical in shape. The plurality of large openings 15A' and the plurality of small openings 15B' extend vertically along the first direction D1. The plurality of large openings 15A' and the plurality of small openings 15B' are alternately arranged along the second direction D2. The plurality of large openings 15A' are arranged along the third direction D3. The plurality of large openings 15A' and the plurality of small openings 15B' penetrate the stacked body SB along the first direction D1.

[0250] After forming the plurality of sacrificial separation openings 15A', 15B', a portion of the lower structure 11 exposed below the plurality of sacrificial separation openings 15A', 15B' is etched. Thus, the bottom surfaces of the plurality of sacrificial separation openings 15A', 15B' extend toward the inside of the lower structure 11. The bottom surfaces of the plurality of sacrificial separation openings 15A', 15B' include a U-shaped profile. The plurality of fourth layers 14 form a mesh-shaped pattern through the plurality of sacrificial separation openings 15A', 15B'.

[0251] The plurality of large openings 15A' include two large segments 15A1 and 15A2, respectively, and the plurality of small openings 15B' include two small segments 15B1 and 15B2, respectively. Thus, the large segments 15A1 and 15A2 and the small segments 15B1 and 15B2 are formed in the stacked body SB.

[0252] Fig. 30A FIG. 1 is a top view of the fourth layer 14 for explaining the method of forming the sacrificial unit separation layers 16A′ and 16B′. Fig. 30B For along Fig. 30A A1-A1' cross-sectional view.

[0253] like Fig. 30A and Fig. 30B As shown, a plurality of sacrificial unit separation layers 16A', 16B' are formed to fill a plurality of sacrificial separation openings 15A', 15B'. The plurality of sacrificial unit separation layers 16A', 16B' include a plurality of first sacrificial unit separation layers 16A' and a plurality of second sacrificial unit separation layers 16B'. The plurality of first sacrificial unit separation layers 16A' fill the large openings 15A', and the plurality of second sacrificial unit separation layers 16B' fill the small openings 15B'.

[0254] The plurality of first sacrificial unit separation layers 16A' and the plurality of second sacrificial unit separation layers 16B' may include the same material. The plurality of first sacrificial unit separation layers 16A' and the plurality of second sacrificial unit separation layers 16B' may be formed of insulating materials. For example, the plurality of first sacrificial unit separation layers 16A' and the plurality of second sacrificial unit separation layers 16B' may include silicon oxide, silicon nitride, silicon carbide oxide, silicon carbon nitride or a combination thereof. The steps of forming the plurality of first sacrificial unit separation layers 16A' and the plurality of second sacrificial unit separation layers 16B' include: the steps of forming an insulating material in the stack SB to fill the plurality of sacrificial separation openings 15A', 15B' and the step of flattening the insulating material to expose the topmost layer of the stack SB. The plurality of first sacrificial unit separation layers 16A' and the plurality of second sacrificial unit separation layers 16B' may be of different sizes or different volumes. For example, the size (or volume) of the plurality of first sacrificial unit separation layers 16A' is larger than the plurality of second sacrificial unit separation layers 16B'.

[0255] A plurality of first sacrificial unit separation layers 16A' and a plurality of second sacrificial unit separation layers 16B' extend vertically along the first direction D1. A plurality of first sacrificial unit separation layers 16A' and a plurality of second sacrificial unit separation layers 16B' are alternately arranged along the second direction D2. A plurality of first sacrificial unit separation layers 16A' are arranged along the third direction D3. A plurality of second sacrificial unit separation layers 16B' are arranged along the third direction D3. A plurality of first sacrificial unit separation layers 16A' and a plurality of second sacrificial unit separation layers 16B' penetrate the stack SB along the first direction D1.

[0256] The plurality of first sacrificial unit separation layers 16A′ respectively include two first sacrificial separation sections 16A1 and 16A2 , and the plurality of second sacrificial unit separation layers 16B′ respectively include two second sacrificial separation sections 16B1 and 16B2 .

[0257] Fig.31A 1 is a top view of the fourth layer 14 for explaining a method of forming a plurality of linear sacrificial openings LV1', LV2'. Fig.31B For along Fig.31A A-A' cross-sectional view. Fig.31C For along Fig.31A A1-A1' cross-sectional view.

[0258] like FIG. 31A to FIG. 31C As shown, a first hard mask layer HM1 is formed on the stacked body SB, the plurality of first sacrificial cell separation layers 16A' and the plurality of second sacrificial cell separation layers 16B'. The first hard mask layer HM1 may include silicon nitride.

[0259] Next, a mask layer MK1 is formed on the first hard mask layer HM1. The mask layer MK1 includes a hard mask material, a photoresist, or a combination thereof as an etching mask layer. The mask layer MK1 includes a plurality of line-type opening patterns ML. The plurality of line-type opening patterns ML extend along the third direction D3.

[0260] Next, the plurality of linear opening patterns ML of the mask layer MK1 are transferred to the first hard mask layer HM1 and the stack SB. For example, the mask layer MK1 is used as an etching barrier layer to etch the first hard mask layer HM1, and then the first hard mask layer HM1 is used as an etching barrier layer to etch the stack SB. Thus, a plurality of linear sacrificial openings LV1', LV2' are formed in the stack SB. The plurality of linear sacrificial openings LV1', LV2' include a plurality of first linear sacrificial openings LV1' and a plurality of second linear sacrificial openings LV2'. When viewed from a top view, the cross-sections of the plurality of first linear sacrificial openings LV1' and the plurality of second linear sacrificial openings LV2' are rectangles extending long along the third direction D3.

[0261] The stacked bodies SB between the first sacrificial separation sections 16A1 and 16A2 of the first sacrificial unit separation layers 16A' are etched to form a plurality of first linear sacrificial openings LV1'. The stacked bodies SB between the second sacrificial separation sections 16B1 and 16B2 of the second sacrificial unit separation layers 16B' are etched to form a plurality of second linear sacrificial openings LV2'.

[0262] The plurality of first line-type sacrificial openings LV1 ′ and the plurality of second line-type sacrificial openings LV2 ′ vertically extend along the first direction D1 .

[0263] The first line-shaped sacrificial openings LV1' and the first sacrificial separation sections 16A1 and 16A2 of the first sacrificial unit separation layers 16A' do not contact each other. The second line-shaped sacrificial openings LV2' and the second sacrificial separation sections 16B1 and 16B2 of the second sacrificial unit separation layers 16B' do not contact each other.

[0264] As described above, in order to form the plurality of first line-type sacrificial openings LV1 ′ and the plurality of second line-type sacrificial openings LV2 ′, line patterning using one mask layer MK1 is performed.

[0265] Fig.32A 1 is a top view for explaining a method for forming the preliminary horizontal layer 14A. Fig.32B For along Fig.32A A1-A1' cross-sectional view. Fig.32C For along Fig.32A A-A' cross-sectional view.

[0266] like FIG. 32A to FIG. 32C As shown, after removing the mask layer MK, a portion of the first hard mask layer HM1 is trimmed.

[0267] Next, the first layer 12A and the third layer 12B are selectively removed through the plurality of line-type sacrificial openings LV1 ′, LV2 ′.

[0268] Next, the plurality of second layers 13 and the plurality of fourth layers 14 are recessed. In order to recess the plurality of second layers 13 and the plurality of fourth layers 14, wet etching or dry etching is used. In the present embodiment, the plurality of fourth layers 14 are partially etched during the removal of the plurality of second layers 13. Thus, the plurality of second layers 13 are removed, and the fourth layer 14 is thinned as shown by the reference numeral "14A". The recessing process for forming the thinned fourth layer 14A (i.e., the preliminary horizontal layer 14A) may be referred to as a thinning process or a trimming process of the fourth layer 14. The plurality of preliminary horizontal layers 14A may be referred to as a thin-body active layer. The plurality of preliminary horizontal layers 14A may include a single crystal silicon layer.

[0269] The plurality of preliminary horizontal layers 14A are formed by the recessing process of the plurality of fourth layers 14 as described above, and a plurality of horizontal type recessed parts 18 are formed between the plurality of preliminary horizontal layers 14A. The upper and lower surfaces of the plurality of preliminary horizontal layers 14A include planes, respectively.

[0270] When viewed from a top view, the plurality of preliminary horizontal layers 14A are in a cross shape. The sides of the plurality of preliminary horizontal layers 14A may be in a bent shape or a rounded shape.

[0271] After forming the plurality of preliminary horizontal layers 14A, the plurality of linear sacrificial openings are expanded as shown by reference numerals LV1 and LV2. The plurality of preliminary horizontal layers 14A are separated from each other in the second direction D2 by the plurality of sacrificial openings LV1 and LV2. The plurality of preliminary horizontal layers 14A are in a merged shape of a plurality of cross shapes along the third direction D3.

[0272] During the formation of the plurality of preliminary horizontal layers 14A, the surface of the lower structure 11 may be recessed by a predetermined depth, thereby increasing the depth of the plurality of linear sacrificial openings LV1 and LV2.

[0273] A plurality of first linear sacrificial openings LV1 and a plurality of second linear sacrificial openings LV2 are alternately arranged between a plurality of preliminary horizontal layers 14A along the second direction D2. A plurality of first linear sacrificial openings LV1 are arranged between a plurality of first sacrificial separation sections 16A1 and 16A2 along the second direction D2, and a plurality of second linear sacrificial openings LV2 are arranged between a plurality of second sacrificial separation sections 16B1 and 16B2 along the second direction D2.

[0274] Fig.33A 1 is a top view for explaining a method of forming the first insulating layer 19 and the second insulating layer 20. Fig.33B For along Fig.33A A1-A1' cross-sectional view. Fig.33C For along Fig.33A A-A' cross-sectional view.

[0275] like FIG. 33A to FIG. 33C As shown, a plurality of first insulating layers 19 are formed to cover the plurality of preliminary horizontal layers 14A. The plurality of first insulating layers 19 may include silicon nitride. The plurality of first insulating layers 19 completely cover the upper surface, the lower surface and the side surfaces of the plurality of preliminary horizontal layers 14A.

[0276] During the formation of the plurality of first insulating layers 19, a dummy insulating layer 19D is formed on the surface of the lower structure 11. Parts of the plurality of first insulating layers 19 completely cover the upper surface, the lower surface, and the side surfaces of the first hard mask layer HM1.

[0277] Next, a second insulating layer 20 is formed on the plurality of first insulating layers 19. The second insulating layer 20 is filled between the plurality of vertically adjacent first insulating layers 19. The second insulating layer 20 may include silicon oxide. A portion of the second insulating layer 20 is conformally formed on the surface of the plurality of linear sacrificial openings LV1, LV2. The plurality of horizontal recesses 18 are filled with the first insulating layer 19 and the second insulating layer 20.

[0278] Next, a sacrificial column 21 is formed on the second insulating layer 20 located at the plurality of linear sacrificial openings LV1, LV2. As a sacrificial material, the sacrificial column 21 may include amorphous carbon. In another embodiment, a column cover layer may be further formed on the upper portion of the sacrificial column 21. The column cover layer may include a metal-based material. The column cover layer may include titanium nitride. The step of forming the sacrificial column 21 includes a step of depositing the sacrificial material and a step of planarizing the sacrificial material. The planarizing step for forming the sacrificial column 21 is performed until the uppermost first insulating layer 19 is exposed. The sacrificial column 21 is not formed between the plurality of vertically stacked first insulating layers 19.

[0279] The second insulating layer 20 and the sacrificial column 21 form a first sacrificial column structure SLV1 and a second sacrificial column structure SLV2 for filling a plurality of linear sacrificial openings LV1 and LV2. The first sacrificial column structure SLV1 fills the first linear sacrificial opening LV1, and the second sacrificial column structure SLV2 fills the second linear sacrificial opening LV2. In another embodiment, the first sacrificial column structure SLV1 and the second sacrificial column structure SLV2 may include an insulating material, a carbon-containing material, a metal-based material, or a combination thereof. In another embodiment, the first sacrificial column structure SLV1 and the second sacrificial column structure SLV2 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof. When viewed from a top view, the first sacrificial column structure SLV1 and the second sacrificial column structure SLV2 are linear sacrificial columns extending along a third direction D3. In another embodiment, a portion of the first insulating layer 19 is conformally formed on the surfaces of the plurality of linear sacrificial openings LV1 , LV2 , and thus the first sacrificial column structure SLV1 and the second sacrificial column structure SLV2 also include a portion of the first insulating layer 19 .

[0280] Refer again Fig.33B , a first insulating layer 19 may be formed between the plurality of preliminary horizontal layers 14A, and a second insulating layer 20 may be disposed inside the first insulating layer 19. The first insulating layer 19 may surround the second insulating layer 20.

[0281] As described above, a cell mold structure is formed by forming a plurality of preliminary horizontal layers 14A, a plurality of first insulating layers 19, and a plurality of second insulating layers 20. The cell mold structure includes a plurality of cell molds CM. Each cell mold CM includes a plurality of mold layers. The plurality of mold layers are a plurality of preliminary horizontal layers 14A, a plurality of first insulating layers 19, and a plurality of second insulating layers 20. In each cell mold CM, a first sacrificial layer, a semiconductor layer, and a second sacrificial layer are stacked in the order of one layer. Among them, the first sacrificial layer and the second sacrificial layer are the first insulating layer 19, and the semiconductor layer is the preliminary horizontal layer 14A. Each cell mold CM includes an ONSN (Oxide-Nitride-Silicon-Nitride) stack. Among them, the ONSN stack is a structure in which silicon oxide, a first silicon nitride, a single crystal silicon layer, and a second silicon nitride are stacked in sequence. Silicon oxide corresponds to a plurality of second insulating layers 20, the first silicon nitride and the second silicon nitride correspond to a plurality of first insulating layers 19, and the single crystal silicon layer corresponds to a plurality of preliminary horizontal layers 14A. The unit mold structure including a plurality of unit molds CM may be referred to as a vertical stack. In another viewpoint, the unit mold structure includes an ONSNO (Oxide-Nitride-Silicon-Nitride-Oxide) stack. The ONSNO stack is a structure in which a first silicon oxide, a first silicon nitride, a single crystal silicon layer, a second silicon nitride, and a second silicon oxide are stacked in sequence.

[0282] pass FIG. 28A to FIG. 33C The sub-stack of the stack SB is replaced by a unit mold. The first layer 12A, the second layer 13, and the third layer 12B are replaced by a plurality of first insulating layers 19 and a plurality of second insulating layers 20. The fourth layer 14 is formed as a preliminary horizontal layer 14A. The plurality of first insulating layers 19 may be referred to as trimming target layers.

[0283] Fig.34A 2 is a top view for explaining a method of forming a plurality of unit separation openings 22A' and 22B'. Fig.34B For along Fig.34A A1-A1' cross-sectional view.

[0284] like Fig.34A and Fig.34BAs shown, in order to form a plurality of unit separation openings 22A', 22B', a plurality of first sacrificial unit separation layers 16A' and a plurality of second sacrificial unit separation layers 16B' are removed. During the removal of the first sacrificial unit separation layers 16A' and the second sacrificial unit separation layers 16B', the first sacrificial column structure SLV1 and the second sacrificial column structure SLV2 are covered by a mask layer (not shown). The side surfaces of the plurality of preliminary horizontal layers 14A and the plurality of first insulating layers 19 are exposed in the third direction D3 due to the plurality of unit separation openings 22A', 22B'.

[0285] The plurality of first unit separation openings 22A' respectively include two first unit separation opening sections 22A1 and 22A2, and the plurality of second unit separation openings 22B' respectively include two second unit separation opening sections 22B1 and 22B2. The first sacrificial column structure SLV1 is located between the plurality of first unit separation opening sections 22A1 and 22A2 along the second direction D2. The second sacrificial column structure SLV2 is located between the plurality of second unit separation opening sections 22B1 and 22B2 along the second direction D2.

[0286] Fig.35A 14B is a top view for explaining a method for forming a plurality of horizontal layers 14B. Fig.35B For along Fig.35A A1-A1' cross-sectional view.

[0287] like Fig.35A and Fig.35B As shown, the side surfaces of the plurality of preliminary horizontal layers 14A are trimmed by the plurality of cell separation openings 22A', 22B'. Thus, a plurality of horizontal layers 14B are formed. Horizontal level gaps 14R are formed on both sides of the plurality of horizontal layers 14B. The horizontal level gaps 14R and the plurality of horizontal layers 14B are disposed between the plurality of first insulating layers 19. The horizontal layers 14B may be referred to as "trimmed horizontal layer patterns".

[0288] During the formation of the plurality of horizontal layers 14B, the surface of the lower structure 11 (eg, the bottom surface of the plurality of cell separation openings 22A′, 22B′) may be recessed to a predetermined depth.

[0289] A plurality of horizontal layers 14B are arranged between a plurality of sacrificial column structures SLV1 and SLV2 along the second direction D2. When viewed from a top view, the plurality of horizontal layers 14B are in a cross-shape. The plurality of horizontal layers 14B are in a cross-shape smaller in size than the plurality of preliminary horizontal layers 14A. The plurality of preliminary horizontal layers 14A are in a shape in which a plurality of cross shapes are merged, and the plurality of horizontal layers 14B are in a shape in which a plurality of cross shapes are separated separately along a third direction D3. A horizontal level gap 14R is formed between the plurality of horizontal layers 14B arranged along the third direction D3. A plurality of first sacrificial column structures SLV1 and a second sacrificial column structure SLV2 are arranged between the plurality of horizontal layers 14B along the second direction D2.

[0290] Fig.36A 2 is a top view for explaining a method for forming a horizontal level spacer 23. Fig.36B For along Fig.36A A1-A1' cross-sectional view.

[0291] like Fig.36A and Fig.36B As shown, horizontal level spacers 23 are formed on the sidewalls of the plurality of horizontal layers 14B. The step of forming the plurality of horizontal level spacers 23 includes the step of forming a spacer material on the side of the plurality of horizontal layers 14B and the step of etching the spacer material. The plurality of horizontal level spacers 23 may include an insulating material, for example, silicon oxide. The horizontal level spacers 23 fill the horizontal level gaps 14R. The plurality of horizontal layers 14B arranged along the third direction D3 are separated from each other by the horizontal level spacers 23.

[0292] Fig.37A 1 is a top view for explaining a method for trimming the plurality of first insulating layers 19. Fig.37B For along Fig.37A A1-A1' cross-sectional view.

[0293] like Fig.37A and Fig.37B As shown, a portion of the plurality of first insulating layers 19 is horizontally trimmed through the plurality of unit separation openings 22A', 22B'. After the trimming, the plurality of first insulating layers 19 remain as shown by reference numeral 19A. Therefore, when viewed from the third direction D3, the second insulating layer 20 is disposed between the plurality of first insulating layers 19A. One second insulating layer 20 is disposed between a pair of first insulating layers 19A.

[0294] according to Fig.35A37C , between the plurality of first cell separation openings 22A' and between the plurality of second cell separation openings 22B', the width of the plurality of first insulating layers 19A in the third direction D3 is greater than the width of the plurality of horizontal layers 14B. Specifically, the trimming depth of the plurality of first insulating layers 19A in the third direction D3 is less than the trimming depth of the plurality of preliminary horizontal layers 14A.

[0295] A pair of first insulating layers 19A are vertically overlapped in one horizontal layer 14B. The trimmed first insulating layer 19A may be referred to as a trimmed first insulating layer.

[0296] Fig.38A 2 is a top view for explaining a method of forming a plurality of unit separation layers 24A' and 24B'. Fig.38B For along Fig.38A A1-A1' cross-sectional view. Fig.38C For along Fig.38A A-A' cross-sectional view. Fig.38A It can be a top view at the level of the first insulating layer 19A for explaining a method of forming the plurality of cell separation layers 24A′ and 24B′.

[0297] like FIG. 38A to FIG. 38C As shown, a plurality of unit separation layers 24A', 24B' are formed to fill the plurality of unit separation openings 22A', 22B'. The plurality of unit separation layers 24A', 24B' include a plurality of first unit separation layers 24A' and a plurality of second unit separation layers 24B'. The plurality of first unit separation layers 24A' and the plurality of second unit separation layers 24B' may contain the same substance. The plurality of first unit separation layers 24A' and the plurality of second unit separation layers 24B' may be formed of an insulating material. For example, the plurality of first unit separation layers 24A' and the plurality of second unit separation layers 24B' may contain silicon oxide, silicon nitride, silicon carbide oxide, silicon carbon nitride, or a combination thereof. When viewed from a top view, the outermost material of the plurality of first unit separation layers 24A' and the plurality of second unit separation layers 24B' may contain silicon carbide oxide.

[0298] The step of forming a plurality of first unit separation layers 24A' and a plurality of second unit separation layers 24B' includes the step of forming an insulating material for filling the plurality of unit separation openings 22A', 22B' and the step of flattening the insulating material to expose the surface of the topmost first insulating layer 19A. The plurality of first unit separation layers 24A' and the plurality of second unit separation layers 24B' may have different sizes or different volumes. The plurality of first unit separation layers 24A' and the plurality of second unit separation layers 24B' may be a dual structure of silicon oxide and silicon carbide oxide. For example, silicon carbide oxide is deposited after silicon oxide is deposited. In another embodiment, the plurality of first unit separation layers 24A' and the plurality of second unit separation layers 24B' include embedded air gaps. The plurality of first unit separation layers 24A' and the plurality of second unit separation layers 24B' extend vertically along the first direction D1.

[0299] The plurality of first cell separation layers 24A' respectively include two first cell separation sections 24A1 and 24A2. The plurality of second cell separation layers 24B' respectively include two second cell separation sections 24B1 and 24B2. The first sacrificial column structure SLV1 is located between the plurality of first cell separation sections 24A1 and 24A2. The second sacrificial column structure SLV2 is located between the plurality of second cell separation sections 24B1 and 24B2.

[0300] The first cell separation layers 24A' and the second cell separation layers 24B' correspond to Fig.28A and Fig.28B The plurality of cell separation layers ISOA and ISOB shown. The plurality of first cell separation layers 24A' and the second cell separation layers 24B' respectively include a stack of a cell separation liner layer and a cell separation gap filling layer. The plurality of cell separation liner layers may include silicon oxide, and the plurality of cell separation gap filling layers may include silicon carbon oxide. In another embodiment, the plurality of first cell separation layers 24A' and the second cell separation layers 24B' include embedded air gaps, which are provided when forming the plurality of cell separation gap filling layers.

[0301] The plurality of first cell separation layers 24A' and the second cell separation layers 24B' are in direct contact with the plurality of first insulating layers 19 A. A horizontal level spacer 23 is provided between the plurality of horizontal layers 14B and the plurality of first cell separation layers 24A' and the second cell separation layers 24B'.

[0302] Fig.39 2 is a top view for explaining a method for forming a plurality of initial linear vertical openings 27. FIG. 40A to FIG. 40C For along Fig.39A-A' cross-sectional view.

[0303] like Fig.40A As shown, in order to form the hard mask level recess 25 , the first hard mask layer HM1 and the uppermost first insulating layer 19A are removed.

[0304] like Fig.40B As shown, a top dielectric layer (26) is formed to fill the hard mask level recess 25. The top dielectric layer 26 may include silicon oxide.

[0305] like Fig.40C As shown, the plurality of first sacrificial pillar structures SLV1 are removed to form a plurality of initial line-shape vertical openings 27 . The plurality of first insulating layers 19A and the dummy insulating layer 19D are exposed through the initial line-shape vertical openings 27 .

[0306] Next, the plurality of second insulating layers 20 are horizontally recessed. The plurality of first insulating layers 19A and the dummy insulating layer 19D are exposed through the initial line-type vertical openings 27 .

[0307] Next, the plurality of first insulating layers 19A and the dummy insulating layers 19D are selectively recessed horizontally, thereby forming a plurality of first insulating layer patterns 19B and a plurality of insulating level recesses 28 . Parts of the plurality of horizontal layers 14B are exposed through the plurality of insulating level recesses 28 .

[0308] Fig.41A FIG. 2 is a top view for explaining a method for forming a plurality of linear vertical sacrificial structures 29. Fig.41B For along Fig.41A A-A' cross-sectional view.

[0309] like Fig.41A and Fig.41B As shown, a plurality of line-type vertical sacrificial structures 29 are formed to fill the plurality of insulating level recesses 28 and the plurality of initial line-type vertical openings 27. The plurality of line-type vertical sacrificial structures 29 may include insulating materials. The plurality of line-type vertical sacrificial structures 29 may include silicon oxide, silicon nitride, titanium nitride, amorphous carbon, or a combination thereof.

[0310] Fig.42A 3 is a top view for explaining a method of forming a first linear vertical opening 32L and a plurality of horizontal level recesses 33. Fig.42B For along Fig.42A A-A' cross-sectional view.

[0311] like Fig.42A and Fig.42BAs shown, a first linear vertical opening 32L is formed between the plurality of second unit separation sections 24B1 and 24B2. The step of forming the first linear vertical opening 32L includes the steps of removing the sacrificial pillar 21 of the second sacrificial pillar structure SLV2, replacing the dummy insulating layer 19D with the first protection layer BF1, and cutting the plurality of second insulating layers 20.

[0312] The steps of replacing the dummy insulating layer 19D with the first protective layer BF1 can be referred to FIG. 17A to FIG. 18B .

[0313] The second protective layer BF2 is formed in the lower region of the first linear vertical opening 32L. For example, in order to form the second protective layer BF2, the surface of the lower structure 11 is oxidized.

[0314] The first linear vertical opening 32L includes a plurality of first vertical expansion portions 32E1 and a second vertical expansion portion 32E2 extending along the second direction D2. The plurality of first vertical expansion portions 32E1 and the second vertical expansion portion 32E2 of the first linear vertical opening 32L are formed by cutting a side surface of the plurality of horizontal layers 14B. The cutting of the plurality of horizontal layers 14B is performed after the step of cutting the plurality of second insulating layers 20. When viewed from a top view, the plurality of first vertical expansion portions 32E1 and the second vertical expansion portion 32E2 of the plurality of first linear vertical openings 32L are in a shape horizontally recessed from a side surface of the plurality of second unit separation sections 24B1, 24B2. The plurality of first vertical expansion portions 32E1 of the plurality of first linear vertical openings 32L are located between the plurality of second unit separation sections 24B1 along the third direction D3. The plurality of second vertical expansion portions 32E2 of the plurality of first linear vertical openings 32L are located between the plurality of second unit separation sections 24B2 along the third direction D3. The plurality of first vertical expansion parts 32E1 and the plurality of second vertical expansion parts 32E2 are symmetrical to each other along the second direction D2 and are spaced apart from each other.

[0315] Subsequently, in order to form a plurality of horizontal level recesses 33, the plurality of first insulating layer patterns 19B are removed through the first line-type vertical openings 32L. Parts of the plurality of horizontal layers 14B are exposed through the plurality of horizontal level recesses 33. The plurality of horizontal level recesses 33 are located between the second insulating layer 20 and the horizontal layer 14B. Two horizontal level recesses 33 face each other with one horizontal layer 14B in between.

[0316] Fig.43A 2 is a top view for explaining a method for forming a plurality of horizontal conductive lines 35. Fig.43B For along Fig.43A A-A' cross-sectional view.

[0317] like Fig.43A and Fig.43BAs shown, an interlayer insulating layer 34 is formed on the exposed portions of the plurality of horizontal layers 14B. The interlayer insulating layer 34 may include a gate insulating layer. The interlayer insulating layer 34 corresponds to Figures 1A to 3B The interlayer insulating layer GD is shown.

[0318] The interlayer insulating layer 34 is formed by oxidizing the surfaces of the plurality of horizontal layers 14B. In another embodiment, the interlayer insulating layer 34 is formed by a deposition process of silicon oxide.

[0319] The interlayer insulating layer 34 may include silicon oxide, silicon nitride, metal oxide, metal oxynitride, metal silicate, high-k material, ferroelectric material, anti-ferroelectric material, or a combination thereof. The interlayer insulating layer 34 may include SiO2, Si3N4, HfO2, Al2O3, ZrO2, AlON, HfON, HfSiO, HfSiON, or a combination thereof.

[0320] A horizontal conductive line 35 for filling a plurality of horizontal level recesses 33 is formed on the interlayer insulating layer 34. The step of forming the horizontal conductive line 35 may include: a step of depositing a conductive material for filling a plurality of horizontal level recesses 33 on the interlayer insulating layer 34 and a step of etching back the conductive material. The horizontal conductive line 35 includes a pair of first horizontal conductive lines 35A and second horizontal conductive lines 35B facing each other with the horizontal layer 14B in between. The first horizontal conductive line 35A and the second horizontal conductive line 35B may include a metal-base material, a semiconductor material, or a combination thereof. The first horizontal conductive line 35A and the second horizontal conductive line 35B may include titanium nitride, tungsten, polysilicon, molybdenum, molybdenum nitride, or a combination thereof. For example, the first horizontal conductive line 35A and the second horizontal conductive line 35B may include a TiN / W stack in which titanium nitride and tungsten are sequentially stacked. The first horizontal conductive line 35A and the second horizontal conductive line 35B may include an N-type work function material or a P-type work function material. The N-type work function material may have a low work function (Low work function) of 4.5 eV or less, and the P-type work function material may have a high work function (High work function) of 4.5 eV or more.

[0321] The horizontal conductive lines 35 correspond to Figures 1A to 1D The second conductive line DWL shown, the first horizontal conductive line 35A and the second horizontal conductive line 35B correspond to the upper horizontal line G1 and the lower horizontal line G2. Figures 1A to 1DAs shown, the first horizontal conductive line 35A and the second horizontal conductive line 35B are each in a cross shape and may include a channel overlapping portion WLP and a plurality of channel non-overlapping portions NOL.

[0322] A first capping layer 36 is formed on one side of the horizontal conductive line 35. The first capping layer 36 may include silicon oxide, silicon nitride, or a combination thereof. To form the first capping layer 36, deposition and etching back of a capping material are performed.

[0323] During or after forming the first cover layer 36 , a portion of the interlayer insulating layer 34 is removed to expose the first edge portion of each horizontal layer 14B.

[0324] Fig.44A 2 is a top view for explaining a method for forming a plurality of vertical conductive lines 39. Fig.44B For along Fig.44A A-A' cross-sectional view.

[0325] like Fig.44A and Fig.44B As shown, a first vertical conductive line 39A and a second vertical conductive line 39B connected to the first edge portion of each horizontal layer 14B are formed. The first vertical conductive line 39A and the second vertical conductive line 39B fill a plurality of first vertical type expansions 32E1 and a second vertical type expansion 32E2, respectively. The first vertical conductive line 39A and the second vertical conductive line 39B are connected to the plurality of horizontal layers 14B in common. The first vertical conductive line 39A and the second vertical conductive line 39B may include titanium nitride, tungsten, or a combination thereof. The first vertical conductive line 39A and the second vertical conductive line 39B include a bit line. The step of forming the first vertical conductive line 39A and the second vertical conductive line 39B may include: a step of depositing a conductive material to fill a plurality of first vertical type expansions 32E1 and a second vertical type expansion 32E2 of a plurality of first line-type vertical openings 32L, and a step of etching back the conductive material. A plurality of first vertical conductive lines 39A fill a plurality of first vertical type expansions 32E1. A plurality of second vertical conductive lines 39B fill a plurality of second vertical type expansions 32E2. The plurality of first vertical conductive lines 39A and the plurality of second vertical conductive lines 39B are electrically separated.

[0326] When viewed from a top view, the plurality of first vertical conductive lines 39A are located between the plurality of second unit separation sections 24B1 along the third direction D3. The plurality of second vertical conductive lines 39B are located between the plurality of second unit separation sections 24B2 along the third direction D3. The plurality of first vertical conductive lines 39A and the plurality of second vertical conductive lines 39B are symmetrical to each other and spaced apart from each other along the second direction D2. One side of the plurality of second unit separation sections 24B1 and one side of the plurality of first vertical conductive lines 39A are self-aligned along the third direction D3. One side of the plurality of second unit separation sections 24B2 and one side of the plurality of second vertical conductive lines 39B are self-aligned along the third direction D3.

[0327] As described above, the first vertical conductive line 39A and the second vertical conductive line 39B are independent vertical conductive lines that respectively fill the first vertical expansion parts 32E1 and the second vertical expansion parts 32E2 of the first line-type vertical opening 32L. The first vertical conductive line 39A and the second vertical conductive line 39B are formed by self-alignment with one side of the plurality of second unit separation sections 24B2. Since the first vertical conductive line 39A and the second vertical conductive line 39B are formed by self-alignment with one side of the plurality of second unit separation sections 24B2, the interval between the adjacent plurality of first vertical conductive lines 39A and the plurality of second vertical conductive lines 39B can be sufficiently ensured, thereby reducing parasitic capacitance.

[0328] Before forming the first vertical conductive line 39A and the second vertical conductive line 39B, an additional second bottom protective layer BF21 is formed on the second bottom protective layer BF2. The additional second bottom protective layer BF21 may include silicon oxide.

[0329] Before forming the first vertical conductive line 39A and the second vertical conductive line 39B, the first doped region 37 is formed. The first doped region 37 is formed in the first edge portion of the plurality of horizontal layers 14B. The step of forming the first doped region 37 includes: a step of depositing polysilicon doped with N-type impurities, a step of heat treatment, and a step of removing the doped polysilicon. The first doped region 37 may include impurities diffused from the doped polysilicon. In another embodiment, the first doped region 37 may be formed by a doping process of impurities.

[0330] like Fig.21A and Fig. 21B As shown, a first contact node 38 is also formed. The first contact node 38 may include doped polysilicon. The first doped region 37 includes impurities diffused from the first contact node 38. A metal silicide layer may also be formed between the first vertical conductive line 39A and the second vertical conductive line 39B and the first contact node 38.

[0331] The first vertical conductive line 39A and the second vertical conductive line 39B correspond to FIG. 28A to FIG. 28E The first vertical conductive line BLA and the second vertical conductive line BLB are shown.

[0332] After forming the first vertical conductive lines 39A and the second vertical conductive lines 39B, a vertical separation layer 39C is formed. The vertical separation layer 39C may include an insulating material. The vertical separation layer 39C is located between the plurality of first vertical conductive lines 39A and the plurality of second vertical conductive lines 39B.

[0333] Fig.45A 4 is a top view for explaining a method of forming a plurality of linear vertical openings 40 and a plurality of storage openings 41. Fig.45B For along Fig.45A A-A' cross-sectional view.

[0334] like Fig.45A and Fig.45B As shown, in order to form a plurality of second linear vertical openings 40 for exposing the second edge portions of the plurality of horizontal layers 14B, a portion of the linear vertical sacrificial structure 29 is removed. One side of the plurality of horizontal layers 14B is exposed through the plurality of second linear vertical openings 40. The plurality of second linear vertical openings 40 extend horizontally along the third direction D3.

[0335] Finally, the plurality of second line-type vertical openings 40 is a structure formed by line patterning of the stacked body SB.

[0336] The third protective layer BF3 is formed on the surface of the lower structure 11. The third protective layer BF3 may include silicon oxide.

[0337] The second edge portions of the plurality of horizontal layers 14B are horizontally recessed along the second direction D2 , so that the horizontal layers remain as indicated by reference numeral “HL”.

[0338] In order to form the second cover layer 29C, the remaining linear vertical sacrificial structure 29 is selectively recessed. As a result, a plurality of second linear vertical openings 40 are horizontally expanded. The second cover layer 29C may include silicon oxide, silicon nitride, or a combination thereof. By forming the second cover layer 29C, a plurality of storage openings 41 are formed. The storage openings 41 may be referred to as capacitor openings.

[0339] During the formation of the second cover layer 29C, by removing a portion of the line-type vertical sacrificial structure 29 , a lowermost level insulating layer 29L is formed on the side surfaces of the plurality of first protection layers BF1 .

[0340] The horizontal layer HL includes a first edge and a second edge. The first edge is a portion connected to the plurality of first vertical conductive lines 39A and the second vertical conductive lines 39B, and the second edge is a portion exposed through the plurality of storage openings 41.

[0341] The plurality of storage openings 41 are located between the plurality of second insulating layers 20. A plurality of second cover layers 29C are disposed at the lower portion and the upper portion of the horizontal layer HL, respectively.

[0342] As described above, the step of forming the horizontal layer HL and the plurality of storage openings 41 includes the step of forming the plurality of second line-type vertical openings 40 , the step of recessing the plurality of horizontal layers 14B, and the step of forming the second cover layer 29C.

[0343] Fig.46A 4 is a top view for explaining a method of forming a plurality of second contact nodes 42. Fig.46B For along Fig.46A A-A' cross-sectional view.

[0344] like Fig.46A and Fig.46B As shown, a second doped region 43 is formed in the second edge of the horizontal layer HL. The step of forming the second doped region 43 includes a step of depositing polysilicon doped with N-type impurities, a step of thermal treatment, and a step of removing the doped polysilicon. The second doped region 43 may include impurities diffused from the doped polysilicon. In another embodiment, after the thermal treatment step, the doped polysilicon may remain.

[0345] A second contact node 42 is formed at a second edge of the horizontal layer HL. The second contact node 42 may include doped polysilicon. The second doped region 43 includes impurities diffused from the second contact node 42.

[0346] The horizontal layer HL includes a first doping region 37, a second doping region 43 and a channel 44 which are horizontally arranged along the second direction D2. The channel 44 is defined between the first doping region 37 and the second doping region 43. The channel 44 vertically overlaps the horizontal conductive line 35. Figures 1A to 1C As shown, the horizontal layer HL is in the shape of a cross, and the channel 44 is also in the shape of a cross.

[0347] A first electrode 45 of the data storage element is formed at the second contact node 42. The first electrode 45 is in a horizontally oriented cylindrical shape. A plurality of first electrodes 45 are respectively disposed at a plurality of storage openings 41. A plurality of first electrodes 45 adjacent along the second direction D2 are separated by a plurality of linear vertical openings 40. A plurality of first electrodes 45 adjacent along the third direction D3 are separated by a plurality of second unit separation layers 24A.

[0348] Then, if Fig.25A and Fig.25B As shown in FIG. 1 , the plurality of second insulating layers 20 are horizontally recessed. Thus, the outer wall of the first electrode 45 is exposed. The recessed plurality of second insulating layers 20 corresponds to Figure 3BThe inter-cell insulating layer IL is shown. During the horizontal depression of the plurality of second insulating layers 20, a portion of the plurality of cell separation layers 24A', 24B' is horizontally depressed. Thus, the outer walls of the plurality of first electrodes 45 adjacent to each other along the third direction D3 are exposed. The plurality of first electrodes 45 may be in a semi-cylindrical shape.

[0349] A dielectric layer 47 and a second electrode 48 are sequentially formed on the plurality of first electrodes 45. The first electrodes 45, the dielectric layer 47 and the second electrode 48 form a data storage element CAP.

[0350] The first electrode 45 includes an inner space and multiple outer sides, and the inner space of the first electrode 45 includes multiple inner sides. The multiple outer sides of the first electrode 45 include a vertical outer side and multiple horizontal outer sides. The vertical outer side of the first electrode 45 extends vertically along the first direction D1, and the multiple horizontal outer sides of the first electrode 45 extend horizontally along the second direction D2 or the third direction D3. The inner space of the first electrode 45 is a three-dimensional space. The dielectric layer 47 conformally covers the multiple inner sides and multiple outer sides of the first electrode 45. A portion of the outer sides of the multiple outer sides of the first electrode 45 are electrically connected to the second doping region 43 of the horizontal layer HL.

[0351] The first electrode 45 is in a cylindrical shape. The cylindrical shape of the first electrode 45 includes a plurality of cylindrical inner side surfaces and a plurality of cylindrical outer side surfaces. A portion of the outer side surfaces of the plurality of cylindrical outer side surfaces of the first electrode 45 are electrically connected to the second doping region 43 of the horizontal layer HL. The dielectric layer 47 and the second electrode 48 are disposed on the plurality of cylindrical inner side surfaces of the first electrode 45.

[0352] The second electrode 48 extends vertically along the first direction D1 and horizontally along the third direction D3 .

[0353] FIG. 47A to FIG. 47C A diagram for explaining an example of a method for manufacturing a semiconductor device according to another embodiment. FIG. 47A to FIG. 47C for 7A to 7C The modified example of the multiple sacrificial openings V1', V2' shown. FIG. 47A to FIG. 47C for FIG. 31A to FIG. 31C A variation of the plurality of sacrificial openings LV1 ′, LV2 ′ is shown.

[0354] Fig.47A It is a top view of the fourth layer 14 level for explaining the method of forming the plurality of sacrificial separation openings 15A′ and 15B.

[0355] Reference Figure 5A , Figure 5B , Figure 5C , Fig.29A , Fig.29B and Fig.47A, the stack SB is formed on the upper part of the lower structure 11. The stack SB is formed by alternately stacking a plurality of sub-stacks. Each sub-stack can be stacked in the order of a first layer 12A, a second layer 13, a third layer 12B and a fourth layer 14. The plurality of first layers 12A and the plurality of third layers 12B are formed of the same material, such as silicon germanium. The plurality of second layers 13 may include single crystal silicon. The fourth layer 14 may include single crystal silicon. The first layer 12A, the second layer 13, the third layer 12B and the fourth layer 14 are formed by an epitaxial growth process.

[0356] A portion of the stacked body SB is etched to form a plurality of sacrificial separation openings 15A', 15B. The plurality of sacrificial separation openings 15A', 15B include a plurality of large openings 15A' and a plurality of small openings 15B as initial openings for device separation.

[0357] The plurality of large openings 15A' respectively include two large segments 15A1 and 15A2, and the plurality of small openings 15B do not include a small segment. Thus, the large segments 15A1 and 15A2 and the plurality of small openings 15B may have the same size.

[0358] As described above, the plurality of large openings 15A' of the sacrificial separation openings are divided into large segments 15A1 and 15A2, and the plurality of small openings 15B are formed in an undivided state in which a plurality of segments are merged.

[0359] Fig.47B It is a top view of the fourth layer 14 for explaining the method of forming the plurality of sacrificial cell separation layers 16A′ and 16B.

[0360] Reference Fig. 6A , Figure 6B , Figure 6C , Fig. 30A , Fig. 30B and Fig.47B , forming a plurality of sacrificial unit separation layers 16A', 16B for filling the plurality of sacrificial separation openings 15A', 15B. The plurality of sacrificial unit separation layers 16A', 16B include a plurality of first sacrificial unit separation layers 16A' and a plurality of second sacrificial unit separation layers 16B. The plurality of first sacrificial unit separation layers 16A' fill the plurality of large openings 15A', and the plurality of second sacrificial unit separation layers 16B fill the plurality of small openings 15B.

[0361] The plurality of first sacrificial unit separation layers 16A′ include two first sacrificial separation sections 16A1 and 16A2 , and the plurality of second sacrificial unit separation layers 16B may not include separation sections.

[0362] Fig.47CIt is a top view of the fourth layer 14 for explaining the method of forming the plurality of sacrificial openings LV1 ′ and HV2 ′.

[0363] Reference Fig. 7A , Figure 7B , Figure 7C , Fig.31A , Fig.31B and Fig.47C A first hard mask layer HM1 is formed on the stacked body SB, the plurality of first sacrificial unit separation layers 16A′, and the plurality of second sacrificial unit separation layers 16B. The first hard mask layer HM1 may include silicon nitride.

[0364] Next, a mask layer MK1 is formed on the first hard mask layer HM1. The mask layer MK1 includes a hard mask material, a photoresist or a combination thereof as an etching mask layer. The mask layer MK1 includes a plurality of line-type opening patterns ML and a plurality of hole-type opening patterns MH. The plurality of line-type opening patterns ML extend along the third direction D3.

[0365] Next, the plurality of linear opening patterns ML and the plurality of hole-type opening patterns MH of the mask layer MK1 are transferred to the first hard mask layer HM1 and the stack SB. For example, the mask layer MK1 is used as an etching barrier layer to etch the first hard mask layer HM1, and then the first hard mask layer HM1 is used as an etching barrier layer to etch the stack SB. Thus, a plurality of linear sacrificial openings LV1' and a plurality of hole-type sacrificial openings HV2' are formed in the stack SB. When viewed from a top view, the cross-section of the plurality of linear sacrificial openings LV1' is a rectangle extending long along the third direction D3.

[0366] The stacked body SB between the first sacrificial separation sections 16A1 and 16A2 of the first sacrificial unit separation layers 16A' is etched to form a plurality of linear sacrificial openings LV1'. The plurality of linear sacrificial openings LV1' are disposed between the plurality of first sacrificial separation sections 16A1 and 16A2 adjacent to each other along the second direction D2. The stacked body SB between the second sacrificial unit separation layers 16B is etched to form a plurality of hole-type sacrificial openings HV2'. The plurality of hole-type sacrificial openings HV2' are disposed between the plurality of second sacrificial unit separation layers 16B adjacent to each other along the third direction D3.

[0367] The plurality of line-type sacrificial openings LV1 ′ and the plurality of hole-type sacrificial openings HV2 ′ vertically extend along the first direction D1 .

[0368] The plurality of line-shaped sacrificial openings LV1' and the plurality of first sacrificial separation sections 16A1 and 16A2 of the plurality of first sacrificial unit separation layers 16A' do not contact each other. The plurality of hole-shaped sacrificial openings HV2' and the plurality of second sacrificial unit separation layers 16B do not contact each other.

[0369] As described above, in order to form a plurality of line-type sacrificial openings LV1 ′ and a plurality of hole-type sacrificial openings HV2 ′, line patterning and hole patterning using one mask layer MK1 are simultaneously performed.

[0370] Then, execute FIG. 8A to FIG. 26B A series of steps shown.

[0371] Fig.48 FIG. 1 is a schematic top view of a semiconductor device according to another embodiment. Fig.48 The semiconductor device 300 utilizes FIG. 47A to FIG. 47C The method shown is formed.

[0372] Fig.48 The semiconductor device 300 may be Figure 2 , Figure 3A and Figure 3B The semiconductor device 100 and Fig.28A The following is a detailed description of the repeated structural elements, which can be referred to in Figure 2 , Figure 3A , Figure 3B , Fig.28A and Fig.28B .

[0373] like Fig.48 As shown, the semiconductor device 300 includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory cells MC21 and MC22. The plurality of memory cells MC21 and MC22 can be connected to Figure 2 , Figure 3A , Figure 3B The plurality of memory cells MC shown are identical.

[0374] The memory cell array MCA includes a three-dimensional array of multiple memory cells MC21 and MC22. The three-dimensional array of multiple memory cells MC21 and MC22 includes a column array of multiple memory cells MC21 and MC22 and a row array of multiple memory cells MC21 and MC22. In the column array of multiple memory cells MC21 and MC22, multiple memory cells MC21 and MC22 are stacked along a first direction D1, and in the row array of multiple memory cells MC21 and MC22, multiple memory cells MC21 and MC22 are horizontally arranged along a second direction D2 and a third direction D3. The memory cell array MCA includes multiple sub-memory cell arrays MCA2 adjacent to each other along the second direction D2. The sub-memory cell array MCA2 includes a three-dimensional array of multiple first memory cells MC21 and a three-dimensional array of multiple second memory cells MC22.

[0375] The plurality of first memory cells MC21 and the second memory cells MC22 include a first conductive line BL, a horizontal layer HL, a second conductive line DWL, and a data storage element CAP. The horizontal layer HL includes a first doped region SR, a channel CH, and a second doped region DR. An interlayer insulating layer GD is located between the horizontal layer HL and the second conductive line DWL. The data storage element CAP includes a first electrode SN, a dielectric layer DE, and a second electrode PN. The plurality of first memory cells MC21 and the second memory cells MC22 also include a second contact node SNC between the horizontal layer HL and the data storage element CAP. Although not shown in the figure, as shown in FIG. Figure 1B As shown, the plurality of first memory cells MC21 and second memory cells MC22 further include a first contact node BLC between the horizontal layer HL and the first vertical conductive line BL. The plurality of second electrodes PN of the plurality of first memory cells MC21 and second memory cells MC22 adjacent along the second direction D2 are merged to form a common plate PL.

[0376] The common plate PL includes a shared portion PL_S that shares the first memory cells MC21 adjacent along the second direction D2 and a merged portion PL_M disposed between the plurality of first cell separation layers ISOA. The common plate PL is a cross-shape extending along the third direction D3 by a combination of the plurality of shared portions PL_S and the plurality of merged portions PL_M. The plurality of first cell separation layers ISOA are disposed between the plurality of data storage elements CAP along the third direction D3. The plurality of second cell separation layers ISOB are disposed between the plurality of first conductive wires BL along the third direction D3. The second conductive wire DWL is disposed between the plurality of first cell separation layers ISOA and the plurality of second cell separation layers ISOB along the second direction D2. The size of the plurality of first cell separation layers ISOA is larger than the plurality of second cell separation layers ISOB.

[0377] A plurality of first cell separation layers ISOA and a plurality of second cell separation layers ISOB are located between a plurality of first memory cells MC21 adjacent to each other along a third direction D3. A plurality of first cell separation layers ISOA are located between a plurality of data storage elements CAP, and a plurality of second cell separation layers ISOB are located between a plurality of first conductive lines BL. A plurality of first cell separation layers ISOA include a plurality of first cell separation sections ISOA1 and ISOA2, respectively. A plurality of second cell separation layers ISOB include a plurality of second cell separation sections ISOB1 and ISOB2, respectively. A first electrode SN of a plurality of data storage elements CAP is located between a plurality of first cell separation sections ISOA2. A plurality of first conductive lines BL are located between a plurality of second cell separation sections ISOB1.

[0378] A plurality of first cell separation layers ISOA and a plurality of second cell separation layers ISOB are located between a plurality of second memory cells MC22 adjacent to each other along a third direction D3. A plurality of first cell separation layers ISOA are located between a plurality of data storage elements CAP, and a plurality of second cell separation layers ISOB are located between a plurality of first conductive lines BL. A plurality of first cell separation layers ISOA include a plurality of first cell separation sections ISOA1 and ISOA2, respectively. A plurality of second cell separation layers ISOB include a plurality of second cell separation sections ISOB1 and ISOB2, respectively. A first electrode SN of a plurality of data storage elements CAP is located between a plurality of first cell separation sections ISOA2. A plurality of first conductive lines BL are located between a plurality of second cell separation sections ISOB1.

[0379] The three-dimensional array of the plurality of first memory cells MC21 shares the first conductive line BL, and the three-dimensional array of the plurality of second memory cells MC22 shares the first conductive line BL. The first memory cells MC21 and the second memory cells MC22 adjacent along the second direction D2 share one first conductive line BL. That is, the first conductive line BL can be referred to as a common first conductive line BL.

[0380] A plurality of first conductive lines BL are formed by hole patterning. Fig. 7A and Fig.47C As shown, hole-type sacrificial openings V2', HV2' may be applied.

[0381] Fig.49A and Fig.49B A diagram for explaining an example of a method for manufacturing a semiconductor device according to another embodiment. Fig.49A and Fig.49B for FIG. 29A to FIG. 31C Another embodiment of a plurality of linear sacrificial openings LV1 ′, LV2 ′ is shown.

[0382] Fig.49A It is a top view of the fourth layer 14 level for explaining a method of forming a plurality of sacrificial separation openings 15A3 .

[0383] Reference Fig.29A , Fig.29B and Fig.49A, the stack SB is formed on the upper part of the lower structure 11. The stack SB is formed by alternately stacking a plurality of sub-stacks. Each sub-stack is stacked in the order of a first layer 12A, a second layer 13, a third layer 12B, and a fourth layer 14. The plurality of first layers 12A and the plurality of third layers 12B are formed of the same material, such as silicon germanium. The plurality of second layers 13 may include single crystal silicon. The fourth layer 14 may include single crystal silicon. The first layer 12A, the second layer 13, the third layer 12B, and the fourth layer 14 are formed by an epitaxial growth process.

[0384] A portion of the stacked body SB is etched to form a plurality of sacrificial separation openings 15A3. The plurality of sacrificial separation openings 15A3 have the same size as a plurality of initial openings for device separation.

[0385] Fig.49B It is a top view of the fourth layer 14 for explaining a method of forming a plurality of linear sacrificial openings LV1 ′, LV2 ′.

[0386] like Fig. 30A , Fig. 30B and Fig.49B As shown, a plurality of sacrificial cell separation layers 16A3 are formed to fill the plurality of sacrificial separation openings 15A3. The plurality of sacrificial cell separation layers 16A3 have the same size.

[0387] Next, a portion of the stacked body SB is etched. Thus, a plurality of linear sacrificial openings LV1', LV2' are formed between the plurality of sacrificial unit separation layers 16A3. The plurality of linear sacrificial openings LV1', LV2' include a first linear sacrificial opening LV1' and a second linear sacrificial opening LV2'. When viewed from a top view, the first linear sacrificial opening LV1' and the second linear sacrificial opening LV2' are a plurality of linear openings extending along the third direction D3. The first linear sacrificial opening LV1' and the second linear sacrificial opening LV2' extend vertically along the first direction D1. The plurality of sacrificial unit separation layers 16A3 are located between the first linear sacrificial opening LV1' and the second linear sacrificial opening LV2' along the second direction D2. When viewed from a top view, the cross-section of the first linear sacrificial opening LV1' and the second linear sacrificial opening LV2' is a rectangle. In another embodiment, the cross-section of the first linear sacrificial opening LV1' and the second linear sacrificial opening LV2' is a circular shape or an elliptical shape. The widths of the first and second line-type sacrificial openings LV1 ′ and LV2 ′ in the second direction D2 are smaller than the widths in the third direction D3 .

[0388] A plurality of data storage elements are formed using the first line-type sacrificial openings LV1 ′, and a vertical conductive line is formed using the second line-type sacrificial openings LV2 ′.

[0389] Fig.50AFIG. 1 is a schematic top view of a semiconductor device according to another embodiment. Fig.50B For along Fig.50A A-A' cross-sectional view. Fig.50C for Fig.50A A simplified three-dimensional diagram of a semiconductor device in FIG. FIG. 50A to FIG. 50C The semiconductor device 400 may be Fig.49A The method to Figure 49C is formed.

[0390] Reference FIG. 50A to FIG. 50C The semiconductor device 400 includes a memory cell array MCA, which includes a three-dimensional array of a plurality of memory cells MC31 and MC32. The memory cell array MCA includes a first sub-cell array MCA1 and a second sub-cell array MCA2.

[0391] The memory cell array MCA includes a plurality of memory cells MC31 and MC32 vertically stacked along a first direction D1. The plurality of memory cells MC31 and MC32 have Figure 1A and Figure 1B The memory cell array MCA includes a plurality of memory cells MC31 and MC32 arranged horizontally along the second direction D2. The memory cell array MCA includes a plurality of memory cells MC31 and MC32 arranged horizontally along the third direction D3. The memory cell array MCA includes a plurality of first conductive lines BL, and the first conductive lines BL include a first vertical conductive line BLA and a second vertical conductive line BLB. The bottom of the first vertical conductive line BLA and the bottom of the second vertical conductive line BLB are spaced apart from each other.

[0392] The first memory cell MC31 of the first sub-cell array MCA1 includes a first vertical conductive line BLA, a switch element TR and a data storage element CAP, and the switch element TR includes a second conductive line GAA_WL and a horizontal layer HL. The second memory cell MC32 of the second sub-cell array MCA2 includes a second vertical conductive line BLB, a switch element TR and a data storage element CAP, and the switch element TR includes a second conductive line GAA_WL and a horizontal layer HL. The second conductive line GAA_WL is a gate allaround structure (GAA). For example, the second conductive line GAA_WL surrounds multiple horizontal layers HL of the same horizontal level and extends along the third direction D3.

[0393] The first conductive line BL extends vertically along the first direction D1 , the horizontal layer HL extends along the second direction D2 , and the second conductive line GAA_WL extends horizontally along the third direction D3 .

[0394] A plurality of first inter-cell dielectric layers IL1 are disposed between a plurality of data storage elements CAP adjacent to each other along the third direction D3 . A plurality of second inter-cell dielectric layers IL are disposed between a plurality of second conductive lines GAA_WL stacked along the first direction D1 .

[0395] The plurality of memory cells MC31 and MC32 further include a contact node SNC. The contact node SNC is disposed between the horizontal layer HL and the first electrode SN. The contact node SNC may include doped polysilicon, and the second doping region DR may include impurities diffused from the contact node SNC.

[0396] The plurality of memory cells MC31 and MC32 further include a first cover layer BC and a second cover layer CC. The plurality of first vertical conductive lines BLA adjacent to each other along the third direction D3 are formed by self-alignment through the plurality of first cover layers BC. The plurality of second vertical conductive lines BLB adjacent to each other along the third direction D3 are formed by self-alignment through the plurality of first cover layers BC.

[0397] The memory cell array MCA includes a hard mask layer HM at a level higher than the second conductive lines GAA_WL at the uppermost level.

[0398] The memory cell array MCA includes a plurality of bottom protection layers BF21, BF2, and BF3.

[0399] The vertical separation layer BLF is located between the first vertical conductive line BLA and the second vertical conductive line BLB of the plurality of first conductive lines BL. The vertical separation layer BLF may include an insulating material.

[0400] Multiple horizontal layers HL of multiple switching elements TR horizontally arranged along the third direction D3 share one second conductive line GAA_WL. Multiple horizontal layers HL of multiple switching elements TR horizontally arranged along the third direction D3 are connected to different first conductive lines BL. Multiple switching elements TR stacked along the first direction D1 share one first conductive line BL. Multiple switching elements TR horizontally arranged along the third direction D3 share one second conductive line GAA_WL.

[0401] The plurality of second electrodes PN of the plurality of data storage elements CAP are connected to a common plate PL.

[0402] Fig.51A FIG. 1 is a schematic top view of a semiconductor device according to another embodiment. Fig.51B For along Fig.51A A-A' cross-sectional view. Fig.51C for Fig.51A A simplified three-dimensional diagram of a semiconductor device. FIG. 51A to FIG. 51C The semiconductor device 401 can be Fig.49A The method to Figure 49C is formed.

[0403] Reference FIG. 51A to FIG. 51C The semiconductor device 401 includes a memory cell array MCA, which includes a three-dimensional array of a plurality of memory cells MC31 and MC32. The memory cell array MCA includes a first sub-cell array MCA1 and a second sub-cell array MCA2.

[0404] The memory cell array MCA includes a plurality of memory cells MC31 and MC32 vertically stacked along a first direction D1. The plurality of memory cells MC31 and MC32 have Figure 1A and Figure 1B The memory cell array MCA includes a plurality of memory cells MC31 and MC32 arranged horizontally along the second direction D2. The memory cell array MCA includes a plurality of memory cells MC31 and MC32 arranged horizontally along the third direction D3. The memory cell array MCA includes a plurality of first conductive lines BL, and the first sub-cell array MCA1 and the second sub-cell array MCA2 share the first conductive lines BL.

[0405] The first memory cell MC31 of the first sub-cell array MCA1 includes a first conductive line BL, a switch element TR and a data storage element CAP, and the switch element TR includes a second conductive line GAA_WL and a horizontal layer HL. The second memory cell MC32 of the second sub-cell array MCA2 includes a first conductive line BL, a switch element TR and a data storage element CAP, and the switch element TR includes a second conductive line GAA_WL and a horizontal layer HL. The second conductive line GAA_WL is a gate all around structure (GAA). For example, the second conductive line GAA_WL surrounds a plurality of horizontal layers HL of the same horizontal level and extends along a third direction D3.

[0406] The first conductive line BL may extend vertically along the first direction D1 , the horizontal layer HL may extend along the second direction D2 , and the second conductive line GAA_WL may extend horizontally along the third direction D3 .

[0407] A plurality of first inter-cell dielectric layers IL1 are disposed between a plurality of data storage elements CAP adjacent to each other along the third direction D3 . A plurality of second inter-cell dielectric layers IL are disposed between a plurality of second conductive lines GAA_WL stacked along the first direction D1 .

[0408] The plurality of memory cells MC31 and MC32 further include a contact node SNC. The contact node SNC is disposed between the horizontal layer HL and the first electrode SN. The contact node SNC may include doped polysilicon, and the second doping region DR may include impurities diffused from the contact node SNC.

[0409] The plurality of memory cells MC31 , MC32 further include a first cover layer BC and a second cover layer CC.

[0410] The memory cell array MCA includes a hard mask layer HM at a level higher than the second conductive lines GAA_WL at the uppermost level.

[0411] The memory cell array MCA includes a plurality of bottom protection layers BF21, BF2, and BF3.

[0412] The vertical separation layer BLF is located between the first vertical conductive line BLA and the second vertical conductive line BLB of the plurality of first conductive lines BL. The vertical separation layer BLF may include an insulating material. The plurality of first conductive lines BL adjacent to each other along the third direction D3 are spaced apart with the vertical separation layer BLF therebetween.

[0413] Multiple horizontal layers HL of multiple switching elements TR arranged horizontally along the third direction D3 share one second conductive line GAA_WL. Multiple horizontal layers HL of multiple switching elements TR arranged horizontally along the second direction D2 share a first conductive line BL. Multiple horizontal layers HL of multiple switching elements TR arranged horizontally along the third direction D3 are connected to different first conductive lines BL. Multiple switching elements TR stacked along the first direction D1 share one first conductive line BL. Multiple switching elements TR arranged horizontally along the third direction D3 share one second conductive line GAA_WL.

[0414] The plurality of second electrodes PN of the plurality of data storage elements CAP are connected to a common plate PL.

[0415] Fig.52A FIG. 1 is a schematic top view of a semiconductor device according to another embodiment. Fig.52B For along Fig.52A A brief cross-sectional view of A-A'. Fig.52A and Fig.52B The semiconductor device 500 and Figure 2 , Figure 3A and Figure 3B Hereinafter, detailed description of the repeated structural elements will be omitted.

[0416] Reference Fig.52A and Fig.52B, the semiconductor device 500 includes a memory cell array MCA. The memory cell array MCA includes a plurality of memory cells MC. Each memory cell MC includes a first conductive line BL, a switch element TR, and a data storage element CAP. As shown in the above embodiments, the first conductive line BL, the switch element TR, and the data storage element CAP are formed by line patterning, hole patterning, or a combination thereof.

[0417] The memory cell array MCA includes a three-dimensional array of a plurality of memory cells MC. The memory cell array MCA is a mirror structure in which two memory cells MC share a first conductive line BL.

[0418] A plurality of interlayer dielectric layers IL are disposed between a plurality of memory cells MC stacked along a first direction D1. A plurality of cell separation layers ISOA and ISOB are disposed between a plurality of memory cells MC adjacent to each other along a third direction D3. The plurality of cell separation layers ISOA and ISOB include a plurality of first cell separation layers ISOA and a plurality of second cell separation layers ISOB. The plurality of first cell separation layers ISOA and the plurality of second cell separation layers ISOB extend vertically along the first direction D1. The plurality of first cell separation layers ISOA and the plurality of second cell separation layers ISOB are pillar structures extending vertically along the first direction D1. The plurality of first cell separation layers ISOA and the plurality of second cell separation layers ISOB are alternately and repeatedly disposed along the second direction D2. The plurality of first cell separation layers ISOA are disposed between a plurality of data storage elements CAP along the third direction D3. The plurality of second cell separation layers ISOB are disposed between a plurality of first conductive lines BL along the third direction D3. The second conductive line DWL is disposed between the plurality of first cell separation layers ISOA and the plurality of second cell separation layers ISOB along the second direction D2.

[0419] The memory cell array MCA is located on the upper portion of the lower structure LS.

[0420] The memory cell array MCA includes a plurality of second conductive lines DWL vertically stacked along a first direction D1. The memory cell array MCA includes a plurality of horizontal layers HL vertically stacked along the first direction D1. The memory cell array MCA includes a plurality of data storage elements CAP vertically stacked along the first direction D1. The memory cell array MCA includes a plurality of first conductive lines BL spaced apart along a third direction D3.

[0421] The plurality of second conductive lines DWL respectively include Figure 1CThe channel overlap portion WLP shown. The channel overlap portion WLP is a cross-shape or a diamond shape. The channel overlap portion WLP completely overlaps with the channel CH. The second conductive line DWL extending along the third direction D3 includes a plurality of channel overlap portions WLP. The second conductive line DWL has a notch-shaped sidewall by alternating a plurality of channel overlap portions WLP and a plurality of channel non-overlap portions (reference numerals omitted) along the third direction D3. The notch-shaped sidewalls of the plurality of second conductive lines DWL may be asymmetric to each other.

[0422] A plurality of dummy conductive wires WLD and a plurality of dummy insulating layers GDD are provided between the bottommost second conductive wire DWL among the plurality of second conductive wires DWL and the lower structure LS. A first protective layer stack BT1, BT2, BT3 is provided between the first conductive wire BL and the lower structure LS. The first protective layer stack BT1, BT2, BT3 includes silicon oxide BT1, silicon nitride BT2 and silicon oxide BT3. A plurality of second protective layer stacks BF31, BF32 are provided between the data storage element CAP and the lower structure LS. The plurality of second protective layer stacks BF31, BF32 may include silicon oxide BF1 and silicon nitride BF3.

[0423] A plurality of first contact nodes BLC extend vertically along a first direction D1 at an upper portion of the lower structure LS. A plurality of horizontal layers HL extend along a second direction D2 intersecting the first direction D1. A second conductive line DWL extends along a third direction D3 intersecting the first direction D1 and the second direction D2. A barrier metal BLM is formed at the first contact node BLC, and a first conductive line BL is formed at the barrier metal BLM. The first contact node BLC may include doped polysilicon, and the barrier metal BLM may include a titanium / titanium nitride stack.

[0424] When viewed from a top view, the plurality of horizontal layers HL are in a cross-shape or a diamond-shape. In another embodiment, the side surface of the horizontal layer HL may be in a curved shape or a circular shape. Figure 1B As shown, the horizontal layer HL includes a channel CH, a first doping region SR between the channel CH and the first conductive line BL, and a second doping region DR between the channel CH and the data storage element CAP.

[0425] The first cover layer BC is located between the second conductive line DWL and the first contact node BLC. The second cover layer CC is located between the second conductive line DWL and the first electrode SN of the data storage element. The first cover layer BC is arranged between the upper horizontal line G1 and the first conductive line BL, and the first cover layer BC is arranged between the lower horizontal line G2 and the first contact node BLC. The second cover layer CC is arranged between the upper horizontal line G1 and the first electrode SN of the data storage element CAP, and the second cover layer CC is arranged between the lower horizontal line G2 and the first electrode SN of the data storage element CAP. A memory cell MC includes a pair of first cover layers BC and a pair of second cover layers CC.

[0426] The first cover layer BC and the second cover layer CC may include insulating materials. The first cover layer BC and the second cover layer CC may include silicon oxide, silicon nitride, silicon oxycarbide, air gaps, or a combination thereof. The first cover layer BC may include silicon oxide, and the second cover layer CC may include a stack of silicon oxide and silicon nitride.

[0427] Multiple horizontal layers HL of multiple switching elements TR horizontally arranged along the third direction D3 share one second conductive line DWL. Multiple horizontal layers HL of multiple switching elements TR horizontally arranged along the third direction D3 are connected to mutually different first conductive lines BL. Multiple switching elements TR stacked along the first direction D1 share one first conductive line BL. Multiple switching elements TR horizontally arranged along the third direction D3 share one second conductive line DWL.

[0428] The plurality of first cell separation layers ISOA are disposed between the plurality of first electrodes SN of the plurality of data storage elements CAP along the third direction D3. The plurality of first electrodes SN are separated from each other by the plurality of first cell separation layers ISOA. The plurality of second electrodes PN of the plurality of data storage elements CAP are connected to a common plate PL.

[0429] A portion of the plurality of second electrodes PN divides the first unit separation layer ISOA. The plurality of second electrodes PN of the plurality of data storage elements CAP are merged into a common plate PL. The plurality of second electrodes PN of the plurality of data storage elements CAP arranged horizontally along the third direction D3 are merged with each other. The plurality of second electrodes PN of the plurality of data storage elements CAP arranged vertically along the first direction D1 are merged with each other. The common plate PL extends horizontally along the third direction D3 while extending vertically along the first direction D1. The common plate PL is in a cross shape extending along the third direction D3. The plurality of first unit separation layers ISOA are divided into a plurality of first unit separation sections ISOA1 and ISOA2 by the common plate PL. The size of the plurality of first unit separation sections ISOA1 and ISOA2 is smaller than or equal to the plurality of second unit separation layers ISOB. The plurality of first electrodes SN of the data storage element are arranged between the plurality of first unit separation sections ISOA1 along the third direction D3. The plurality of first electrodes SN of the data storage element are arranged between the plurality of first unit separation sections ISOA2 along the third direction D3.

[0430] A plurality of first cell separation layers ISOA are disposed between a plurality of data storage elements CAP along a third direction D3. A plurality of second cell separation layers ISOB are disposed between a plurality of first conductive lines BL along a third direction D3. A second conductive line DWL is disposed between a plurality of first cell separation layers ISOA and a plurality of second cell separation layers ISOB along a second direction D2. A size of the plurality of first cell separation layers ISOA is greater than that of the plurality of second cell separation layers ISOB.

[0431] The lower structure LS includes a semiconductor substrate, a metal wiring structure, an insulating structure, a conductive structure, a pad structure, and other memory or peripheral circuit parts.

[0432] The plurality of second electrodes PN of the data storage element CAP may include a stack of a metal nitride liner N1 and a polysilicon layer N2.

[0433] The present invention described above is not limited to the above embodiments and drawings, and various substitutions, deformations and changes can be made without departing from the technical concept of the present invention, which is obvious to ordinary technicians in the technical field to which the present invention belongs.

[0434] Description of Reference Numerals

[0435] BL: first conductive line DWL: second conductive line

[0436] HL: horizontal layer GD: interlayer insulation layer

[0437] CH: Channel SR: First doping region

[0438] DR: Second doping region TR: Switching element

[0439] CAP: Data storage element SN: First electrode

[0440] DE: Dielectric layer PN: Second electrode

[0441] PL: Common Plate MCA: Memory Cell Array

[0442] MC: memory cell PL_M: merging unit

[0443] PL_S: shared part BLC: first contact node

[0444] SNC: Second contact node ISOA: First unit separation layer

[0445] ISOB: Second unit separation layer

Claims

1. A method for manufacturing a semiconductor device, characterized in that: include: forming a unit mold having a plurality of mold layers stacked on an upper portion of the lower structure; a step of forming a linear vertical opening in the unit mold vertically oriented along a stacking direction of the unit mold; The step of forming a storage opening extending horizontally from the linear vertical opening; as well as The step of forming a data storage element within the storage opening.

2. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming the linear vertical opening include: forming a mask layer defining a line-type opening pattern on the unit mold; The step of using the mask layer as an etching barrier layer to etch the unit mold to form a linear sacrificial opening; forming a sacrificial structure for filling the linear sacrificial opening; and The step of removing the sacrificial structure to form the linear vertical opening.

3. The method for manufacturing a semiconductor device according to claim 1, wherein: The step of forming the storage opening includes the step of horizontally recessing the mold layer from the linear vertical opening.

4. The method for manufacturing a semiconductor device according to claim 1, wherein: The steps of forming the data storage element include: forming a first electrode on the inner side of the storage opening; forming a dielectric layer on the first electrode; and A step of forming a second electrode on the dielectric layer to fill the storage opening.

5. The method for manufacturing a semiconductor device according to claim 1, wherein: The first electrode includes a cylindrical shape.

6. The method for manufacturing a semiconductor device according to claim 1, wherein: The data storage element includes a capacitor.

7. The method for manufacturing a semiconductor device according to claim 1, wherein: The mold layer includes a stack of a sacrificial layer and a semiconductor layer, and The semiconductor layer includes single crystal silicon or an oxide semiconductor material.

8. The method for manufacturing a semiconductor device according to claim 1, wherein: Before the step of forming the data storage element, the method further includes the step of forming a contact node on the inner side surface of the storage opening.

9. The method for manufacturing a semiconductor device according to claim 1, wherein: After the step of forming the unit mold, the method further comprises: forming a switching element including a horizontal conductive line in the unit mold; and The step of forming a vertical conductive line connected to the switching element.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: The mold layer includes a stack of a first sacrificial layer, a semiconductor layer and a second sacrificial layer, The steps of forming the switch element include: A step of etching the unit mold to form a hole-shaped vertical opening; and The step of replacing a portion of the first sacrificial layer and a portion of the second sacrificial layer with the horizontal conductive line from the hole-shaped vertical opening.

11. A method for manufacturing a semiconductor device, characterized in that: include: The step of forming a unit mold having a first sacrificial layer, a semiconductor layer, and a second sacrificial layer stacked in sequence on an upper portion of the lower structure; a step of removing a first portion of the unit mold to form a linear vertical opening oriented vertically along a stacking direction of the unit mold; The step of removing the second portion of the unit mold to form a hole-shaped vertical opening vertically oriented along the stacking direction of the unit mold; The step of forming a switch element oriented horizontally from the vertical opening of the hole pattern; The step of forming a vertical conductive line connected to the switching element in the hole-shaped vertical opening; The step of forming a storage opening extending horizontally from the linear vertical opening; as well as The step of forming a data storage element within the storage opening.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The steps of forming the linear vertical opening include: forming a mask layer defining a line-type opening pattern on the unit mold; The step of using the mask layer as an etching barrier layer to etch the first portion of the unit mold to form a linear sacrificial opening; forming a sacrificial structure for filling the linear sacrificial opening; and The step of removing the sacrificial structure to form the linear vertical opening.

13. The method for manufacturing a semiconductor device according to claim 11, wherein: The step of forming the storage opening includes: making the first sacrificial layer, the semiconductor layer and the second sacrificial layer horizontally recessed from the linear vertical opening, The recessed semiconductor layer forms a horizontal layer, and the recessed first sacrificial layer and the second sacrificial layer form a capping layer.

14. The method for manufacturing a semiconductor device according to claim 11, wherein: The steps of forming the data storage element include: forming a first electrode on the inner side of the storage opening; forming a dielectric layer on the first electrode; and A step of forming a second electrode on the dielectric layer to fill the storage opening.

15. The method for manufacturing a semiconductor device according to claim 11, wherein: The semiconductor layer includes single crystal silicon or an oxide semiconductor material.

16. The method for manufacturing a semiconductor device according to claim 11, wherein: Before the step of forming the data storage element, the method further includes the step of forming a contact node on the inner side surface of the storage opening.

17. The method for manufacturing a semiconductor device according to claim 11, wherein: The step of forming the linear vertical opening and the step of forming the hole-type vertical opening include: forming a mask layer defining a line-type opening pattern and a hole-type opening pattern on the unit mold; The step of using the mask layer as an etching barrier layer to etch the first part and the second part of the unit mold to form a line-type sacrificial opening and a hole-type sacrificial opening; The step of forming a linear sacrificial structure and a hole-shaped sacrificial structure for filling the linear sacrificial opening and the hole-shaped sacrificial opening respectively; A step of removing the linear sacrificial structure to form the linear vertical opening; and The step of removing the hole-shaped sacrificial structure to form the hole-shaped vertical opening.

18. A method for manufacturing a semiconductor device, characterized in that: include: The step of forming a unit mold including a horizontal layer on the upper portion of the lower structure; forming a first unit separation layer and a second unit separation layer in the unit mold; a step of etching a first portion of the unit mold to form a first line-shaped vertical opening between the second unit separation layers; forming a horizontal conductive line horizontally spaced apart from the first line-type vertical opening and overlapping the horizontal layer; The step of cutting a portion of the horizontal layer from the first linear vertical opening to form a vertical expansion portion; as well as A step of forming a vertical conductive line in the vertical expansion portion, wherein the vertical conductive line is connected to a side surface of the horizontal layer and is self-aligned with a side surface of the second cell separation layer.

19. The method for manufacturing a semiconductor device according to claim 18, wherein: After the step of forming the vertical conductive line, the method further comprises: a step of removing a second portion of the unit mold to form a second linear vertical opening between the first unit separation layers; forming a storage opening extending horizontally from the second linear vertical opening and exposing the other side of the horizontal layer; and The step of forming a data storage element in the storage opening connected to another side of the horizontal layer.

20. The method for manufacturing a semiconductor device according to claim 18, wherein: The unit mold includes a first sacrificial layer and a second sacrificial layer which are vertically arranged with the horizontal layer in between. The step of forming the horizontal conductive line includes the step of replacing a portion of the first sacrificial layer and a portion of the second sacrificial layer with the horizontal conductive line from the first line-shaped vertical opening.

21. The method for manufacturing a semiconductor device according to claim 18, wherein: The second cell separation layer is formed to include two second cell separation segments, and the first line-type vertical opening is formed between the second cell separation segments.

22. The method for manufacturing a semiconductor device according to claim 21, wherein: The first cell separation layer is formed to include two first cell separation sections.

23. A method for manufacturing a semiconductor device, characterized in that: include: The step of forming a unit mold including a horizontal layer on the upper portion of the lower structure; forming a first unit separation layer and a second unit separation layer in the unit mold; a step of etching a first portion of the unit mold to form a first line-shaped vertical opening between the second unit separation layers; forming a horizontal conductive line horizontally spaced apart from the first line-type vertical opening and overlapping the horizontal layer; and The step of forming a vertical conductive line commonly connected to the horizontal layers horizontally adjacent to each other with the first line-type vertical opening therebetween.

24. The method for manufacturing a semiconductor device according to claim 23, wherein: After the step of forming the vertical conductive line, the method further comprises: a step of removing a second portion of the unit mold to form a second linear vertical opening between the first unit separation layers; forming a storage opening extending horizontally from the second linear vertical opening and exposing the other side of the horizontal layer; and The step of forming a data storage element in the storage opening connected to another side of the horizontal layer.

25. The method for manufacturing a semiconductor device according to claim 23, wherein: The second cell separation layer is formed to include two second cell separation segments, and the first line-type vertical opening is formed between the second cell separation segments.

26. The method for manufacturing a semiconductor device according to claim 25, wherein: The first cell separation layer is formed to include two first cell separation sections.

27. The method for manufacturing a semiconductor device according to claim 23, wherein: The unit mold includes a first sacrificial layer and a second sacrificial layer vertically arranged with the horizontal layer interposed therebetween, and The step of forming the horizontal conductive line includes the step of replacing a portion of the first sacrificial layer and a portion of the second sacrificial layer with the horizontal conductive line from the first line-shaped vertical opening.

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